1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_IPP_HW_H 27 #define _SYS_NXGE_NXGE_IPP_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_defs.h> 34 35 /* IPP Registers */ 36 #define IPP_CONFIG_REG 0x000 37 #define IPP_DISCARD_PKT_CNT_REG 0x020 38 #define IPP_BAD_CKSUM_ERR_CNT_REG 0x028 39 #define IPP_ECC_ERR_COUNTER_REG 0x030 40 #define IPP_INT_STATUS_REG 0x040 41 #define IPP_INT_MASK_REG 0x048 42 43 #define IPP_PFIFO_RD_DATA0_REG 0x060 44 #define IPP_PFIFO_RD_DATA1_REG 0x068 45 #define IPP_PFIFO_RD_DATA2_REG 0x070 46 #define IPP_PFIFO_RD_DATA3_REG 0x078 47 #define IPP_PFIFO_RD_DATA4_REG 0x080 48 #define IPP_PFIFO_WR_DATA0_REG 0x088 49 #define IPP_PFIFO_WR_DATA1_REG 0x090 50 #define IPP_PFIFO_WR_DATA2_REG 0x098 51 #define IPP_PFIFO_WR_DATA3_REG 0x0a0 52 #define IPP_PFIFO_WR_DATA4_REG 0x0a8 53 #define IPP_PFIFO_RD_PTR_REG 0x0b0 54 #define IPP_PFIFO_WR_PTR_REG 0x0b8 55 #define IPP_DFIFO_RD_DATA0_REG 0x0c0 56 #define IPP_DFIFO_RD_DATA1_REG 0x0c8 57 #define IPP_DFIFO_RD_DATA2_REG 0x0d0 58 #define IPP_DFIFO_RD_DATA3_REG 0x0d8 59 #define IPP_DFIFO_RD_DATA4_REG 0x0e0 60 #define IPP_DFIFO_WR_DATA0_REG 0x0e8 61 #define IPP_DFIFO_WR_DATA1_REG 0x0f0 62 #define IPP_DFIFO_WR_DATA2_REG 0x0f8 63 #define IPP_DFIFO_WR_DATA3_REG 0x100 64 #define IPP_DFIFO_WR_DATA4_REG 0x108 65 #define IPP_DFIFO_RD_PTR_REG 0x110 66 #define IPP_DFIFO_WR_PTR_REG 0x118 67 #define IPP_STATE_MACHINE_REG 0x120 68 #define IPP_CKSUM_STATUS_REG 0x128 69 #define IPP_FFLP_CKSUM_INFO_REG 0x130 70 #define IPP_DEBUG_SELECT_REG 0x138 71 #define IPP_DFIFO_ECC_SYNDROME_REG 0x140 72 #define IPP_DFIFO_EOPM_RD_PTR_REG 0x148 73 #define IPP_ECC_CTRL_REG 0x150 74 75 #define IPP_PORT_OFFSET 0x4000 76 #define IPP_PORT0_OFFSET 0 77 #define IPP_PORT1_OFFSET 0x8000 78 #define IPP_PORT2_OFFSET 0x4000 79 #define IPP_PORT3_OFFSET 0xc000 80 #define IPP_REG_ADDR(port_num, reg)\ 81 ((port_num == 0) ? FZC_IPP + reg : \ 82 FZC_IPP + reg + (((port_num % 2) * IPP_PORT_OFFSET) + \ 83 ((port_num / 3) * IPP_PORT_OFFSET) + IPP_PORT_OFFSET)) 84 #define IPP_PORT_ADDR(port_num)\ 85 ((port_num == 0) ? FZC_IPP: \ 86 FZC_IPP + (((port_num % 2) * IPP_PORT_OFFSET) + \ 87 ((port_num / 3) * IPP_PORT_OFFSET) + IPP_PORT_OFFSET)) 88 89 /* IPP Configuration Register */ 90 91 #define IPP_SOFT_RESET (1ULL << 31) 92 #define IPP_IP_MAX_PKT_BYTES_SHIFT 8 93 #define IPP_IP_MAX_PKT_BYTES_MASK 0x1FFFF 94 #define IPP_FFLP_CKSUM_INFO_PIO_WR_EN (1 << 7) 95 #define IPP_PRE_FIFO_PIO_WR_EN (1 << 6) 96 #define IPP_DFIFO_PIO_WR_EN (1 << 5) 97 #define IPP_TCP_UDP_CKSUM_EN (1 << 4) 98 #define IPP_DROP_BAD_CRC_EN (1 << 3) 99 #define IPP_DFIFO_ECC_CORRECT_EN (1 << 2) 100 #define IPP_EN (1 << 0) 101 102 /* IPP Interrupt Status Registers */ 103 104 #define IPP_DFIFO_MISSED_SOP (1ULL << 31) 105 #define IPP_DFIFO_MISSED_EOP (1 << 30) 106 #define IPP_DFIFO_ECC_UNCORR_ERR_MASK 0x3 107 #define IPP_DFIFO_ECC_UNCORR_ERR_SHIFT 28 108 #define IPP_DFIFO_ECC_CORR_ERR_MASK 0x3 109 #define IPP_DFIFO_ECC_CORR_ERR_SHIFT 26 110 #define IPP_DFIFO_ECC_ERR_MASK 0x3 111 #define IPP_DFIFO_ECC_ERR_SHIFT 24 112 #define IPP_DFIFO_NO_ECC_ERR (1 << 23) 113 #define IPP_DFIFO_ECC_ERR_ENTRY_INDEX_MASK 0x7FF 114 #define IPP_DFIFO_ECC_ERR_ENTRY_INDEX_SHIFT 12 115 #define IPP_PRE_FIFO_PERR (1 << 11) 116 #define IPP_ECC_ERR_CNT_MAX (1 << 10) 117 #define IPP_PRE_FIFO_PERR_ENTRY_INDEX_MASK 0x3F 118 #define IPP_PRE_FIFO_PERR_ENTRY_INDEX_SHIFT 4 119 #define IPP_PRE_FIFO_OVERRUN (1 << 3) 120 #define IPP_PRE_FIFO_UNDERRUN (1 << 2) 121 #define IPP_BAD_TCPIP_CHKSUM_CNT_MAX (1 << 1) 122 #define IPP_PKT_DISCARD_CNT_MAX (1 << 0) 123 124 #define IPP_P0_P1_DFIFO_ENTRIES 2048 125 #define IPP_P2_P3_DFIFO_ENTRIES 1024 126 #define IPP_NIU_DFIFO_ENTRIES 1024 127 128 typedef union _ipp_status { 129 uint64_t value; 130 131 struct { 132 #if defined(_BIG_ENDIAN) 133 uint32_t w1; 134 #endif 135 struct { 136 #if defined(_BIT_FIELDS_HTOL) 137 uint32_t dfifo_missed_sop : 1; 138 uint32_t dfifo_missed_eop : 1; 139 uint32_t dfifo_uncorr_ecc_err : 2; 140 uint32_t dfifo_corr_ecc_err : 2; 141 uint32_t dfifo_ecc_err : 2; 142 uint32_t dfifo_no_ecc_err : 1; 143 uint32_t dfifo_ecc_err_idx : 11; 144 uint32_t pre_fifo_perr : 1; 145 uint32_t ecc_err_cnt_ovfl : 1; 146 uint32_t pre_fifo_perr_idx : 6; 147 uint32_t pre_fifo_overrun : 1; 148 uint32_t pre_fifo_underrun : 1; 149 uint32_t bad_cksum_cnt_ovfl : 1; 150 uint32_t pkt_discard_cnt_ovfl : 1; 151 #elif defined(_BIT_FIELDS_LTOH) 152 uint32_t pkt_discard_cnt_ovfl : 1; 153 uint32_t bad_cksum_cnt_ovfl : 1; 154 uint32_t pre_fifo_underrun : 1; 155 uint32_t pre_fifo_overrun : 1; 156 uint32_t pre_fifo_perr_idx : 6; 157 uint32_t ecc_err_cnt_ovfl : 1; 158 uint32_t pre_fifo_perr : 1; 159 uint32_t dfifo_ecc_err_idx : 11; 160 uint32_t dfifo_no_ecc_err : 1; 161 uint32_t dfifo_ecc_err : 2; 162 uint32_t dfifo_corr_ecc_err : 2; 163 uint32_t dfifo_uncorr_ecc_err : 2; 164 uint32_t dfifo_missed_eop : 1; 165 uint32_t dfifo_missed_sop : 1; 166 #else 167 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined 168 #endif 169 } w0; 170 171 #if !defined(_BIG_ENDIAN) 172 uint32_t w1; 173 #endif 174 } bits; 175 } ipp_status_t; 176 177 typedef union _ipp_ecc_ctrl { 178 uint64_t value; 179 180 struct { 181 #if defined(_BIG_ENDIAN) 182 uint32_t w1; 183 #endif 184 struct { 185 #if defined(_BIT_FIELDS_HTOL) 186 uint32_t dis_dbl : 1; 187 uint32_t res3 : 13; 188 uint32_t cor_dbl : 1; 189 uint32_t cor_sng : 1; 190 uint32_t rsvd : 5; 191 uint32_t cor_all : 1; 192 uint32_t res2 : 1; 193 uint32_t cor_1 : 1; 194 uint32_t res1 : 5; 195 uint32_t cor_lst : 1; 196 uint32_t cor_snd : 1; 197 uint32_t cor_fst : 1; 198 #elif defined(_BIT_FIELDS_LTOH) 199 uint32_t cor_fst : 1; 200 uint32_t cor_snd : 1; 201 uint32_t cor_lst : 1; 202 uint32_t res1 : 5; 203 uint32_t cor_1 : 1; 204 uint32_t res2 : 1; 205 uint32_t cor_all : 1; 206 uint32_t rsvd : 5; 207 uint32_t cor_sng : 1; 208 uint32_t cor_dbl : 1; 209 uint32_t res3 : 13; 210 uint32_t dis_dbl : 1; 211 #else 212 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined 213 #endif 214 } w0; 215 216 #if !defined(_BIG_ENDIAN) 217 uint32_t w1; 218 #endif 219 } bits; 220 } ipp_ecc_ctrl_t; 221 222 223 /* IPP Interrupt Mask Registers */ 224 225 #define IPP_ECC_ERR_CNT_MAX_INTR_DIS (1 << 7) 226 #define IPP_DFIFO_MISSING_EOP_SOP_INTR_DIS (1 << 6) 227 #define IPP_DFIFO_ECC_UNCORR_ERR_INTR_DIS (1 << 5) 228 #define IPP_PRE_FIFO_PERR_INTR_DIS (1 << 4) 229 #define IPP_PRE_FIFO_OVERRUN_INTR_DIS (1 << 3) 230 #define IPP_PRE_FIFO_UNDERRUN_INTR_DIS (1 << 2) 231 #define IPP_BAD_TCPIP_CKSUM_CNT_INTR_DIS (1 << 1) 232 #define IPP_PKT_DISCARD_CNT_INTR_DIS (1 << 0) 233 234 #define IPP_RESET_WAIT 10 235 236 /* DFIFO RD/WR pointers mask */ 237 238 #define IPP_XMAC_DFIFO_PTR_MASK 0x7FF 239 #define IPP_BMAC_DFIFO_PTR_MASK 0x3FF 240 241 #define IPP_ECC_CNT_MASK 0xFF 242 #define IPP_BAD_CS_CNT_MASK 0x3FFF 243 #define IPP_PKT_DIS_CNT_MASK 0x3FFF 244 245 #ifdef __cplusplus 246 } 247 #endif 248 249 #endif /* _SYS_NXGE_NXGE_IPP_HW_H */ 250