1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_FFLP_HW_H 27 #define _SYS_NXGE_NXGE_FFLP_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_defs.h> 34 35 36 /* FZC_FFLP Offsets */ 37 #define FFLP_ENET_VLAN_TBL_REG (FZC_FFLP + 0x00000) 38 39 /* defines for FFLP_ENET_VLAN_TBL */ 40 #define ENET_VLAN_TBL_VLANRDCTBLN0_MASK 0x0000000000000003ULL 41 #define ENET_VLAN_TBL_VLANRDCTBLN0_SHIFT 0 42 #define ENET_VLAN_TBL_VPR0_MASK 0x00000000000000008ULL 43 #define ENET_VLAN_TBL_VPR0_SHIFT 3 44 45 #define ENET_VLAN_TBL_VLANRDCTBLN1_MASK 0x0000000000000030ULL 46 #define ENET_VLAN_TBL_VLANRDCTBLN1_SHIFT 4 47 #define ENET_VLAN_TBL_VPR1_MASK 0x00000000000000080ULL 48 #define ENET_VLAN_TBL_VPR1_SHIFT 7 49 50 #define ENET_VLAN_TBL_VLANRDCTBLN2_MASK 0x0000000000000300ULL 51 #define ENET_VLAN_TBL_VLANRDCTBLN2_SHIFT 8 52 #define ENET_VLAN_TBL_VPR2_MASK 0x00000000000000800ULL 53 #define ENET_VLAN_TBL_VPR2_SHIFT 11 54 55 #define ENET_VLAN_TBL_VLANRDCTBLN3_MASK 0x0000000000003000ULL 56 #define ENET_VLAN_TBL_VLANRDCTBLN3_SHIFT 12 57 #define ENET_VLAN_TBL_VPR3_MASK 0x0000000000008000ULL 58 #define ENET_VLAN_TBL_VPR3_SHIFT 15 59 60 #define ENET_VLAN_TBL_PARITY0_MASK 0x0000000000010000ULL 61 #define ENET_VLAN_TBL_PARITY0_SHIFT 16 62 #define ENET_VLAN_TBL_PARITY1_MASK 0x0000000000020000ULL 63 #define ENET_VLAN_TBL_PARITY1_SHIFT 17 64 65 typedef union _fflp_enet_vlan_tbl_t { 66 uint64_t value; 67 struct { 68 #if defined(_BIG_ENDIAN) 69 uint32_t hdw; 70 #endif 71 struct { 72 #ifdef _BIT_FIELDS_HTOL 73 uint32_t rsrvd:14; 74 uint32_t parity1:1; 75 uint32_t parity0:1; 76 uint32_t vpr3:1; 77 uint32_t vlanrdctbln3:3; 78 uint32_t vpr2:1; 79 uint32_t vlanrdctbln2:3; 80 uint32_t vpr1:1; 81 uint32_t vlanrdctbln1:3; 82 uint32_t vpr0:1; 83 uint32_t vlanrdctbln0:3; 84 #else 85 uint32_t vlanrdctbln0:3; 86 uint32_t vpr0:1; 87 uint32_t vlanrdctbln1:3; 88 uint32_t vpr1:1; 89 uint32_t vlanrdctbln2:3; 90 uint32_t vpr2:1; 91 uint32_t vlanrdctbln3:3; 92 uint32_t vpr3:1; 93 uint32_t parity0:1; 94 uint32_t parity1:1; 95 uint32_t rsrvd:14; 96 #endif 97 } ldw; 98 #ifndef _BIG_ENDIAN 99 uint32_t hdw; 100 #endif 101 } bits; 102 } fflp_enet_vlan_tbl_t, *p_fflp_enet_vlan_tbl_t; 103 104 #define FFLP_TCAM_CLS_BASE_OFFSET (FZC_FFLP + 0x20000) 105 #define FFLP_L2_CLS_ENET1_REG (FZC_FFLP + 0x20000) 106 #define FFLP_L2_CLS_ENET2_REG (FZC_FFLP + 0x20008) 107 108 typedef union _tcam_class_prg_ether_t { 109 #define TCAM_ENET_USR_CLASS_ENABLE 0x1 110 #define TCAM_ENET_USR_CLASS_DISABLE 0x0 111 112 uint64_t value; 113 struct { 114 #ifdef _BIG_ENDIAN 115 uint32_t hdw; 116 #endif 117 struct { 118 #ifdef _BIT_FIELDS_HTOL 119 uint32_t rsrvd:15; 120 uint32_t valid:1; 121 uint32_t etype:16; 122 #else 123 uint32_t etype:16; 124 uint32_t valid:1; 125 uint32_t rsrvd:15; 126 #endif 127 } ldw; 128 #ifndef _BIG_ENDIAN 129 uint32_t hdw; 130 #endif 131 } bits; 132 } tcam_class_prg_ether_t, *p_tcam_class_prg_ether_t; 133 134 #define FFLP_L3_CLS_IP_U4_REG (FZC_FFLP + 0x20010) 135 #define FFLP_L3_CLS_IP_U5_REG (FZC_FFLP + 0x20018) 136 #define FFLP_L3_CLS_IP_U6_REG (FZC_FFLP + 0x20020) 137 #define FFLP_L3_CLS_IP_U7_REG (FZC_FFLP + 0x20028) 138 139 typedef union _tcam_class_prg_ip_t { 140 #define TCAM_IP_USR_CLASS_ENABLE 0x1 141 #define TCAM_IP_USR_CLASS_DISABLE 0x0 142 143 uint64_t value; 144 struct { 145 #if defined(_BIG_ENDIAN) 146 uint32_t hdw; 147 #endif 148 struct { 149 #ifdef _BIT_FIELDS_HTOL 150 uint32_t rsrvd:6; 151 uint32_t valid:1; 152 uint32_t ipver:1; 153 uint32_t pid:8; 154 uint32_t tosmask:8; 155 uint32_t tos:8; 156 #else 157 uint32_t tos:8; 158 uint32_t tosmask:8; 159 uint32_t pid:8; 160 uint32_t ipver:1; 161 uint32_t valid:1; 162 uint32_t rsrvd:6; 163 #endif 164 } ldw; 165 #ifndef _BIG_ENDIAN 166 uint32_t hdw; 167 #endif 168 } bits; 169 } tcam_class_prg_ip_t, *p_tcam_class_prg_ip_t; 170 171 /* 172 * New fields added to the L3 programmable class register for RF-NIU 173 * and Neptune-L. 174 */ 175 #define L3_UCLS_TOS_SH 0 176 #define L3_UCLS_TOS_MSK 0xff 177 #define L3_UCLS_TOSM_SH 8 178 #define L3_UCLS_TOSM_MSK 0xff 179 #define L3_UCLS_PID_SH 16 180 #define L3_UCLS_PID_MSK 0xff 181 #define L3_UCLS_VALID_SH 25 182 #define L3_UCLS_VALID_MSK 0x01 183 #define L3_UCLS_L4B23_SEL_SH 26 184 #define L3_UCLS_L4B23_SEL_MSK 0x01 185 #define L3_UCLS_L4B23_VAL_SH 27 186 #define L3_UCLS_L4B23_VAL_MSK 0xffff 187 #define L3_UCLS_L4B0_MASK_SH 43 188 #define L3_UCLS_L4B0_MASK_MSK 0xff 189 #define L3_UCLS_L4B0_VAL_SH 51 190 #define L3_UCLS_L4B0_VAL_MSK 0xff 191 #define L3_UCLS_L4_MODE_SH 59 192 #define L3_UCLS_L4_MODE_MSK 0x01 193 /* define the classes which use the above structure */ 194 195 typedef enum fflp_tcam_class { 196 TCAM_CLASS_INVALID = 0, 197 TCAM_CLASS_DUMMY = 1, 198 TCAM_CLASS_ETYPE_1 = 2, 199 TCAM_CLASS_ETYPE_2, 200 TCAM_CLASS_IP_USER_4, 201 TCAM_CLASS_IP_USER_5, 202 TCAM_CLASS_IP_USER_6, 203 TCAM_CLASS_IP_USER_7, 204 TCAM_CLASS_TCP_IPV4, 205 TCAM_CLASS_UDP_IPV4, 206 TCAM_CLASS_AH_ESP_IPV4, 207 TCAM_CLASS_SCTP_IPV4, 208 TCAM_CLASS_TCP_IPV6, 209 TCAM_CLASS_UDP_IPV6, 210 TCAM_CLASS_AH_ESP_IPV6, 211 TCAM_CLASS_SCTP_IPV6, 212 TCAM_CLASS_ARP, 213 TCAM_CLASS_RARP, 214 TCAM_CLASS_DUMMY_12, 215 TCAM_CLASS_DUMMY_13, 216 TCAM_CLASS_DUMMY_14, 217 TCAM_CLASS_DUMMY_15, 218 TCAM_CLASS_IPV6_FRAG = 0x1F 219 } tcam_class_t; 220 221 #define TCAM_CLASS_MAX TCAM_CLASS_IPV6_FRAG 222 223 /* 224 * Specify how to build TCAM key for L3 225 * IP Classes. Both User configured and 226 * hardwired IP services are included. 227 * These are the supported 12 classes. 228 */ 229 #define FFLP_TCAM_KEY_BASE_OFFSET (FZC_FFLP + 0x20030) 230 #define FFLP_TCAM_KEY_IP_USR4_REG (FZC_FFLP + 0x20030) 231 #define FFLP_TCAM_KEY_IP_USR5_REG (FZC_FFLP + 0x20038) 232 #define FFLP_TCAM_KEY_IP_USR6_REG (FZC_FFLP + 0x20040) 233 #define FFLP_TCAM_KEY_IP_USR7_REG (FZC_FFLP + 0x20048) 234 #define FFLP_TCAM_KEY_IP4_TCP_REG (FZC_FFLP + 0x20050) 235 #define FFLP_TCAM_KEY_IP4_UDP_REG (FZC_FFLP + 0x20058) 236 #define FFLP_TCAM_KEY_IP4_AH_ESP_REG (FZC_FFLP + 0x20060) 237 #define FFLP_TCAM_KEY_IP4_SCTP_REG (FZC_FFLP + 0x20068) 238 #define FFLP_TCAM_KEY_IP6_TCP_REG (FZC_FFLP + 0x20070) 239 #define FFLP_TCAM_KEY_IP6_UDP_REG (FZC_FFLP + 0x20078) 240 #define FFLP_TCAM_KEY_IP6_AH_ESP_REG (FZC_FFLP + 0x20080) 241 #define FFLP_TCAM_KEY_IP6_SCTP_REG (FZC_FFLP + 0x20088) 242 243 244 typedef union _tcam_class_key_ip_t { 245 uint64_t value; 246 struct { 247 #if defined(_BIG_ENDIAN) 248 uint32_t hdw; 249 #endif 250 struct { 251 #ifdef _BIT_FIELDS_HTOL 252 uint32_t rsrvd2:28; 253 uint32_t discard:1; 254 uint32_t tsel:1; 255 uint32_t rsrvd:1; 256 uint32_t ipaddr:1; 257 #else 258 uint32_t ipaddr:1; 259 uint32_t rsrvd:1; 260 uint32_t tsel:1; 261 uint32_t discard:1; 262 uint32_t rsrvd2:28; 263 #endif 264 } ldw; 265 #ifndef _BIG_ENDIAN 266 uint32_t hdw; 267 #endif 268 } bits; 269 } tcam_class_key_ip_t, *p_tcam_class_key_ip_t; 270 271 272 273 #define FFLP_TCAM_KEY_0_REG (FZC_FFLP + 0x20090) 274 #define FFLP_TCAM_KEY_1_REG (FZC_FFLP + 0x20098) 275 #define FFLP_TCAM_KEY_2_REG (FZC_FFLP + 0x200A0) 276 #define FFLP_TCAM_KEY_3_REG (FZC_FFLP + 0x200A8) 277 #define FFLP_TCAM_MASK_0_REG (FZC_FFLP + 0x200B0) 278 #define FFLP_TCAM_MASK_1_REG (FZC_FFLP + 0x200B8) 279 #define FFLP_TCAM_MASK_2_REG (FZC_FFLP + 0x200C0) 280 #define FFLP_TCAM_MASK_3_REG (FZC_FFLP + 0x200C8) 281 282 #define FFLP_TCAM_CTL_REG (FZC_FFLP + 0x200D0) 283 284 /* bit defines for FFLP_TCAM_CTL register */ 285 #define TCAM_CTL_TCAM_WR 0x0ULL 286 #define TCAM_CTL_TCAM_RD 0x040000ULL 287 #define TCAM_CTL_TCAM_CMP 0x080000ULL 288 #define TCAM_CTL_RAM_WR 0x100000ULL 289 #define TCAM_CTL_RAM_RD 0x140000ULL 290 #define TCAM_CTL_RWC_STAT 0x0020000ULL 291 #define TCAM_CTL_RWC_MATCH 0x0010000ULL 292 293 294 typedef union _tcam_ctl_t { 295 #define TCAM_CTL_RWC_TCAM_WR 0x0 296 #define TCAM_CTL_RWC_TCAM_RD 0x1 297 #define TCAM_CTL_RWC_TCAM_CMP 0x2 298 #define TCAM_CTL_RWC_RAM_WR 0x4 299 #define TCAM_CTL_RWC_RAM_RD 0x5 300 #define TCAM_CTL_RWC_RWC_STAT 0x1 301 #define TCAM_CTL_RWC_RWC_MATCH 0x1 302 303 uint64_t value; 304 struct { 305 #if defined(_BIG_ENDIAN) 306 uint32_t hdw; 307 #endif 308 struct { 309 #ifdef _BIT_FIELDS_HTOL 310 uint32_t rsrvd2:11; 311 uint32_t rwc:3; 312 uint32_t stat:1; 313 uint32_t match:1; 314 uint32_t rsrvd:6; 315 uint32_t location:10; 316 #else 317 uint32_t location:10; 318 uint32_t rsrvd:6; 319 uint32_t match:1; 320 uint32_t stat:1; 321 uint32_t rwc:3; 322 uint32_t rsrvd2:11; 323 #endif 324 } ldw; 325 #ifndef _BIG_ENDIAN 326 uint32_t hdw; 327 #endif 328 } bits; 329 } tcam_ctl_t, *p_tcam_ctl_t; 330 331 332 333 /* Bit defines for TCAM ASC RAM */ 334 335 336 typedef union _tcam_res_t { 337 uint64_t value; 338 struct { 339 #if defined(_BIG_ENDIAN) 340 struct { 341 uint32_t rsrvd:22; 342 uint32_t syndrome:10; 343 } hdw; 344 #endif 345 struct { 346 #ifdef _BIT_FIELDS_HTOL 347 uint32_t syndrome:6; 348 uint32_t zfid:12; 349 uint32_t v4_ecc_ck:1; 350 uint32_t disc:1; 351 uint32_t tres:2; 352 uint32_t rdctbl:3; 353 uint32_t offset:5; 354 uint32_t zfld:1; 355 uint32_t age:1; 356 #else 357 uint32_t age:1; 358 uint32_t zfld:1; 359 uint32_t offset:5; 360 uint32_t rdctbl:3; 361 uint32_t tres:2; 362 uint32_t disc:1; 363 uint32_t v4_ecc_ck:1; 364 uint32_t zfid:12; 365 uint32_t syndrome:6; 366 #endif 367 } ldw; 368 #ifndef _BIG_ENDIAN 369 struct { 370 uint32_t syndrome:10; 371 uint32_t rsrvd:22; 372 } hdw; 373 #endif 374 } bits; 375 } tcam_res_t, *p_tcam_res_t; 376 377 378 379 #define TCAM_ASC_DATA_AGE 0x0000000000000001ULL 380 #define TCAM_ASC_DATA_AGE_SHIFT 0x0 381 #define TCAM_ASC_DATA_ZFVLD 0x0000000000000002ULL 382 #define TCAM_ASC_DATA_ZFVLD_SHIFT 1 383 384 #define TCAM_ASC_DATA_OFFSET_MASK 0x000000000000007CULL 385 #define TCAM_ASC_DATA_OFFSET_SHIFT 2 386 387 #define TCAM_ASC_DATA_RDCTBL_MASK 0x0000000000000038ULL 388 #define TCAM_ASC_DATA_RDCTBL_SHIFT 7 389 #define TCAM_ASC_DATA_TRES_MASK 0x0000000000000C00ULL 390 #define TRES_CONT_USE_L2RDC 0x00 391 #define TRES_TERM_USE_OFFSET 0x01 392 #define TRES_CONT_OVRD_L2RDC 0x02 393 #define TRES_TERM_OVRD_L2RDC 0x03 394 395 #define TCAM_ASC_DATA_TRES_SHIFT 10 396 #define TCAM_TRES_CONT_USE_L2RDC \ 397 (0x0000000000000000ULL << TCAM_ASC_DATA_TRES_SHIFT) 398 #define TCAM_TRES_TERM_USE_OFFSET \ 399 (0x0000000000000001ULL << TCAM_ASC_DATA_TRES_SHIFT) 400 #define TCAM_TRES_CONT_OVRD_L2RDC \ 401 (0x0000000000000002ULL << TCAM_ASC_DATA_TRES_SHIFT) 402 #define TCAM_TRES_TERM_OVRD_L2RDC \ 403 (0x0000000000000003ULL << TCAM_ASC_DATA_TRES_SHIFT) 404 405 #define TCAM_ASC_DATA_DISC_MASK 0x0000000000001000ULL 406 #define TCAM_ASC_DATA_DISC_SHIFT 12 407 #define TCAM_ASC_DATA_V4_ECC_OK_MASK 0x0000000000002000ULL 408 #define TCAM_ASC_DATA_V4_ECC_OK_SHIFT 13 409 #define TCAM_ASC_DATA_V4_ECC_OK \ 410 (0x0000000000000001ULL << TCAM_ASC_DATA_V4_ECC_OK_MASK_SHIFT) 411 412 #define TCAM_ASC_DATA_ZFID_MASK 0x0000000003FF3000ULL 413 #define TCAM_ASC_DATA_ZFID_SHIFT 14 414 #define TCAM_ASC_DATA_ZFID(value) \ 415 ((value & TCAM_ASC_DATA_ZFID_MASK) >> TCAM_ASC_DATA_ZFID_SHIFT) 416 417 #define TCAM_ASC_DATA_SYNDR_MASK 0x000003FFF3000000ULL 418 #define TCAM_ASC_DATA_SYNDR_SHIFT 26 419 #define TCAM_ASC_DATA_SYNDR(value) \ 420 ((value & TCAM_ASC_DATA_SYNDR_MASK) >> TCAM_ASC_DATA_SYNDR_SHIFT) 421 422 423 /* error registers */ 424 425 #define FFLP_VLAN_PAR_ERR_REG (FZC_FFLP + 0x08000) 426 427 typedef union _vlan_par_err_t { 428 uint64_t value; 429 struct { 430 #if defined(_BIG_ENDIAN) 431 uint32_t hdw; 432 #endif 433 struct { 434 #ifdef _BIT_FIELDS_HTOL 435 uint32_t err:1; 436 uint32_t m_err:1; 437 uint32_t addr:12; 438 uint32_t data:18; 439 #else 440 uint32_t data:18; 441 uint32_t addr:12; 442 uint32_t m_err:1; 443 uint32_t err:1; 444 #endif 445 } ldw; 446 #ifndef _BIG_ENDIAN 447 uint32_t hdw; 448 #endif 449 } bits; 450 } vlan_par_err_t, *p_vlan_par_err_t; 451 452 453 #define FFLP_TCAM_ERR_REG (FZC_FFLP + 0x200D8) 454 455 typedef union _tcam_err_t { 456 uint64_t value; 457 struct { 458 #if defined(_BIG_ENDIAN) 459 uint32_t hdw; 460 #endif 461 struct { 462 #ifdef _BIT_FIELDS_HTOL 463 uint32_t err:1; 464 uint32_t p_ecc:1; 465 uint32_t mult:1; 466 uint32_t rsrvd:5; 467 uint32_t addr:8; 468 uint32_t syndrome:16; 469 #else 470 uint32_t syndrome:16; 471 uint32_t addr:8; 472 uint32_t rsrvd:5; 473 uint32_t mult:1; 474 uint32_t p_ecc:1; 475 uint32_t err:1; 476 #endif 477 } ldw; 478 #ifndef _BIG_ENDIAN 479 uint32_t hdw; 480 #endif 481 } bits; 482 } tcam_err_t, *p_tcam_err_t; 483 484 485 #define TCAM_ERR_SYNDROME_MASK 0x000000000000FFFFULL 486 #define TCAM_ERR_MULT_SHIFT 29 487 #define TCAM_ERR_MULT 0x0000000020000000ULL 488 #define TCAM_ERR_P_ECC 0x0000000040000000ULL 489 #define TCAM_ERR_ERR 0x0000000080000000ULL 490 491 #define HASH_LKUP_ERR_LOG1_REG (FZC_FFLP + 0x200E0) 492 #define HASH_LKUP_ERR_LOG2_REG (FZC_FFLP + 0x200E8) 493 494 495 496 typedef union _hash_lookup_err_log1_t { 497 uint64_t value; 498 struct { 499 #if defined(_BIG_ENDIAN) 500 uint32_t hdw; 501 #endif 502 struct { 503 #ifdef _BIT_FIELDS_HTOL 504 uint32_t rsrvd:28; 505 uint32_t ecc_err:1; 506 uint32_t mult_lk:1; 507 uint32_t cu:1; 508 uint32_t mult_bit:1; 509 #else 510 uint32_t mult_bit:1; 511 uint32_t cu:1; 512 uint32_t mult_lk:1; 513 uint32_t ecc_err:1; 514 uint32_t rsrvd:28; 515 #endif 516 } ldw; 517 #ifndef _BIG_ENDIAN 518 uint32_t hdw; 519 #endif 520 } bits; 521 } hash_lookup_err_log1_t, *p_hash_lookup_err_log1_t; 522 523 524 525 typedef union _hash_lookup_err_log2_t { 526 uint64_t value; 527 struct { 528 #if defined(_BIG_ENDIAN) 529 uint32_t hdw; 530 #endif 531 struct { 532 #ifdef _BIT_FIELDS_HTOL 533 uint32_t rsrvd:1; 534 uint32_t h1:20; 535 uint32_t subarea:3; 536 uint32_t syndrome:8; 537 #else 538 uint32_t syndrome:8; 539 uint32_t subarea:3; 540 uint32_t h1:20; 541 uint32_t rsrvd:1; 542 #endif 543 } ldw; 544 #ifndef _BIG_ENDIAN 545 uint32_t hdw; 546 #endif 547 } bits; 548 } hash_lookup_err_log2_t, *p_hash_lookup_err_log2_t; 549 550 551 552 #define FFLP_FCRAM_ERR_TST0_REG (FZC_FFLP + 0x20128) 553 554 typedef union _fcram_err_tst0_t { 555 uint64_t value; 556 struct { 557 #if defined(_BIG_ENDIAN) 558 uint32_t hdw; 559 #endif 560 struct { 561 #ifdef _BIT_FIELDS_HTOL 562 uint32_t rsrvd:24; 563 uint32_t syndrome_mask:8; 564 #else 565 uint32_t syndrome_mask:10; 566 uint32_t rsrvd:24; 567 #endif 568 } ldw; 569 #ifndef _BIG_ENDIAN 570 uint32_t hdw; 571 #endif 572 } bits; 573 } fcram_err_tst0_t, *p_fcram_err_tst0_t; 574 575 576 #define FFLP_FCRAM_ERR_TST1_REG (FZC_FFLP + 0x20130) 577 #define FFLP_FCRAM_ERR_TST2_REG (FZC_FFLP + 0x20138) 578 579 typedef union _fcram_err_tst_t { 580 uint64_t value; 581 struct { 582 #if defined(_BIG_ENDIAN) 583 struct { 584 uint32_t dat; 585 } hdw; 586 #endif 587 struct { 588 uint32_t dat; 589 } ldw; 590 #ifndef _BIG_ENDIAN 591 struct { 592 uint32_t dat; 593 } hdw; 594 #endif 595 } bits; 596 } fcram_err_tst1_t, *p_fcram_err_tst1_t, 597 fcram_err_tst2_t, *p_fcram_err_tst2_t, 598 fcram_err_data_t, *p_fcram_err_data_t; 599 600 601 602 #define FFLP_ERR_MSK_REG (FZC_FFLP + 0x20140) 603 604 typedef union _fflp_err_mask_t { 605 uint64_t value; 606 struct { 607 #if defined(_BIG_ENDIAN) 608 uint32_t hdw; 609 #endif 610 struct { 611 #ifdef _BIT_FIELDS_HTOL 612 uint32_t rsrvd:21; 613 uint32_t hash_tbl_dat:8; 614 uint32_t hash_tbl_lkup:1; 615 uint32_t tcam:1; 616 uint32_t vlan:1; 617 #else 618 uint32_t vlan:1; 619 uint32_t tcam:1; 620 uint32_t hash_tbl_lkup:1; 621 uint32_t hash_tbl_dat:8; 622 uint32_t rsrvd:21; 623 #endif 624 } ldw; 625 #ifndef _BIG_ENDIAN 626 uint32_t hdw; 627 #endif 628 } bits; 629 } fflp_err_mask_t, *p_fflp_err_mask_t; 630 631 #define FFLP_ERR_VLAN_MASK 0x00000001ULL 632 #define FFLP_ERR_VLAN 0x00000001ULL 633 #define FFLP_ERR_VLAN_SHIFT 0x0 634 635 #define FFLP_ERR_TCAM_MASK 0x00000002ULL 636 #define FFLP_ERR_TCAM 0x00000001ULL 637 #define FFLP_ERR_TCAM_SHIFT 0x1 638 639 #define FFLP_ERR_HASH_TBL_LKUP_MASK 0x00000004ULL 640 #define FFLP_ERR_HASH_TBL_LKUP 0x00000001ULL 641 #define FFLP_ERR_HASH_TBL_LKUP_SHIFT 0x2 642 643 #define FFLP_ERR_HASH_TBL_DAT_MASK 0x00000007F8ULL 644 #define FFLP_ERR_HASH_TBL_DAT 0x0000000FFULL 645 #define FFLP_ERR_HASH_TBL_DAT_SHIFT 0x3 646 647 #define FFLP_ERR_MASK_ALL (FFLP_ERR_VLAN_MASK | FFLP_ERR_TCAM_MASK | \ 648 FFLP_ERR_HASH_TBL_LKUP_MASK | \ 649 FFLP_ERR_HASH_TBL_DAT_MASK) 650 651 652 #define FFLP_CFG_1_REG (FZC_FFLP + 0x20100) 653 654 typedef union _fflp_cfg_1_t { 655 uint64_t value; 656 struct { 657 #if defined(_BIG_ENDIAN) 658 uint32_t hdw; 659 #endif 660 struct { 661 #ifdef _BIT_FIELDS_HTOL 662 uint32_t rsrvd:5; 663 uint32_t tcam_disable:1; 664 uint32_t pio_dbg_sel:3; 665 uint32_t pio_fio_rst:1; 666 uint32_t pio_fio_lat:2; 667 uint32_t camlatency:4; 668 uint32_t camratio:4; 669 uint32_t fcramratio:4; 670 uint32_t fcramoutdr:4; 671 uint32_t fcramqs:1; 672 uint32_t errordis:1; 673 uint32_t fflpinitdone:1; 674 uint32_t llcsnap:1; 675 #else 676 uint32_t llcsnap:1; 677 uint32_t fflpinitdone:1; 678 uint32_t errordis:1; 679 uint32_t fcramqs:1; 680 uint32_t fcramoutdr:4; 681 uint32_t fcramratio:4; 682 uint32_t camratio:4; 683 uint32_t camlatency:4; 684 uint32_t pio_fio_lat:2; 685 uint32_t pio_fio_rst:1; 686 uint32_t pio_dbg_sel:3; 687 uint32_t tcam_disable:1; 688 uint32_t rsrvd:5; 689 #endif 690 } ldw; 691 #ifndef _BIG_ENDIAN 692 uint32_t hdw; 693 #endif 694 } bits; 695 } fflp_cfg_1_t, *p_fflp_cfg_1_t; 696 697 698 typedef enum fflp_fcram_output_drive { 699 FCRAM_OUTDR_NORMAL = 0x0, 700 FCRAM_OUTDR_STRONG = 0x5, 701 FCRAM_OUTDR_WEAK = 0xa 702 } fflp_fcram_output_drive_t; 703 704 705 typedef enum fflp_fcram_qs { 706 FCRAM_QS_MODE_QS = 0x0, 707 FCRAM_QS_MODE_FREE = 0x1 708 } fflp_fcram_qs_t; 709 710 #define FCRAM_PIO_HIGH_PRI 0xf 711 #define FCRAM_PIO_MED_PRI 0xa 712 #define FCRAM_LOOKUP_HIGH_PRI 0x0 713 #define FCRAM_LOOKUP_HIGH_PRI 0x0 714 #define FCRAM_IO_DEFAULT_PRI FCRAM_PIO_MED_PRI 715 716 #define TCAM_PIO_HIGH_PRI 0xf 717 #define TCAM_PIO_MED_PRI 0xa 718 #define TCAM_LOOKUP_HIGH_PRI 0x0 719 #define TCAM_LOOKUP_HIGH_PRI 0x0 720 #define TCAM_IO_DEFAULT_PRI TCAM_PIO_MED_PRI 721 722 #define TCAM_DEFAULT_LATENCY 0x4 723 724 725 #define FFLP_DBG_TRAIN_VCT_REG (FZC_FFLP + 0x20148) 726 727 typedef union _fflp_dbg_train_vct_t { 728 uint64_t value; 729 struct { 730 #if defined(_BIG_ENDIAN) 731 uint32_t hdw; 732 #endif 733 struct { 734 #ifdef _BIT_FIELDS_HTOL 735 uint32_t vector; 736 #else 737 uint32_t vector; 738 #endif 739 } ldw; 740 #ifndef _BIG_ENDIAN 741 uint32_t hdw; 742 #endif 743 } bits; 744 } fflp_dbg_train_vct_t, *p_fflp_dbg_train_vct_t; 745 746 747 748 #define FFLP_TCP_CFLAG_MSK_REG (FZC_FFLP + 0x20108) 749 750 typedef union _tcp_cflag_mask_t { 751 uint64_t value; 752 struct { 753 #if defined(_BIG_ENDIAN) 754 uint32_t hdw; 755 #endif 756 struct { 757 #ifdef _BIT_FIELDS_HTOL 758 uint32_t rsrvd:20; 759 uint32_t mask:12; 760 #else 761 uint32_t mask:12; 762 uint32_t rsrvd:20; 763 #endif 764 } ldw; 765 #ifndef _BIG_ENDIAN 766 uint32_t hdw; 767 #endif 768 } bits; 769 } tcp_cflag_mask_t, *p_tcp_cflag_mask_t; 770 771 772 773 #define FFLP_FCRAM_REF_TMR_REG (FZC_FFLP + 0x20110) 774 775 776 typedef union _fcram_ref_tmr_t { 777 #define FCRAM_REFRESH_DEFAULT_MAX_TIME 0x200 778 #define FCRAM_REFRESH_DEFAULT_MIN_TIME 0x200 779 #define FCRAM_REFRESH_DEFAULT_SYS_TIME 0x200 780 #define FCRAM_REFRESH_MAX_TICK 39 /* usecs */ 781 #define FCRAM_REFRESH_MIN_TICK 400 /* nsecs */ 782 783 uint64_t value; 784 struct { 785 #if defined(_BIG_ENDIAN) 786 uint32_t hdw; 787 #endif 788 struct { 789 #ifdef _BIT_FIELDS_HTOL 790 uint32_t max:16; 791 uint32_t min:16; 792 #else 793 uint32_t min:16; 794 uint32_t max:16; 795 #endif 796 } ldw; 797 #ifndef _BIG_ENDIAN 798 uint32_t hdw; 799 #endif 800 } bits; 801 } fcram_ref_tmr_t, *p_fcram_ref_tmr_t; 802 803 804 805 806 #define FFLP_FCRAM_FIO_ADDR_REG (FZC_FFLP + 0x20118) 807 808 typedef union _fcram_fio_addr_t { 809 uint64_t value; 810 struct { 811 #if defined(_BIG_ENDIAN) 812 uint32_t hdw; 813 #endif 814 struct { 815 #ifdef _BIT_FIELDS_HTOL 816 uint32_t rsrvd:22; 817 uint32_t addr:10; 818 #else 819 uint32_t addr:10; 820 uint32_t rsrvd:22; 821 #endif 822 } ldw; 823 #ifndef _BIG_ENDIAN 824 uint32_t hdw; 825 #endif 826 } bits; 827 } fcram_fio_addr_t, *p_fcram_fio_addr_t; 828 829 830 #define FFLP_FCRAM_FIO_DAT_REG (FZC_FFLP + 0x20120) 831 832 typedef union _fcram_fio_dat_t { 833 uint64_t value; 834 struct { 835 #if defined(_BIG_ENDIAN) 836 uint32_t hdw; 837 #endif 838 struct { 839 #ifdef _BIT_FIELDS_HTOL 840 uint32_t rsrvd:22; 841 uint32_t addr:10; 842 #else 843 uint32_t addr:10; 844 uint32_t rsrvd:22; 845 #endif 846 } ldw; 847 #ifndef _BIG_ENDIAN 848 uint32_t hdw; 849 #endif 850 } bits; 851 } fcram_fio_dat_t, *p_fcram_fio_dat_t; 852 853 854 #define FFLP_FCRAM_PHY_RD_LAT_REG (FZC_FFLP + 0x20150) 855 856 typedef union _fcram_phy_rd_lat_t { 857 uint64_t value; 858 struct { 859 #if defined(_BIG_ENDIAN) 860 uint32_t hdw; 861 #endif 862 struct { 863 #ifdef _BIT_FIELDS_HTOL 864 uint32_t rsrvd:24; 865 uint32_t lat:8; 866 #else 867 uint32_t lat:8; 868 uint32_t rsrvd:24; 869 #endif 870 } ldw; 871 #ifndef _BIG_ENDIAN 872 uint32_t hdw; 873 #endif 874 } bits; 875 } fcram_phy_rd_lat_t, *p_fcram_phy_rd_lat_t; 876 877 878 /* 879 * Specify how to build a flow key for IP 880 * classes, both programmable and hardwired 881 */ 882 #define FFLP_FLOW_KEY_BASE_OFFSET (FZC_FFLP + 0x40000) 883 #define FFLP_FLOW_KEY_IP_USR4_REG (FZC_FFLP + 0x40000) 884 #define FFLP_FLOW_KEY_IP_USR5_REG (FZC_FFLP + 0x40008) 885 #define FFLP_FLOW_KEY_IP_USR6_REG (FZC_FFLP + 0x40010) 886 #define FFLP_FLOW_KEY_IP_USR7_REG (FZC_FFLP + 0x40018) 887 #define FFLP_FLOW_KEY_IP4_TCP_REG (FZC_FFLP + 0x40020) 888 #define FFLP_FLOW_KEY_IP4_UDP_REG (FZC_FFLP + 0x40028) 889 #define FFLP_FLOW_KEY_IP4_AH_ESP_REG (FZC_FFLP + 0x40030) 890 #define FFLP_FLOW_KEY_IP4_SCTP_REG (FZC_FFLP + 0x40038) 891 #define FFLP_FLOW_KEY_IP6_TCP_REG (FZC_FFLP + 0x40040) 892 #define FFLP_FLOW_KEY_IP6_UDP_REG (FZC_FFLP + 0x40048) 893 #define FFLP_FLOW_KEY_IP6_AH_ESP_REG (FZC_FFLP + 0x40050) 894 #define FFLP_FLOW_KEY_IP6_SCTP_REG (FZC_FFLP + 0x40058) 895 /* 896 * New FLOW KEY register added for IPV6 Fragments for RF-NIU 897 * and Neptune-L. 898 */ 899 #define FFLP_FLOW_KEY_IP6_FRAG_REG (FZC_FFLP + 0x400B0) 900 901 #define FL_KEY_USR_L4XOR_MSK 0x03ff 902 903 typedef union _flow_class_key_ip_t { 904 uint64_t value; 905 struct { 906 #if defined(_BIG_ENDIAN) 907 uint32_t hdw; 908 #endif 909 struct { 910 #ifdef _BIT_FIELDS_HTOL 911 uint32_t rsrvd2:10; 912 /* These bits added for L3 programmable classes in RF-NIU and Neptune-L */ 913 uint32_t l4_xor:10; 914 uint32_t l4_mode:1; 915 /* This bit added for SNORT support in RF-NIU and Neptune-L */ 916 uint32_t sym:1; 917 uint32_t port:1; 918 uint32_t l2da:1; 919 uint32_t vlan:1; 920 uint32_t ipsa:1; 921 uint32_t ipda:1; 922 uint32_t proto:1; 923 uint32_t l4_0:2; 924 uint32_t l4_1:2; 925 #else 926 uint32_t l4_1:2; 927 uint32_t l4_0:2; 928 uint32_t proto:1; 929 uint32_t ipda:1; 930 uint32_t ipsa:1; 931 uint32_t vlan:1; 932 uint32_t l2da:1; 933 uint32_t port:1; 934 uint32_t sym:1; 935 uint32_t l4_mode:1; 936 uint32_t l4_xor:10; 937 uint32_t rsrvd2:10; 938 #endif 939 } ldw; 940 #ifndef _BIG_ENDIAN 941 uint32_t hdw; 942 #endif 943 } bits; 944 } flow_class_key_ip_t, *p_flow_class_key_ip_t; 945 946 #define FFLP_H1POLY_REG (FZC_FFLP + 0x40060) 947 948 949 typedef union _hash_h1poly_t { 950 uint64_t value; 951 struct { 952 #if defined(_BIG_ENDIAN) 953 uint32_t hdw; 954 #endif 955 struct { 956 uint32_t init_value; 957 } ldw; 958 #ifndef _BIG_ENDIAN 959 uint32_t hdw; 960 #endif 961 } bits; 962 } hash_h1poly_t, *p_hash_h1poly_t; 963 964 #define FFLP_H2POLY_REG (FZC_FFLP + 0x40068) 965 966 typedef union _hash_h2poly_t { 967 uint64_t value; 968 struct { 969 #if defined(_BIG_ENDIAN) 970 uint32_t hdw; 971 #endif 972 struct { 973 #ifdef _BIT_FIELDS_HTOL 974 uint32_t rsrvd:16; 975 uint32_t init_value:16; 976 #else 977 uint32_t init_value:16; 978 uint32_t rsrvd:16; 979 #endif 980 } ldw; 981 #ifndef _BIG_ENDIAN 982 uint32_t hdw; 983 #endif 984 } bits; 985 } hash_h2poly_t, *p_hash_h2poly_t; 986 987 #define FFLP_FLW_PRT_SEL_REG (FZC_FFLP + 0x40070) 988 989 990 typedef union _flow_prt_sel_t { 991 #define FFLP_FCRAM_MAX_PARTITION 8 992 uint64_t value; 993 struct { 994 #if defined(_BIG_ENDIAN) 995 uint32_t hdw; 996 #endif 997 struct { 998 #ifdef _BIT_FIELDS_HTOL 999 uint32_t rsrvd3:15; 1000 uint32_t ext:1; 1001 uint32_t rsrvd2:3; 1002 uint32_t mask:5; 1003 uint32_t rsrvd:3; 1004 uint32_t base:5; 1005 #else 1006 uint32_t base:5; 1007 uint32_t rsrvd:3; 1008 uint32_t mask:5; 1009 uint32_t rsrvd2:3; 1010 uint32_t ext:1; 1011 uint32_t rsrvd3:15; 1012 #endif 1013 } ldw; 1014 #ifndef _BIG_ENDIAN 1015 uint32_t hdw; 1016 #endif 1017 } bits; 1018 } flow_prt_sel_t, *p_flow_prt_sel_t; 1019 1020 1021 1022 /* FFLP Offsets */ 1023 1024 1025 #define FFLP_HASH_TBL_ADDR_REG (FFLP + 0x00000) 1026 1027 typedef union _hash_tbl_addr_t { 1028 uint64_t value; 1029 struct { 1030 #if defined(_BIG_ENDIAN) 1031 uint32_t hdw; 1032 #endif 1033 struct { 1034 #ifdef _BIT_FIELDS_HTOL 1035 uint32_t rsrvd:8; 1036 uint32_t autoinc:1; 1037 uint32_t addr:23; 1038 #else 1039 uint32_t addr:23; 1040 uint32_t autoinc:1; 1041 uint32_t rsrvd:8; 1042 #endif 1043 } ldw; 1044 #ifndef _BIG_ENDIAN 1045 uint32_t hdw; 1046 #endif 1047 } bits; 1048 } hash_tbl_addr_t, *p_hash_tbl_addr_t; 1049 1050 1051 #define FFLP_HASH_TBL_DATA_REG (FFLP + 0x00008) 1052 1053 typedef union _hash_tbl_data_t { 1054 uint64_t value; 1055 struct { 1056 #ifdef _BIG_ENDIAN 1057 uint32_t hdw; 1058 uint32_t ldw; 1059 #else 1060 uint32_t ldw; 1061 uint32_t hdw; 1062 #endif 1063 } bits; 1064 } hash_tbl_data_t, *p_hash_tbl_data_t; 1065 1066 1067 #define FFLP_HASH_TBL_DATA_LOG_REG (FFLP + 0x00010) 1068 1069 1070 typedef union _hash_tbl_data_log_t { 1071 uint64_t value; 1072 struct { 1073 #if defined(_BIG_ENDIAN) 1074 uint32_t hdw; 1075 #endif 1076 struct { 1077 #ifdef _BIT_FIELDS_HTOL 1078 uint32_t pio_err:1; 1079 uint32_t fcram_addr:23; 1080 uint32_t syndrome:8; 1081 #else 1082 uint32_t syndrome:8; 1083 uint32_t fcram_addr:23; 1084 uint32_t pio_err:1; 1085 #endif 1086 } ldw; 1087 #ifndef _BIG_ENDIAN 1088 uint32_t hdw; 1089 #endif 1090 } bits; 1091 } hash_tbl_data_log_t, *p_hash_tbl_data_log_t; 1092 1093 1094 1095 #define REG_PIO_WRITE64(handle, offset, value) \ 1096 NXGE_REG_WR64((handle), (offset), (value)) 1097 #define REG_PIO_READ64(handle, offset, val_p) \ 1098 NXGE_REG_RD64((handle), (offset), (val_p)) 1099 1100 1101 #define WRITE_TCAM_REG_CTL(handle, ctl) \ 1102 REG_PIO_WRITE64(handle, FFLP_TCAM_CTL_REG, ctl) 1103 1104 #define READ_TCAM_REG_CTL(handle, val_p) \ 1105 REG_PIO_READ64(handle, FFLP_TCAM_CTL_REG, val_p) 1106 1107 1108 #define WRITE_TCAM_REG_KEY0(handle, key) \ 1109 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_0_REG, key) 1110 #define WRITE_TCAM_REG_KEY1(handle, key) \ 1111 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_1_REG, key) 1112 #define WRITE_TCAM_REG_KEY2(handle, key) \ 1113 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_2_REG, key) 1114 #define WRITE_TCAM_REG_KEY3(handle, key) \ 1115 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_3_REG, key) 1116 #define WRITE_TCAM_REG_MASK0(handle, mask) \ 1117 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_0_REG, mask) 1118 #define WRITE_TCAM_REG_MASK1(handle, mask) \ 1119 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_1_REG, mask) 1120 #define WRITE_TCAM_REG_MASK2(handle, mask) \ 1121 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_2_REG, mask) 1122 #define WRITE_TCAM_REG_MASK3(handle, mask) \ 1123 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_3_REG, mask) 1124 1125 #define READ_TCAM_REG_KEY0(handle, val_p) \ 1126 REG_PIO_READ64(handle, FFLP_TCAM_KEY_0_REG, val_p) 1127 #define READ_TCAM_REG_KEY1(handle, val_p) \ 1128 REG_PIO_READ64(handle, FFLP_TCAM_KEY_1_REG, val_p) 1129 #define READ_TCAM_REG_KEY2(handle, val_p) \ 1130 REG_PIO_READ64(handle, FFLP_TCAM_KEY_2_REG, val_p) 1131 #define READ_TCAM_REG_KEY3(handle, val_p) \ 1132 REG_PIO_READ64(handle, FFLP_TCAM_KEY_3_REG, val_p) 1133 #define READ_TCAM_REG_MASK0(handle, val_p) \ 1134 REG_PIO_READ64(handle, FFLP_TCAM_MASK_0_REG, val_p) 1135 #define READ_TCAM_REG_MASK1(handle, val_p) \ 1136 REG_PIO_READ64(handle, FFLP_TCAM_MASK_1_REG, val_p) 1137 #define READ_TCAM_REG_MASK2(handle, val_p) \ 1138 REG_PIO_READ64(handle, FFLP_TCAM_MASK_2_REG, val_p) 1139 #define READ_TCAM_REG_MASK3(handle, val_p) \ 1140 REG_PIO_READ64(handle, FFLP_TCAM_MASK_3_REG, val_p) 1141 1142 1143 1144 1145 typedef struct tcam_ipv4 { 1146 #if defined(_BIG_ENDIAN) 1147 uint32_t reserved6; /* 255 : 224 */ 1148 uint32_t reserved5 : 24; /* 223 : 200 */ 1149 uint32_t cls_code : 5; /* 199 : 195 */ 1150 uint32_t reserved4 : 3; /* 194 : 192 */ 1151 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1152 uint32_t noport : 1; /* 186 */ 1153 uint32_t reserved3 : 26; /* 185: 160 */ 1154 uint32_t reserved2; /* 159: 128 */ 1155 uint32_t reserved : 16; /* 127 : 112 */ 1156 uint32_t tos : 8; /* 111 : 104 */ 1157 uint32_t proto : 8; /* 103 : 96 */ 1158 uint32_t l4_port_spi; /* 95 : 64 */ 1159 uint32_t ip_src; /* 63 : 32 */ 1160 uint32_t ip_dest; /* 31 : 0 */ 1161 #else 1162 uint32_t ip_dest; /* 31 : 0 */ 1163 uint32_t ip_src; /* 63 : 32 */ 1164 uint32_t l4_port_spi; /* 95 : 64 */ 1165 uint32_t proto : 8; /* 103 : 96 */ 1166 uint32_t tos : 8; /* 111 : 104 */ 1167 uint32_t reserved : 16; /* 127 : 112 */ 1168 uint32_t reserved2; /* 159: 128 */ 1169 uint32_t reserved3 : 26; /* 185: 160 */ 1170 uint32_t noport : 1; /* 186 */ 1171 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1172 uint32_t reserved4 : 3; /* 194 : 192 */ 1173 uint32_t cls_code : 5; /* 199 : 195 */ 1174 uint32_t reserved5 : 24; /* 223 : 200 */ 1175 uint32_t reserved6; /* 255 : 224 */ 1176 #endif 1177 } tcam_ipv4_t; 1178 1179 1180 1181 typedef struct tcam_reg { 1182 #if defined(_BIG_ENDIAN) 1183 uint64_t reg0; 1184 uint64_t reg1; 1185 uint64_t reg2; 1186 uint64_t reg3; 1187 #else 1188 uint64_t reg3; 1189 uint64_t reg2; 1190 uint64_t reg1; 1191 uint64_t reg0; 1192 #endif 1193 } tcam_reg_t; 1194 1195 1196 typedef struct tcam_ether { 1197 #if defined(_BIG_ENDIAN) 1198 uint8_t reserved3[7]; /* 255 : 200 */ 1199 uint8_t cls_code : 5; /* 199 : 195 */ 1200 uint8_t reserved2 : 3; /* 194 : 192 */ 1201 uint8_t ethframe[11]; /* 191 : 104 */ 1202 uint8_t reserved[13]; /* 103 : 0 */ 1203 #else 1204 uint8_t reserved[13]; /* 103 : 0 */ 1205 uint8_t ethframe[11]; /* 191 : 104 */ 1206 uint8_t reserved2 : 3; /* 194 : 192 */ 1207 uint8_t cls_code : 5; /* 199 : 195 */ 1208 uint8_t reserved3[7]; /* 255 : 200 */ 1209 #endif 1210 } tcam_ether_t; 1211 1212 1213 typedef struct tcam_ipv6 { 1214 #if defined(_BIG_ENDIAN) 1215 uint32_t reserved4; /* 255 : 224 */ 1216 uint32_t reserved3 : 24; /* 223 : 200 */ 1217 uint32_t cls_code : 5; /* 199 : 195 */ 1218 uint32_t reserved2 : 3; /* 194 : 192 */ 1219 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1220 uint32_t noport : 1; /* 186 */ 1221 uint32_t reserved : 10; /* 185 : 176 */ 1222 uint32_t tos : 8; /* 175 : 168 */ 1223 uint32_t nxt_hdr : 8; /* 167 : 160 */ 1224 uint32_t l4_port_spi; /* 159 : 128 */ 1225 uint32_t ip_addr[4]; /* 127 : 0 */ 1226 #else 1227 uint32_t ip_addr[4]; /* 127 : 0 */ 1228 uint32_t l4_port_spi; /* 159 : 128 */ 1229 uint32_t nxt_hdr : 8; /* 167 : 160 */ 1230 uint32_t tos : 8; /* 175 : 168 */ 1231 uint32_t reserved : 10; /* 185 : 176 */ 1232 uint32_t noport : 1; /* 186 */ 1233 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1234 uint32_t reserved2 : 3; /* 194 : 192 */ 1235 uint32_t cls_code : 5; /* 199 : 195 */ 1236 uint32_t reserved3 : 24; /* 223 : 200 */ 1237 uint32_t reserved4; /* 255 : 224 */ 1238 #endif 1239 } tcam_ipv6_t; 1240 1241 1242 typedef struct tcam_entry { 1243 union _tcam_entry { 1244 tcam_reg_t regs_e; 1245 tcam_ether_t ether_e; 1246 tcam_ipv4_t ipv4_e; 1247 tcam_ipv6_t ipv6_e; 1248 } key, mask; 1249 tcam_res_t match_action; 1250 } tcam_entry_t; 1251 1252 1253 #define key_reg0 key.regs_e.reg0 1254 #define key_reg1 key.regs_e.reg1 1255 #define key_reg2 key.regs_e.reg2 1256 #define key_reg3 key.regs_e.reg3 1257 #define mask_reg0 mask.regs_e.reg0 1258 #define mask_reg1 mask.regs_e.reg1 1259 #define mask_reg2 mask.regs_e.reg2 1260 #define mask_reg3 mask.regs_e.reg3 1261 1262 1263 #define key0 key.regs_e.reg0 1264 #define key1 key.regs_e.reg1 1265 #define key2 key.regs_e.reg2 1266 #define key3 key.regs_e.reg3 1267 #define mask0 mask.regs_e.reg0 1268 #define mask1 mask.regs_e.reg1 1269 #define mask2 mask.regs_e.reg2 1270 #define mask3 mask.regs_e.reg3 1271 1272 1273 #define ip4_src_key key.ipv4_e.ip_src 1274 #define ip4_dest_key key.ipv4_e.ip_dest 1275 #define ip4_proto_key key.ipv4_e.proto 1276 #define ip4_port_key key.ipv4_e.l4_port_spi 1277 #define ip4_tos_key key.ipv4_e.tos 1278 #define ip4_noport_key key.ipv4_e.noport 1279 #define ip4_nrdc_key key.ipv4_e.l2rdc_tbl_num 1280 #define ip4_class_key key.ipv4_e.cls_code 1281 1282 #define ip4_src_mask mask.ipv4_e.ip_src 1283 #define ip4_dest_mask mask.ipv4_e.ip_dest 1284 #define ip4_proto_mask mask.ipv4_e.proto 1285 #define ip4_port_mask mask.ipv4_e.l4_port_spi 1286 #define ip4_tos_mask mask.ipv4_e.tos 1287 #define ip4_nrdc_mask mask.ipv4_e.l2rdc_tbl_num 1288 #define ip4_noport_mask mask.ipv4_e.noport 1289 #define ip4_class_mask mask.ipv4_e.cls_code 1290 1291 1292 #define ip6_ip_addr_key key.ipv6_e.ip_addr 1293 #define ip6_port_key key.ipv6_e.l4_port_spi 1294 #define ip6_nxt_hdr_key key.ipv6_e.nxt_hdr 1295 #define ip6_tos_key key.ipv6_e.tos 1296 #define ip6_nrdc_key key.ipv6_e.l2rdc_tbl_num 1297 #define ip6_noport_key key.ipv6_e.noport 1298 #define ip6_class_key key.ipv6_e.cls_code 1299 1300 1301 #define ip6_ip_addr_mask mask.ipv6_e.ip_addr 1302 #define ip6_port_mask mask.ipv6_e.l4_port_spi 1303 #define ip6_nxt_hdr_mask mask.ipv6_e.nxt_hdr 1304 #define ip6_tos_mask mask.ipv6_e.tos 1305 #define ip6_nrdc_mask mask.ipv6_e.l2rdc_tbl_num 1306 #define ip6_noport_mask mask.ipv6_e.noport 1307 #define ip6_class_mask mask.ipv6_e.cls_code 1308 1309 #define ether_class_key key.ether_e.cls_code 1310 #define ether_ethframe_key key.ether_e.ethframe 1311 #define ether_class_mask mask.ether_e.cls_code 1312 #define ether_ethframe_mask mask.ether_e.ethframe 1313 1314 1315 /* 1316 * flow template structure 1317 * The flow header is passed through the hash function 1318 * which generates the H1 (and the H2 ) hash value. 1319 * Hash computation is started at the 22 zeros. 1320 * 1321 * Since this structure uses the ip address fields, 1322 * /usr/include/netinet/in.h has to be included 1323 * before this header file. 1324 * Need to move these includes to impl files ... 1325 */ 1326 1327 #include <netinet/in.h> 1328 1329 typedef union flow_template { 1330 1331 struct { 1332 #if defined(_BIG_ENDIAN) 1333 uint32_t l4_0:16; /* src port */ 1334 uint32_t l4_1:16; /* dest Port */ 1335 1336 uint32_t pid:8; 1337 uint32_t port:2; 1338 uint32_t zeros:22; /* 0 */ 1339 1340 union { 1341 struct { 1342 struct in6_addr daddr; 1343 struct in6_addr saddr; 1344 } ip6_addr; 1345 1346 struct { 1347 uint32_t rsrvd1; 1348 struct in_addr daddr; 1349 uint32_t rsrvd2[3]; 1350 struct in_addr saddr; 1351 uint32_t rsrvd5[2]; 1352 } ip4_addr; 1353 } ipaddr; 1354 1355 union { 1356 uint64_t l2_info; 1357 struct { 1358 uint32_t vlan_valid : 4; 1359 uint32_t l2da_1 : 28; 1360 uint32_t l2da_0 : 20; 1361 uint32_t vlanid : 12; 1362 1363 }l2_bits; 1364 }l2; 1365 #else 1366 1367 uint32_t l4_1:16; /* dest Port */ 1368 uint32_t l4_0:16; /* src port */ 1369 1370 uint32_t zeros:22; /* 0 */ 1371 uint32_t port:2; 1372 uint32_t pid:8; 1373 1374 union { 1375 struct { 1376 struct in6_addr daddr; 1377 struct in6_addr saddr; 1378 } ip6_addr; 1379 1380 struct { 1381 uint32_t rsrvd1; 1382 struct in_addr daddr; 1383 uint32_t rsrvd2[3]; 1384 struct in_addr saddr; 1385 uint32_t rsrvd5[2]; 1386 } ip4_addr; 1387 } ipaddr; 1388 1389 union { 1390 uint64_t l2_info; 1391 struct { 1392 1393 uint32_t l2da_1 : 28; 1394 uint32_t vlan_valid : 4; 1395 1396 uint32_t vlanid : 12; 1397 uint32_t l2da_0 : 20; 1398 }l2_bits; 1399 }l2; 1400 #endif 1401 } bits; 1402 1403 } flow_template_t; 1404 1405 1406 1407 #define ip4_saddr bits.ipaddr.ip4_addr.saddr.s_addr 1408 #define ip4_daddr bits.ipaddr.ip4_addr.daddr.s_addr 1409 1410 #define ip_src_port bits.l4_0 1411 #define ip_dst_port bits.l4_1 1412 #define ip_proto bits.pid 1413 1414 #define ip6_saddr bits.ipaddr.ip6_addr.saddr 1415 #define ip6_daddr bits.ipaddr.ip6_addr.daddr 1416 1417 1418 1419 1420 typedef struct _flow_key_cfg_t { 1421 uint32_t rsrvd:11; 1422 /* The following 3 bit fields added for RF-NIU and Neptune-L */ 1423 uint32_t l4_xor_sel:10; 1424 uint32_t use_l4_md:1; 1425 uint32_t use_sym:1; 1426 uint32_t use_portnum:1; 1427 uint32_t use_l2da:1; 1428 uint32_t use_vlan:1; 1429 uint32_t use_saddr:1; 1430 uint32_t use_daddr:1; 1431 uint32_t use_sport:1; 1432 uint32_t use_dport:1; 1433 uint32_t use_proto:1; 1434 uint32_t ip_opts_exist:1; 1435 } flow_key_cfg_t; 1436 1437 1438 typedef struct _tcam_key_cfg_t { 1439 uint32_t rsrvd:28; 1440 uint32_t use_ip_daddr:1; 1441 uint32_t use_ip_saddr:1; 1442 uint32_t lookup_enable:1; 1443 uint32_t discard:1; 1444 } tcam_key_cfg_t; 1445 1446 1447 1448 /* 1449 * FCRAM Entry Formats 1450 * 1451 * ip6 and ip4 entries, the first 64 bits layouts are identical 1452 * optimistic entry has only 64 bit layout 1453 * The first three bits, fmt, ext and valid are the same 1454 * accoross all the entries 1455 */ 1456 1457 typedef union hash_optim { 1458 uint64_t value; 1459 struct _bits { 1460 #if defined(_BIG_ENDIAN) 1461 uint32_t fmt : 1; /* 63 set to zero */ 1462 uint32_t ext : 1; /* 62 set to zero */ 1463 uint32_t valid : 1; /* 61 */ 1464 uint32_t rdc_offset : 5; /* 60 : 56 */ 1465 uint32_t h2 : 16; /* 55 : 40 */ 1466 uint32_t rsrvd : 8; /* 32 : 32 */ 1467 uint32_t usr_info; /* 31 : 0 */ 1468 #else 1469 uint32_t usr_info; /* 31 : 0 */ 1470 uint32_t rsrvd : 8; /* 39 : 32 */ 1471 uint32_t h2 : 16; /* 55 : 40 */ 1472 uint32_t rdc_offset : 5; /* 60 : 56 */ 1473 uint32_t valid : 1; /* 61 */ 1474 uint32_t ext : 1; /* 62 set to zero */ 1475 uint32_t fmt : 1; /* 63 set to zero */ 1476 #endif 1477 } bits; 1478 } hash_optim_t; 1479 1480 1481 typedef union _hash_hdr { 1482 uint64_t value; 1483 struct _exact_hdr { 1484 #if defined(_BIG_ENDIAN) 1485 uint32_t fmt : 1; /* 63 1 for ipv6, 0 for ipv4 */ 1486 uint32_t ext : 1; /* 62 set to 1 */ 1487 uint32_t valid : 1; /* 61 */ 1488 uint32_t rsrvd : 1; /* 60 */ 1489 uint32_t l2da_1 : 28; /* 59 : 32 */ 1490 uint32_t l2da_0 : 20; /* 31 : 12 */ 1491 uint32_t vlan : 12; /* 12 : 0 */ 1492 #else 1493 uint32_t vlan : 12; /* 12 : 0 */ 1494 uint32_t l2da_0 : 20; /* 31 : 12 */ 1495 uint32_t l2da_1 : 28; /* 59 : 32 */ 1496 uint32_t rsrvd : 1; /* 60 */ 1497 uint32_t valid : 1; /* 61 */ 1498 uint32_t ext : 1; /* 62 set to 1 */ 1499 uint32_t fmt : 1; /* 63 1 for ipv6, 0 for ipv4 */ 1500 #endif 1501 } exact_hdr; 1502 hash_optim_t optim_hdr; 1503 } hash_hdr_t; 1504 1505 1506 1507 typedef union _hash_ports { 1508 uint64_t value; 1509 struct _ports_bits { 1510 #if defined(_BIG_ENDIAN) 1511 uint32_t ip_dport : 16; /* 63 : 48 */ 1512 uint32_t ip_sport : 16; /* 47 : 32 */ 1513 uint32_t proto : 8; /* 31 : 24 */ 1514 uint32_t port : 2; /* 23 : 22 */ 1515 uint32_t rsrvd : 22; /* 21 : 0 */ 1516 #else 1517 uint32_t rsrvd : 22; /* 21 : 0 */ 1518 uint32_t port : 2; /* 23 : 22 */ 1519 uint32_t proto : 8; /* 31 : 24 */ 1520 uint32_t ip_sport : 16; /* 47 : 32 */ 1521 uint32_t ip_dport : 16; /* 63 : 48 */ 1522 #endif 1523 } ports_bits; 1524 } hash_ports_t; 1525 1526 1527 1528 typedef union _hash_match_action { 1529 uint64_t value; 1530 struct _action_bits { 1531 #if defined(_BIG_ENDIAN) 1532 uint32_t rsrvd2 : 3; /* 63 : 61 */ 1533 uint32_t rdc_offset : 5; /* 60 : 56 */ 1534 uint32_t zfvld : 1; /* 55 */ 1535 uint32_t rsrvd : 3; /* 54 : 52 */ 1536 uint32_t zfid : 12; /* 51 : 40 */ 1537 uint32_t _rsrvd : 8; /* 39 : 32 */ 1538 uint32_t usr_info; /* 31 : 0 */ 1539 #else 1540 uint32_t usr_info; /* 31 : 0 */ 1541 uint32_t _rsrvd : 8; /* 39 : 32 */ 1542 uint32_t zfid : 12; /* 51 : 40 */ 1543 uint32_t rsrvd : 3; /* 54 : 52 */ 1544 uint32_t zfvld : 1; /* 55 */ 1545 uint32_t rdc_offset : 5; /* 60 : 56 */ 1546 uint32_t rsrvd2 : 1; /* 63 : 61 */ 1547 #endif 1548 } action_bits; 1549 } hash_match_action_t; 1550 1551 1552 typedef struct _ipaddr6 { 1553 struct in6_addr saddr; 1554 struct in6_addr daddr; 1555 } ip6_addr_t; 1556 1557 1558 typedef struct _ipaddr4 { 1559 #if defined(_BIG_ENDIAN) 1560 struct in_addr saddr; 1561 struct in_addr daddr; 1562 #else 1563 struct in_addr daddr; 1564 struct in_addr saddr; 1565 #endif 1566 } ip4_addr_t; 1567 1568 1569 /* ipv4 has 32 byte layout */ 1570 1571 typedef struct hash_ipv4 { 1572 hash_hdr_t hdr; 1573 ip4_addr_t ip_addr; 1574 hash_ports_t proto_ports; 1575 hash_match_action_t action; 1576 } hash_ipv4_t; 1577 1578 1579 /* ipv4 has 56 byte layout */ 1580 typedef struct hash_ipv6 { 1581 hash_hdr_t hdr; 1582 ip6_addr_t ip_addr; 1583 hash_ports_t proto_ports; 1584 hash_match_action_t action; 1585 } hash_ipv6_t; 1586 1587 1588 1589 typedef union fcram_entry { 1590 uint64_t value[8]; 1591 hash_tbl_data_t dreg[8]; 1592 hash_ipv6_t ipv6_entry; 1593 hash_ipv4_t ipv4_entry; 1594 hash_optim_t optim_entry; 1595 } fcram_entry_t; 1596 1597 1598 1599 #define hash_hdr_fmt ipv4_entry.hdr.exact_hdr.fmt 1600 #define hash_hdr_ext ipv4_entry.hdr.exact_hdr.ext 1601 #define hash_hdr_valid ipv4_entry.hdr.exact_hdr.valid 1602 1603 #define HASH_ENTRY_EXACT(fc) \ 1604 (fc->ipv4_entry.hdr.exact_hdr.ext == 1) 1605 #define HASH_ENTRY_OPTIM(fc) \ 1606 ((fc->ipv4_entry.hdr.exact_hdr.ext == 0) && \ 1607 (fc->ipv6_entry.hdr.exact_hdr.fmt == 0)) 1608 #define HASH_ENTRY_EXACT_IP6(fc) \ 1609 ((fc->ipv6_entry.hdr.exact_hdr.fmt == 1) && \ 1610 (fc->ipv4_entry.hdr.exact_hdr.ext == 1)) 1611 1612 #define HASH_ENTRY_EXACT_IP4(fc) \ 1613 ((fc->ipv6_entry.hdr.exact_hdr.fmt == 0) && \ 1614 (fc->ipv4_entry.hdr.exact_hdr.ext == 1)) 1615 1616 #define HASH_ENTRY_TYPE(fc) \ 1617 (fc->ipv4_entry.hdr.exact_hdr.ext | \ 1618 (fc->ipv4_entry.hdr.exact_hdr.fmt << 1)) 1619 1620 1621 1622 typedef enum fcram_entry_format { 1623 FCRAM_ENTRY_OPTIM = 0x0, 1624 FCRAM_ENTRY_EX_IP4 = 0x2, 1625 FCRAM_ENTRY_EX_IP6 = 0x3, 1626 FCRAM_ENTRY_UNKOWN = 0x1 1627 } fcram_entry_format_t; 1628 1629 1630 #define HASH_ENTRY_TYPE_OPTIM FCRAM_ENTRY_OPTIM 1631 #define HASH_ENTRY_TYPE_OPTIM_IP4 FCRAM_ENTRY_OPTIM 1632 #define HASH_ENTRY_TYPE_OPTIM_IP4 FCRAM_ENTRY_OPTIM 1633 #define HASH_ENTRY_TYPE_EX_IP4 FCRAM_ENTRY_EX_IP4 1634 #define HASH_ENTRY_TYPE_EX_IP6 FCRAM_ENTRY_EX_IP6 1635 1636 1637 1638 1639 /* error xxx formats */ 1640 1641 1642 typedef struct _hash_lookup_err_log { 1643 uint32_t rsrvd:28; 1644 uint32_t lookup_err:1; 1645 uint32_t ecc_err:1; 1646 uint32_t uncor_err:1; 1647 uint32_t multi_lkup:1; 1648 uint32_t multi_bit:1; 1649 uint32_t subarea:3; 1650 uint32_t syndrome:8; 1651 uint32_t h1:20; 1652 } hash_lookup_err_log_t, *p_hash_lookup_err_log_t; 1653 1654 1655 1656 typedef struct _hash_pio_err_log { 1657 uint32_t rsrvd:32; 1658 uint32_t pio_err:1; 1659 uint32_t syndrome:8; 1660 uint32_t addr:23; 1661 } hash_pio_err_log_t, *p_hash_pio_err_log_t; 1662 1663 1664 1665 typedef struct _tcam_err_log { 1666 uint32_t rsrvd:2; 1667 uint32_t tcam_err:1; 1668 uint32_t parity_err:1; 1669 uint32_t ecc_err:1; 1670 uint32_t multi_lkup:1; 1671 uint32_t location:8; 1672 uint32_t syndrome:16; 1673 } tcam_err_log_t, *p_tcam_err_log_t; 1674 1675 1676 typedef struct _vlan_tbl_err_log { 1677 uint32_t rsrvd:32; 1678 uint32_t err:1; 1679 uint32_t multi:1; 1680 uint32_t addr:12; 1681 uint32_t data:18; 1682 } vlan_tbl_err_log_t, *p_vlan_tbl_err_log_t; 1683 1684 1685 #define NEPTUNE_TCAM_SIZE 0x100 1686 #define NIU_TCAM_SIZE 0x80 1687 #define FCRAM_SIZE 0x100000 1688 1689 #ifdef __cplusplus 1690 } 1691 #endif 1692 1693 #endif /* _SYS_NXGE_NXGE_FFLP_HW_H */ 1694