1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_FFLP_HW_H 27 #define _SYS_NXGE_NXGE_FFLP_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_defs.h> 34 35 36 /* FZC_FFLP Offsets */ 37 #define FFLP_ENET_VLAN_TBL_REG (FZC_FFLP + 0x00000) 38 39 /* defines for FFLP_ENET_VLAN_TBL */ 40 #define ENET_VLAN_TBL_VLANRDCTBLN0_MASK 0x0000000000000003ULL 41 #define ENET_VLAN_TBL_VLANRDCTBLN0_SHIFT 0 42 #define ENET_VLAN_TBL_VPR0_MASK 0x00000000000000008ULL 43 #define ENET_VLAN_TBL_VPR0_SHIFT 3 44 45 #define ENET_VLAN_TBL_VLANRDCTBLN1_MASK 0x0000000000000030ULL 46 #define ENET_VLAN_TBL_VLANRDCTBLN1_SHIFT 4 47 #define ENET_VLAN_TBL_VPR1_MASK 0x00000000000000080ULL 48 #define ENET_VLAN_TBL_VPR1_SHIFT 7 49 50 #define ENET_VLAN_TBL_VLANRDCTBLN2_MASK 0x0000000000000300ULL 51 #define ENET_VLAN_TBL_VLANRDCTBLN2_SHIFT 8 52 #define ENET_VLAN_TBL_VPR2_MASK 0x00000000000000800ULL 53 #define ENET_VLAN_TBL_VPR2_SHIFT 11 54 55 #define ENET_VLAN_TBL_VLANRDCTBLN3_MASK 0x0000000000003000ULL 56 #define ENET_VLAN_TBL_VLANRDCTBLN3_SHIFT 12 57 #define ENET_VLAN_TBL_VPR3_MASK 0x0000000000008000ULL 58 #define ENET_VLAN_TBL_VPR3_SHIFT 15 59 60 #define ENET_VLAN_TBL_PARITY0_MASK 0x0000000000010000ULL 61 #define ENET_VLAN_TBL_PARITY0_SHIFT 16 62 #define ENET_VLAN_TBL_PARITY1_MASK 0x0000000000020000ULL 63 #define ENET_VLAN_TBL_PARITY1_SHIFT 17 64 65 typedef union _fflp_enet_vlan_tbl_t { 66 uint64_t value; 67 struct { 68 #if defined(_BIG_ENDIAN) 69 uint32_t hdw; 70 #endif 71 struct { 72 #ifdef _BIT_FIELDS_HTOL 73 uint32_t rsrvd:14; 74 uint32_t parity1:1; 75 uint32_t parity0:1; 76 uint32_t vpr3:1; 77 uint32_t vlanrdctbln3:3; 78 uint32_t vpr2:1; 79 uint32_t vlanrdctbln2:3; 80 uint32_t vpr1:1; 81 uint32_t vlanrdctbln1:3; 82 uint32_t vpr0:1; 83 uint32_t vlanrdctbln0:3; 84 #else 85 uint32_t vlanrdctbln0:3; 86 uint32_t vpr0:1; 87 uint32_t vlanrdctbln1:3; 88 uint32_t vpr1:1; 89 uint32_t vlanrdctbln2:3; 90 uint32_t vpr2:1; 91 uint32_t vlanrdctbln3:3; 92 uint32_t vpr3:1; 93 uint32_t parity0:1; 94 uint32_t parity1:1; 95 uint32_t rsrvd:14; 96 #endif 97 } ldw; 98 #ifndef _BIG_ENDIAN 99 uint32_t hdw; 100 #endif 101 } bits; 102 } fflp_enet_vlan_tbl_t, *p_fflp_enet_vlan_tbl_t; 103 104 #define FFLP_TCAM_CLS_BASE_OFFSET (FZC_FFLP + 0x20000) 105 #define FFLP_L2_CLS_ENET1_REG (FZC_FFLP + 0x20000) 106 #define FFLP_L2_CLS_ENET2_REG (FZC_FFLP + 0x20008) 107 108 typedef union _tcam_class_prg_ether_t { 109 #define TCAM_ENET_USR_CLASS_ENABLE 0x1 110 #define TCAM_ENET_USR_CLASS_DISABLE 0x0 111 112 uint64_t value; 113 struct { 114 #ifdef _BIG_ENDIAN 115 uint32_t hdw; 116 #endif 117 struct { 118 #ifdef _BIT_FIELDS_HTOL 119 uint32_t rsrvd:15; 120 uint32_t valid:1; 121 uint32_t etype:16; 122 #else 123 uint32_t etype:16; 124 uint32_t valid:1; 125 uint32_t rsrvd:15; 126 #endif 127 } ldw; 128 #ifndef _BIG_ENDIAN 129 uint32_t hdw; 130 #endif 131 } bits; 132 } tcam_class_prg_ether_t, *p_tcam_class_prg_ether_t; 133 134 #define FFLP_L3_CLS_IP_U4_REG (FZC_FFLP + 0x20010) 135 #define FFLP_L3_CLS_IP_U5_REG (FZC_FFLP + 0x20018) 136 #define FFLP_L3_CLS_IP_U6_REG (FZC_FFLP + 0x20020) 137 #define FFLP_L3_CLS_IP_U7_REG (FZC_FFLP + 0x20028) 138 139 typedef union _tcam_class_prg_ip_t { 140 #define TCAM_IP_USR_CLASS_ENABLE 0x1 141 #define TCAM_IP_USR_CLASS_DISABLE 0x0 142 143 uint64_t value; 144 struct { 145 #if defined(_BIG_ENDIAN) 146 uint32_t hdw; 147 #endif 148 struct { 149 #ifdef _BIT_FIELDS_HTOL 150 uint32_t rsrvd:6; 151 uint32_t valid:1; 152 uint32_t ipver:1; 153 uint32_t pid:8; 154 uint32_t tosmask:8; 155 uint32_t tos:8; 156 #else 157 uint32_t tos:8; 158 uint32_t tosmask:8; 159 uint32_t pid:8; 160 uint32_t ipver:1; 161 uint32_t valid:1; 162 uint32_t rsrvd:6; 163 #endif 164 } ldw; 165 #ifndef _BIG_ENDIAN 166 uint32_t hdw; 167 #endif 168 } bits; 169 } tcam_class_prg_ip_t, *p_tcam_class_prg_ip_t; 170 /* define the classes which use the above structure */ 171 172 typedef enum fflp_tcam_class { 173 TCAM_CLASS_INVALID = 0, 174 TCAM_CLASS_DUMMY = 1, 175 TCAM_CLASS_ETYPE_1 = 2, 176 TCAM_CLASS_ETYPE_2, 177 TCAM_CLASS_IP_USER_4, 178 TCAM_CLASS_IP_USER_5, 179 TCAM_CLASS_IP_USER_6, 180 TCAM_CLASS_IP_USER_7, 181 TCAM_CLASS_TCP_IPV4, 182 TCAM_CLASS_UDP_IPV4, 183 TCAM_CLASS_AH_ESP_IPV4, 184 TCAM_CLASS_SCTP_IPV4, 185 TCAM_CLASS_TCP_IPV6, 186 TCAM_CLASS_UDP_IPV6, 187 TCAM_CLASS_AH_ESP_IPV6, 188 TCAM_CLASS_SCTP_IPV6, 189 TCAM_CLASS_ARP, 190 TCAM_CLASS_RARP, 191 TCAM_CLASS_DUMMY_12, 192 TCAM_CLASS_DUMMY_13, 193 TCAM_CLASS_DUMMY_14, 194 TCAM_CLASS_DUMMY_15, 195 TCAM_CLASS_MAX 196 } tcam_class_t; 197 198 /* 199 * Specify how to build TCAM key for L3 200 * IP Classes. Both User configured and 201 * hardwired IP services are included. 202 * These are the supported 12 classes. 203 */ 204 #define FFLP_TCAM_KEY_BASE_OFFSET (FZC_FFLP + 0x20030) 205 #define FFLP_TCAM_KEY_IP_USR4_REG (FZC_FFLP + 0x20030) 206 #define FFLP_TCAM_KEY_IP_USR5_REG (FZC_FFLP + 0x20038) 207 #define FFLP_TCAM_KEY_IP_USR6_REG (FZC_FFLP + 0x20040) 208 #define FFLP_TCAM_KEY_IP_USR7_REG (FZC_FFLP + 0x20048) 209 #define FFLP_TCAM_KEY_IP4_TCP_REG (FZC_FFLP + 0x20050) 210 #define FFLP_TCAM_KEY_IP4_UDP_REG (FZC_FFLP + 0x20058) 211 #define FFLP_TCAM_KEY_IP4_AH_ESP_REG (FZC_FFLP + 0x20060) 212 #define FFLP_TCAM_KEY_IP4_SCTP_REG (FZC_FFLP + 0x20068) 213 #define FFLP_TCAM_KEY_IP6_TCP_REG (FZC_FFLP + 0x20070) 214 #define FFLP_TCAM_KEY_IP6_UDP_REG (FZC_FFLP + 0x20078) 215 #define FFLP_TCAM_KEY_IP6_AH_ESP_REG (FZC_FFLP + 0x20080) 216 #define FFLP_TCAM_KEY_IP6_SCTP_REG (FZC_FFLP + 0x20088) 217 218 219 typedef union _tcam_class_key_ip_t { 220 uint64_t value; 221 struct { 222 #if defined(_BIG_ENDIAN) 223 uint32_t hdw; 224 #endif 225 struct { 226 #ifdef _BIT_FIELDS_HTOL 227 uint32_t rsrvd2:28; 228 uint32_t discard:1; 229 uint32_t tsel:1; 230 uint32_t rsrvd:1; 231 uint32_t ipaddr:1; 232 #else 233 uint32_t ipaddr:1; 234 uint32_t rsrvd:1; 235 uint32_t tsel:1; 236 uint32_t discard:1; 237 uint32_t rsrvd2:28; 238 #endif 239 } ldw; 240 #ifndef _BIG_ENDIAN 241 uint32_t hdw; 242 #endif 243 } bits; 244 } tcam_class_key_ip_t, *p_tcam_class_key_ip_t; 245 246 247 248 #define FFLP_TCAM_KEY_0_REG (FZC_FFLP + 0x20090) 249 #define FFLP_TCAM_KEY_1_REG (FZC_FFLP + 0x20098) 250 #define FFLP_TCAM_KEY_2_REG (FZC_FFLP + 0x200A0) 251 #define FFLP_TCAM_KEY_3_REG (FZC_FFLP + 0x200A8) 252 #define FFLP_TCAM_MASK_0_REG (FZC_FFLP + 0x200B0) 253 #define FFLP_TCAM_MASK_1_REG (FZC_FFLP + 0x200B8) 254 #define FFLP_TCAM_MASK_2_REG (FZC_FFLP + 0x200C0) 255 #define FFLP_TCAM_MASK_3_REG (FZC_FFLP + 0x200C8) 256 257 #define FFLP_TCAM_CTL_REG (FZC_FFLP + 0x200D0) 258 259 /* bit defines for FFLP_TCAM_CTL register */ 260 #define TCAM_CTL_TCAM_WR 0x0ULL 261 #define TCAM_CTL_TCAM_RD 0x040000ULL 262 #define TCAM_CTL_TCAM_CMP 0x080000ULL 263 #define TCAM_CTL_RAM_WR 0x100000ULL 264 #define TCAM_CTL_RAM_RD 0x140000ULL 265 #define TCAM_CTL_RWC_STAT 0x0020000ULL 266 #define TCAM_CTL_RWC_MATCH 0x0010000ULL 267 268 269 typedef union _tcam_ctl_t { 270 #define TCAM_CTL_RWC_TCAM_WR 0x0 271 #define TCAM_CTL_RWC_TCAM_RD 0x1 272 #define TCAM_CTL_RWC_TCAM_CMP 0x2 273 #define TCAM_CTL_RWC_RAM_WR 0x4 274 #define TCAM_CTL_RWC_RAM_RD 0x5 275 #define TCAM_CTL_RWC_RWC_STAT 0x1 276 #define TCAM_CTL_RWC_RWC_MATCH 0x1 277 278 uint64_t value; 279 struct { 280 #if defined(_BIG_ENDIAN) 281 uint32_t hdw; 282 #endif 283 struct { 284 #ifdef _BIT_FIELDS_HTOL 285 uint32_t rsrvd2:11; 286 uint32_t rwc:3; 287 uint32_t stat:1; 288 uint32_t match:1; 289 uint32_t rsrvd:6; 290 uint32_t location:10; 291 #else 292 uint32_t location:10; 293 uint32_t rsrvd:6; 294 uint32_t match:1; 295 uint32_t stat:1; 296 uint32_t rwc:3; 297 uint32_t rsrvd2:11; 298 #endif 299 } ldw; 300 #ifndef _BIG_ENDIAN 301 uint32_t hdw; 302 #endif 303 } bits; 304 } tcam_ctl_t, *p_tcam_ctl_t; 305 306 307 308 /* Bit defines for TCAM ASC RAM */ 309 310 311 typedef union _tcam_res_t { 312 uint64_t value; 313 struct { 314 #if defined(_BIG_ENDIAN) 315 struct { 316 uint32_t rsrvd:22; 317 uint32_t syndrome:10; 318 } hdw; 319 #endif 320 struct { 321 #ifdef _BIT_FIELDS_HTOL 322 uint32_t syndrome:6; 323 uint32_t zfid:12; 324 uint32_t v4_ecc_ck:1; 325 uint32_t disc:1; 326 uint32_t tres:2; 327 uint32_t rdctbl:3; 328 uint32_t offset:5; 329 uint32_t zfld:1; 330 uint32_t age:1; 331 #else 332 uint32_t age:1; 333 uint32_t zfld:1; 334 uint32_t offset:5; 335 uint32_t rdctbl:3; 336 uint32_t tres:2; 337 uint32_t disc:1; 338 uint32_t v4_ecc_ck:1; 339 uint32_t zfid:12; 340 uint32_t syndrome:6; 341 #endif 342 } ldw; 343 #ifndef _BIG_ENDIAN 344 struct { 345 uint32_t syndrome:10; 346 uint32_t rsrvd:22; 347 } hdw; 348 #endif 349 } bits; 350 } tcam_res_t, *p_tcam_res_t; 351 352 353 354 #define TCAM_ASC_DATA_AGE 0x0000000000000001ULL 355 #define TCAM_ASC_DATA_AGE_SHIFT 0x0 356 #define TCAM_ASC_DATA_ZFVLD 0x0000000000000002ULL 357 #define TCAM_ASC_DATA_ZFVLD_SHIFT 1 358 359 #define TCAM_ASC_DATA_OFFSET_MASK 0x000000000000007CULL 360 #define TCAM_ASC_DATA_OFFSET_SHIFT 2 361 362 #define TCAM_ASC_DATA_RDCTBL_MASK 0x0000000000000038ULL 363 #define TCAM_ASC_DATA_RDCTBL_SHIFT 7 364 #define TCAM_ASC_DATA_TRES_MASK 0x0000000000000C00ULL 365 #define TRES_CONT_USE_L2RDC 0x00 366 #define TRES_TERM_USE_OFFSET 0x01 367 #define TRES_CONT_OVRD_L2RDC 0x02 368 #define TRES_TERM_OVRD_L2RDC 0x03 369 370 #define TCAM_ASC_DATA_TRES_SHIFT 10 371 #define TCAM_TRES_CONT_USE_L2RDC \ 372 (0x0000000000000000ULL << TCAM_ASC_DATA_TRES_SHIFT) 373 #define TCAM_TRES_TERM_USE_OFFSET \ 374 (0x0000000000000001ULL << TCAM_ASC_DATA_TRES_SHIFT) 375 #define TCAM_TRES_CONT_OVRD_L2RDC \ 376 (0x0000000000000002ULL << TCAM_ASC_DATA_TRES_SHIFT) 377 #define TCAM_TRES_TERM_OVRD_L2RDC \ 378 (0x0000000000000003ULL << TCAM_ASC_DATA_TRES_SHIFT) 379 380 #define TCAM_ASC_DATA_DISC_MASK 0x0000000000001000ULL 381 #define TCAM_ASC_DATA_DISC_SHIFT 12 382 #define TCAM_ASC_DATA_V4_ECC_OK_MASK 0x0000000000002000ULL 383 #define TCAM_ASC_DATA_V4_ECC_OK_SHIFT 13 384 #define TCAM_ASC_DATA_V4_ECC_OK \ 385 (0x0000000000000001ULL << TCAM_ASC_DATA_V4_ECC_OK_MASK_SHIFT) 386 387 #define TCAM_ASC_DATA_ZFID_MASK 0x0000000003FF3000ULL 388 #define TCAM_ASC_DATA_ZFID_SHIFT 14 389 #define TCAM_ASC_DATA_ZFID(value) \ 390 ((value & TCAM_ASC_DATA_ZFID_MASK) >> TCAM_ASC_DATA_ZFID_SHIFT) 391 392 #define TCAM_ASC_DATA_SYNDR_MASK 0x000003FFF3000000ULL 393 #define TCAM_ASC_DATA_SYNDR_SHIFT 26 394 #define TCAM_ASC_DATA_SYNDR(value) \ 395 ((value & TCAM_ASC_DATA_SYNDR_MASK) >> TCAM_ASC_DATA_SYNDR_SHIFT) 396 397 398 /* error registers */ 399 400 #define FFLP_VLAN_PAR_ERR_REG (FZC_FFLP + 0x08000) 401 402 typedef union _vlan_par_err_t { 403 uint64_t value; 404 struct { 405 #if defined(_BIG_ENDIAN) 406 uint32_t hdw; 407 #endif 408 struct { 409 #ifdef _BIT_FIELDS_HTOL 410 uint32_t err:1; 411 uint32_t m_err:1; 412 uint32_t addr:12; 413 uint32_t data:18; 414 #else 415 uint32_t data:18; 416 uint32_t addr:12; 417 uint32_t m_err:1; 418 uint32_t err:1; 419 #endif 420 } ldw; 421 #ifndef _BIG_ENDIAN 422 uint32_t hdw; 423 #endif 424 } bits; 425 } vlan_par_err_t, *p_vlan_par_err_t; 426 427 428 #define FFLP_TCAM_ERR_REG (FZC_FFLP + 0x200D8) 429 430 typedef union _tcam_err_t { 431 uint64_t value; 432 struct { 433 #if defined(_BIG_ENDIAN) 434 uint32_t hdw; 435 #endif 436 struct { 437 #ifdef _BIT_FIELDS_HTOL 438 uint32_t err:1; 439 uint32_t p_ecc:1; 440 uint32_t mult:1; 441 uint32_t rsrvd:5; 442 uint32_t addr:8; 443 uint32_t syndrome:16; 444 #else 445 uint32_t syndrome:16; 446 uint32_t addr:8; 447 uint32_t rsrvd:5; 448 uint32_t mult:1; 449 uint32_t p_ecc:1; 450 uint32_t err:1; 451 #endif 452 } ldw; 453 #ifndef _BIG_ENDIAN 454 uint32_t hdw; 455 #endif 456 } bits; 457 } tcam_err_t, *p_tcam_err_t; 458 459 460 #define TCAM_ERR_SYNDROME_MASK 0x000000000000FFFFULL 461 #define TCAM_ERR_MULT_SHIFT 29 462 #define TCAM_ERR_MULT 0x0000000020000000ULL 463 #define TCAM_ERR_P_ECC 0x0000000040000000ULL 464 #define TCAM_ERR_ERR 0x0000000080000000ULL 465 466 #define HASH_LKUP_ERR_LOG1_REG (FZC_FFLP + 0x200E0) 467 #define HASH_LKUP_ERR_LOG2_REG (FZC_FFLP + 0x200E8) 468 469 470 471 typedef union _hash_lookup_err_log1_t { 472 uint64_t value; 473 struct { 474 #if defined(_BIG_ENDIAN) 475 uint32_t hdw; 476 #endif 477 struct { 478 #ifdef _BIT_FIELDS_HTOL 479 uint32_t rsrvd:28; 480 uint32_t ecc_err:1; 481 uint32_t mult_lk:1; 482 uint32_t cu:1; 483 uint32_t mult_bit:1; 484 #else 485 uint32_t mult_bit:1; 486 uint32_t cu:1; 487 uint32_t mult_lk:1; 488 uint32_t ecc_err:1; 489 uint32_t rsrvd:28; 490 #endif 491 } ldw; 492 #ifndef _BIG_ENDIAN 493 uint32_t hdw; 494 #endif 495 } bits; 496 } hash_lookup_err_log1_t, *p_hash_lookup_err_log1_t; 497 498 499 500 typedef union _hash_lookup_err_log2_t { 501 uint64_t value; 502 struct { 503 #if defined(_BIG_ENDIAN) 504 uint32_t hdw; 505 #endif 506 struct { 507 #ifdef _BIT_FIELDS_HTOL 508 uint32_t rsrvd:1; 509 uint32_t h1:20; 510 uint32_t subarea:3; 511 uint32_t syndrome:8; 512 #else 513 uint32_t syndrome:8; 514 uint32_t subarea:3; 515 uint32_t h1:20; 516 uint32_t rsrvd:1; 517 #endif 518 } ldw; 519 #ifndef _BIG_ENDIAN 520 uint32_t hdw; 521 #endif 522 } bits; 523 } hash_lookup_err_log2_t, *p_hash_lookup_err_log2_t; 524 525 526 527 #define FFLP_FCRAM_ERR_TST0_REG (FZC_FFLP + 0x20128) 528 529 typedef union _fcram_err_tst0_t { 530 uint64_t value; 531 struct { 532 #if defined(_BIG_ENDIAN) 533 uint32_t hdw; 534 #endif 535 struct { 536 #ifdef _BIT_FIELDS_HTOL 537 uint32_t rsrvd:24; 538 uint32_t syndrome_mask:8; 539 #else 540 uint32_t syndrome_mask:10; 541 uint32_t rsrvd:24; 542 #endif 543 } ldw; 544 #ifndef _BIG_ENDIAN 545 uint32_t hdw; 546 #endif 547 } bits; 548 } fcram_err_tst0_t, *p_fcram_err_tst0_t; 549 550 551 #define FFLP_FCRAM_ERR_TST1_REG (FZC_FFLP + 0x20130) 552 #define FFLP_FCRAM_ERR_TST2_REG (FZC_FFLP + 0x20138) 553 554 typedef union _fcram_err_tst_t { 555 uint64_t value; 556 struct { 557 #if defined(_BIG_ENDIAN) 558 struct { 559 uint32_t dat; 560 } hdw; 561 #endif 562 struct { 563 uint32_t dat; 564 } ldw; 565 #ifndef _BIG_ENDIAN 566 struct { 567 uint32_t dat; 568 } hdw; 569 #endif 570 } bits; 571 } fcram_err_tst1_t, *p_fcram_err_tst1_t, 572 fcram_err_tst2_t, *p_fcram_err_tst2_t, 573 fcram_err_data_t, *p_fcram_err_data_t; 574 575 576 577 #define FFLP_ERR_MSK_REG (FZC_FFLP + 0x20140) 578 579 typedef union _fflp_err_mask_t { 580 uint64_t value; 581 struct { 582 #if defined(_BIG_ENDIAN) 583 uint32_t hdw; 584 #endif 585 struct { 586 #ifdef _BIT_FIELDS_HTOL 587 uint32_t rsrvd:21; 588 uint32_t hash_tbl_dat:8; 589 uint32_t hash_tbl_lkup:1; 590 uint32_t tcam:1; 591 uint32_t vlan:1; 592 #else 593 uint32_t vlan:1; 594 uint32_t tcam:1; 595 uint32_t hash_tbl_lkup:1; 596 uint32_t hash_tbl_dat:8; 597 uint32_t rsrvd:21; 598 #endif 599 } ldw; 600 #ifndef _BIG_ENDIAN 601 uint32_t hdw; 602 #endif 603 } bits; 604 } fflp_err_mask_t, *p_fflp_err_mask_t; 605 606 #define FFLP_ERR_VLAN_MASK 0x00000001ULL 607 #define FFLP_ERR_VLAN 0x00000001ULL 608 #define FFLP_ERR_VLAN_SHIFT 0x0 609 610 #define FFLP_ERR_TCAM_MASK 0x00000002ULL 611 #define FFLP_ERR_TCAM 0x00000001ULL 612 #define FFLP_ERR_TCAM_SHIFT 0x1 613 614 #define FFLP_ERR_HASH_TBL_LKUP_MASK 0x00000004ULL 615 #define FFLP_ERR_HASH_TBL_LKUP 0x00000001ULL 616 #define FFLP_ERR_HASH_TBL_LKUP_SHIFT 0x2 617 618 #define FFLP_ERR_HASH_TBL_DAT_MASK 0x00000007F8ULL 619 #define FFLP_ERR_HASH_TBL_DAT 0x0000000FFULL 620 #define FFLP_ERR_HASH_TBL_DAT_SHIFT 0x3 621 622 #define FFLP_ERR_MASK_ALL (FFLP_ERR_VLAN_MASK | FFLP_ERR_TCAM_MASK | \ 623 FFLP_ERR_HASH_TBL_LKUP_MASK | \ 624 FFLP_ERR_HASH_TBL_DAT_MASK) 625 626 627 #define FFLP_CFG_1_REG (FZC_FFLP + 0x20100) 628 629 typedef union _fflp_cfg_1_t { 630 uint64_t value; 631 struct { 632 #if defined(_BIG_ENDIAN) 633 uint32_t hdw; 634 #endif 635 struct { 636 #ifdef _BIT_FIELDS_HTOL 637 uint32_t rsrvd:5; 638 uint32_t tcam_disable:1; 639 uint32_t pio_dbg_sel:3; 640 uint32_t pio_fio_rst:1; 641 uint32_t pio_fio_lat:2; 642 uint32_t camlatency:4; 643 uint32_t camratio:4; 644 uint32_t fcramratio:4; 645 uint32_t fcramoutdr:4; 646 uint32_t fcramqs:1; 647 uint32_t errordis:1; 648 uint32_t fflpinitdone:1; 649 uint32_t llcsnap:1; 650 #else 651 uint32_t llcsnap:1; 652 uint32_t fflpinitdone:1; 653 uint32_t errordis:1; 654 uint32_t fcramqs:1; 655 uint32_t fcramoutdr:4; 656 uint32_t fcramratio:4; 657 uint32_t camratio:4; 658 uint32_t camlatency:4; 659 uint32_t pio_fio_lat:2; 660 uint32_t pio_fio_rst:1; 661 uint32_t pio_dbg_sel:3; 662 uint32_t tcam_disable:1; 663 uint32_t rsrvd:5; 664 #endif 665 } ldw; 666 #ifndef _BIG_ENDIAN 667 uint32_t hdw; 668 #endif 669 } bits; 670 } fflp_cfg_1_t, *p_fflp_cfg_1_t; 671 672 673 typedef enum fflp_fcram_output_drive { 674 FCRAM_OUTDR_NORMAL = 0x0, 675 FCRAM_OUTDR_STRONG = 0x5, 676 FCRAM_OUTDR_WEAK = 0xa 677 } fflp_fcram_output_drive_t; 678 679 680 typedef enum fflp_fcram_qs { 681 FCRAM_QS_MODE_QS = 0x0, 682 FCRAM_QS_MODE_FREE = 0x1 683 } fflp_fcram_qs_t; 684 685 #define FCRAM_PIO_HIGH_PRI 0xf 686 #define FCRAM_PIO_MED_PRI 0xa 687 #define FCRAM_LOOKUP_HIGH_PRI 0x0 688 #define FCRAM_LOOKUP_HIGH_PRI 0x0 689 #define FCRAM_IO_DEFAULT_PRI FCRAM_PIO_MED_PRI 690 691 #define TCAM_PIO_HIGH_PRI 0xf 692 #define TCAM_PIO_MED_PRI 0xa 693 #define TCAM_LOOKUP_HIGH_PRI 0x0 694 #define TCAM_LOOKUP_HIGH_PRI 0x0 695 #define TCAM_IO_DEFAULT_PRI TCAM_PIO_MED_PRI 696 697 #define TCAM_DEFAULT_LATENCY 0x4 698 699 700 #define FFLP_DBG_TRAIN_VCT_REG (FZC_FFLP + 0x20148) 701 702 typedef union _fflp_dbg_train_vct_t { 703 uint64_t value; 704 struct { 705 #if defined(_BIG_ENDIAN) 706 uint32_t hdw; 707 #endif 708 struct { 709 #ifdef _BIT_FIELDS_HTOL 710 uint32_t vector; 711 #else 712 uint32_t vector; 713 #endif 714 } ldw; 715 #ifndef _BIG_ENDIAN 716 uint32_t hdw; 717 #endif 718 } bits; 719 } fflp_dbg_train_vct_t, *p_fflp_dbg_train_vct_t; 720 721 722 723 #define FFLP_TCP_CFLAG_MSK_REG (FZC_FFLP + 0x20108) 724 725 typedef union _tcp_cflag_mask_t { 726 uint64_t value; 727 struct { 728 #if defined(_BIG_ENDIAN) 729 uint32_t hdw; 730 #endif 731 struct { 732 #ifdef _BIT_FIELDS_HTOL 733 uint32_t rsrvd:20; 734 uint32_t mask:12; 735 #else 736 uint32_t mask:12; 737 uint32_t rsrvd:20; 738 #endif 739 } ldw; 740 #ifndef _BIG_ENDIAN 741 uint32_t hdw; 742 #endif 743 } bits; 744 } tcp_cflag_mask_t, *p_tcp_cflag_mask_t; 745 746 747 748 #define FFLP_FCRAM_REF_TMR_REG (FZC_FFLP + 0x20110) 749 750 751 typedef union _fcram_ref_tmr_t { 752 #define FCRAM_REFRESH_DEFAULT_MAX_TIME 0x200 753 #define FCRAM_REFRESH_DEFAULT_MIN_TIME 0x200 754 #define FCRAM_REFRESH_DEFAULT_SYS_TIME 0x200 755 #define FCRAM_REFRESH_MAX_TICK 39 /* usecs */ 756 #define FCRAM_REFRESH_MIN_TICK 400 /* nsecs */ 757 758 uint64_t value; 759 struct { 760 #if defined(_BIG_ENDIAN) 761 uint32_t hdw; 762 #endif 763 struct { 764 #ifdef _BIT_FIELDS_HTOL 765 uint32_t max:16; 766 uint32_t min:16; 767 #else 768 uint32_t min:16; 769 uint32_t max:16; 770 #endif 771 } ldw; 772 #ifndef _BIG_ENDIAN 773 uint32_t hdw; 774 #endif 775 } bits; 776 } fcram_ref_tmr_t, *p_fcram_ref_tmr_t; 777 778 779 780 781 #define FFLP_FCRAM_FIO_ADDR_REG (FZC_FFLP + 0x20118) 782 783 typedef union _fcram_fio_addr_t { 784 uint64_t value; 785 struct { 786 #if defined(_BIG_ENDIAN) 787 uint32_t hdw; 788 #endif 789 struct { 790 #ifdef _BIT_FIELDS_HTOL 791 uint32_t rsrvd:22; 792 uint32_t addr:10; 793 #else 794 uint32_t addr:10; 795 uint32_t rsrvd:22; 796 #endif 797 } ldw; 798 #ifndef _BIG_ENDIAN 799 uint32_t hdw; 800 #endif 801 } bits; 802 } fcram_fio_addr_t, *p_fcram_fio_addr_t; 803 804 805 #define FFLP_FCRAM_FIO_DAT_REG (FZC_FFLP + 0x20120) 806 807 typedef union _fcram_fio_dat_t { 808 uint64_t value; 809 struct { 810 #if defined(_BIG_ENDIAN) 811 uint32_t hdw; 812 #endif 813 struct { 814 #ifdef _BIT_FIELDS_HTOL 815 uint32_t rsrvd:22; 816 uint32_t addr:10; 817 #else 818 uint32_t addr:10; 819 uint32_t rsrvd:22; 820 #endif 821 } ldw; 822 #ifndef _BIG_ENDIAN 823 uint32_t hdw; 824 #endif 825 } bits; 826 } fcram_fio_dat_t, *p_fcram_fio_dat_t; 827 828 829 #define FFLP_FCRAM_PHY_RD_LAT_REG (FZC_FFLP + 0x20150) 830 831 typedef union _fcram_phy_rd_lat_t { 832 uint64_t value; 833 struct { 834 #if defined(_BIG_ENDIAN) 835 uint32_t hdw; 836 #endif 837 struct { 838 #ifdef _BIT_FIELDS_HTOL 839 uint32_t rsrvd:24; 840 uint32_t lat:8; 841 #else 842 uint32_t lat:8; 843 uint32_t rsrvd:24; 844 #endif 845 } ldw; 846 #ifndef _BIG_ENDIAN 847 uint32_t hdw; 848 #endif 849 } bits; 850 } fcram_phy_rd_lat_t, *p_fcram_phy_rd_lat_t; 851 852 853 /* 854 * Specify how to build a flow key for IP 855 * classes, both programmable and hardwired 856 */ 857 #define FFLP_FLOW_KEY_BASE_OFFSET (FZC_FFLP + 0x40000) 858 #define FFLP_FLOW_KEY_IP_USR4_REG (FZC_FFLP + 0x40000) 859 #define FFLP_FLOW_KEY_IP_USR5_REG (FZC_FFLP + 0x40008) 860 #define FFLP_FLOW_KEY_IP_USR6_REG (FZC_FFLP + 0x40010) 861 #define FFLP_FLOW_KEY_IP_USR7_REG (FZC_FFLP + 0x40018) 862 #define FFLP_FLOW_KEY_IP4_TCP_REG (FZC_FFLP + 0x40020) 863 #define FFLP_FLOW_KEY_IP4_UDP_REG (FZC_FFLP + 0x40028) 864 #define FFLP_FLOW_KEY_IP4_AH_ESP_REG (FZC_FFLP + 0x40030) 865 #define FFLP_FLOW_KEY_IP4_SCTP_REG (FZC_FFLP + 0x40038) 866 #define FFLP_FLOW_KEY_IP6_TCP_REG (FZC_FFLP + 0x40040) 867 #define FFLP_FLOW_KEY_IP6_UDP_REG (FZC_FFLP + 0x40048) 868 #define FFLP_FLOW_KEY_IP6_AH_ESP_REG (FZC_FFLP + 0x40050) 869 #define FFLP_FLOW_KEY_IP6_SCTP_REG (FZC_FFLP + 0x40058) 870 871 typedef union _flow_class_key_ip_t { 872 uint64_t value; 873 struct { 874 #if defined(_BIG_ENDIAN) 875 uint32_t hdw; 876 #endif 877 struct { 878 #ifdef _BIT_FIELDS_HTOL 879 uint32_t rsrvd2:22; 880 uint32_t port:1; 881 uint32_t l2da:1; 882 uint32_t vlan:1; 883 uint32_t ipsa:1; 884 uint32_t ipda:1; 885 uint32_t proto:1; 886 uint32_t l4_0:2; 887 uint32_t l4_1:2; 888 #else 889 uint32_t l4_1:2; 890 uint32_t l4_0:2; 891 uint32_t proto:1; 892 uint32_t ipda:1; 893 uint32_t ipsa:1; 894 uint32_t vlan:1; 895 uint32_t l2da:1; 896 uint32_t port:1; 897 uint32_t rsrvd2:22; 898 #endif 899 } ldw; 900 #ifndef _BIG_ENDIAN 901 uint32_t hdw; 902 #endif 903 } bits; 904 } flow_class_key_ip_t, *p_flow_class_key_ip_t; 905 906 907 #define FFLP_H1POLY_REG (FZC_FFLP + 0x40060) 908 909 910 typedef union _hash_h1poly_t { 911 uint64_t value; 912 struct { 913 #if defined(_BIG_ENDIAN) 914 uint32_t hdw; 915 #endif 916 struct { 917 uint32_t init_value; 918 } ldw; 919 #ifndef _BIG_ENDIAN 920 uint32_t hdw; 921 #endif 922 } bits; 923 } hash_h1poly_t, *p_hash_h1poly_t; 924 925 #define FFLP_H2POLY_REG (FZC_FFLP + 0x40068) 926 927 typedef union _hash_h2poly_t { 928 uint64_t value; 929 struct { 930 #if defined(_BIG_ENDIAN) 931 uint32_t hdw; 932 #endif 933 struct { 934 #ifdef _BIT_FIELDS_HTOL 935 uint32_t rsrvd:16; 936 uint32_t init_value:16; 937 #else 938 uint32_t init_value:16; 939 uint32_t rsrvd:16; 940 #endif 941 } ldw; 942 #ifndef _BIG_ENDIAN 943 uint32_t hdw; 944 #endif 945 } bits; 946 } hash_h2poly_t, *p_hash_h2poly_t; 947 948 #define FFLP_FLW_PRT_SEL_REG (FZC_FFLP + 0x40070) 949 950 951 typedef union _flow_prt_sel_t { 952 #define FFLP_FCRAM_MAX_PARTITION 8 953 uint64_t value; 954 struct { 955 #if defined(_BIG_ENDIAN) 956 uint32_t hdw; 957 #endif 958 struct { 959 #ifdef _BIT_FIELDS_HTOL 960 uint32_t rsrvd3:15; 961 uint32_t ext:1; 962 uint32_t rsrvd2:3; 963 uint32_t mask:5; 964 uint32_t rsrvd:3; 965 uint32_t base:5; 966 #else 967 uint32_t base:5; 968 uint32_t rsrvd:3; 969 uint32_t mask:5; 970 uint32_t rsrvd2:3; 971 uint32_t ext:1; 972 uint32_t rsrvd3:15; 973 #endif 974 } ldw; 975 #ifndef _BIG_ENDIAN 976 uint32_t hdw; 977 #endif 978 } bits; 979 } flow_prt_sel_t, *p_flow_prt_sel_t; 980 981 982 983 /* FFLP Offsets */ 984 985 986 #define FFLP_HASH_TBL_ADDR_REG (FFLP + 0x00000) 987 988 typedef union _hash_tbl_addr_t { 989 uint64_t value; 990 struct { 991 #if defined(_BIG_ENDIAN) 992 uint32_t hdw; 993 #endif 994 struct { 995 #ifdef _BIT_FIELDS_HTOL 996 uint32_t rsrvd:8; 997 uint32_t autoinc:1; 998 uint32_t addr:23; 999 #else 1000 uint32_t addr:23; 1001 uint32_t autoinc:1; 1002 uint32_t rsrvd:8; 1003 #endif 1004 } ldw; 1005 #ifndef _BIG_ENDIAN 1006 uint32_t hdw; 1007 #endif 1008 } bits; 1009 } hash_tbl_addr_t, *p_hash_tbl_addr_t; 1010 1011 1012 #define FFLP_HASH_TBL_DATA_REG (FFLP + 0x00008) 1013 1014 typedef union _hash_tbl_data_t { 1015 uint64_t value; 1016 struct { 1017 #ifdef _BIG_ENDIAN 1018 uint32_t hdw; 1019 uint32_t ldw; 1020 #else 1021 uint32_t ldw; 1022 uint32_t hdw; 1023 #endif 1024 } bits; 1025 } hash_tbl_data_t, *p_hash_tbl_data_t; 1026 1027 1028 #define FFLP_HASH_TBL_DATA_LOG_REG (FFLP + 0x00010) 1029 1030 1031 typedef union _hash_tbl_data_log_t { 1032 uint64_t value; 1033 struct { 1034 #if defined(_BIG_ENDIAN) 1035 uint32_t hdw; 1036 #endif 1037 struct { 1038 #ifdef _BIT_FIELDS_HTOL 1039 uint32_t pio_err:1; 1040 uint32_t fcram_addr:23; 1041 uint32_t syndrome:8; 1042 #else 1043 uint32_t syndrome:8; 1044 uint32_t fcram_addr:23; 1045 uint32_t pio_err:1; 1046 #endif 1047 } ldw; 1048 #ifndef _BIG_ENDIAN 1049 uint32_t hdw; 1050 #endif 1051 } bits; 1052 } hash_tbl_data_log_t, *p_hash_tbl_data_log_t; 1053 1054 1055 1056 #define REG_PIO_WRITE64(handle, offset, value) \ 1057 NXGE_REG_WR64((handle), (offset), (value)) 1058 #define REG_PIO_READ64(handle, offset, val_p) \ 1059 NXGE_REG_RD64((handle), (offset), (val_p)) 1060 1061 1062 #define WRITE_TCAM_REG_CTL(handle, ctl) \ 1063 REG_PIO_WRITE64(handle, FFLP_TCAM_CTL_REG, ctl) 1064 1065 #define READ_TCAM_REG_CTL(handle, val_p) \ 1066 REG_PIO_READ64(handle, FFLP_TCAM_CTL_REG, val_p) 1067 1068 1069 #define WRITE_TCAM_REG_KEY0(handle, key) \ 1070 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_0_REG, key) 1071 #define WRITE_TCAM_REG_KEY1(handle, key) \ 1072 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_1_REG, key) 1073 #define WRITE_TCAM_REG_KEY2(handle, key) \ 1074 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_2_REG, key) 1075 #define WRITE_TCAM_REG_KEY3(handle, key) \ 1076 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_3_REG, key) 1077 #define WRITE_TCAM_REG_MASK0(handle, mask) \ 1078 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_0_REG, mask) 1079 #define WRITE_TCAM_REG_MASK1(handle, mask) \ 1080 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_1_REG, mask) 1081 #define WRITE_TCAM_REG_MASK2(handle, mask) \ 1082 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_2_REG, mask) 1083 #define WRITE_TCAM_REG_MASK3(handle, mask) \ 1084 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_3_REG, mask) 1085 1086 #define READ_TCAM_REG_KEY0(handle, val_p) \ 1087 REG_PIO_READ64(handle, FFLP_TCAM_KEY_0_REG, val_p) 1088 #define READ_TCAM_REG_KEY1(handle, val_p) \ 1089 REG_PIO_READ64(handle, FFLP_TCAM_KEY_1_REG, val_p) 1090 #define READ_TCAM_REG_KEY2(handle, val_p) \ 1091 REG_PIO_READ64(handle, FFLP_TCAM_KEY_2_REG, val_p) 1092 #define READ_TCAM_REG_KEY3(handle, val_p) \ 1093 REG_PIO_READ64(handle, FFLP_TCAM_KEY_3_REG, val_p) 1094 #define READ_TCAM_REG_MASK0(handle, val_p) \ 1095 REG_PIO_READ64(handle, FFLP_TCAM_MASK_0_REG, val_p) 1096 #define READ_TCAM_REG_MASK1(handle, val_p) \ 1097 REG_PIO_READ64(handle, FFLP_TCAM_MASK_1_REG, val_p) 1098 #define READ_TCAM_REG_MASK2(handle, val_p) \ 1099 REG_PIO_READ64(handle, FFLP_TCAM_MASK_2_REG, val_p) 1100 #define READ_TCAM_REG_MASK3(handle, val_p) \ 1101 REG_PIO_READ64(handle, FFLP_TCAM_MASK_3_REG, val_p) 1102 1103 1104 1105 1106 typedef struct tcam_ipv4 { 1107 #if defined(_BIG_ENDIAN) 1108 uint32_t reserved6; /* 255 : 224 */ 1109 uint32_t reserved5 : 24; /* 223 : 200 */ 1110 uint32_t cls_code : 5; /* 199 : 195 */ 1111 uint32_t reserved4 : 3; /* 194 : 192 */ 1112 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1113 uint32_t noport : 1; /* 186 */ 1114 uint32_t reserved3 : 26; /* 185: 160 */ 1115 uint32_t reserved2; /* 159: 128 */ 1116 uint32_t reserved : 16; /* 127 : 112 */ 1117 uint32_t tos : 8; /* 111 : 104 */ 1118 uint32_t proto : 8; /* 103 : 96 */ 1119 uint32_t l4_port_spi; /* 95 : 64 */ 1120 uint32_t ip_src; /* 63 : 32 */ 1121 uint32_t ip_dest; /* 31 : 0 */ 1122 #else 1123 uint32_t ip_dest; /* 31 : 0 */ 1124 uint32_t ip_src; /* 63 : 32 */ 1125 uint32_t l4_port_spi; /* 95 : 64 */ 1126 uint32_t proto : 8; /* 103 : 96 */ 1127 uint32_t tos : 8; /* 111 : 104 */ 1128 uint32_t reserved : 16; /* 127 : 112 */ 1129 uint32_t reserved2; /* 159: 128 */ 1130 uint32_t reserved3 : 26; /* 185: 160 */ 1131 uint32_t noport : 1; /* 186 */ 1132 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1133 uint32_t reserved4 : 3; /* 194 : 192 */ 1134 uint32_t cls_code : 5; /* 199 : 195 */ 1135 uint32_t reserved5 : 24; /* 223 : 200 */ 1136 uint32_t reserved6; /* 255 : 224 */ 1137 #endif 1138 } tcam_ipv4_t; 1139 1140 1141 1142 typedef struct tcam_reg { 1143 #if defined(_BIG_ENDIAN) 1144 uint64_t reg0; 1145 uint64_t reg1; 1146 uint64_t reg2; 1147 uint64_t reg3; 1148 #else 1149 uint64_t reg3; 1150 uint64_t reg2; 1151 uint64_t reg1; 1152 uint64_t reg0; 1153 #endif 1154 } tcam_reg_t; 1155 1156 1157 typedef struct tcam_ether { 1158 #if defined(_BIG_ENDIAN) 1159 uint8_t reserved3[7]; /* 255 : 200 */ 1160 uint8_t cls_code : 5; /* 199 : 195 */ 1161 uint8_t reserved2 : 3; /* 194 : 192 */ 1162 uint8_t ethframe[11]; /* 191 : 104 */ 1163 uint8_t reserved[13]; /* 103 : 0 */ 1164 #else 1165 uint8_t reserved[13]; /* 103 : 0 */ 1166 uint8_t ethframe[11]; /* 191 : 104 */ 1167 uint8_t reserved2 : 3; /* 194 : 192 */ 1168 uint8_t cls_code : 5; /* 199 : 195 */ 1169 uint8_t reserved3[7]; /* 255 : 200 */ 1170 #endif 1171 } tcam_ether_t; 1172 1173 1174 typedef struct tcam_ipv6 { 1175 #if defined(_BIG_ENDIAN) 1176 uint32_t reserved4; /* 255 : 224 */ 1177 uint32_t reserved3 : 24; /* 223 : 200 */ 1178 uint32_t cls_code : 5; /* 199 : 195 */ 1179 uint32_t reserved2 : 3; /* 194 : 192 */ 1180 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1181 uint32_t noport : 1; /* 186 */ 1182 uint32_t reserved : 10; /* 185 : 176 */ 1183 uint32_t tos : 8; /* 175 : 168 */ 1184 uint32_t nxt_hdr : 8; /* 167 : 160 */ 1185 uint32_t l4_port_spi; /* 159 : 128 */ 1186 uint32_t ip_addr[4]; /* 127 : 0 */ 1187 #else 1188 uint32_t ip_addr[4]; /* 127 : 0 */ 1189 uint32_t l4_port_spi; /* 159 : 128 */ 1190 uint32_t nxt_hdr : 8; /* 167 : 160 */ 1191 uint32_t tos : 8; /* 175 : 168 */ 1192 uint32_t reserved : 10; /* 185 : 176 */ 1193 uint32_t noport : 1; /* 186 */ 1194 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1195 uint32_t reserved2 : 3; /* 194 : 192 */ 1196 uint32_t cls_code : 5; /* 199 : 195 */ 1197 uint32_t reserved3 : 24; /* 223 : 200 */ 1198 uint32_t reserved4; /* 255 : 224 */ 1199 #endif 1200 } tcam_ipv6_t; 1201 1202 1203 typedef struct tcam_entry { 1204 union _tcam_entry { 1205 tcam_reg_t regs_e; 1206 tcam_ether_t ether_e; 1207 tcam_ipv4_t ipv4_e; 1208 tcam_ipv6_t ipv6_e; 1209 } key, mask; 1210 tcam_res_t match_action; 1211 } tcam_entry_t; 1212 1213 1214 #define key_reg0 key.regs_e.reg0 1215 #define key_reg1 key.regs_e.reg1 1216 #define key_reg2 key.regs_e.reg2 1217 #define key_reg3 key.regs_e.reg3 1218 #define mask_reg0 mask.regs_e.reg0 1219 #define mask_reg1 mask.regs_e.reg1 1220 #define mask_reg2 mask.regs_e.reg2 1221 #define mask_reg3 mask.regs_e.reg3 1222 1223 1224 #define key0 key.regs_e.reg0 1225 #define key1 key.regs_e.reg1 1226 #define key2 key.regs_e.reg2 1227 #define key3 key.regs_e.reg3 1228 #define mask0 mask.regs_e.reg0 1229 #define mask1 mask.regs_e.reg1 1230 #define mask2 mask.regs_e.reg2 1231 #define mask3 mask.regs_e.reg3 1232 1233 1234 #define ip4_src_key key.ipv4_e.ip_src 1235 #define ip4_dest_key key.ipv4_e.ip_dest 1236 #define ip4_proto_key key.ipv4_e.proto 1237 #define ip4_port_key key.ipv4_e.l4_port_spi 1238 #define ip4_tos_key key.ipv4_e.tos 1239 #define ip4_noport_key key.ipv4_e.noport 1240 #define ip4_nrdc_key key.ipv4_e.l2rdc_tbl_num 1241 #define ip4_class_key key.ipv4_e.cls_code 1242 1243 #define ip4_src_mask mask.ipv4_e.ip_src 1244 #define ip4_dest_mask mask.ipv4_e.ip_dest 1245 #define ip4_proto_mask mask.ipv4_e.proto 1246 #define ip4_port_mask mask.ipv4_e.l4_port_spi 1247 #define ip4_tos_mask mask.ipv4_e.tos 1248 #define ip4_nrdc_mask mask.ipv4_e.l2rdc_tbl_num 1249 #define ip4_noport_mask mask.ipv4_e.noport 1250 #define ip4_class_mask mask.ipv4_e.cls_code 1251 1252 1253 #define ip6_ip_addr_key key.ipv6_e.ip_addr 1254 #define ip6_port_key key.ipv6_e.l4_port_spi 1255 #define ip6_nxt_hdr_key key.ipv6_e.nxt_hdr 1256 #define ip6_tos_key key.ipv6_e.tos 1257 #define ip6_nrdc_key key.ipv6_e.l2rdc_tbl_num 1258 #define ip6_noport_key key.ipv6_e.noport 1259 #define ip6_class_key key.ipv6_e.cls_code 1260 1261 1262 #define ip6_ip_addr_mask mask.ipv6_e.ip_addr 1263 #define ip6_port_mask mask.ipv6_e.l4_port_spi 1264 #define ip6_nxt_hdr_mask mask.ipv6_e.nxt_hdr 1265 #define ip6_tos_mask mask.ipv6_e.tos 1266 #define ip6_nrdc_mask mask.ipv6_e.l2rdc_tbl_num 1267 #define ip6_noport_mask mask.ipv6_e.noport 1268 #define ip6_class_mask mask.ipv6_e.cls_code 1269 1270 #define ether_class_key key.ether_e.cls_code 1271 #define ether_ethframe_key key.ether_e.ethframe 1272 #define ether_class_mask mask.ether_e.cls_code 1273 #define ether_ethframe_mask mask.ether_e.ethframe 1274 1275 1276 /* 1277 * flow template structure 1278 * The flow header is passed through the hash function 1279 * which generates the H1 (and the H2 ) hash value. 1280 * Hash computation is started at the 22 zeros. 1281 * 1282 * Since this structure uses the ip address fields, 1283 * /usr/include/netinet/in.h has to be included 1284 * before this header file. 1285 * Need to move these includes to impl files ... 1286 */ 1287 1288 #include <netinet/in.h> 1289 1290 typedef union flow_template { 1291 1292 struct { 1293 #if defined(_BIG_ENDIAN) 1294 uint32_t l4_0:16; /* src port */ 1295 uint32_t l4_1:16; /* dest Port */ 1296 1297 uint32_t pid:8; 1298 uint32_t port:2; 1299 uint32_t zeros:22; /* 0 */ 1300 1301 union { 1302 struct { 1303 struct in6_addr daddr; 1304 struct in6_addr saddr; 1305 } ip6_addr; 1306 1307 struct { 1308 uint32_t rsrvd1; 1309 struct in_addr daddr; 1310 uint32_t rsrvd2[3]; 1311 struct in_addr saddr; 1312 uint32_t rsrvd5[2]; 1313 } ip4_addr; 1314 } ipaddr; 1315 1316 union { 1317 uint64_t l2_info; 1318 struct { 1319 uint32_t vlan_valid : 4; 1320 uint32_t l2da_1 : 28; 1321 uint32_t l2da_0 : 20; 1322 uint32_t vlanid : 12; 1323 1324 }l2_bits; 1325 }l2; 1326 #else 1327 1328 uint32_t l4_1:16; /* dest Port */ 1329 uint32_t l4_0:16; /* src port */ 1330 1331 uint32_t zeros:22; /* 0 */ 1332 uint32_t port:2; 1333 uint32_t pid:8; 1334 1335 union { 1336 struct { 1337 struct in6_addr daddr; 1338 struct in6_addr saddr; 1339 } ip6_addr; 1340 1341 struct { 1342 uint32_t rsrvd1; 1343 struct in_addr daddr; 1344 uint32_t rsrvd2[3]; 1345 struct in_addr saddr; 1346 uint32_t rsrvd5[2]; 1347 } ip4_addr; 1348 } ipaddr; 1349 1350 union { 1351 uint64_t l2_info; 1352 struct { 1353 1354 uint32_t l2da_1 : 28; 1355 uint32_t vlan_valid : 4; 1356 1357 uint32_t vlanid : 12; 1358 uint32_t l2da_0 : 20; 1359 }l2_bits; 1360 }l2; 1361 #endif 1362 } bits; 1363 1364 } flow_template_t; 1365 1366 1367 1368 #define ip4_saddr bits.ipaddr.ip4_addr.saddr.s_addr 1369 #define ip4_daddr bits.ipaddr.ip4_addr.daddr.s_addr 1370 1371 #define ip_src_port bits.l4_0 1372 #define ip_dst_port bits.l4_1 1373 #define ip_proto bits.pid 1374 1375 #define ip6_saddr bits.ipaddr.ip6_addr.saddr 1376 #define ip6_daddr bits.ipaddr.ip6_addr.daddr 1377 1378 1379 1380 1381 typedef struct _flow_key_cfg_t { 1382 uint32_t rsrvd:23; 1383 uint32_t use_portnum:1; 1384 uint32_t use_l2da:1; 1385 uint32_t use_vlan:1; 1386 uint32_t use_saddr:1; 1387 uint32_t use_daddr:1; 1388 uint32_t use_sport:1; 1389 uint32_t use_dport:1; 1390 uint32_t use_proto:1; 1391 uint32_t ip_opts_exist:1; 1392 } flow_key_cfg_t; 1393 1394 1395 typedef struct _tcam_key_cfg_t { 1396 uint32_t rsrvd:28; 1397 uint32_t use_ip_daddr:1; 1398 uint32_t use_ip_saddr:1; 1399 uint32_t lookup_enable:1; 1400 uint32_t discard:1; 1401 } tcam_key_cfg_t; 1402 1403 1404 1405 /* 1406 * FCRAM Entry Formats 1407 * 1408 * ip6 and ip4 entries, the first 64 bits layouts are identical 1409 * optimistic entry has only 64 bit layout 1410 * The first three bits, fmt, ext and valid are the same 1411 * accoross all the entries 1412 */ 1413 1414 typedef union hash_optim { 1415 uint64_t value; 1416 struct _bits { 1417 #if defined(_BIG_ENDIAN) 1418 uint32_t fmt : 1; /* 63 set to zero */ 1419 uint32_t ext : 1; /* 62 set to zero */ 1420 uint32_t valid : 1; /* 61 */ 1421 uint32_t rdc_offset : 5; /* 60 : 56 */ 1422 uint32_t h2 : 16; /* 55 : 40 */ 1423 uint32_t rsrvd : 8; /* 32 : 32 */ 1424 uint32_t usr_info; /* 31 : 0 */ 1425 #else 1426 uint32_t usr_info; /* 31 : 0 */ 1427 uint32_t rsrvd : 8; /* 39 : 32 */ 1428 uint32_t h2 : 16; /* 55 : 40 */ 1429 uint32_t rdc_offset : 5; /* 60 : 56 */ 1430 uint32_t valid : 1; /* 61 */ 1431 uint32_t ext : 1; /* 62 set to zero */ 1432 uint32_t fmt : 1; /* 63 set to zero */ 1433 #endif 1434 } bits; 1435 } hash_optim_t; 1436 1437 1438 typedef union _hash_hdr { 1439 uint64_t value; 1440 struct _exact_hdr { 1441 #if defined(_BIG_ENDIAN) 1442 uint32_t fmt : 1; /* 63 1 for ipv6, 0 for ipv4 */ 1443 uint32_t ext : 1; /* 62 set to 1 */ 1444 uint32_t valid : 1; /* 61 */ 1445 uint32_t rsrvd : 1; /* 60 */ 1446 uint32_t l2da_1 : 28; /* 59 : 32 */ 1447 uint32_t l2da_0 : 20; /* 31 : 12 */ 1448 uint32_t vlan : 12; /* 12 : 0 */ 1449 #else 1450 uint32_t vlan : 12; /* 12 : 0 */ 1451 uint32_t l2da_0 : 20; /* 31 : 12 */ 1452 uint32_t l2da_1 : 28; /* 59 : 32 */ 1453 uint32_t rsrvd : 1; /* 60 */ 1454 uint32_t valid : 1; /* 61 */ 1455 uint32_t ext : 1; /* 62 set to 1 */ 1456 uint32_t fmt : 1; /* 63 1 for ipv6, 0 for ipv4 */ 1457 #endif 1458 } exact_hdr; 1459 hash_optim_t optim_hdr; 1460 } hash_hdr_t; 1461 1462 1463 1464 typedef union _hash_ports { 1465 uint64_t value; 1466 struct _ports_bits { 1467 #if defined(_BIG_ENDIAN) 1468 uint32_t ip_dport : 16; /* 63 : 48 */ 1469 uint32_t ip_sport : 16; /* 47 : 32 */ 1470 uint32_t proto : 8; /* 31 : 24 */ 1471 uint32_t port : 2; /* 23 : 22 */ 1472 uint32_t rsrvd : 22; /* 21 : 0 */ 1473 #else 1474 uint32_t rsrvd : 22; /* 21 : 0 */ 1475 uint32_t port : 2; /* 23 : 22 */ 1476 uint32_t proto : 8; /* 31 : 24 */ 1477 uint32_t ip_sport : 16; /* 47 : 32 */ 1478 uint32_t ip_dport : 16; /* 63 : 48 */ 1479 #endif 1480 } ports_bits; 1481 } hash_ports_t; 1482 1483 1484 1485 typedef union _hash_match_action { 1486 uint64_t value; 1487 struct _action_bits { 1488 #if defined(_BIG_ENDIAN) 1489 uint32_t rsrvd2 : 3; /* 63 : 61 */ 1490 uint32_t rdc_offset : 5; /* 60 : 56 */ 1491 uint32_t zfvld : 1; /* 55 */ 1492 uint32_t rsrvd : 3; /* 54 : 52 */ 1493 uint32_t zfid : 12; /* 51 : 40 */ 1494 uint32_t _rsrvd : 8; /* 39 : 32 */ 1495 uint32_t usr_info; /* 31 : 0 */ 1496 #else 1497 uint32_t usr_info; /* 31 : 0 */ 1498 uint32_t _rsrvd : 8; /* 39 : 32 */ 1499 uint32_t zfid : 12; /* 51 : 40 */ 1500 uint32_t rsrvd : 3; /* 54 : 52 */ 1501 uint32_t zfvld : 1; /* 55 */ 1502 uint32_t rdc_offset : 5; /* 60 : 56 */ 1503 uint32_t rsrvd2 : 1; /* 63 : 61 */ 1504 #endif 1505 } action_bits; 1506 } hash_match_action_t; 1507 1508 1509 typedef struct _ipaddr6 { 1510 struct in6_addr saddr; 1511 struct in6_addr daddr; 1512 } ip6_addr_t; 1513 1514 1515 typedef struct _ipaddr4 { 1516 #if defined(_BIG_ENDIAN) 1517 struct in_addr saddr; 1518 struct in_addr daddr; 1519 #else 1520 struct in_addr daddr; 1521 struct in_addr saddr; 1522 #endif 1523 } ip4_addr_t; 1524 1525 1526 /* ipv4 has 32 byte layout */ 1527 1528 typedef struct hash_ipv4 { 1529 hash_hdr_t hdr; 1530 ip4_addr_t ip_addr; 1531 hash_ports_t proto_ports; 1532 hash_match_action_t action; 1533 } hash_ipv4_t; 1534 1535 1536 /* ipv4 has 56 byte layout */ 1537 typedef struct hash_ipv6 { 1538 hash_hdr_t hdr; 1539 ip6_addr_t ip_addr; 1540 hash_ports_t proto_ports; 1541 hash_match_action_t action; 1542 } hash_ipv6_t; 1543 1544 1545 1546 typedef union fcram_entry { 1547 uint64_t value[8]; 1548 hash_tbl_data_t dreg[8]; 1549 hash_ipv6_t ipv6_entry; 1550 hash_ipv4_t ipv4_entry; 1551 hash_optim_t optim_entry; 1552 } fcram_entry_t; 1553 1554 1555 1556 #define hash_hdr_fmt ipv4_entry.hdr.exact_hdr.fmt 1557 #define hash_hdr_ext ipv4_entry.hdr.exact_hdr.ext 1558 #define hash_hdr_valid ipv4_entry.hdr.exact_hdr.valid 1559 1560 #define HASH_ENTRY_EXACT(fc) \ 1561 (fc->ipv4_entry.hdr.exact_hdr.ext == 1) 1562 #define HASH_ENTRY_OPTIM(fc) \ 1563 ((fc->ipv4_entry.hdr.exact_hdr.ext == 0) && \ 1564 (fc->ipv6_entry.hdr.exact_hdr.fmt == 0)) 1565 #define HASH_ENTRY_EXACT_IP6(fc) \ 1566 ((fc->ipv6_entry.hdr.exact_hdr.fmt == 1) && \ 1567 (fc->ipv4_entry.hdr.exact_hdr.ext == 1)) 1568 1569 #define HASH_ENTRY_EXACT_IP4(fc) \ 1570 ((fc->ipv6_entry.hdr.exact_hdr.fmt == 0) && \ 1571 (fc->ipv4_entry.hdr.exact_hdr.ext == 1)) 1572 1573 #define HASH_ENTRY_TYPE(fc) \ 1574 (fc->ipv4_entry.hdr.exact_hdr.ext | \ 1575 (fc->ipv4_entry.hdr.exact_hdr.fmt << 1)) 1576 1577 1578 1579 typedef enum fcram_entry_format { 1580 FCRAM_ENTRY_OPTIM = 0x0, 1581 FCRAM_ENTRY_EX_IP4 = 0x2, 1582 FCRAM_ENTRY_EX_IP6 = 0x3, 1583 FCRAM_ENTRY_UNKOWN = 0x1 1584 } fcram_entry_format_t; 1585 1586 1587 #define HASH_ENTRY_TYPE_OPTIM FCRAM_ENTRY_OPTIM 1588 #define HASH_ENTRY_TYPE_OPTIM_IP4 FCRAM_ENTRY_OPTIM 1589 #define HASH_ENTRY_TYPE_OPTIM_IP4 FCRAM_ENTRY_OPTIM 1590 #define HASH_ENTRY_TYPE_EX_IP4 FCRAM_ENTRY_EX_IP4 1591 #define HASH_ENTRY_TYPE_EX_IP6 FCRAM_ENTRY_EX_IP6 1592 1593 1594 1595 1596 /* error xxx formats */ 1597 1598 1599 typedef struct _hash_lookup_err_log { 1600 uint32_t rsrvd:28; 1601 uint32_t lookup_err:1; 1602 uint32_t ecc_err:1; 1603 uint32_t uncor_err:1; 1604 uint32_t multi_lkup:1; 1605 uint32_t multi_bit:1; 1606 uint32_t subarea:3; 1607 uint32_t syndrome:8; 1608 uint32_t h1:20; 1609 } hash_lookup_err_log_t, *p_hash_lookup_err_log_t; 1610 1611 1612 1613 typedef struct _hash_pio_err_log { 1614 uint32_t rsrvd:32; 1615 uint32_t pio_err:1; 1616 uint32_t syndrome:8; 1617 uint32_t addr:23; 1618 } hash_pio_err_log_t, *p_hash_pio_err_log_t; 1619 1620 1621 1622 typedef struct _tcam_err_log { 1623 uint32_t rsrvd:2; 1624 uint32_t tcam_err:1; 1625 uint32_t parity_err:1; 1626 uint32_t ecc_err:1; 1627 uint32_t multi_lkup:1; 1628 uint32_t location:8; 1629 uint32_t syndrome:16; 1630 } tcam_err_log_t, *p_tcam_err_log_t; 1631 1632 1633 typedef struct _vlan_tbl_err_log { 1634 uint32_t rsrvd:32; 1635 uint32_t err:1; 1636 uint32_t multi:1; 1637 uint32_t addr:12; 1638 uint32_t data:18; 1639 } vlan_tbl_err_log_t, *p_vlan_tbl_err_log_t; 1640 1641 1642 #define NEPTUNE_TCAM_SIZE 0x100 1643 #define NIU_TCAM_SIZE 0x80 1644 #define FCRAM_SIZE 0x100000 1645 1646 #ifdef __cplusplus 1647 } 1648 #endif 1649 1650 #endif /* _SYS_NXGE_NXGE_FFLP_HW_H */ 1651