1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_FFLP_HW_H 27 #define _SYS_NXGE_NXGE_FFLP_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 37 38 /* FZC_FFLP Offsets */ 39 #define FFLP_ENET_VLAN_TBL_REG (FZC_FFLP + 0x00000) 40 41 /* defines for FFLP_ENET_VLAN_TBL */ 42 43 #define ENET_VLAN_TBL_VLANRDCTBLN0_MASK 0x0000000000000003ULL 44 #define ENET_VLAN_TBL_VLANRDCTBLN0_SHIFT 0 45 #define ENET_VLAN_TBL_VPR0_MASK 0x00000000000000008ULL 46 #define ENET_VLAN_TBL_VPR0_SHIFT 3 47 48 #define ENET_VLAN_TBL_VLANRDCTBLN1_MASK 0x0000000000000030ULL 49 #define ENET_VLAN_TBL_VLANRDCTBLN1_SHIFT 4 50 #define ENET_VLAN_TBL_VPR1_MASK 0x00000000000000080ULL 51 #define ENET_VLAN_TBL_VPR1_SHIFT 7 52 53 #define ENET_VLAN_TBL_VLANRDCTBLN2_MASK 0x0000000000000300ULL 54 #define ENET_VLAN_TBL_VLANRDCTBLN2_SHIFT 8 55 #define ENET_VLAN_TBL_VPR2_MASK 0x00000000000000800ULL 56 #define ENET_VLAN_TBL_VPR2_SHIFT 11 57 58 #define ENET_VLAN_TBL_VLANRDCTBLN3_MASK 0x0000000000003000ULL 59 #define ENET_VLAN_TBL_VLANRDCTBLN3_SHIFT 12 60 #define ENET_VLAN_TBL_VPR3_MASK 0x0000000000008000ULL 61 #define ENET_VLAN_TBL_VPR3_SHIFT 15 62 63 #define ENET_VLAN_TBL_PARITY0_MASK 0x0000000000010000ULL 64 #define ENET_VLAN_TBL_PARITY0_SHIFT 16 65 #define ENET_VLAN_TBL_PARITY1_MASK 0x0000000000020000ULL 66 #define ENET_VLAN_TBL_PARITY1_SHIFT 17 67 68 69 70 typedef union _fflp_enet_vlan_tbl_t { 71 uint64_t value; 72 struct { 73 #if defined(_BIG_ENDIAN) 74 uint32_t hdw; 75 #endif 76 struct { 77 #ifdef _BIT_FIELDS_HTOL 78 uint32_t rsrvd:14; 79 uint32_t parity1:1; 80 uint32_t parity0:1; 81 uint32_t vpr3:1; 82 uint32_t vlanrdctbln3:3; 83 uint32_t vpr2:1; 84 uint32_t vlanrdctbln2:3; 85 uint32_t vpr1:1; 86 uint32_t vlanrdctbln1:3; 87 uint32_t vpr0:1; 88 uint32_t vlanrdctbln0:3; 89 #else 90 uint32_t vlanrdctbln0:3; 91 uint32_t vpr0:1; 92 uint32_t vlanrdctbln1:3; 93 uint32_t vpr1:1; 94 uint32_t vlanrdctbln2:3; 95 uint32_t vpr2:1; 96 uint32_t vlanrdctbln3:3; 97 uint32_t vpr3:1; 98 uint32_t parity0:1; 99 uint32_t parity1:1; 100 uint32_t rsrvd:14; 101 #endif 102 } ldw; 103 #ifndef _BIG_ENDIAN 104 uint32_t hdw; 105 #endif 106 } bits; 107 } fflp_enet_vlan_tbl_t, *p_fflp_enet_vlan_tbl_t; 108 109 110 #define FFLP_TCAM_CLS_BASE_OFFSET (FZC_FFLP + 0x20000) 111 #define FFLP_L2_CLS_ENET1_REG (FZC_FFLP + 0x20000) 112 #define FFLP_L2_CLS_ENET2_REG (FZC_FFLP + 0x20008) 113 114 115 116 typedef union _tcam_class_prg_ether_t { 117 #define TCAM_ENET_USR_CLASS_ENABLE 0x1 118 #define TCAM_ENET_USR_CLASS_DISABLE 0x0 119 120 uint64_t value; 121 struct { 122 #ifdef _BIG_ENDIAN 123 uint32_t hdw; 124 #endif 125 struct { 126 #ifdef _BIT_FIELDS_HTOL 127 uint32_t rsrvd:15; 128 uint32_t valid:1; 129 uint32_t etype:16; 130 #else 131 uint32_t etype:16; 132 uint32_t valid:1; 133 uint32_t rsrvd:15; 134 #endif 135 } ldw; 136 #ifndef _BIG_ENDIAN 137 uint32_t hdw; 138 #endif 139 } bits; 140 } tcam_class_prg_ether_t, *p_tcam_class_prg_ether_t; 141 142 143 #define FFLP_L3_CLS_IP_U4_REG (FZC_FFLP + 0x20010) 144 #define FFLP_L3_CLS_IP_U5_REG (FZC_FFLP + 0x20018) 145 #define FFLP_L3_CLS_IP_U6_REG (FZC_FFLP + 0x20020) 146 #define FFLP_L3_CLS_IP_U7_REG (FZC_FFLP + 0x20028) 147 148 typedef union _tcam_class_prg_ip_t { 149 #define TCAM_IP_USR_CLASS_ENABLE 0x1 150 #define TCAM_IP_USR_CLASS_DISABLE 0x0 151 152 uint64_t value; 153 struct { 154 #if defined(_BIG_ENDIAN) 155 uint32_t hdw; 156 #endif 157 struct { 158 #ifdef _BIT_FIELDS_HTOL 159 uint32_t rsrvd:6; 160 uint32_t valid:1; 161 uint32_t ipver:1; 162 uint32_t pid:8; 163 uint32_t tosmask:8; 164 uint32_t tos:8; 165 #else 166 uint32_t tos:8; 167 uint32_t tosmask:8; 168 uint32_t pid:8; 169 uint32_t ipver:1; 170 uint32_t valid:1; 171 uint32_t rsrvd:6; 172 #endif 173 } ldw; 174 #ifndef _BIG_ENDIAN 175 uint32_t hdw; 176 #endif 177 } bits; 178 } tcam_class_prg_ip_t, *p_tcam_class_prg_ip_t; 179 /* define the classes which use the above structure */ 180 181 typedef enum fflp_tcam_class { 182 TCAM_CLASS_INVALID = 0, 183 TCAM_CLASS_DUMMY = 1, 184 TCAM_CLASS_ETYPE_1 = 2, 185 TCAM_CLASS_ETYPE_2, 186 TCAM_CLASS_IP_USER_4, 187 TCAM_CLASS_IP_USER_5, 188 TCAM_CLASS_IP_USER_6, 189 TCAM_CLASS_IP_USER_7, 190 TCAM_CLASS_TCP_IPV4, 191 TCAM_CLASS_UDP_IPV4, 192 TCAM_CLASS_AH_ESP_IPV4, 193 TCAM_CLASS_SCTP_IPV4, 194 TCAM_CLASS_TCP_IPV6, 195 TCAM_CLASS_UDP_IPV6, 196 TCAM_CLASS_AH_ESP_IPV6, 197 TCAM_CLASS_SCTP_IPV6, 198 TCAM_CLASS_ARP, 199 TCAM_CLASS_RARP, 200 TCAM_CLASS_DUMMY_12, 201 TCAM_CLASS_DUMMY_13, 202 TCAM_CLASS_DUMMY_14, 203 TCAM_CLASS_DUMMY_15, 204 TCAM_CLASS_MAX 205 } tcam_class_t; 206 207 208 209 /* 210 * Specify how to build TCAM key for L3 211 * IP Classes. Both User configured and 212 * hardwired IP services are included. 213 * These are the supported 12 classes. 214 */ 215 216 #define FFLP_TCAM_KEY_BASE_OFFSET (FZC_FFLP + 0x20030) 217 #define FFLP_TCAM_KEY_IP_USR4_REG (FZC_FFLP + 0x20030) 218 #define FFLP_TCAM_KEY_IP_USR5_REG (FZC_FFLP + 0x20038) 219 #define FFLP_TCAM_KEY_IP_USR6_REG (FZC_FFLP + 0x20040) 220 #define FFLP_TCAM_KEY_IP_USR7_REG (FZC_FFLP + 0x20048) 221 #define FFLP_TCAM_KEY_IP4_TCP_REG (FZC_FFLP + 0x20050) 222 #define FFLP_TCAM_KEY_IP4_UDP_REG (FZC_FFLP + 0x20058) 223 #define FFLP_TCAM_KEY_IP4_AH_ESP_REG (FZC_FFLP + 0x20060) 224 #define FFLP_TCAM_KEY_IP4_SCTP_REG (FZC_FFLP + 0x20068) 225 #define FFLP_TCAM_KEY_IP6_TCP_REG (FZC_FFLP + 0x20070) 226 #define FFLP_TCAM_KEY_IP6_UDP_REG (FZC_FFLP + 0x20078) 227 #define FFLP_TCAM_KEY_IP6_AH_ESP_REG (FZC_FFLP + 0x20080) 228 #define FFLP_TCAM_KEY_IP6_SCTP_REG (FZC_FFLP + 0x20088) 229 230 231 typedef union _tcam_class_key_ip_t { 232 uint64_t value; 233 struct { 234 #if defined(_BIG_ENDIAN) 235 uint32_t hdw; 236 #endif 237 struct { 238 #ifdef _BIT_FIELDS_HTOL 239 uint32_t rsrvd2:28; 240 uint32_t discard:1; 241 uint32_t tsel:1; 242 uint32_t rsrvd:1; 243 uint32_t ipaddr:1; 244 #else 245 uint32_t ipaddr:1; 246 uint32_t rsrvd:1; 247 uint32_t tsel:1; 248 uint32_t discard:1; 249 uint32_t rsrvd2:28; 250 #endif 251 } ldw; 252 #ifndef _BIG_ENDIAN 253 uint32_t hdw; 254 #endif 255 } bits; 256 } tcam_class_key_ip_t, *p_tcam_class_key_ip_t; 257 258 259 260 #define FFLP_TCAM_KEY_0_REG (FZC_FFLP + 0x20090) 261 #define FFLP_TCAM_KEY_1_REG (FZC_FFLP + 0x20098) 262 #define FFLP_TCAM_KEY_2_REG (FZC_FFLP + 0x200A0) 263 #define FFLP_TCAM_KEY_3_REG (FZC_FFLP + 0x200A8) 264 #define FFLP_TCAM_MASK_0_REG (FZC_FFLP + 0x200B0) 265 #define FFLP_TCAM_MASK_1_REG (FZC_FFLP + 0x200B8) 266 #define FFLP_TCAM_MASK_2_REG (FZC_FFLP + 0x200C0) 267 #define FFLP_TCAM_MASK_3_REG (FZC_FFLP + 0x200C8) 268 269 #define FFLP_TCAM_CTL_REG (FZC_FFLP + 0x200D0) 270 271 /* bit defines for FFLP_TCAM_CTL register */ 272 #define TCAM_CTL_TCAM_WR 0x0ULL 273 #define TCAM_CTL_TCAM_RD 0x040000ULL 274 #define TCAM_CTL_TCAM_CMP 0x080000ULL 275 #define TCAM_CTL_RAM_WR 0x100000ULL 276 #define TCAM_CTL_RAM_RD 0x140000ULL 277 #define TCAM_CTL_RWC_STAT 0x0020000ULL 278 #define TCAM_CTL_RWC_MATCH 0x0010000ULL 279 280 281 typedef union _tcam_ctl_t { 282 #define TCAM_CTL_RWC_TCAM_WR 0x0 283 #define TCAM_CTL_RWC_TCAM_RD 0x1 284 #define TCAM_CTL_RWC_TCAM_CMP 0x2 285 #define TCAM_CTL_RWC_RAM_WR 0x4 286 #define TCAM_CTL_RWC_RAM_RD 0x5 287 #define TCAM_CTL_RWC_RWC_STAT 0x1 288 #define TCAM_CTL_RWC_RWC_MATCH 0x1 289 290 uint64_t value; 291 struct { 292 #if defined(_BIG_ENDIAN) 293 uint32_t hdw; 294 #endif 295 struct { 296 #ifdef _BIT_FIELDS_HTOL 297 uint32_t rsrvd2:11; 298 uint32_t rwc:3; 299 uint32_t stat:1; 300 uint32_t match:1; 301 uint32_t rsrvd:6; 302 uint32_t location:10; 303 #else 304 uint32_t location:10; 305 uint32_t rsrvd:6; 306 uint32_t match:1; 307 uint32_t stat:1; 308 uint32_t rwc:3; 309 uint32_t rsrvd2:11; 310 #endif 311 } ldw; 312 #ifndef _BIG_ENDIAN 313 uint32_t hdw; 314 #endif 315 } bits; 316 } tcam_ctl_t, *p_tcam_ctl_t; 317 318 319 320 /* Bit defines for TCAM ASC RAM */ 321 322 323 typedef union _tcam_res_t { 324 uint64_t value; 325 struct { 326 #if defined(_BIG_ENDIAN) 327 struct { 328 uint32_t rsrvd:22; 329 uint32_t syndrome:10; 330 } hdw; 331 #endif 332 struct { 333 #ifdef _BIT_FIELDS_HTOL 334 uint32_t syndrome:6; 335 uint32_t zfid:12; 336 uint32_t v4_ecc_ck:1; 337 uint32_t disc:1; 338 uint32_t tres:2; 339 uint32_t rdctbl:3; 340 uint32_t offset:5; 341 uint32_t zfld:1; 342 uint32_t age:1; 343 #else 344 uint32_t age:1; 345 uint32_t zfld:1; 346 uint32_t offset:5; 347 uint32_t rdctbl:3; 348 uint32_t tres:2; 349 uint32_t disc:1; 350 uint32_t v4_ecc_ck:1; 351 uint32_t zfid:12; 352 uint32_t syndrome:6; 353 #endif 354 } ldw; 355 #ifndef _BIG_ENDIAN 356 struct { 357 uint32_t syndrome:10; 358 uint32_t rsrvd:22; 359 } hdw; 360 #endif 361 } bits; 362 } tcam_res_t, *p_tcam_res_t; 363 364 365 366 #define TCAM_ASC_DATA_AGE 0x0000000000000001ULL 367 #define TCAM_ASC_DATA_AGE_SHIFT 0x0 368 #define TCAM_ASC_DATA_ZFVLD 0x0000000000000002ULL 369 #define TCAM_ASC_DATA_ZFVLD_SHIFT 1 370 371 #define TCAM_ASC_DATA_OFFSET_MASK 0x000000000000007CULL 372 #define TCAM_ASC_DATA_OFFSET_SHIFT 2 373 374 #define TCAM_ASC_DATA_RDCTBL_MASK 0x0000000000000038ULL 375 #define TCAM_ASC_DATA_RDCTBL_SHIFT 7 376 #define TCAM_ASC_DATA_TRES_MASK 0x0000000000000C00ULL 377 #define TRES_CONT_USE_L2RDC 0x00 378 #define TRES_TERM_USE_OFFSET 0x01 379 #define TRES_CONT_OVRD_L2RDC 0x02 380 #define TRES_TERM_OVRD_L2RDC 0x03 381 382 #define TCAM_ASC_DATA_TRES_SHIFT 10 383 #define TCAM_TRES_CONT_USE_L2RDC \ 384 (0x0000000000000000ULL << TCAM_ASC_DATA_TRES_SHIFT) 385 #define TCAM_TRES_TERM_USE_OFFSET \ 386 (0x0000000000000001ULL << TCAM_ASC_DATA_TRES_SHIFT) 387 #define TCAM_TRES_CONT_OVRD_L2RDC \ 388 (0x0000000000000002ULL << TCAM_ASC_DATA_TRES_SHIFT) 389 #define TCAM_TRES_TERM_OVRD_L2RDC \ 390 (0x0000000000000003ULL << TCAM_ASC_DATA_TRES_SHIFT) 391 392 #define TCAM_ASC_DATA_DISC_MASK 0x0000000000001000ULL 393 #define TCAM_ASC_DATA_DISC_SHIFT 12 394 #define TCAM_ASC_DATA_V4_ECC_OK_MASK 0x0000000000002000ULL 395 #define TCAM_ASC_DATA_V4_ECC_OK_SHIFT 13 396 #define TCAM_ASC_DATA_V4_ECC_OK \ 397 (0x0000000000000001ULL << TCAM_ASC_DATA_V4_ECC_OK_MASK_SHIFT) 398 399 #define TCAM_ASC_DATA_ZFID_MASK 0x0000000003FF3000ULL 400 #define TCAM_ASC_DATA_ZFID_SHIFT 14 401 #define TCAM_ASC_DATA_ZFID(value) \ 402 ((value & TCAM_ASC_DATA_ZFID_MASK) >> TCAM_ASC_DATA_ZFID_SHIFT) 403 404 #define TCAM_ASC_DATA_SYNDR_MASK 0x000003FFF3000000ULL 405 #define TCAM_ASC_DATA_SYNDR_SHIFT 26 406 #define TCAM_ASC_DATA_SYNDR(value) \ 407 ((value & TCAM_ASC_DATA_SYNDR_MASK) >> TCAM_ASC_DATA_SYNDR_SHIFT) 408 409 410 /* error registers */ 411 412 #define FFLP_VLAN_PAR_ERR_REG (FZC_FFLP + 0x08000) 413 414 typedef union _vlan_par_err_t { 415 uint64_t value; 416 struct { 417 #if defined(_BIG_ENDIAN) 418 uint32_t hdw; 419 #endif 420 struct { 421 #ifdef _BIT_FIELDS_HTOL 422 uint32_t err:1; 423 uint32_t m_err:1; 424 uint32_t addr:12; 425 uint32_t data:18; 426 #else 427 uint32_t data:18; 428 uint32_t addr:12; 429 uint32_t m_err:1; 430 uint32_t err:1; 431 #endif 432 } ldw; 433 #ifndef _BIG_ENDIAN 434 uint32_t hdw; 435 #endif 436 } bits; 437 } vlan_par_err_t, *p_vlan_par_err_t; 438 439 440 #define FFLP_TCAM_ERR_REG (FZC_FFLP + 0x200D8) 441 442 typedef union _tcam_err_t { 443 uint64_t value; 444 struct { 445 #if defined(_BIG_ENDIAN) 446 uint32_t hdw; 447 #endif 448 struct { 449 #ifdef _BIT_FIELDS_HTOL 450 uint32_t err:1; 451 uint32_t p_ecc:1; 452 uint32_t mult:1; 453 uint32_t rsrvd:5; 454 uint32_t addr:8; 455 uint32_t syndrome:16; 456 #else 457 uint32_t syndrome:16; 458 uint32_t addr:8; 459 uint32_t rsrvd:5; 460 uint32_t mult:1; 461 uint32_t p_ecc:1; 462 uint32_t err:1; 463 #endif 464 } ldw; 465 #ifndef _BIG_ENDIAN 466 uint32_t hdw; 467 #endif 468 } bits; 469 } tcam_err_t, *p_tcam_err_t; 470 471 472 #define TCAM_ERR_SYNDROME_MASK 0x000000000000FFFFULL 473 #define TCAM_ERR_MULT_SHIFT 29 474 #define TCAM_ERR_MULT 0x0000000020000000ULL 475 #define TCAM_ERR_P_ECC 0x0000000040000000ULL 476 #define TCAM_ERR_ERR 0x0000000080000000ULL 477 478 #define HASH_LKUP_ERR_LOG1_REG (FZC_FFLP + 0x200E0) 479 #define HASH_LKUP_ERR_LOG2_REG (FZC_FFLP + 0x200E8) 480 481 482 483 typedef union _hash_lookup_err_log1_t { 484 uint64_t value; 485 struct { 486 #if defined(_BIG_ENDIAN) 487 uint32_t hdw; 488 #endif 489 struct { 490 #ifdef _BIT_FIELDS_HTOL 491 uint32_t rsrvd:28; 492 uint32_t ecc_err:1; 493 uint32_t mult_lk:1; 494 uint32_t cu:1; 495 uint32_t mult_bit:1; 496 #else 497 uint32_t mult_bit:1; 498 uint32_t cu:1; 499 uint32_t mult_lk:1; 500 uint32_t ecc_err:1; 501 uint32_t rsrvd:28; 502 #endif 503 } ldw; 504 #ifndef _BIG_ENDIAN 505 uint32_t hdw; 506 #endif 507 } bits; 508 } hash_lookup_err_log1_t, *p_hash_lookup_err_log1_t; 509 510 511 512 typedef union _hash_lookup_err_log2_t { 513 uint64_t value; 514 struct { 515 #if defined(_BIG_ENDIAN) 516 uint32_t hdw; 517 #endif 518 struct { 519 #ifdef _BIT_FIELDS_HTOL 520 uint32_t rsrvd:1; 521 uint32_t h1:20; 522 uint32_t subarea:3; 523 uint32_t syndrome:8; 524 #else 525 uint32_t syndrome:8; 526 uint32_t subarea:3; 527 uint32_t h1:20; 528 uint32_t rsrvd:1; 529 #endif 530 } ldw; 531 #ifndef _BIG_ENDIAN 532 uint32_t hdw; 533 #endif 534 } bits; 535 } hash_lookup_err_log2_t, *p_hash_lookup_err_log2_t; 536 537 538 539 #define FFLP_FCRAM_ERR_TST0_REG (FZC_FFLP + 0x20128) 540 541 typedef union _fcram_err_tst0_t { 542 uint64_t value; 543 struct { 544 #if defined(_BIG_ENDIAN) 545 uint32_t hdw; 546 #endif 547 struct { 548 #ifdef _BIT_FIELDS_HTOL 549 uint32_t rsrvd:24; 550 uint32_t syndrome_mask:8; 551 #else 552 uint32_t syndrome_mask:10; 553 uint32_t rsrvd:24; 554 #endif 555 } ldw; 556 #ifndef _BIG_ENDIAN 557 uint32_t hdw; 558 #endif 559 } bits; 560 } fcram_err_tst0_t, *p_fcram_err_tst0_t; 561 562 563 #define FFLP_FCRAM_ERR_TST1_REG (FZC_FFLP + 0x20130) 564 #define FFLP_FCRAM_ERR_TST2_REG (FZC_FFLP + 0x20138) 565 566 typedef union _fcram_err_tst_t { 567 uint64_t value; 568 struct { 569 #if defined(_BIG_ENDIAN) 570 struct { 571 uint32_t dat; 572 } hdw; 573 #endif 574 struct { 575 uint32_t dat; 576 } ldw; 577 #ifndef _BIG_ENDIAN 578 struct { 579 uint32_t dat; 580 } hdw; 581 #endif 582 } bits; 583 } fcram_err_tst1_t, *p_fcram_err_tst1_t, 584 fcram_err_tst2_t, *p_fcram_err_tst2_t, 585 fcram_err_data_t, *p_fcram_err_data_t; 586 587 588 589 #define FFLP_ERR_MSK_REG (FZC_FFLP + 0x20140) 590 591 typedef union _fflp_err_mask_t { 592 uint64_t value; 593 struct { 594 #if defined(_BIG_ENDIAN) 595 uint32_t hdw; 596 #endif 597 struct { 598 #ifdef _BIT_FIELDS_HTOL 599 uint32_t rsrvd:21; 600 uint32_t hash_tbl_dat:8; 601 uint32_t hash_tbl_lkup:1; 602 uint32_t tcam:1; 603 uint32_t vlan:1; 604 #else 605 uint32_t vlan:1; 606 uint32_t tcam:1; 607 uint32_t hash_tbl_lkup:1; 608 uint32_t hash_tbl_dat:8; 609 uint32_t rsrvd:21; 610 #endif 611 } ldw; 612 #ifndef _BIG_ENDIAN 613 uint32_t hdw; 614 #endif 615 } bits; 616 } fflp_err_mask_t, *p_fflp_err_mask_t; 617 618 #define FFLP_ERR_VLAN_MASK 0x00000001ULL 619 #define FFLP_ERR_VLAN 0x00000001ULL 620 #define FFLP_ERR_VLAN_SHIFT 0x0 621 622 #define FFLP_ERR_TCAM_MASK 0x00000002ULL 623 #define FFLP_ERR_TCAM 0x00000001ULL 624 #define FFLP_ERR_TCAM_SHIFT 0x1 625 626 #define FFLP_ERR_HASH_TBL_LKUP_MASK 0x00000004ULL 627 #define FFLP_ERR_HASH_TBL_LKUP 0x00000001ULL 628 #define FFLP_ERR_HASH_TBL_LKUP_SHIFT 0x2 629 630 #define FFLP_ERR_HASH_TBL_DAT_MASK 0x00000007F8ULL 631 #define FFLP_ERR_HASH_TBL_DAT 0x0000000FFULL 632 #define FFLP_ERR_HASH_TBL_DAT_SHIFT 0x3 633 634 #define FFLP_ERR_MASK_ALL (FFLP_ERR_VLAN_MASK | FFLP_ERR_TCAM_MASK | \ 635 FFLP_ERR_HASH_TBL_LKUP_MASK | \ 636 FFLP_ERR_HASH_TBL_DAT_MASK) 637 638 639 #define FFLP_CFG_1_REG (FZC_FFLP + 0x20100) 640 641 typedef union _fflp_cfg_1_t { 642 uint64_t value; 643 struct { 644 #if defined(_BIG_ENDIAN) 645 uint32_t hdw; 646 #endif 647 struct { 648 #ifdef _BIT_FIELDS_HTOL 649 uint32_t rsrvd:5; 650 uint32_t tcam_disable:1; 651 uint32_t pio_dbg_sel:3; 652 uint32_t pio_fio_rst:1; 653 uint32_t pio_fio_lat:2; 654 uint32_t camlatency:4; 655 uint32_t camratio:4; 656 uint32_t fcramratio:4; 657 uint32_t fcramoutdr:4; 658 uint32_t fcramqs:1; 659 uint32_t errordis:1; 660 uint32_t fflpinitdone:1; 661 uint32_t llcsnap:1; 662 #else 663 uint32_t llcsnap:1; 664 uint32_t fflpinitdone:1; 665 uint32_t errordis:1; 666 uint32_t fcramqs:1; 667 uint32_t fcramoutdr:4; 668 uint32_t fcramratio:4; 669 uint32_t camratio:4; 670 uint32_t camlatency:4; 671 uint32_t pio_fio_lat:2; 672 uint32_t pio_fio_rst:1; 673 uint32_t pio_dbg_sel:3; 674 uint32_t tcam_disable:1; 675 uint32_t rsrvd:5; 676 #endif 677 } ldw; 678 #ifndef _BIG_ENDIAN 679 uint32_t hdw; 680 #endif 681 } bits; 682 } fflp_cfg_1_t, *p_fflp_cfg_1_t; 683 684 685 typedef enum fflp_fcram_output_drive { 686 FCRAM_OUTDR_NORMAL = 0x0, 687 FCRAM_OUTDR_STRONG = 0x5, 688 FCRAM_OUTDR_WEAK = 0xa 689 } fflp_fcram_output_drive_t; 690 691 692 typedef enum fflp_fcram_qs { 693 FCRAM_QS_MODE_QS = 0x0, 694 FCRAM_QS_MODE_FREE = 0x1 695 } fflp_fcram_qs_t; 696 697 #define FCRAM_PIO_HIGH_PRI 0xf 698 #define FCRAM_PIO_MED_PRI 0xa 699 #define FCRAM_LOOKUP_HIGH_PRI 0x0 700 #define FCRAM_LOOKUP_HIGH_PRI 0x0 701 #define FCRAM_IO_DEFAULT_PRI FCRAM_PIO_MED_PRI 702 703 #define TCAM_PIO_HIGH_PRI 0xf 704 #define TCAM_PIO_MED_PRI 0xa 705 #define TCAM_LOOKUP_HIGH_PRI 0x0 706 #define TCAM_LOOKUP_HIGH_PRI 0x0 707 #define TCAM_IO_DEFAULT_PRI TCAM_PIO_MED_PRI 708 709 #define TCAM_DEFAULT_LATENCY 0x4 710 711 712 #define FFLP_DBG_TRAIN_VCT_REG (FZC_FFLP + 0x20148) 713 714 typedef union _fflp_dbg_train_vct_t { 715 uint64_t value; 716 struct { 717 #if defined(_BIG_ENDIAN) 718 uint32_t hdw; 719 #endif 720 struct { 721 #ifdef _BIT_FIELDS_HTOL 722 uint32_t vector; 723 #else 724 uint32_t vector; 725 #endif 726 } ldw; 727 #ifndef _BIG_ENDIAN 728 uint32_t hdw; 729 #endif 730 } bits; 731 } fflp_dbg_train_vct_t, *p_fflp_dbg_train_vct_t; 732 733 734 735 #define FFLP_TCP_CFLAG_MSK_REG (FZC_FFLP + 0x20108) 736 737 typedef union _tcp_cflag_mask_t { 738 uint64_t value; 739 struct { 740 #if defined(_BIG_ENDIAN) 741 uint32_t hdw; 742 #endif 743 struct { 744 #ifdef _BIT_FIELDS_HTOL 745 uint32_t rsrvd:20; 746 uint32_t mask:12; 747 #else 748 uint32_t mask:12; 749 uint32_t rsrvd:20; 750 #endif 751 } ldw; 752 #ifndef _BIG_ENDIAN 753 uint32_t hdw; 754 #endif 755 } bits; 756 } tcp_cflag_mask_t, *p_tcp_cflag_mask_t; 757 758 759 760 #define FFLP_FCRAM_REF_TMR_REG (FZC_FFLP + 0x20110) 761 762 763 typedef union _fcram_ref_tmr_t { 764 #define FCRAM_REFRESH_DEFAULT_MAX_TIME 0x200 765 #define FCRAM_REFRESH_DEFAULT_MIN_TIME 0x200 766 #define FCRAM_REFRESH_DEFAULT_SYS_TIME 0x200 767 #define FCRAM_REFRESH_MAX_TICK 39 /* usecs */ 768 #define FCRAM_REFRESH_MIN_TICK 400 /* nsecs */ 769 770 uint64_t value; 771 struct { 772 #if defined(_BIG_ENDIAN) 773 uint32_t hdw; 774 #endif 775 struct { 776 #ifdef _BIT_FIELDS_HTOL 777 uint32_t max:16; 778 uint32_t min:16; 779 #else 780 uint32_t min:16; 781 uint32_t max:16; 782 #endif 783 } ldw; 784 #ifndef _BIG_ENDIAN 785 uint32_t hdw; 786 #endif 787 } bits; 788 } fcram_ref_tmr_t, *p_fcram_ref_tmr_t; 789 790 791 792 793 #define FFLP_FCRAM_FIO_ADDR_REG (FZC_FFLP + 0x20118) 794 795 typedef union _fcram_fio_addr_t { 796 uint64_t value; 797 struct { 798 #if defined(_BIG_ENDIAN) 799 uint32_t hdw; 800 #endif 801 struct { 802 #ifdef _BIT_FIELDS_HTOL 803 uint32_t rsrvd:22; 804 uint32_t addr:10; 805 #else 806 uint32_t addr:10; 807 uint32_t rsrvd:22; 808 #endif 809 } ldw; 810 #ifndef _BIG_ENDIAN 811 uint32_t hdw; 812 #endif 813 } bits; 814 } fcram_fio_addr_t, *p_fcram_fio_addr_t; 815 816 817 #define FFLP_FCRAM_FIO_DAT_REG (FZC_FFLP + 0x20120) 818 819 typedef union _fcram_fio_dat_t { 820 uint64_t value; 821 struct { 822 #if defined(_BIG_ENDIAN) 823 uint32_t hdw; 824 #endif 825 struct { 826 #ifdef _BIT_FIELDS_HTOL 827 uint32_t rsrvd:22; 828 uint32_t addr:10; 829 #else 830 uint32_t addr:10; 831 uint32_t rsrvd:22; 832 #endif 833 } ldw; 834 #ifndef _BIG_ENDIAN 835 uint32_t hdw; 836 #endif 837 } bits; 838 } fcram_fio_dat_t, *p_fcram_fio_dat_t; 839 840 841 #define FFLP_FCRAM_PHY_RD_LAT_REG (FZC_FFLP + 0x20150) 842 843 typedef union _fcram_phy_rd_lat_t { 844 uint64_t value; 845 struct { 846 #if defined(_BIG_ENDIAN) 847 uint32_t hdw; 848 #endif 849 struct { 850 #ifdef _BIT_FIELDS_HTOL 851 uint32_t rsrvd:24; 852 uint32_t lat:8; 853 #else 854 uint32_t lat:8; 855 uint32_t rsrvd:24; 856 #endif 857 } ldw; 858 #ifndef _BIG_ENDIAN 859 uint32_t hdw; 860 #endif 861 } bits; 862 } fcram_phy_rd_lat_t, *p_fcram_phy_rd_lat_t; 863 864 865 /* 866 * Specify how to build a flow key for IP 867 * classes, both programmable and hardwired 868 */ 869 #define FFLP_FLOW_KEY_BASE_OFFSET (FZC_FFLP + 0x40000) 870 #define FFLP_FLOW_KEY_IP_USR4_REG (FZC_FFLP + 0x40000) 871 #define FFLP_FLOW_KEY_IP_USR5_REG (FZC_FFLP + 0x40008) 872 #define FFLP_FLOW_KEY_IP_USR6_REG (FZC_FFLP + 0x40010) 873 #define FFLP_FLOW_KEY_IP_USR7_REG (FZC_FFLP + 0x40018) 874 #define FFLP_FLOW_KEY_IP4_TCP_REG (FZC_FFLP + 0x40020) 875 #define FFLP_FLOW_KEY_IP4_UDP_REG (FZC_FFLP + 0x40028) 876 #define FFLP_FLOW_KEY_IP4_AH_ESP_REG (FZC_FFLP + 0x40030) 877 #define FFLP_FLOW_KEY_IP4_SCTP_REG (FZC_FFLP + 0x40038) 878 #define FFLP_FLOW_KEY_IP6_TCP_REG (FZC_FFLP + 0x40040) 879 #define FFLP_FLOW_KEY_IP6_UDP_REG (FZC_FFLP + 0x40048) 880 #define FFLP_FLOW_KEY_IP6_AH_ESP_REG (FZC_FFLP + 0x40050) 881 #define FFLP_FLOW_KEY_IP6_SCTP_REG (FZC_FFLP + 0x40058) 882 883 typedef union _flow_class_key_ip_t { 884 uint64_t value; 885 struct { 886 #if defined(_BIG_ENDIAN) 887 uint32_t hdw; 888 #endif 889 struct { 890 #ifdef _BIT_FIELDS_HTOL 891 uint32_t rsrvd2:22; 892 uint32_t port:1; 893 uint32_t l2da:1; 894 uint32_t vlan:1; 895 uint32_t ipsa:1; 896 uint32_t ipda:1; 897 uint32_t proto:1; 898 uint32_t l4_0:2; 899 uint32_t l4_1:2; 900 #else 901 uint32_t l4_1:2; 902 uint32_t l4_0:2; 903 uint32_t proto:1; 904 uint32_t ipda:1; 905 uint32_t ipsa:1; 906 uint32_t vlan:1; 907 uint32_t l2da:1; 908 uint32_t port:1; 909 uint32_t rsrvd2:22; 910 #endif 911 } ldw; 912 #ifndef _BIG_ENDIAN 913 uint32_t hdw; 914 #endif 915 } bits; 916 } flow_class_key_ip_t, *p_flow_class_key_ip_t; 917 918 919 #define FFLP_H1POLY_REG (FZC_FFLP + 0x40060) 920 921 922 typedef union _hash_h1poly_t { 923 uint64_t value; 924 struct { 925 #if defined(_BIG_ENDIAN) 926 uint32_t hdw; 927 #endif 928 struct { 929 uint32_t init_value; 930 } ldw; 931 #ifndef _BIG_ENDIAN 932 uint32_t hdw; 933 #endif 934 } bits; 935 } hash_h1poly_t, *p_hash_h1poly_t; 936 937 #define FFLP_H2POLY_REG (FZC_FFLP + 0x40068) 938 939 typedef union _hash_h2poly_t { 940 uint64_t value; 941 struct { 942 #if defined(_BIG_ENDIAN) 943 uint32_t hdw; 944 #endif 945 struct { 946 #ifdef _BIT_FIELDS_HTOL 947 uint32_t rsrvd:16; 948 uint32_t init_value:16; 949 #else 950 uint32_t init_value:16; 951 uint32_t rsrvd:16; 952 #endif 953 } ldw; 954 #ifndef _BIG_ENDIAN 955 uint32_t hdw; 956 #endif 957 } bits; 958 } hash_h2poly_t, *p_hash_h2poly_t; 959 960 #define FFLP_FLW_PRT_SEL_REG (FZC_FFLP + 0x40070) 961 962 963 typedef union _flow_prt_sel_t { 964 #define FFLP_FCRAM_MAX_PARTITION 8 965 uint64_t value; 966 struct { 967 #if defined(_BIG_ENDIAN) 968 uint32_t hdw; 969 #endif 970 struct { 971 #ifdef _BIT_FIELDS_HTOL 972 uint32_t rsrvd3:15; 973 uint32_t ext:1; 974 uint32_t rsrvd2:3; 975 uint32_t mask:5; 976 uint32_t rsrvd:3; 977 uint32_t base:5; 978 #else 979 uint32_t base:5; 980 uint32_t rsrvd:3; 981 uint32_t mask:5; 982 uint32_t rsrvd2:3; 983 uint32_t ext:1; 984 uint32_t rsrvd3:15; 985 #endif 986 } ldw; 987 #ifndef _BIG_ENDIAN 988 uint32_t hdw; 989 #endif 990 } bits; 991 } flow_prt_sel_t, *p_flow_prt_sel_t; 992 993 994 995 /* FFLP Offsets */ 996 997 998 #define FFLP_HASH_TBL_ADDR_REG (FFLP + 0x00000) 999 1000 typedef union _hash_tbl_addr_t { 1001 uint64_t value; 1002 struct { 1003 #if defined(_BIG_ENDIAN) 1004 uint32_t hdw; 1005 #endif 1006 struct { 1007 #ifdef _BIT_FIELDS_HTOL 1008 uint32_t rsrvd:8; 1009 uint32_t autoinc:1; 1010 uint32_t addr:23; 1011 #else 1012 uint32_t addr:23; 1013 uint32_t autoinc:1; 1014 uint32_t rsrvd:8; 1015 #endif 1016 } ldw; 1017 #ifndef _BIG_ENDIAN 1018 uint32_t hdw; 1019 #endif 1020 } bits; 1021 } hash_tbl_addr_t, *p_hash_tbl_addr_t; 1022 1023 1024 #define FFLP_HASH_TBL_DATA_REG (FFLP + 0x00008) 1025 1026 typedef union _hash_tbl_data_t { 1027 uint64_t value; 1028 struct { 1029 #ifdef _BIG_ENDIAN 1030 uint32_t hdw; 1031 uint32_t ldw; 1032 #else 1033 uint32_t ldw; 1034 uint32_t hdw; 1035 #endif 1036 } bits; 1037 } hash_tbl_data_t, *p_hash_tbl_data_t; 1038 1039 1040 #define FFLP_HASH_TBL_DATA_LOG_REG (FFLP + 0x00010) 1041 1042 1043 typedef union _hash_tbl_data_log_t { 1044 uint64_t value; 1045 struct { 1046 #if defined(_BIG_ENDIAN) 1047 uint32_t hdw; 1048 #endif 1049 struct { 1050 #ifdef _BIT_FIELDS_HTOL 1051 uint32_t pio_err:1; 1052 uint32_t fcram_addr:23; 1053 uint32_t syndrome:8; 1054 #else 1055 uint32_t syndrome:8; 1056 uint32_t fcram_addr:23; 1057 uint32_t pio_err:1; 1058 #endif 1059 } ldw; 1060 #ifndef _BIG_ENDIAN 1061 uint32_t hdw; 1062 #endif 1063 } bits; 1064 } hash_tbl_data_log_t, *p_hash_tbl_data_log_t; 1065 1066 1067 1068 #define REG_PIO_WRITE64(handle, offset, value) \ 1069 NXGE_REG_WR64((handle), (offset), (value)) 1070 #define REG_PIO_READ64(handle, offset, val_p) \ 1071 NXGE_REG_RD64((handle), (offset), (val_p)) 1072 1073 1074 #define WRITE_TCAM_REG_CTL(handle, ctl) \ 1075 REG_PIO_WRITE64(handle, FFLP_TCAM_CTL_REG, ctl) 1076 1077 #define READ_TCAM_REG_CTL(handle, val_p) \ 1078 REG_PIO_READ64(handle, FFLP_TCAM_CTL_REG, val_p) 1079 1080 1081 #define WRITE_TCAM_REG_KEY0(handle, key) \ 1082 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_0_REG, key) 1083 #define WRITE_TCAM_REG_KEY1(handle, key) \ 1084 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_1_REG, key) 1085 #define WRITE_TCAM_REG_KEY2(handle, key) \ 1086 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_2_REG, key) 1087 #define WRITE_TCAM_REG_KEY3(handle, key) \ 1088 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_3_REG, key) 1089 #define WRITE_TCAM_REG_MASK0(handle, mask) \ 1090 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_0_REG, mask) 1091 #define WRITE_TCAM_REG_MASK1(handle, mask) \ 1092 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_1_REG, mask) 1093 #define WRITE_TCAM_REG_MASK2(handle, mask) \ 1094 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_2_REG, mask) 1095 #define WRITE_TCAM_REG_MASK3(handle, mask) \ 1096 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_3_REG, mask) 1097 1098 #define READ_TCAM_REG_KEY0(handle, val_p) \ 1099 REG_PIO_READ64(handle, FFLP_TCAM_KEY_0_REG, val_p) 1100 #define READ_TCAM_REG_KEY1(handle, val_p) \ 1101 REG_PIO_READ64(handle, FFLP_TCAM_KEY_1_REG, val_p) 1102 #define READ_TCAM_REG_KEY2(handle, val_p) \ 1103 REG_PIO_READ64(handle, FFLP_TCAM_KEY_2_REG, val_p) 1104 #define READ_TCAM_REG_KEY3(handle, val_p) \ 1105 REG_PIO_READ64(handle, FFLP_TCAM_KEY_3_REG, val_p) 1106 #define READ_TCAM_REG_MASK0(handle, val_p) \ 1107 REG_PIO_READ64(handle, FFLP_TCAM_MASK_0_REG, val_p) 1108 #define READ_TCAM_REG_MASK1(handle, val_p) \ 1109 REG_PIO_READ64(handle, FFLP_TCAM_MASK_1_REG, val_p) 1110 #define READ_TCAM_REG_MASK2(handle, val_p) \ 1111 REG_PIO_READ64(handle, FFLP_TCAM_MASK_2_REG, val_p) 1112 #define READ_TCAM_REG_MASK3(handle, val_p) \ 1113 REG_PIO_READ64(handle, FFLP_TCAM_MASK_3_REG, val_p) 1114 1115 1116 1117 1118 typedef struct tcam_ipv4 { 1119 #if defined(_BIG_ENDIAN) 1120 uint32_t reserved6; /* 255 : 224 */ 1121 uint32_t reserved5 : 24; /* 223 : 200 */ 1122 uint32_t cls_code : 5; /* 199 : 195 */ 1123 uint32_t reserved4 : 3; /* 194 : 192 */ 1124 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1125 uint32_t noport : 1; /* 186 */ 1126 uint32_t reserved3 : 26; /* 185: 160 */ 1127 uint32_t reserved2; /* 159: 128 */ 1128 uint32_t reserved : 16; /* 127 : 112 */ 1129 uint32_t tos : 8; /* 111 : 104 */ 1130 uint32_t proto : 8; /* 103 : 96 */ 1131 uint32_t l4_port_spi; /* 95 : 64 */ 1132 uint32_t ip_src; /* 63 : 32 */ 1133 uint32_t ip_dest; /* 31 : 0 */ 1134 #else 1135 uint32_t ip_dest; /* 31 : 0 */ 1136 uint32_t ip_src; /* 63 : 32 */ 1137 uint32_t l4_port_spi; /* 95 : 64 */ 1138 uint32_t proto : 8; /* 103 : 96 */ 1139 uint32_t tos : 8; /* 111 : 104 */ 1140 uint32_t reserved : 16; /* 127 : 112 */ 1141 uint32_t reserved2; /* 159: 128 */ 1142 uint32_t reserved3 : 26; /* 185: 160 */ 1143 uint32_t noport : 1; /* 186 */ 1144 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1145 uint32_t reserved4 : 3; /* 194 : 192 */ 1146 uint32_t cls_code : 5; /* 199 : 195 */ 1147 uint32_t reserved5 : 24; /* 223 : 200 */ 1148 uint32_t reserved6; /* 255 : 224 */ 1149 #endif 1150 } tcam_ipv4_t; 1151 1152 1153 1154 typedef struct tcam_reg { 1155 #if defined(_BIG_ENDIAN) 1156 uint64_t reg0; 1157 uint64_t reg1; 1158 uint64_t reg2; 1159 uint64_t reg3; 1160 #else 1161 uint64_t reg3; 1162 uint64_t reg2; 1163 uint64_t reg1; 1164 uint64_t reg0; 1165 #endif 1166 } tcam_reg_t; 1167 1168 1169 typedef struct tcam_ether { 1170 #if defined(_BIG_ENDIAN) 1171 uint8_t reserved3[7]; /* 255 : 200 */ 1172 uint8_t cls_code : 5; /* 199 : 195 */ 1173 uint8_t reserved2 : 3; /* 194 : 192 */ 1174 uint8_t ethframe[11]; /* 191 : 104 */ 1175 uint8_t reserved[13]; /* 103 : 0 */ 1176 #else 1177 uint8_t reserved[13]; /* 103 : 0 */ 1178 uint8_t ethframe[11]; /* 191 : 104 */ 1179 uint8_t reserved2 : 3; /* 194 : 192 */ 1180 uint8_t cls_code : 5; /* 199 : 195 */ 1181 uint8_t reserved3[7]; /* 255 : 200 */ 1182 #endif 1183 } tcam_ether_t; 1184 1185 1186 typedef struct tcam_ipv6 { 1187 #if defined(_BIG_ENDIAN) 1188 uint32_t reserved4; /* 255 : 224 */ 1189 uint32_t reserved3 : 24; /* 223 : 200 */ 1190 uint32_t cls_code : 5; /* 199 : 195 */ 1191 uint32_t reserved2 : 3; /* 194 : 192 */ 1192 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1193 uint32_t noport : 1; /* 186 */ 1194 uint32_t reserved : 10; /* 185 : 176 */ 1195 uint32_t tos : 8; /* 175 : 168 */ 1196 uint32_t nxt_hdr : 8; /* 167 : 160 */ 1197 uint32_t l4_port_spi; /* 159 : 128 */ 1198 uint32_t ip_addr[4]; /* 127 : 0 */ 1199 #else 1200 uint32_t ip_addr[4]; /* 127 : 0 */ 1201 uint32_t l4_port_spi; /* 159 : 128 */ 1202 uint32_t nxt_hdr : 8; /* 167 : 160 */ 1203 uint32_t tos : 8; /* 175 : 168 */ 1204 uint32_t reserved : 10; /* 185 : 176 */ 1205 uint32_t noport : 1; /* 186 */ 1206 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 1207 uint32_t reserved2 : 3; /* 194 : 192 */ 1208 uint32_t cls_code : 5; /* 199 : 195 */ 1209 uint32_t reserved3 : 24; /* 223 : 200 */ 1210 uint32_t reserved4; /* 255 : 224 */ 1211 #endif 1212 } tcam_ipv6_t; 1213 1214 1215 typedef struct tcam_entry { 1216 union _tcam_entry { 1217 tcam_reg_t regs_e; 1218 tcam_ether_t ether_e; 1219 tcam_ipv4_t ipv4_e; 1220 tcam_ipv6_t ipv6_e; 1221 } key, mask; 1222 tcam_res_t match_action; 1223 } tcam_entry_t; 1224 1225 1226 #define key_reg0 key.regs_e.reg0 1227 #define key_reg1 key.regs_e.reg1 1228 #define key_reg2 key.regs_e.reg2 1229 #define key_reg3 key.regs_e.reg3 1230 #define mask_reg0 mask.regs_e.reg0 1231 #define mask_reg1 mask.regs_e.reg1 1232 #define mask_reg2 mask.regs_e.reg2 1233 #define mask_reg3 mask.regs_e.reg3 1234 1235 1236 #define key0 key.regs_e.reg0 1237 #define key1 key.regs_e.reg1 1238 #define key2 key.regs_e.reg2 1239 #define key3 key.regs_e.reg3 1240 #define mask0 mask.regs_e.reg0 1241 #define mask1 mask.regs_e.reg1 1242 #define mask2 mask.regs_e.reg2 1243 #define mask3 mask.regs_e.reg3 1244 1245 1246 #define ip4_src_key key.ipv4_e.ip_src 1247 #define ip4_dest_key key.ipv4_e.ip_dest 1248 #define ip4_proto_key key.ipv4_e.proto 1249 #define ip4_port_key key.ipv4_e.l4_port_spi 1250 #define ip4_tos_key key.ipv4_e.tos 1251 #define ip4_noport_key key.ipv4_e.noport 1252 #define ip4_nrdc_key key.ipv4_e.l2rdc_tbl_num 1253 #define ip4_class_key key.ipv4_e.cls_code 1254 1255 #define ip4_src_mask mask.ipv4_e.ip_src 1256 #define ip4_dest_mask mask.ipv4_e.ip_dest 1257 #define ip4_proto_mask mask.ipv4_e.proto 1258 #define ip4_port_mask mask.ipv4_e.l4_port_spi 1259 #define ip4_tos_mask mask.ipv4_e.tos 1260 #define ip4_nrdc_mask mask.ipv4_e.l2rdc_tbl_num 1261 #define ip4_noport_mask mask.ipv4_e.noport 1262 #define ip4_class_mask mask.ipv4_e.cls_code 1263 1264 1265 #define ip6_ip_addr_key key.ipv6_e.ip_addr 1266 #define ip6_port_key key.ipv6_e.l4_port_spi 1267 #define ip6_nxt_hdr_key key.ipv6_e.nxt_hdr 1268 #define ip6_tos_key key.ipv6_e.tos 1269 #define ip6_nrdc_key key.ipv6_e.l2rdc_tbl_num 1270 #define ip6_noport_key key.ipv6_e.noport 1271 #define ip6_class_key key.ipv6_e.cls_code 1272 1273 1274 #define ip6_ip_addr_mask mask.ipv6_e.ip_addr 1275 #define ip6_port_mask mask.ipv6_e.l4_port_spi 1276 #define ip6_nxt_hdr_mask mask.ipv6_e.nxt_hdr 1277 #define ip6_tos_mask mask.ipv6_e.tos 1278 #define ip6_nrdc_mask mask.ipv6_e.l2rdc_tbl_num 1279 #define ip6_noport_mask mask.ipv6_e.noport 1280 #define ip6_class_mask mask.ipv6_e.cls_code 1281 1282 #define ether_class_key key.ether_e.cls_code 1283 #define ether_ethframe_key key.ether_e.ethframe 1284 #define ether_class_mask mask.ether_e.cls_code 1285 #define ether_ethframe_mask mask.ether_e.ethframe 1286 1287 1288 /* 1289 * flow template structure 1290 * The flow header is passed through the hash function 1291 * which generates the H1 (and the H2 ) hash value. 1292 * Hash computation is started at the 22 zeros. 1293 * 1294 * Since this structure uses the ip address fields, 1295 * /usr/include/netinet/in.h has to be included 1296 * before this header file. 1297 * Need to move these includes to impl files ... 1298 */ 1299 1300 #if defined(SOLARIS) || defined(COSIM) 1301 #include <netinet/in.h> 1302 #endif 1303 1304 typedef union flow_template { 1305 1306 struct { 1307 #if defined(_BIG_ENDIAN) 1308 uint32_t l4_0:16; /* src port */ 1309 uint32_t l4_1:16; /* dest Port */ 1310 1311 uint32_t pid:8; 1312 uint32_t port:2; 1313 uint32_t zeros:22; /* 0 */ 1314 1315 union { 1316 struct { 1317 struct in6_addr daddr; 1318 struct in6_addr saddr; 1319 } ip6_addr; 1320 1321 struct { 1322 uint32_t rsrvd1; 1323 struct in_addr daddr; 1324 uint32_t rsrvd2[3]; 1325 struct in_addr saddr; 1326 uint32_t rsrvd5[2]; 1327 } ip4_addr; 1328 } ipaddr; 1329 1330 union { 1331 uint64_t l2_info; 1332 struct { 1333 uint32_t vlan_valid : 4; 1334 uint32_t l2da_1 : 28; 1335 uint32_t l2da_0 : 20; 1336 uint32_t vlanid : 12; 1337 1338 }l2_bits; 1339 }l2; 1340 #else 1341 1342 uint32_t l4_1:16; /* dest Port */ 1343 uint32_t l4_0:16; /* src port */ 1344 1345 uint32_t zeros:22; /* 0 */ 1346 uint32_t port:2; 1347 uint32_t pid:8; 1348 1349 union { 1350 struct { 1351 struct in6_addr daddr; 1352 struct in6_addr saddr; 1353 } ip6_addr; 1354 1355 struct { 1356 uint32_t rsrvd1; 1357 struct in_addr daddr; 1358 uint32_t rsrvd2[3]; 1359 struct in_addr saddr; 1360 uint32_t rsrvd5[2]; 1361 } ip4_addr; 1362 } ipaddr; 1363 1364 union { 1365 uint64_t l2_info; 1366 struct { 1367 1368 uint32_t l2da_1 : 28; 1369 uint32_t vlan_valid : 4; 1370 1371 uint32_t vlanid : 12; 1372 uint32_t l2da_0 : 20; 1373 }l2_bits; 1374 }l2; 1375 #endif 1376 } bits; 1377 1378 } flow_template_t; 1379 1380 1381 1382 #define ip4_saddr bits.ipaddr.ip4_addr.saddr.s_addr 1383 #define ip4_daddr bits.ipaddr.ip4_addr.daddr.s_addr 1384 1385 #define ip_src_port bits.l4_0 1386 #define ip_dst_port bits.l4_1 1387 #define ip_proto bits.pid 1388 1389 #define ip6_saddr bits.ipaddr.ip6_addr.saddr 1390 #define ip6_daddr bits.ipaddr.ip6_addr.daddr 1391 1392 1393 1394 1395 typedef struct _flow_key_cfg_t { 1396 uint32_t rsrvd:23; 1397 uint32_t use_portnum:1; 1398 uint32_t use_l2da:1; 1399 uint32_t use_vlan:1; 1400 uint32_t use_saddr:1; 1401 uint32_t use_daddr:1; 1402 uint32_t use_sport:1; 1403 uint32_t use_dport:1; 1404 uint32_t use_proto:1; 1405 uint32_t ip_opts_exist:1; 1406 } flow_key_cfg_t; 1407 1408 1409 typedef struct _tcam_key_cfg_t { 1410 uint32_t rsrvd:28; 1411 uint32_t use_ip_daddr:1; 1412 uint32_t use_ip_saddr:1; 1413 uint32_t lookup_enable:1; 1414 uint32_t discard:1; 1415 } tcam_key_cfg_t; 1416 1417 1418 1419 /* 1420 * FCRAM Entry Formats 1421 * 1422 * ip6 and ip4 entries, the first 64 bits layouts are identical 1423 * optimistic entry has only 64 bit layout 1424 * The first three bits, fmt, ext and valid are the same 1425 * accoross all the entries 1426 */ 1427 1428 typedef union hash_optim { 1429 uint64_t value; 1430 struct _bits { 1431 #if defined(_BIG_ENDIAN) 1432 uint32_t fmt : 1; /* 63 set to zero */ 1433 uint32_t ext : 1; /* 62 set to zero */ 1434 uint32_t valid : 1; /* 61 */ 1435 uint32_t rdc_offset : 5; /* 60 : 56 */ 1436 uint32_t h2 : 16; /* 55 : 40 */ 1437 uint32_t rsrvd : 8; /* 32 : 32 */ 1438 uint32_t usr_info; /* 31 : 0 */ 1439 #else 1440 uint32_t usr_info; /* 31 : 0 */ 1441 uint32_t rsrvd : 8; /* 39 : 32 */ 1442 uint32_t h2 : 16; /* 55 : 40 */ 1443 uint32_t rdc_offset : 5; /* 60 : 56 */ 1444 uint32_t valid : 1; /* 61 */ 1445 uint32_t ext : 1; /* 62 set to zero */ 1446 uint32_t fmt : 1; /* 63 set to zero */ 1447 #endif 1448 } bits; 1449 } hash_optim_t; 1450 1451 1452 typedef union _hash_hdr { 1453 uint64_t value; 1454 struct _exact_hdr { 1455 #if defined(_BIG_ENDIAN) 1456 uint32_t fmt : 1; /* 63 1 for ipv6, 0 for ipv4 */ 1457 uint32_t ext : 1; /* 62 set to 1 */ 1458 uint32_t valid : 1; /* 61 */ 1459 uint32_t rsrvd : 1; /* 60 */ 1460 uint32_t l2da_1 : 28; /* 59 : 32 */ 1461 uint32_t l2da_0 : 20; /* 31 : 12 */ 1462 uint32_t vlan : 12; /* 12 : 0 */ 1463 #else 1464 uint32_t vlan : 12; /* 12 : 0 */ 1465 uint32_t l2da_0 : 20; /* 31 : 12 */ 1466 uint32_t l2da_1 : 28; /* 59 : 32 */ 1467 uint32_t rsrvd : 1; /* 60 */ 1468 uint32_t valid : 1; /* 61 */ 1469 uint32_t ext : 1; /* 62 set to 1 */ 1470 uint32_t fmt : 1; /* 63 1 for ipv6, 0 for ipv4 */ 1471 #endif 1472 } exact_hdr; 1473 hash_optim_t optim_hdr; 1474 } hash_hdr_t; 1475 1476 1477 1478 typedef union _hash_ports { 1479 uint64_t value; 1480 struct _ports_bits { 1481 #if defined(_BIG_ENDIAN) 1482 uint32_t ip_dport : 16; /* 63 : 48 */ 1483 uint32_t ip_sport : 16; /* 47 : 32 */ 1484 uint32_t proto : 8; /* 31 : 24 */ 1485 uint32_t port : 2; /* 23 : 22 */ 1486 uint32_t rsrvd : 22; /* 21 : 0 */ 1487 #else 1488 uint32_t rsrvd : 22; /* 21 : 0 */ 1489 uint32_t port : 2; /* 23 : 22 */ 1490 uint32_t proto : 8; /* 31 : 24 */ 1491 uint32_t ip_sport : 16; /* 47 : 32 */ 1492 uint32_t ip_dport : 16; /* 63 : 48 */ 1493 #endif 1494 } ports_bits; 1495 } hash_ports_t; 1496 1497 1498 1499 typedef union _hash_match_action { 1500 uint64_t value; 1501 struct _action_bits { 1502 #if defined(_BIG_ENDIAN) 1503 uint32_t rsrvd2 : 3; /* 63 : 61 */ 1504 uint32_t rdc_offset : 5; /* 60 : 56 */ 1505 uint32_t zfvld : 1; /* 55 */ 1506 uint32_t rsrvd : 3; /* 54 : 52 */ 1507 uint32_t zfid : 12; /* 51 : 40 */ 1508 uint32_t _rsrvd : 8; /* 39 : 32 */ 1509 uint32_t usr_info; /* 31 : 0 */ 1510 #else 1511 uint32_t usr_info; /* 31 : 0 */ 1512 uint32_t _rsrvd : 8; /* 39 : 32 */ 1513 uint32_t zfid : 12; /* 51 : 40 */ 1514 uint32_t rsrvd : 3; /* 54 : 52 */ 1515 uint32_t zfvld : 1; /* 55 */ 1516 uint32_t rdc_offset : 5; /* 60 : 56 */ 1517 uint32_t rsrvd2 : 1; /* 63 : 61 */ 1518 #endif 1519 } action_bits; 1520 } hash_match_action_t; 1521 1522 1523 typedef struct _ipaddr6 { 1524 struct in6_addr saddr; 1525 struct in6_addr daddr; 1526 } ip6_addr_t; 1527 1528 1529 typedef struct _ipaddr4 { 1530 #if defined(_BIG_ENDIAN) 1531 struct in_addr saddr; 1532 struct in_addr daddr; 1533 #else 1534 struct in_addr daddr; 1535 struct in_addr saddr; 1536 #endif 1537 } ip4_addr_t; 1538 1539 1540 /* ipv4 has 32 byte layout */ 1541 1542 typedef struct hash_ipv4 { 1543 hash_hdr_t hdr; 1544 ip4_addr_t ip_addr; 1545 hash_ports_t proto_ports; 1546 hash_match_action_t action; 1547 } hash_ipv4_t; 1548 1549 1550 /* ipv4 has 56 byte layout */ 1551 typedef struct hash_ipv6 { 1552 hash_hdr_t hdr; 1553 ip6_addr_t ip_addr; 1554 hash_ports_t proto_ports; 1555 hash_match_action_t action; 1556 } hash_ipv6_t; 1557 1558 1559 1560 typedef union fcram_entry { 1561 uint64_t value[8]; 1562 hash_tbl_data_t dreg[8]; 1563 hash_ipv6_t ipv6_entry; 1564 hash_ipv4_t ipv4_entry; 1565 hash_optim_t optim_entry; 1566 } fcram_entry_t; 1567 1568 1569 1570 #define hash_hdr_fmt ipv4_entry.hdr.exact_hdr.fmt 1571 #define hash_hdr_ext ipv4_entry.hdr.exact_hdr.ext 1572 #define hash_hdr_valid ipv4_entry.hdr.exact_hdr.valid 1573 1574 #define HASH_ENTRY_EXACT(fc) \ 1575 (fc->ipv4_entry.hdr.exact_hdr.ext == 1) 1576 #define HASH_ENTRY_OPTIM(fc) \ 1577 ((fc->ipv4_entry.hdr.exact_hdr.ext == 0) && \ 1578 (fc->ipv6_entry.hdr.exact_hdr.fmt == 0)) 1579 #define HASH_ENTRY_EXACT_IP6(fc) \ 1580 ((fc->ipv6_entry.hdr.exact_hdr.fmt == 1) && \ 1581 (fc->ipv4_entry.hdr.exact_hdr.ext == 1)) 1582 1583 #define HASH_ENTRY_EXACT_IP4(fc) \ 1584 ((fc->ipv6_entry.hdr.exact_hdr.fmt == 0) && \ 1585 (fc->ipv4_entry.hdr.exact_hdr.ext == 1)) 1586 1587 #define HASH_ENTRY_TYPE(fc) \ 1588 (fc->ipv4_entry.hdr.exact_hdr.ext | \ 1589 (fc->ipv4_entry.hdr.exact_hdr.fmt << 1)) 1590 1591 1592 1593 typedef enum fcram_entry_format { 1594 FCRAM_ENTRY_OPTIM = 0x0, 1595 FCRAM_ENTRY_EX_IP4 = 0x2, 1596 FCRAM_ENTRY_EX_IP6 = 0x3, 1597 FCRAM_ENTRY_UNKOWN = 0x1 1598 } fcram_entry_format_t; 1599 1600 1601 #define HASH_ENTRY_TYPE_OPTIM FCRAM_ENTRY_OPTIM 1602 #define HASH_ENTRY_TYPE_OPTIM_IP4 FCRAM_ENTRY_OPTIM 1603 #define HASH_ENTRY_TYPE_OPTIM_IP4 FCRAM_ENTRY_OPTIM 1604 #define HASH_ENTRY_TYPE_EX_IP4 FCRAM_ENTRY_EX_IP4 1605 #define HASH_ENTRY_TYPE_EX_IP6 FCRAM_ENTRY_EX_IP6 1606 1607 1608 1609 1610 /* error xxx formats */ 1611 1612 1613 typedef struct _hash_lookup_err_log { 1614 uint32_t rsrvd:28; 1615 uint32_t lookup_err:1; 1616 uint32_t ecc_err:1; 1617 uint32_t uncor_err:1; 1618 uint32_t multi_lkup:1; 1619 uint32_t multi_bit:1; 1620 uint32_t subarea:3; 1621 uint32_t syndrome:8; 1622 uint32_t h1:20; 1623 } hash_lookup_err_log_t, *p_hash_lookup_err_log_t; 1624 1625 1626 1627 typedef struct _hash_pio_err_log { 1628 uint32_t rsrvd:32; 1629 uint32_t pio_err:1; 1630 uint32_t syndrome:8; 1631 uint32_t addr:23; 1632 } hash_pio_err_log_t, *p_hash_pio_err_log_t; 1633 1634 1635 1636 typedef struct _tcam_err_log { 1637 uint32_t rsrvd:2; 1638 uint32_t tcam_err:1; 1639 uint32_t parity_err:1; 1640 uint32_t ecc_err:1; 1641 uint32_t multi_lkup:1; 1642 uint32_t location:8; 1643 uint32_t syndrome:16; 1644 } tcam_err_log_t, *p_tcam_err_log_t; 1645 1646 1647 typedef struct _vlan_tbl_err_log { 1648 uint32_t rsrvd:32; 1649 uint32_t err:1; 1650 uint32_t multi:1; 1651 uint32_t addr:12; 1652 uint32_t data:18; 1653 } vlan_tbl_err_log_t, *p_vlan_tbl_err_log_t; 1654 1655 1656 #define NEPTUNE_TCAM_SIZE 0x100 1657 #define NIU_TCAM_SIZE 0x80 1658 #define FCRAM_SIZE 0x100000 1659 1660 #ifdef __cplusplus 1661 } 1662 #endif 1663 1664 #endif /* _SYS_NXGE_NXGE_FFLP_HW_H */ 1665