1*6f45ec7bSml29623 /* 2*6f45ec7bSml29623 * CDDL HEADER START 3*6f45ec7bSml29623 * 4*6f45ec7bSml29623 * The contents of this file are subject to the terms of the 5*6f45ec7bSml29623 * Common Development and Distribution License (the "License"). 6*6f45ec7bSml29623 * You may not use this file except in compliance with the License. 7*6f45ec7bSml29623 * 8*6f45ec7bSml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*6f45ec7bSml29623 * or http://www.opensolaris.org/os/licensing. 10*6f45ec7bSml29623 * See the License for the specific language governing permissions 11*6f45ec7bSml29623 * and limitations under the License. 12*6f45ec7bSml29623 * 13*6f45ec7bSml29623 * When distributing Covered Code, include this CDDL HEADER in each 14*6f45ec7bSml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*6f45ec7bSml29623 * If applicable, add the following below this CDDL HEADER, with the 16*6f45ec7bSml29623 * fields enclosed by brackets "[]" replaced with your own identifying 17*6f45ec7bSml29623 * information: Portions Copyright [yyyy] [name of copyright owner] 18*6f45ec7bSml29623 * 19*6f45ec7bSml29623 * CDDL HEADER END 20*6f45ec7bSml29623 */ 21*6f45ec7bSml29623 /* 22*6f45ec7bSml29623 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23*6f45ec7bSml29623 * Use is subject to license terms. 24*6f45ec7bSml29623 */ 25*6f45ec7bSml29623 26*6f45ec7bSml29623 #ifndef _SYS_NXGE_NXGE_ESPC_HW_H 27*6f45ec7bSml29623 #define _SYS_NXGE_NXGE_ESPC_HW_H 28*6f45ec7bSml29623 29*6f45ec7bSml29623 #ifdef __cplusplus 30*6f45ec7bSml29623 extern "C" { 31*6f45ec7bSml29623 #endif 32*6f45ec7bSml29623 33*6f45ec7bSml29623 #include <nxge_defs.h> 34*6f45ec7bSml29623 35*6f45ec7bSml29623 /* EPC / SPC Registers offsets */ 36*6f45ec7bSml29623 #define ESPC_PIO_EN_REG 0x040000 37*6f45ec7bSml29623 #define ESPC_PIO_EN_MASK 0x0000000000000001ULL 38*6f45ec7bSml29623 #define ESPC_PIO_STATUS_REG 0x040008 39*6f45ec7bSml29623 40*6f45ec7bSml29623 /* EPC Status Register */ 41*6f45ec7bSml29623 #define EPC_READ_INITIATE (1ULL << 31) 42*6f45ec7bSml29623 #define EPC_READ_COMPLETE (1 << 30) 43*6f45ec7bSml29623 #define EPC_WRITE_INITIATE (1 << 29) 44*6f45ec7bSml29623 #define EPC_WRITE_COMPLETE (1 << 28) 45*6f45ec7bSml29623 #define EPC_EEPROM_ADDR_BITS 0x3FFFF 46*6f45ec7bSml29623 #define EPC_EEPROM_ADDR_SHIFT 8 47*6f45ec7bSml29623 #define EPC_EEPROM_ADDR_MASK (EPC_EEPROM_ADDR_BITS << EPC_EEPROM_ADDR_SHIFT) 48*6f45ec7bSml29623 #define EPC_EEPROM_DATA_MASK 0xFF 49*6f45ec7bSml29623 50*6f45ec7bSml29623 #define EPC_RW_WAIT 10 /* TBD */ 51*6f45ec7bSml29623 52*6f45ec7bSml29623 #define ESPC_NCR_REG 0x040020 /* Count 128, step 8 */ 53*6f45ec7bSml29623 #define ESPC_REG_ADDR(reg) (FZC_PROM + (reg)) 54*6f45ec7bSml29623 55*6f45ec7bSml29623 #define ESPC_NCR_REGN(n) ((ESPC_REG_ADDR(ESPC_NCR_REG)) + n*8) 56*6f45ec7bSml29623 #define ESPC_NCR_VAL_MASK 0x00000000FFFFFFFFULL 57*6f45ec7bSml29623 58*6f45ec7bSml29623 #ifdef __cplusplus 59*6f45ec7bSml29623 } 60*6f45ec7bSml29623 #endif 61*6f45ec7bSml29623 62*6f45ec7bSml29623 #endif /* _SYS_NXGE_NXGE_ESPC_HW_H */ 63