xref: /illumos-gate/usr/src/uts/common/sys/nxge/nxge_espc.h (revision 9b9d39d2a32ff806d2431dbcc50968ef1e6d46b2)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_NXGE_NXGE_ESPC_H
27 #define	_SYS_NXGE_NXGE_ESPC_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #include <nxge_espc_hw.h>
34 
35 #define	ESPC_MAC_ADDR_0		ESPC_NCR_REGN(0)
36 #define	ESPC_MAC_ADDR_1		ESPC_NCR_REGN(1)
37 #define	ESPC_NUM_PORTS_MACS	ESPC_NCR_REGN(2)
38 #define	ESPC_MOD_STR_LEN	ESPC_NCR_REGN(4)
39 #define	ESPC_MOD_STR_1		ESPC_NCR_REGN(5)
40 #define	ESPC_MOD_STR_2		ESPC_NCR_REGN(6)
41 #define	ESPC_MOD_STR_3		ESPC_NCR_REGN(7)
42 #define	ESPC_MOD_STR_4		ESPC_NCR_REGN(8)
43 #define	ESPC_MOD_STR_5		ESPC_NCR_REGN(9)
44 #define	ESPC_MOD_STR_6		ESPC_NCR_REGN(10)
45 #define	ESPC_MOD_STR_7		ESPC_NCR_REGN(11)
46 #define	ESPC_MOD_STR_8		ESPC_NCR_REGN(12)
47 #define	ESPC_BD_MOD_STR_LEN	ESPC_NCR_REGN(13)
48 #define	ESPC_BD_MOD_STR_1	ESPC_NCR_REGN(14)
49 #define	ESPC_BD_MOD_STR_2	ESPC_NCR_REGN(15)
50 #define	ESPC_BD_MOD_STR_3	ESPC_NCR_REGN(16)
51 #define	ESPC_BD_MOD_STR_4	ESPC_NCR_REGN(17)
52 #define	ESPC_PHY_TYPE		ESPC_NCR_REGN(18)
53 #define	ESPC_MAX_FM_SZ		ESPC_NCR_REGN(19)
54 #define	ESPC_INTR_NUM		ESPC_NCR_REGN(20)
55 #define	ESPC_VER_IMGSZ		ESPC_NCR_REGN(21)
56 #define	ESPC_CHKSUM		ESPC_NCR_REGN(22)
57 
58 #define	NUM_PORTS_MASK		0xff
59 #define	NUM_MAC_ADDRS_MASK	0xff0000
60 #define	NUM_MAC_ADDRS_SHIFT	16
61 #define	MOD_STR_LEN_MASK	0xffff
62 #define	BD_MOD_STR_LEN_MASK	0xffff
63 #define	MAX_FM_SZ_MASK		0xffff
64 #define	VER_NUM_MASK		0xffff
65 #define	IMG_SZ_MASK		0xffff0000
66 #define	IMG_SZ_SHIFT		16
67 #define	CHKSUM_MASK		0xff
68 
69 /* 0 <= n < 8 */
70 #define	ESPC_MOD_STR(n)		(ESPC_MOD_STR_1 + n*8)
71 #define	MAX_MOD_STR_LEN		32
72 
73 /* 0 <= n < 4 */
74 #define	ESPC_BD_MOD_STR(n)	(ESPC_BD_MOD_STR_1 + n*8)
75 #define	MAX_BD_MOD_STR_LEN	16
76 
77 #define	ESC_PHY_10G_FIBER	0x0
78 #define	ESC_PHY_10G_COPPER	0x1
79 #define	ESC_PHY_1G_FIBER	0x2
80 #define	ESC_PHY_1G_COPPER	0x3
81 #define	ESC_PHY_NONE		0xf
82 
83 #define	ESC_IMG_CHKSUM_VAL	0xab
84 
85 typedef union _mac_addr_0_t {
86 	uint64_t value;
87 
88 	struct {
89 #if defined(_BIG_ENDIAN)
90 		uint32_t msw;	/* Most significant word */
91 		uint32_t lsw;	/* Least significant word */
92 #elif defined(_LITTLE_ENDIAN)
93 		uint32_t lsw;	/* Least significant word */
94 		uint32_t msw;	/* Most significant word */
95 #endif
96 	} val;
97 	struct {
98 #if defined(_BIG_ENDIAN)
99 		uint32_t	w1;
100 #endif
101 		struct {
102 #if defined(_BIT_FIELDS_HTOL)
103 		uint32_t byte3		: 8;
104 		uint32_t byte2		: 8;
105 		uint32_t byte1		: 8;
106 		uint32_t byte0		: 8;
107 #elif defined(_BIT_FIELDS_LTOH)
108 		uint32_t byte0		: 8;
109 		uint32_t byte1		: 8;
110 		uint32_t byte2		: 8;
111 		uint32_t byte3		: 8;
112 #endif
113 		} w0;
114 
115 #if defined(_LITTLE_ENDIAN)
116 		uint32_t	w1;
117 #endif
118 	} bits;
119 } mac_addr_0_t;
120 
121 typedef union _mac_addr_1_t {
122 	uint64_t value;
123 
124 	struct {
125 #if defined(_BIG_ENDIAN)
126 		uint32_t msw;	/* Most significant word */
127 		uint32_t lsw;	/* Least significant word */
128 #elif defined(_LITTLE_ENDIAN)
129 		uint32_t lsw;	/* Least significant word */
130 		uint32_t msw;	/* Most significant word */
131 #endif
132 	} val;
133 	struct {
134 #if defined(_BIG_ENDIAN)
135 		uint32_t	w1;
136 #endif
137 		struct {
138 #if defined(_BIT_FIELDS_HTOL)
139 		uint32_t res		: 16;
140 		uint32_t byte5		: 8;
141 		uint32_t byte4		: 8;
142 #elif defined(_BIT_FIELDS_LTOH)
143 		uint32_t byte4		: 8;
144 		uint32_t byte5		: 8;
145 		uint32_t res		: 16;
146 #endif
147 		} w0;
148 
149 #if defined(_LITTLE_ENDIAN)
150 		uint32_t	w1;
151 #endif
152 	} bits;
153 } mac_addr_1_t;
154 
155 
156 typedef union _phy_type_t {
157 	uint64_t value;
158 
159 	struct {
160 #if defined(_BIG_ENDIAN)
161 		uint32_t msw;	/* Most significant word */
162 		uint32_t lsw;	/* Least significant word */
163 #elif defined(_LITTLE_ENDIAN)
164 		uint32_t lsw;	/* Least significant word */
165 		uint32_t msw;	/* Most significant word */
166 #endif
167 	} val;
168 	struct {
169 #if defined(_BIG_ENDIAN)
170 		uint32_t	w1;
171 #endif
172 		struct {
173 #if defined(_BIT_FIELDS_HTOL)
174 		uint32_t pt0_phy_type	: 8;
175 		uint32_t pt1_phy_type	: 8;
176 		uint32_t pt2_phy_type	: 8;
177 		uint32_t pt3_phy_type	: 8;
178 #elif defined(_BIT_FIELDS_LTOH)
179 		uint32_t pt3_phy_type	: 8;
180 		uint32_t pt2_phy_type	: 8;
181 		uint32_t pt1_phy_type	: 8;
182 		uint32_t pt0_phy_type	: 8;
183 #endif
184 		} w0;
185 
186 #if defined(_LITTLE_ENDIAN)
187 		uint32_t	w1;
188 #endif
189 	} bits;
190 } phy_type_t;
191 
192 
193 typedef union _intr_num_t {
194 	uint64_t value;
195 
196 	struct {
197 #if defined(_BIG_ENDIAN)
198 		uint32_t msw;	/* Most significant word */
199 		uint32_t lsw;	/* Least significant word */
200 #elif defined(_LITTLE_ENDIAN)
201 		uint32_t lsw;	/* Least significant word */
202 		uint32_t msw;	/* Most significant word */
203 #endif
204 	} val;
205 	struct {
206 #if defined(_BIG_ENDIAN)
207 		uint32_t	w1;
208 #endif
209 		struct {
210 #if defined(_BIT_FIELDS_HTOL)
211 		uint32_t pt0_intr_num	: 8;
212 		uint32_t pt1_intr_num	: 8;
213 		uint32_t pt2_intr_num	: 8;
214 		uint32_t pt3_intr_num	: 8;
215 #elif defined(_BIT_FIELDS_LTOH)
216 		uint32_t pt3_intr_num	: 8;
217 		uint32_t pt2_intr_num	: 8;
218 		uint32_t pt1_intr_num	: 8;
219 		uint32_t pt0_intr_num	: 8;
220 #endif
221 		} w0;
222 
223 #if defined(_LITTLE_ENDIAN)
224 		uint32_t	w1;
225 #endif
226 	} bits;
227 } intr_num_t;
228 
229 
230 #ifdef __cplusplus
231 }
232 #endif
233 
234 #endif	/* _SYS_NXGE_NXGE_ESPC_H */
235