1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_COMMON_IMPL_H 27 #define _SYS_NXGE_NXGE_COMMON_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define NPI_REGH(npi_handle) (npi_handle.regh) 36 #define NPI_REGP(npi_handle) (npi_handle.regp) 37 38 #if defined(NXGE_DEBUG_DMA) || defined(NXGE_DEBUG_TXC) 39 #define __NXGE_STATIC 40 #define __NXGE_INLINE 41 #else 42 #define __NXGE_STATIC static 43 #define __NXGE_INLINE inline 44 #endif 45 46 #ifdef AXIS_DEBUG 47 #define AXIS_WAIT (100000) 48 #define AXIS_LONG_WAIT (100000) 49 #define AXIS_WAIT_W (80000) 50 #define AXIS_WAIT_R (100000) 51 #define AXIS_WAIT_LOOP (4000) 52 #define AXIS_WAIT_PER_LOOP (AXIS_WAIT_R/AXIS_WAIT_LOOP) 53 #endif 54 55 #define NO_DEBUG 0x0000000000000000ULL 56 #define MDT_CTL 0x0000000000000001ULL 57 #define RX_CTL 0x0000000000000002ULL 58 #define TX_CTL 0x0000000000000004ULL 59 #define OBP_CTL 0x0000000000000008ULL 60 61 #define VPD_CTL 0x0000000000000010ULL 62 #define DDI_CTL 0x0000000000000020ULL 63 #define MEM_CTL 0x0000000000000040ULL 64 #define SAP_CTL 0x0000000000000080ULL 65 66 #define IOC_CTL 0x0000000000000100ULL 67 #define MOD_CTL 0x0000000000000200ULL 68 #define DMA_CTL 0x0000000000000400ULL 69 #define STR_CTL 0x0000000000000800ULL 70 71 #define INT_CTL 0x0000000000001000ULL 72 #define SYSERR_CTL 0x0000000000002000ULL 73 #define KST_CTL 0x0000000000004000ULL 74 #define PCS_CTL 0x0000000000008000ULL 75 76 #define MII_CTL 0x0000000000010000ULL 77 #define MIF_CTL 0x0000000000020000ULL 78 #define FCRAM_CTL 0x0000000000040000ULL 79 #define MAC_CTL 0x0000000000080000ULL 80 81 #define IPP_CTL 0x0000000000100000ULL 82 #define DMA2_CTL 0x0000000000200000ULL 83 #define RX2_CTL 0x0000000000400000ULL 84 #define TX2_CTL 0x0000000000800000ULL 85 86 #define MEM2_CTL 0x0000000001000000ULL 87 #define MEM3_CTL 0x0000000002000000ULL 88 #define NXGE_CTL 0x0000000004000000ULL 89 #define NDD_CTL 0x0000000008000000ULL 90 #define NDD2_CTL 0x0000000010000000ULL 91 92 #define TCAM_CTL 0x0000000020000000ULL 93 #define CFG_CTL 0x0000000040000000ULL 94 #define CFG2_CTL 0x0000000080000000ULL 95 96 #define FFLP_CTL TCAM_CTL | FCRAM_CTL 97 98 #define VIR_CTL 0x0000000100000000ULL 99 #define VIR2_CTL 0x0000000200000000ULL 100 101 #define HIO_CTL 0x0000000400000000ULL 102 103 #define NXGE_NOTE 0x0000001000000000ULL 104 #define NXGE_ERR_CTL 0x0000002000000000ULL 105 106 #define DUMP_ALWAYS 0x2000000000000000ULL 107 108 /* NPI Debug and Error defines */ 109 #define NPI_RDC_CTL 0x0000000000000001ULL 110 #define NPI_TDC_CTL 0x0000000000000002ULL 111 #define NPI_TXC_CTL 0x0000000000000004ULL 112 #define NPI_IPP_CTL 0x0000000000000008ULL 113 114 #define NPI_XPCS_CTL 0x0000000000000010ULL 115 #define NPI_PCS_CTL 0x0000000000000020ULL 116 #define NPI_ESR_CTL 0x0000000000000040ULL 117 #define NPI_BMAC_CTL 0x0000000000000080ULL 118 #define NPI_XMAC_CTL 0x0000000000000100ULL 119 #define NPI_MAC_CTL NPI_BMAC_CTL | NPI_XMAC_CTL 120 121 #define NPI_ZCP_CTL 0x0000000000000200ULL 122 #define NPI_TCAM_CTL 0x0000000000000400ULL 123 #define NPI_FCRAM_CTL 0x0000000000000800ULL 124 #define NPI_FFLP_CTL NPI_TCAM_CTL | NPI_FCRAM_CTL 125 126 #define NPI_VIR_CTL 0x0000000000001000ULL 127 #define NPI_PIO_CTL 0x0000000000002000ULL 128 #define NPI_VIO_CTL 0x0000000000004000ULL 129 130 #define NPI_REG_CTL 0x0000000040000000ULL 131 #define NPI_CTL 0x0000000080000000ULL 132 #define NPI_ERR_CTL 0x0000000080000000ULL 133 134 #if defined(SOLARIS) && defined(_KERNEL) 135 136 #include <sys/types.h> 137 #include <sys/ddi.h> 138 #include <sys/sunddi.h> 139 #include <sys/dditypes.h> 140 #include <sys/ethernet.h> 141 142 #ifdef NXGE_DEBUG 143 #define NXGE_DEBUG_MSG(params) nxge_debug_msg params 144 #else 145 #define NXGE_DEBUG_MSG(params) 146 #endif 147 148 #if 1 149 #define NXGE_ERROR_MSG(params) nxge_debug_msg params 150 #define NXGE_WARN_MSG(params) nxge_debug_msg params 151 #else 152 #define NXGE_ERROR_MSG(params) 153 #define NXGE_WARN_MSG(params) 154 #endif 155 156 typedef kmutex_t nxge_os_mutex_t; 157 typedef krwlock_t nxge_os_rwlock_t; 158 159 typedef dev_info_t nxge_dev_info_t; 160 typedef ddi_iblock_cookie_t nxge_intr_cookie_t; 161 162 typedef ddi_acc_handle_t nxge_os_acc_handle_t; 163 typedef nxge_os_acc_handle_t npi_reg_handle_t; 164 #if defined(__i386) 165 typedef uint32_t npi_reg_ptr_t; 166 #else 167 typedef uint64_t npi_reg_ptr_t; 168 #endif 169 170 typedef ddi_dma_handle_t nxge_os_dma_handle_t; 171 typedef struct _nxge_dma_common_t nxge_os_dma_common_t; 172 typedef struct _nxge_block_mv_t nxge_os_block_mv_t; 173 typedef frtn_t nxge_os_frtn_t; 174 175 #define NXGE_MUTEX_DRIVER MUTEX_DRIVER 176 #define MUTEX_INIT(lock, name, type, arg) \ 177 mutex_init(lock, name, type, arg) 178 #define MUTEX_ENTER(lock) mutex_enter(lock) 179 #define MUTEX_TRY_ENTER(lock) mutex_tryenter(lock) 180 #define MUTEX_EXIT(lock) mutex_exit(lock) 181 #define MUTEX_DESTROY(lock) mutex_destroy(lock) 182 183 #define RW_INIT(lock, name, type, arg) rw_init(lock, name, type, arg) 184 #define RW_ENTER_WRITER(lock) rw_enter(lock, RW_WRITER) 185 #define RW_ENTER_READER(lock) rw_enter(lock, RW_READER) 186 #define RW_TRY_ENTER(lock, type) rw_tryenter(lock, type) 187 #define RW_EXIT(lock) rw_exit(lock) 188 #define RW_DESTROY(lock) rw_destroy(lock) 189 #define KMEM_ALLOC(size, flag) kmem_alloc(size, flag) 190 #define KMEM_ZALLOC(size, flag) kmem_zalloc(size, flag) 191 #define KMEM_FREE(buf, size) kmem_free(buf, size) 192 193 #define NXGE_DELAY(microseconds) (drv_usecwait(microseconds)) 194 195 #define NXGE_PIO_READ8(handle, devaddr, offset) \ 196 (ddi_get8(handle, (uint8_t *)((caddr_t)devaddr + offset))) 197 198 #define NXGE_PIO_READ16(handle, devaddr, offset) \ 199 (ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset))) 200 201 #define NXGE_PIO_READ32(handle, devaddr, offset) \ 202 (ddi_get32(handle, (uint32_t *)((caddr_t)devaddr + offset))) 203 204 #define NXGE_PIO_READ64(handle, devaddr, offset) \ 205 (ddi_get64(handle, (uint64_t *)((caddr_t)devaddr + offset))) 206 207 #define NXGE_PIO_WRITE8(handle, devaddr, offset, data) \ 208 (ddi_put8(handle, (uint8_t *)((caddr_t)devaddr + offset), data)) 209 210 #define NXGE_PIO_WRITE16(handle, devaddr, offset, data) \ 211 (ddi_get16(handle, (uint16_t *)((caddr_t)devaddr + offset), data)) 212 213 #define NXGE_PIO_WRITE32(handle, devaddr, offset, data) \ 214 (ddi_put32(handle, (uint32_t *)((caddr_t)devaddr + offset), data)) 215 216 #define NXGE_PIO_WRITE64(handle, devaddr, offset, data) \ 217 (ddi_put64(handle, (uint64_t *)((caddr_t)devaddr + offset), data)) 218 219 #define NXGE_NPI_PIO_READ8(npi_handle, offset) \ 220 (ddi_get8(NPI_REGH(npi_handle), \ 221 (uint8_t *)(NPI_REGP(npi_handle) + offset))) 222 223 #define NXGE_NPI_PIO_READ16(npi_handle, offset) \ 224 (ddi_get16(NPI_REGH(npi_handle), \ 225 (uint16_t *)(NPI_REGP(npi_handle) + offset))) 226 227 #define NXGE_NPI_PIO_READ32(npi_handle, offset) \ 228 (ddi_get32(NPI_REGH(npi_handle), \ 229 (uint32_t *)(NPI_REGP(npi_handle) + offset))) 230 231 #if defined(__i386) 232 #define NXGE_NPI_PIO_READ64(npi_handle, offset) \ 233 (ddi_get64(NPI_REGH(npi_handle), \ 234 (uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset))) 235 #else 236 #define NXGE_NPI_PIO_READ64(npi_handle, offset) \ 237 (ddi_get64(NPI_REGH(npi_handle), \ 238 (uint64_t *)(NPI_REGP(npi_handle) + offset))) 239 #endif 240 241 #define NXGE_NPI_PIO_WRITE8(npi_handle, offset, data) \ 242 (ddi_put8(NPI_REGH(npi_handle), \ 243 (uint8_t *)(NPI_REGP(npi_handle) + offset), data)) 244 245 #define NXGE_NPI_PIO_WRITE16(npi_handle, offset, data) \ 246 (ddi_put16(NPI_REGH(npi_handle), \ 247 (uint16_t *)(NPI_REGP(npi_handle) + offset), data)) 248 249 #define NXGE_NPI_PIO_WRITE32(npi_handle, offset, data) \ 250 (ddi_put32(NPI_REGH(npi_handle), \ 251 (uint32_t *)(NPI_REGP(npi_handle) + offset), data)) 252 253 #if defined(__i386) 254 #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \ 255 (ddi_put64(NPI_REGH(npi_handle), \ 256 (uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset), data)) 257 #else 258 #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \ 259 (ddi_put64(NPI_REGH(npi_handle), \ 260 (uint64_t *)(NPI_REGP(npi_handle) + offset), data)) 261 #endif 262 263 #define NXGE_MEM_PIO_READ8(npi_handle) \ 264 (ddi_get8(NPI_REGH(npi_handle), (uint8_t *)NPI_REGP(npi_handle))) 265 266 #define NXGE_MEM_PIO_READ16(npi_handle) \ 267 (ddi_get16(NPI_REGH(npi_handle), (uint16_t *)NPI_REGP(npi_handle))) 268 269 #define NXGE_MEM_PIO_READ32(npi_handle) \ 270 (ddi_get32(NPI_REGH(npi_handle), (uint32_t *)NPI_REGP(npi_handle))) 271 272 #define NXGE_MEM_PIO_READ64(npi_handle) \ 273 (ddi_get64(NPI_REGH(npi_handle), (uint64_t *)NPI_REGP(npi_handle))) 274 275 #define NXGE_MEM_PIO_WRITE8(npi_handle, data) \ 276 (ddi_put8(NPI_REGH(npi_handle), (uint8_t *)NPI_REGP(npi_handle), data)) 277 278 #define NXGE_MEM_PIO_WRITE16(npi_handle, data) \ 279 (ddi_put16(NPI_REGH(npi_handle), \ 280 (uint16_t *)NPI_REGP(npi_handle), data)) 281 282 #define NXGE_MEM_PIO_WRITE32(npi_handle, data) \ 283 (ddi_put32(NPI_REGH(npi_handle), \ 284 (uint32_t *)NPI_REGP(npi_handle), data)) 285 286 #define NXGE_MEM_PIO_WRITE64(npi_handle, data) \ 287 (ddi_put64(NPI_REGH(npi_handle), \ 288 (uint64_t *)NPI_REGP(npi_handle), data)) 289 290 #define SERVICE_LOST DDI_SERVICE_LOST 291 #define SERVICE_DEGRADED DDI_SERVICE_DEGRADED 292 #define SERVICE_UNAFFECTED DDI_SERVICE_UNAFFECTED 293 #define SERVICE_RESTORED DDI_SERVICE_RESTORED 294 295 #define DATAPATH_FAULT DDI_DATAPATH_FAULT 296 #define DEVICE_FAULT DDI_DEVICE_FAULT 297 #define EXTERNAL_FAULT DDI_EXTERNAL_FAULT 298 299 #define NOTE_LINK_UP DL_NOTE_LINK_UP 300 #define NOTE_LINK_DOWN DL_NOTE_LINK_DOWN 301 #define NOTE_SPEED DL_NOTE_SPEED 302 #define NOTE_PHYS_ADDR DL_NOTE_PHYS_ADDR 303 #define NOTE_AGGR_AVAIL DL_NOTE_AGGR_AVAIL 304 #define NOTE_AGGR_UNAVAIL DL_NOTE_AGGR_UNAVAIL 305 306 #define FM_REPORT_FAULT(nxgep, impact, location, msg)\ 307 ddi_dev_report_fault(nxgep->dip, impact, location, msg) 308 #define FM_CHECK_DEV_HANDLE(nxgep)\ 309 ddi_check_acc_handle(nxgep->dev_regs->nxge_regh) 310 #define FM_GET_DEVSTATE(nxgep)\ 311 ddi_get_devstate(nxgep->dip) 312 #define FM_SERVICE_RESTORED(nxgep)\ 313 ddi_fm_service_impact(nxgep->dip, DDI_SERVICE_RESTORED) 314 #define NXGE_FM_REPORT_ERROR(nxgep, portn, chan, ereport_id)\ 315 nxge_fm_report_error(nxgep, portn, chan, ereport_id) 316 #define FM_CHECK_ACC_HANDLE(nxgep, handle)\ 317 fm_check_acc_handle(handle) 318 #define FM_CHECK_DMA_HANDLE(nxgep, handle)\ 319 fm_check_dma_handle(handle) 320 321 #endif 322 323 #if defined(REG_TRACE) 324 #define NXGE_REG_RD64(handle, offset, val_p) {\ 325 *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\ 326 npi_rtrace_update(handle, B_FALSE, &npi_rtracebuf, (uint32_t)offset, \ 327 (uint64_t)(*(val_p)));\ 328 } 329 #elif defined(REG_SHOW) 330 /* 331 * Send 0xbadbad to tell rs_show_reg that we do not have 332 * a valid RTBUF index to pass 333 */ 334 #define NXGE_REG_RD64(handle, offset, val_p) {\ 335 *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\ 336 rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, (uint64_t)(*(val_p)));\ 337 } 338 #elif defined(AXIS_DEBUG) && !defined(LEGION) 339 #define NXGE_REG_RD64(handle, offset, val_p) {\ 340 int n; \ 341 for (n = 0; n < AXIS_WAIT_LOOP; n++) { \ 342 *(val_p) = 0; \ 343 *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\ 344 if (*(val_p) != (~0)) { \ 345 break; \ 346 } \ 347 drv_usecwait(AXIS_WAIT_PER_LOOP); \ 348 if (n < 20) { \ 349 cmn_err(CE_WARN, "NXGE_REG_RD64: loop %d " \ 350 "REG 0x%x(0x%llx)", \ 351 n, offset, *val_p);\ 352 } \ 353 } \ 354 if (n >= AXIS_WAIT_LOOP) { \ 355 cmn_err(CE_WARN, "(FATAL)NXGE_REG_RD64 on offset 0x%x " \ 356 "with -1!!!", offset); \ 357 } \ 358 } 359 #else 360 361 #define NXGE_REG_RD64(handle, offset, val_p) {\ 362 *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\ 363 } 364 #endif 365 366 /* 367 * In COSIM mode, we could loop for very long time when polling 368 * for the completion of a Clause45 frame MDIO operations. Display 369 * one rtrace line for each poll can result in messy screen. Add 370 * this MACRO for no rtrace show. 371 */ 372 #define NXGE_REG_RD64_NO_SHOW(handle, offset, val_p) {\ 373 *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\ 374 } 375 376 377 #if defined(REG_TRACE) 378 #define NXGE_REG_WR64(handle, offset, val) {\ 379 NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\ 380 npi_rtrace_update(handle, B_TRUE, &npi_rtracebuf, (uint32_t)offset,\ 381 (uint64_t)(val));\ 382 } 383 #elif defined(REG_SHOW) 384 /* 385 * Send 0xbadbad to tell rs_show_reg that we do not have 386 * a valid RTBUF index to pass 387 */ 388 #define NXGE_REG_WR64(handle, offset, val) {\ 389 NXGE_NPI_PIO_WRITE64(handle, offset, (val));\ 390 rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\ 391 } 392 #else 393 #define NXGE_REG_WR64(handle, offset, val) {\ 394 NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\ 395 } 396 #endif 397 398 #ifdef __cplusplus 399 } 400 #endif 401 402 #endif /* _SYS_NXGE_NXGE_COMMON_IMPL_H */ 403