1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2024 Oxide Computer Company 14 */ 15 16 #ifndef _SYS_NVME_OCP_H 17 #define _SYS_NVME_OCP_H 18 19 /* 20 * This header defines vendor-specific NVMe interfaces and is not a committed 21 * interface. Its contents and existence are subject to change. 22 * 23 * This covers the OCP Datacenter NVMe SSD Specification versions 2.0 and 2.5. 24 * Version 1.0 of this specification was previously called the OCP NVMe Cloud 25 * SSD Specification. 26 */ 27 28 #include <sys/isa_defs.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 typedef enum { 35 /* 36 * This is the OCP variant of SMART information. Present since v1.0. 37 * Scoped to the NVM subsystem. Tracked by the ocp_vul_smart_t. 38 */ 39 OCP_LOG_DSSD_SMART = 0xc0, 40 /* 41 * Error recovery information. Present since v1.0. Scoped to the NVM 42 * subsystem. 43 */ 44 OCP_LOG_DSSD_ERROR_REC = 0xc1, 45 /* 46 * This log page covers firmware activation history. It was added in 47 * v1.0 of the specification, but v2.5 removed this as obsolete. Scoped 48 * to the NVM subsystem. 49 */ 50 OCP_LOG_DSSD_FWACT = 0xc2, 51 /* 52 * This is the latency monitor log page that has information in tandem 53 * with the Latency monitor feature (0xc5). Added in v2.0. Scoped to the 54 * controller. 55 */ 56 OCP_LOG_DSSD_LATENCY = 0xc3, 57 /* 58 * This log page indicates various device capabilities. Added in v2.0. 59 * Scoped to the NVM subsystem. 60 */ 61 OCP_LOG_DSSD_DEV_CAP = 0xc4, 62 /* 63 * This log page indicates which requirements aren't actually 64 * implemented by a device. Added in v2.0. Scoped to the NVM subsystem. 65 */ 66 OCP_LOG_DSSD_UNSUP_REQ = 0xc5, 67 /* 68 * This log page covers various trusted computing group configuration. 69 * Added in v2.5. Scoped to the NVM subsystem. 70 */ 71 OCP_LOG_DSSD_TCG = 0xc7, 72 /* 73 * This is the telemetry string log. Added in v2.5. Scoped to the NVM 74 * subsystem. 75 */ 76 OCP_LOG_DSSD_TELEMTRY = 0xc9 77 } ocp_vul_t; 78 79 typedef enum { 80 /* 81 * Error injection feature. Added in v1.0. Scoped to the NVM subsystem. 82 */ 83 OCP_FEAT_DSSD_ERR_INJ = 0xc0, 84 /* 85 * Clear the firmware activation and update history log. Added in v1.0, 86 * but marked obsolete in v2.5. Scoped to the NVM subsystem. 87 */ 88 OCP_FEAT_DSSD_CLEAR_FWACT = 0xc1, 89 /* 90 * Controls the failure mode on device EOL or power loss protection 91 * (PLP) failure. Added in v1.0. Scoped to the NVM subsystem. 92 */ 93 OCP_FEAT_DSSD_EOLPLP = 0xc2, 94 /* 95 * Clears the PCIe correctable error counters. Added in v1.0. Scoped to 96 * the controller. 97 */ 98 OCP_FEAT_DSSD_CLEAR_PCIE_ERRCOR = 0xc3, 99 /* 100 * Manipulates the IEEE1667 silo which ties into the OPAL security 101 * feature set. Added in v1.0. Scoped to the NVM subsystem. 102 */ 103 OCP_FEAT_DSSD_IEEE1667 = 0xc4, 104 /* 105 * Controls the latency monitor feature. Added in v2.0. Scoped to the 106 * controller. 107 */ 108 OCP_FEAT_DSSD_LATENCY = 0xc5, 109 /* 110 * Controls the PLP health check interval. Added in v2.0. Scoped to the 111 * NVM subsystem. 112 */ 113 OCP_FEAT_DSSD_PLP_HEALTH = 0xc6, 114 /* 115 * Controls the power state that the device is in. Added in v2.0. Scoped 116 * to the NVM subsystem. 117 */ 118 OCP_FEAT_DSSD_POWER_STATE = 0xc7, 119 /* 120 * Controls the OCP DSSD telemetry profile that should be active. Added 121 * in v2.5. Scoped to the NVM subsystem. 122 */ 123 OCP_FEAT_DSSD_TEL_PROFILE = 0xc8, 124 /* 125 * Controls whether additional spec-specific events should be sent with 126 * the asynchronous event commands. 127 */ 128 OCP_FEAT_DSSD_ASYNC_EVENT = 0xc9 129 } ocp_vuf_t; 130 131 /* 132 * All data structures must be packed to account for the layout from the various 133 * specifications. All fields are required to be in little endian. 134 */ 135 #pragma pack(1) 136 137 /* 138 * OCP SMART / Health log page. A number in parentheses like (2.0) indicates the 139 * version something was added in if it was not v1.0. 140 */ 141 typedef struct { 142 /* 143 * Physical media units read and written. 144 */ 145 uint8_t osh_pmed_write[16]; 146 uint8_t osh_pmed_read[16]; 147 /* 148 * Bad user and system NAND blocks. Both a raw count and normalized 149 * value (percentage remaining). 150 */ 151 uint8_t osh_bunb_raw[6]; 152 uint16_t osh_bunb_norm; 153 uint8_t osh_bsnb_raw[6]; 154 uint16_t osh_bsnb_norm; 155 /* 156 * Various error and recovery metrics: 157 * - XOR 158 * - Uncorrectable reads 159 * - Soft ECC errors 160 * - End to end errors detected and corrected 161 */ 162 uint64_t osh_xor_rec; 163 uint64_t osh_read_unrec; 164 uint64_t osh_soft_ecc_err; 165 uint32_t osh_e2e_det; 166 uint32_t osh_e2e_corr; 167 /* 168 * Tracks the normalized percent used of the device by estimated erase 169 * cycles per block. 170 */ 171 uint8_t osh_sys_used; 172 /* 173 * This is the count of blocks that have been refreshed. 174 */ 175 uint8_t osh_refresh[7]; 176 /* 177 * Tracks the maximum and minimum erase count across NAND reserved for 178 * the user. 179 */ 180 uint32_t osh_udec_max; 181 uint32_t osh_udec_min; 182 /* 183 * The number of events and the current level of throttling. 184 */ 185 uint8_t osh_therm_event; 186 uint8_t osh_throt_level; 187 /* 188 * DSSD versioning for the device. (2.0). 189 */ 190 uint8_t osh_vers_errata; 191 uint16_t osh_vers_point; 192 uint16_t osh_vers_minor; 193 uint8_t osh_vers_major; 194 /* 195 * PCIe Correctable error count. 196 */ 197 uint64_t osh_pcie_errcor; 198 /* 199 * Incomplete shutdowns. 200 */ 201 uint32_t osh_inc_shut; 202 uint8_t osh_rsvd116[4]; 203 /* 204 * Normalized free percentage. 205 */ 206 uint8_t osh_free; 207 uint8_t osh_rsvd121[7]; 208 /* 209 * Capacitor health as a percentage. 210 */ 211 uint16_t osh_cap_health; 212 /* 213 * NVMe base spec errata version (2.0). 214 * NVMe cmd spec errata version (2.5). 215 */ 216 uint8_t osh_nvme_base_errata; 217 uint8_t osh_nvme_cmd_errata; 218 uint8_t osh_rsvd132[4]; 219 /* 220 * Quantity of unaligned I/O 221 */ 222 uint64_t osh_unaligned; 223 /* 224 * An incrementing integer representing a security version that 225 * shouldn't be rolled back across. 226 */ 227 uint64_t osh_sec_vers; 228 /* 229 * Namespace utilization. 230 */ 231 uint64_t osh_nuse; 232 /* 233 * Count of events where PLP kicked in. 234 */ 235 uint8_t osh_plp_start[16]; 236 /* 237 * Estimation of total data that can be written to the device in bytes. 238 */ 239 uint8_t osh_endurnace[16]; 240 /* 241 * Count of PCIe retraining events (2.0). 242 */ 243 uint64_t osh_pcie_retrain; 244 /* 245 * Count of power state changes, regardless of initiator. (2.0). 246 */ 247 uint64_t osh_ps_change; 248 /* 249 * Minimum permitted firmware version for rollback purposes. 250 */ 251 uint64_t osh_min_fwrev; 252 uint8_t osh_rsvd216[278]; 253 /* 254 * v1.0: 2, v2.0: 3, v2.5: 4 255 */ 256 uint16_t osh_vers; 257 /* 258 * Log page GUID: AFD514C97C6F4F9CA4f2BFEA2810AFC5h. 259 */ 260 uint8_t osh_guid[16]; 261 } ocp_vul_smart_t; 262 263 /* 264 * OCP Error Recovery log. 265 */ 266 typedef struct { 267 /* 268 * Time in ms to wait for a reset to complete. 269 */ 270 uint16_t oer_prwt; 271 /* 272 * List of reset actions we should consider taking. See ocp_errrec_pra_t 273 * for bit meanings. 274 */ 275 uint8_t oer_pra; 276 /* 277 * List of steps to take to handle the device's recovery from a given 278 * situation. See ocp_errrec_dra_t for bit meanings. 279 */ 280 uint8_t oer_dra; 281 uint64_t oer_panic_id; 282 /* 283 * See ocp_errrec_devcap_t for more information. 284 */ 285 uint32_t oer_devcap; 286 /* 287 * Information for how to send the vendor specific recovery command. The 288 * timout was added in 2.0. 289 */ 290 uint8_t oer_vsr_opcode; 291 uint8_t oer_rsvd17[3]; 292 uint32_t oer_vsr_cdw12; 293 uint32_t oer_vsr_cdw13; 294 uint8_t oer_vsr_to; 295 /* 296 * Secondary recovery actions post-reset (2.5). Uses the same bits as 297 * ocp_errrec_dra_t. 298 */ 299 uint8_t oer_dra2; 300 uint8_t oer_dra2_to; 301 uint8_t oer_npanic; 302 uint64_t oer_old_panics[4]; 303 uint8_t oer_rsvd54[430]; 304 /* 305 * V1.0: 1, V2.0: 2, V2.5: 3 306 */ 307 uint16_t oer_vers; 308 /* 309 * Log page GUID: 5A1983BA3DFD4DABAE3430FE2131D944h. 310 */ 311 uint8_t oer_guid[16]; 312 } ocp_vul_errrec_t; 313 314 /* 315 * List of panic reset actions that should be taken to recover. 316 */ 317 typedef enum { 318 /* NVMe Controller Reset */ 319 OCP_LOG_ERRREC_F_PRA_CTRL = 1 << 0, 320 /* NVM Subsystem Reset */ 321 OCP_LOG_ERRREC_F_PRA_SUBSYS = 1 << 1, 322 /* PCIe Function Level Reset */ 323 OCP_LOG_ERRREC_F_PRA_FLR = 1 << 2, 324 /* ASSERT #PERST (PCIe Fundamental Reset) */ 325 OCP_LOG_ERRREC_F_PRA_PERST = 1 << 3, 326 /* Power cycle the device */ 327 OCP_LOG_ERRREC_F_PRA_POWER = 1 << 4, 328 /* PCIe conventional hot reset */ 329 OCP_LOG_ERRREC_F_PRA_HOT = 1 << 5 330 } ocp_errrec_pra_t; 331 332 typedef enum { 333 /* Do nothing */ 334 OCP_LOG_ERRREC_F_DRA_NONE = 1 << 0, 335 /* Format required */ 336 OCP_LOG_ERRREC_F_DRA_FMT = 1 << 1, 337 /* Vendor specific commad */ 338 OCP_LOG_ERRREC_F_DRA_VSC = 1 << 2, 339 /* Vendor analysis required */ 340 OCP_LOG_ERRREC_F_DRA_VAR = 1 << 3, 341 /* Replace the device */ 342 OCP_LOG_ERRREC_F_DRA_REPLACE = 1 << 4, 343 /* Sanitize required */ 344 OCP_LOG_ERRREC_F_DRA_SANITIZE = 1 << 5, 345 /* 346 * Indicates that there is permanent data loss in some LBAs. The LBAs 347 * are identified by the LBA Status log 0xe. 348 */ 349 OCP_LOG_ERRREC_F_DRA_DATALOSS = 1 << 6, 350 } ocp_errrec_dra_t; 351 352 /* 353 * Device capabilities. Used to indicate how a message about a panic can be sent 354 * today. 355 */ 356 typedef enum { 357 OCP_LOG_ERRREC_F_DEVCAP_AEN = 1 << 0, 358 OCP_LOG_ERRREC_F_DEVCAP_CFS = 1 << 1 359 } ocp_errrec_devcap_t; 360 361 /* 362 * OCP Firmware Activation. Present in 1.0 and 2.0. Removed in 2.5. 363 */ 364 typedef struct { 365 uint8_t ofe_vers; 366 uint8_t ofe_len; 367 uint8_t ofe_rsvd2[2]; 368 uint16_t ofe_count; 369 uint64_t ofe_ts; 370 uint8_t ofe_rsvd14[8]; 371 uint64_t ofe_pcc; 372 uint64_t ofe_prev_fw; 373 uint64_t ofe_new_fw; 374 uint8_t ofe_slot; 375 uint8_t ofe_ctype; 376 uint16_t ofe_res; 377 uint8_t ofe_rsvd50[14]; 378 } ocp_fwact_entry_t; 379 380 typedef struct { 381 uint8_t ofw_lid; 382 uint8_t ofw_rsvd1[3]; 383 uint32_t ofw_nents; 384 ocp_fwact_entry_t ofw_hist[20]; 385 uint8_t ofw_rsvd1288[2790]; 386 /* 387 * V1.0: 1, V2.0: 1 388 */ 389 uint16_t ofw_vers; 390 /* 391 * Log Page GUID: 3AC8AB24DE2A3F6DAB4769A796Dh. 392 */ 393 uint8_t ofw_guid[16]; 394 } ocp_vul_fwact_t; 395 396 /* 397 * Latency Monitor log. Added in V2.0. 398 */ 399 typedef struct { 400 uint32_t obc_read; 401 uint32_t obc_write; 402 uint32_t obc_dealloc; 403 uint32_t obc_rsvd; 404 } ocp_lat_bkt_ctr_t; 405 406 typedef struct { 407 uint64_t ola_read; 408 uint64_t ola_write; 409 uint64_t ola_dealloc; 410 } ocp_lat_alts_t; 411 412 typedef struct { 413 uint16_t olm_read; 414 uint16_t olm_write; 415 uint16_t olm_dealloc; 416 } ocp_lat_aml_t; 417 418 typedef struct { 419 /* 420 * Latency monitor features. See ocp_lat_lmfs_t. 421 */ 422 uint8_t ol_lmfs; 423 uint8_t ol_rsvd1[1]; 424 /* 425 * Active bucket timer, its threshold, and general thresholds. 426 */ 427 uint16_t ol_abt; 428 uint16_t ol_abt_thresh; 429 uint8_t ol_thresh_a; 430 uint8_t ol_thresh_b; 431 uint8_t ol_thresh_c; 432 uint8_t ol_thresh_d; 433 /* 434 * Active latency configuration. See ocp_lat_alc_t. 435 */ 436 uint16_t ol_alc; 437 uint8_t ol_alw_min; 438 uint8_t ol_rsvd13[19]; 439 /* 440 * Active bucket counters. 441 */ 442 ocp_lat_bkt_ctr_t ol_ctr0; 443 ocp_lat_bkt_ctr_t ol_ctr1; 444 ocp_lat_bkt_ctr_t ol_ctr2; 445 ocp_lat_bkt_ctr_t ol_ctr3; 446 /* 447 * Active Latency Stamps. These contain 64-bit timestamps for when 448 * events occurred. Grouped by bucket. 449 */ 450 ocp_lat_alts_t ol_ts0; 451 ocp_lat_alts_t ol_ts1; 452 ocp_lat_alts_t ol_ts2; 453 ocp_lat_alts_t ol_ts3; 454 /* 455 * Active Measured Latency. Grouped by bucket. 456 */ 457 ocp_lat_aml_t ol_aml0; 458 ocp_lat_aml_t ol_aml1; 459 ocp_lat_aml_t ol_aml2; 460 ocp_lat_aml_t ol_aml3; 461 uint16_t ol_als_units; 462 uint8_t ol_rsvd218[22]; 463 /* 464 * Static versions of everything above. 465 */ 466 ocp_lat_bkt_ctr_t ol_sb0; 467 ocp_lat_bkt_ctr_t ol_sb1; 468 ocp_lat_bkt_ctr_t ol_sb2; 469 ocp_lat_bkt_ctr_t ol_sb3; 470 ocp_lat_alts_t ol_sts0; 471 ocp_lat_alts_t ol_sts1; 472 ocp_lat_alts_t ol_sts2; 473 ocp_lat_alts_t ol_sts3; 474 ocp_lat_aml_t ol_saml0; 475 ocp_lat_aml_t ol_saml1; 476 ocp_lat_aml_t ol_saml2; 477 ocp_lat_aml_t ol_saml3; 478 uint16_t ol_als_sunits; 479 uint8_t ol_rsvd426[10]; 480 /* 481 * Debug log related fields. The number of dword fields is specific to 482 * v2.5. 483 */ 484 uint8_t ol_dbg_ndw[12]; 485 uint16_t ol_dbg_trig; 486 uint16_t ol_dbg_ml; 487 uint64_t ol_dbg_ts; 488 uint16_t ol_dbg_ptr; 489 uint16_t ol_dbg_src; 490 uint8_t ol_dbg_units; 491 uint8_t ol_rsvd465[29]; 492 /* 493 * V2.0: 1, V2.5: 4 494 */ 495 uint16_t ol_vers; 496 /* 497 * Log page GUID: 85D45E58D4E643709C6C84D08CC07A92h. 498 */ 499 uint8_t ol_guid[16]; 500 } ocp_vul_lat_t; 501 502 typedef enum { 503 OPC_LOG_LAT_F_LFMS_EN = 1 << 0, 504 OPC_LOG_LAT_F_LFMS_ALC_SUP = 1 << 1, 505 OPC_LOG_LAT_F_LFMS_AML_SUP = 1 << 2, 506 } ocp_lat_lmfs_t; 507 508 typedef enum { 509 OCP_LOG_LAT_F_ALC_B0_READ = 1 << 0, 510 OCP_LOG_LAT_F_ALC_B0_WRITE = 1 << 1, 511 OCP_LOG_LAT_F_ALC_B0_DEALLOC = 1 << 2, 512 OCP_LOG_LAT_F_ALC_B1_READ = 1 << 3, 513 OCP_LOG_LAT_F_ALC_B1_WRITE = 1 << 4, 514 OCP_LOG_LAT_F_ALC_B1_DEALLOC = 1 << 5, 515 OCP_LOG_LAT_F_ALC_B2_READ = 1 << 6, 516 OCP_LOG_LAT_F_ALC_B2_WRITE = 1 << 7, 517 OCP_LOG_LAT_F_ALC_B2_DEALLOC = 1 << 8, 518 OCP_LOG_LAT_F_ALC_B3_READ = 1 << 9, 519 OCP_LOG_LAT_F_ALC_B3_WRITE = 1 << 10, 520 OCP_LOG_LAT_F_ALC_B3_DEALLOC = 1 << 11 521 } ocp_lat_alc_t; 522 523 /* 524 * Device Capabilities Log. Introduced in v2.0. 525 */ 526 typedef struct { 527 #ifdef _BIT_FIELDS_LTOH 528 uint8_t odp_nps:5; 529 uint8_t odp_rsvd5:2; 530 uint8_t odp_valid:1; 531 #else 532 uint8_t odp_valid:1; 533 uint8_t odp_rsvd5:2; 534 uint8_t odp_nps:5; 535 #endif /* _BIT_FIELDS_LTOH */ 536 } ocp_dssd_ps_t; 537 538 typedef struct { 539 uint16_t odc_nports; 540 uint16_t odc_oob_sup; 541 uint16_t odc_wz_sup; 542 uint16_t odc_san_sup; 543 uint16_t odc_dsmgmt_sup; 544 uint16_t odc_wunc_sup; 545 uint16_t odc_fuse_sup; 546 uint16_t odc_dssd_min_valid; 547 ocp_dssd_ps_t odc_dssd[128]; 548 uint8_t odc_rsvd144[3934]; 549 /* 550 * V2.0: 1, V2.5: 1 551 */ 552 uint16_t odc_vers; 553 /* 554 * Log page GUID: B7053C914B58495D98C9E1D10D054297h 555 */ 556 uint8_t odc_guid[16]; 557 } ocp_vul_devcap_t; 558 559 typedef enum { 560 /* PCIe VDM Supported */ 561 OCP_LOG_DEVCAP_F_OOB_VDM = 1 << 0, 562 /* NVMe Basic Management Command supported */ 563 OCP_LOG_DEVCAP_F_OOB_BMC = 1 << 1, 564 /* Passed compliance testing */ 565 OCP_LOG_DEVCAP_F_OOB_COMPLY = 1 << 15, 566 } ocp_devcap_oob_t; 567 568 typedef enum { 569 /* Write Zeros command supported */ 570 OCP_LOG_DEVCAP_F_WZ_SUP = 1 << 0, 571 /* Write Zeros deallocate bit */ 572 OCP_LOG_DEVCAP_F_WZ_DEAC = 1 << 1, 573 /* Write Zeros force unit access */ 574 OCP_LOG_DEVCAP_F_WZ_FUA = 1 << 2, 575 /* Adheres to spec req NVME-IO-5 */ 576 OCP_LOG_DEVCAP_F_WZ_IO5 = 1 << 3, 577 /* Adheres to spec req NVME-IO-6 */ 578 OCP_LOG_DEVCAP_F_WZ_IO6 = 1 << 4, 579 /* Passed compliance testing */ 580 OCP_LOG_DEVCAP_F_WZ_COMPLY = 1 << 15 581 } ocp_devcap_wz_t; 582 583 typedef enum { 584 /* Dataset Management command supported */ 585 OCP_LOG_DEVCAP_F_DSMGMT_SUP = 1 << 0, 586 /* Attribute deallocate supported */ 587 OCP_LOG_DEVCAP_F_DSMGMT_AD = 1 << 1, 588 /* Passed compliance testing */ 589 OCP_LOG_DEVCAP_F_DSMGMT_COMPLY = 1 << 15 590 } ocp_devcap_dsmgmt_t; 591 592 typedef enum { 593 /* Write uncorrectable supported */ 594 OCP_LOG_DEVCAP_F_WUNC_SUP = 1 << 0, 595 /* Works with a single LBA */ 596 OCP_LOG_DEVCAP_F_WUNC_ONE = 1 << 1, 597 /* Works with max LBAs per NVMe spec */ 598 OCP_LOG_DEVCAP_F_WUNC_MAX = 1 << 2, 599 /* Adheres to spec req NVME-IO-14 */ 600 OCP_LOG_DEVCAP_F_WUNC_IO14 = 1 << 3, 601 /* Passed compliance testing */ 602 OCP_LOG_DEVCAP_F_WUNC_COMPLY = 1 << 15 603 } ocp_devcap_wunc_t; 604 605 typedef enum { 606 /* Fused operation supported */ 607 OCP_LOG_DEVCAP_F_FUSE_SUP = 1 << 0, 608 /* Passed compliance testing */ 609 OCP_LOG_DEVCAP_F_FUSE_COMPLY = 1 << 15 610 } ocp_devcap_fuse_t; 611 612 /* 613 * Unsupported Requirements log. This log is structured such that each 614 * unimplemented requirement must fit into a single 16 byte array which should 615 * be padded with zeros (but nothing in the spec suggests it guarantees 616 * termination). We keep the requirements string as a uint8_t as opposed to a 617 * char to indicate that this should not be trusted and must be parsed. 618 */ 619 typedef struct { 620 uint8_t ors_str[16]; 621 } ocp_req_str_t; 622 623 typedef struct { 624 uint16_t our_nunsup; 625 uint8_t our_rsvd2[14]; 626 ocp_req_str_t ors_reqs[253]; 627 uint8_t our_rsvd4064[14]; 628 /* 629 * V2.0: 1, V2.5: 1 630 */ 631 uint16_t our_vers; 632 /* 633 * Log page GUID: C7BB98B7D0324863BB2C23990E9C722Fh 634 */ 635 uint8_t our_guid[16]; 636 } ocp_vul_unsup_req_t; 637 638 /* 639 * Our current version of smatch cannot handle packed structures. 640 */ 641 #ifndef __CHECKER__ 642 CTASSERT(sizeof (ocp_vul_smart_t) == 512); 643 CTASSERT(offsetof(ocp_vul_smart_t, osh_therm_event) == 96); 644 CTASSERT(offsetof(ocp_vul_smart_t, osh_vers) == 494); 645 CTASSERT(sizeof (ocp_vul_errrec_t) == 512); 646 CTASSERT(offsetof(ocp_vul_errrec_t, oer_npanic) == 31); 647 CTASSERT(offsetof(ocp_vul_errrec_t, oer_npanic) == 31); 648 CTASSERT(sizeof (ocp_fwact_entry_t) == 64); 649 CTASSERT(offsetof(ocp_fwact_entry_t, ofe_rsvd50) == 50); 650 CTASSERT(sizeof (ocp_vul_fwact_t) == 4096); 651 CTASSERT(offsetof(ocp_vul_fwact_t, ofw_rsvd1288) == 1288); 652 CTASSERT(offsetof(ocp_vul_fwact_t, ofw_vers) == 4078); 653 CTASSERT(sizeof (ocp_lat_bkt_ctr_t) == 16); 654 CTASSERT(sizeof (ocp_lat_alts_t) == 24); 655 CTASSERT(sizeof (ocp_lat_aml_t) == 6); 656 CTASSERT(offsetof(ocp_vul_lat_t, ol_aml0) == 192); 657 CTASSERT(offsetof(ocp_vul_lat_t, ol_rsvd218) == 218); 658 CTASSERT(offsetof(ocp_vul_lat_t, ol_als_sunits) == 424); 659 CTASSERT(sizeof (ocp_vul_lat_t) == 512); 660 CTASSERT(sizeof (ocp_vul_devcap_t) == 4096); 661 CTASSERT(offsetof(ocp_vul_devcap_t, odc_rsvd144) == 144); 662 CTASSERT(sizeof (ocp_req_str_t) == 16); 663 CTASSERT(sizeof (ocp_vul_unsup_req_t) == 4096); 664 #endif 665 666 #pragma pack() /* pack(1) */ 667 668 #ifdef __cplusplus 669 } 670 #endif 671 672 #endif /* _SYS_NVME_OCP_H */ 673