1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2016 Nexenta Systems, Inc. 14 * Copyright 2020 Joyent, Inc. 15 * Copyright 2019 Western Digital Corporation 16 * Copyright 2021 Oxide Computer Company 17 */ 18 19 #ifndef _SYS_NVME_H 20 #define _SYS_NVME_H 21 22 #include <sys/types.h> 23 24 #ifdef _KERNEL 25 #include <sys/types32.h> 26 #else 27 #include <stdint.h> 28 #endif 29 30 /* 31 * Declarations used for communication between nvmeadm(1M) and nvme(7D) 32 */ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * NVMe ioctl definitions 40 */ 41 42 #define NVME_IOC (('N' << 24) | ('V' << 16) | ('M' << 8)) 43 #define NVME_IOC_IDENTIFY_CTRL (NVME_IOC | 1) 44 #define NVME_IOC_IDENTIFY_NSID (NVME_IOC | 2) 45 #define NVME_IOC_CAPABILITIES (NVME_IOC | 3) 46 #define NVME_IOC_GET_LOGPAGE (NVME_IOC | 4) 47 #define NVME_IOC_GET_FEATURES (NVME_IOC | 5) 48 #define NVME_IOC_INTR_CNT (NVME_IOC | 6) 49 #define NVME_IOC_VERSION (NVME_IOC | 7) 50 #define NVME_IOC_FORMAT (NVME_IOC | 8) 51 #define NVME_IOC_DETACH (NVME_IOC | 9) 52 #define NVME_IOC_ATTACH (NVME_IOC | 10) 53 #define NVME_IOC_FIRMWARE_DOWNLOAD (NVME_IOC | 11) 54 #define NVME_IOC_FIRMWARE_COMMIT (NVME_IOC | 12) 55 #define NVME_IOC_MAX NVME_IOC_FIRMWARE_COMMIT 56 57 #define IS_NVME_IOC(x) ((x) > NVME_IOC && (x) <= NVME_IOC_MAX) 58 #define NVME_IOC_CMD(x) ((x) & 0xff) 59 60 typedef struct { 61 size_t n_len; 62 uintptr_t n_buf; 63 uint64_t n_arg; 64 } nvme_ioctl_t; 65 66 #ifdef _KERNEL 67 typedef struct { 68 size32_t n_len; 69 uintptr32_t n_buf; 70 uint64_t n_arg; 71 } nvme_ioctl32_t; 72 #endif 73 74 /* 75 * NVMe capabilities 76 */ 77 typedef struct { 78 uint32_t mpsmax; /* Memory Page Size Maximum */ 79 uint32_t mpsmin; /* Memory Page Size Minimum */ 80 } nvme_capabilities_t; 81 82 /* 83 * NVMe version 84 */ 85 typedef struct { 86 uint16_t v_minor; 87 uint16_t v_major; 88 } nvme_version_t; 89 90 #define NVME_VERSION_ATLEAST(v, maj, min) \ 91 (((v)->v_major) > (maj) || \ 92 ((v)->v_major == (maj) && (v)->v_minor >= (min))) 93 94 #define NVME_VERSION_HIGHER(v, maj, min) \ 95 (((v)->v_major) > (maj) || \ 96 ((v)->v_major == (maj) && (v)->v_minor > (min))) 97 98 99 #pragma pack(1) 100 101 typedef struct { 102 uint64_t lo; 103 uint64_t hi; 104 } nvme_uint128_t; 105 106 /* 107 * NVMe Identify data structures 108 */ 109 110 #define NVME_IDENTIFY_BUFSIZE 4096 /* buffer size for Identify */ 111 112 /* NVMe Queue Entry Size bitfield */ 113 typedef struct { 114 uint8_t qes_min:4; /* minimum entry size */ 115 uint8_t qes_max:4; /* maximum entry size */ 116 } nvme_idctl_qes_t; 117 118 /* NVMe Power State Descriptor */ 119 typedef struct { 120 uint16_t psd_mp; /* Maximum Power */ 121 uint8_t psd_rsvd1; 122 uint8_t psd_mps:1; /* Max Power Scale (1.1) */ 123 uint8_t psd_nops:1; /* Non-Operational State (1.1) */ 124 uint8_t psd_rsvd2:6; 125 uint32_t psd_enlat; /* Entry Latency */ 126 uint32_t psd_exlat; /* Exit Latency */ 127 uint8_t psd_rrt:5; /* Relative Read Throughput */ 128 uint8_t psd_rsvd3:3; 129 uint8_t psd_rrl:5; /* Relative Read Latency */ 130 uint8_t psd_rsvd4:3; 131 uint8_t psd_rwt:5; /* Relative Write Throughput */ 132 uint8_t psd_rsvd5:3; 133 uint8_t psd_rwl:5; /* Relative Write Latency */ 134 uint8_t psd_rsvd6:3; 135 uint16_t psd_idlp; /* Idle Power (1.2) */ 136 uint8_t psd_rsvd7:6; 137 uint8_t psd_ips:2; /* Idle Power Scale (1.2) */ 138 uint8_t psd_rsvd8; 139 uint16_t psd_actp; /* Active Power (1.2) */ 140 uint8_t psd_apw:3; /* Active Power Workload (1.2) */ 141 uint8_t psd_rsvd9:3; 142 uint8_t psd_aps:2; /* Active Power Scale */ 143 uint8_t psd_rsvd10[9]; 144 } nvme_idctl_psd_t; 145 146 #define NVME_SERIAL_SZ 20 147 #define NVME_MODEL_SZ 40 148 149 /* NVMe Identify Controller Data Structure */ 150 typedef struct { 151 /* Controller Capabilities & Features */ 152 uint16_t id_vid; /* PCI vendor ID */ 153 uint16_t id_ssvid; /* PCI subsystem vendor ID */ 154 char id_serial[NVME_SERIAL_SZ]; /* Serial Number */ 155 char id_model[NVME_MODEL_SZ]; /* Model Number */ 156 char id_fwrev[8]; /* Firmware Revision */ 157 uint8_t id_rab; /* Recommended Arbitration Burst */ 158 uint8_t id_oui[3]; /* vendor IEEE OUI */ 159 struct { /* Multi-Interface Capabilities */ 160 uint8_t m_multi_pci:1; /* HW has multiple PCIe interfaces */ 161 uint8_t m_multi_ctrl:1; /* HW has multiple controllers (1.1) */ 162 uint8_t m_sr_iov:1; /* Controller is SR-IOV virt fn (1.1) */ 163 uint8_t m_anar_sup:1; /* ANA Reporting Supported (1.4) */ 164 uint8_t m_rsvd:4; 165 } id_mic; 166 uint8_t id_mdts; /* Maximum Data Transfer Size */ 167 uint16_t id_cntlid; /* Unique Controller Identifier (1.1) */ 168 /* Added in NVMe 1.2 */ 169 uint32_t id_ver; /* Version (1.2) */ 170 uint32_t id_rtd3r; /* RTD3 Resume Latency (1.2) */ 171 uint32_t id_rtd3e; /* RTD3 Entry Latency (1.2) */ 172 struct { 173 uint32_t oaes_rsvd0:8; 174 uint32_t oaes_nsan:1; /* Namespace Attribute Notices (1.2) */ 175 uint32_t oaes_fwact:1; /* Firmware Activation Notices (1.2) */ 176 uint32_t oaes_rsvd1:1; 177 uint32_t oaes_ansacn:1; /* Asymmetric NS Access Change (1.4) */ 178 uint32_t oaes_plat:1; /* Predictable Lat Event Agg. (1.4) */ 179 uint32_t oaes_lbasi:1; /* LBA Status Information (1.4) */ 180 uint32_t oaes_egeal:1; /* Endurance Group Event Agg. (1.4) */ 181 uint32_t oaes_rsvd2:17; 182 } id_oaes; 183 struct { 184 uint32_t ctrat_hid:1; /* 128-bit Host Identifier (1.2) */ 185 uint32_t ctrat_nops:1; /* Non-Operational Power State (1.3) */ 186 uint32_t ctrat_nvmset:1; /* NVMe Sets (1.4) */ 187 uint32_t ctrat_rrl:1; /* Read Recovery Levels (1.4) */ 188 uint32_t ctrat_engrp:1; /* Endurance Groups (1.4) */ 189 uint32_t ctrat_plm:1; /* Predictable Latency Mode (1.4) */ 190 uint32_t ctrat_tbkas:1; /* Traffic Based Keep Alive (1.4) */ 191 uint32_t ctrat_nsg:1; /* Namespace Granularity (1.4) */ 192 uint32_t ctrat_sqass:1; /* SQ Associations (1.4) */ 193 uint32_t ctrat_uuid:1; /* UUID List (1.4) */ 194 uint32_t ctrat_rsvd:22; 195 } id_ctratt; 196 uint16_t id_rrls; /* Read Recovery Levels (1.4) */ 197 uint8_t id_rsvd_cc[111-102]; 198 uint8_t id_cntrltype; /* Controller Type (1.4) */ 199 uint8_t id_frguid[16]; /* FRU GUID (1.3) */ 200 uint16_t id_crdt1; /* Command Retry Delay Time 1 (1.4) */ 201 uint16_t id_crdt2; /* Command Retry Delay Time 2 (1.4) */ 202 uint16_t id_crdt3; /* Command Retry Delay Time 3 (1.4) */ 203 uint8_t id_rsvd2_cc[240 - 134]; 204 uint8_t id_rsvd_nvmemi[253 - 240]; 205 /* NVMe-MI region */ 206 struct { /* NVMe Subsystem Report */ 207 uint8_t nvmsr_nvmesd:1; /* NVMe Storage Device */ 208 uint8_t nvmsr_nvmee:1; /* NVMe Enclosure */ 209 uint8_t nvmsr_rsvd:6; 210 } id_nvmsr; 211 struct { /* VPD Write Cycle Information */ 212 uint8_t vwci_crem:7; /* Write Cycles Remaining */ 213 uint8_t vwci_valid:1; /* Write Cycles Remaining Valid */ 214 } id_vpdwc; 215 struct { /* Management Endpoint Capabilities */ 216 uint8_t mec_smbusme:1; /* SMBus Port Management Endpoint */ 217 uint8_t mec_pcieme:1; /* PCIe Port Management Endpoint */ 218 uint8_t mec_rsvd:6; 219 } id_mec; 220 221 /* Admin Command Set Attributes */ 222 struct { /* Optional Admin Command Support */ 223 uint16_t oa_security:1; /* Security Send & Receive */ 224 uint16_t oa_format:1; /* Format NVM */ 225 uint16_t oa_firmware:1; /* Firmware Activate & Download */ 226 uint16_t oa_nsmgmt:1; /* Namespace Management (1.2) */ 227 uint16_t oa_selftest:1; /* Self Test (1.3) */ 228 uint16_t oa_direct:1; /* Directives (1.3) */ 229 uint16_t oa_nvmemi:1; /* MI-Send/Recv (1.3) */ 230 uint16_t oa_virtmgmt:1; /* Virtualization Management (1.3) */ 231 uint16_t oa_doorbell:1; /* Doorbell Buffer Config (1.3) */ 232 uint16_t oa_lbastat:1; /* LBA Status (1.4) */ 233 uint16_t oa_rsvd:6; 234 } id_oacs; 235 uint8_t id_acl; /* Abort Command Limit */ 236 uint8_t id_aerl; /* Asynchronous Event Request Limit */ 237 struct { /* Firmware Updates */ 238 uint8_t fw_readonly:1; /* Slot 1 is Read-Only */ 239 uint8_t fw_nslot:3; /* number of firmware slots */ 240 uint8_t fw_norst:1; /* Activate w/o reset (1.2) */ 241 uint8_t fw_rsvd:3; 242 } id_frmw; 243 struct { /* Log Page Attributes */ 244 uint8_t lp_smart:1; /* SMART/Health information per NS */ 245 uint8_t lp_cmdeff:1; /* Command Effects (1.2) */ 246 uint8_t lp_extsup:1; /* Extended Get Log Page (1.2) */ 247 uint8_t lp_telemetry:1; /* Telemetry Log Pages (1.3) */ 248 uint8_t lp_persist:1; /* Persistent Log Page (1.4) */ 249 uint8_t lp_rsvd:3; 250 } id_lpa; 251 uint8_t id_elpe; /* Error Log Page Entries */ 252 uint8_t id_npss; /* Number of Power States */ 253 struct { /* Admin Vendor Specific Command Conf */ 254 uint8_t av_spec:1; /* use format from spec */ 255 uint8_t av_rsvd:7; 256 } id_avscc; 257 struct { /* Autonomous Power State Trans (1.1) */ 258 uint8_t ap_sup:1; /* APST supported (1.1) */ 259 uint8_t ap_rsvd:7; 260 } id_apsta; 261 uint16_t ap_wctemp; /* Warning Composite Temp. (1.2) */ 262 uint16_t ap_cctemp; /* Critical Composite Temp. (1.2) */ 263 uint16_t ap_mtfa; /* Maximum Firmware Activation (1.2) */ 264 uint32_t ap_hmpre; /* Host Memory Buf Pref Size (1.2) */ 265 uint32_t ap_hmmin; /* Host Memory Buf Min Size (1.2) */ 266 nvme_uint128_t ap_tnvmcap; /* Total NVM Capacity in Bytes (1.2) */ 267 nvme_uint128_t ap_unvmcap; /* Unallocated NVM Capacity (1.2) */ 268 struct { /* Replay Protected Mem. Block (1.2) */ 269 uint32_t rpmbs_units:3; /* Number of targets */ 270 uint32_t rpmbs_auth:3; /* Auth method */ 271 uint32_t rpmbs_rsvd:10; 272 uint32_t rpmbs_tot:8; /* Total size in 128KB */ 273 uint32_t rpmbs_acc:8; /* Access size in 512B */ 274 } ap_rpmbs; 275 /* Added in NVMe 1.3 */ 276 uint16_t ap_edstt; /* Ext. Device Self-test time (1.3) */ 277 struct { /* Device Self-test Options */ 278 uint8_t dsto_sub:1; /* Subsystem level self-test (1.3) */ 279 uint8_t dsto_rsvd:7; 280 } ap_dsto; 281 uint8_t ap_fwug; /* Firmware Update Granularity (1.3) */ 282 uint16_t ap_kas; /* Keep Alive Support (1.2) */ 283 struct { /* Host Thermal Management (1.3) */ 284 uint16_t hctma_hctm:1; /* Host Controlled (1.3) */ 285 uint16_t hctma_rsvd:15; 286 } ap_hctma; 287 uint16_t ap_mntmt; /* Minimum Thermal Temperature (1.3) */ 288 uint16_t ap_mxtmt; /* Maximum Thermal Temperature (1.3) */ 289 struct { /* Sanitize Caps */ 290 uint32_t san_ces:1; /* Crypto Erase Support (1.3) */ 291 uint32_t san_bes:1; /* Block Erase Support (1.3) */ 292 uint32_t san_ows:1; /* Overwite Support (1.3) */ 293 uint32_t san_rsvd:26; 294 uint32_t san_ndi:1; /* No-deallocate Inhibited (1.4) */ 295 uint32_t san_nodmmas:2; /* No-Deallocate Modifies Media (1.4) */ 296 } ap_sanitize; 297 uint32_t ap_hmminds; /* Host Mem Buf Min Desc Entry (1.4) */ 298 uint16_t ap_hmmaxd; /* How Mem Max Desc Entries (1.4) */ 299 uint16_t ap_nsetidmax; /* Max NVMe set identifier (1.4) */ 300 uint16_t ap_engidmax; /* Max Endurance Group ID (1.4) */ 301 uint8_t ap_anatt; /* ANA Transition Time (1.4) */ 302 struct { /* Asymmetric Namespace Access Caps */ 303 uint8_t anacap_opt:1; /* Optimized State (1.4) */ 304 uint8_t anacap_unopt:1; /* Un-optimized State (1.4) */ 305 uint8_t anacap_inacc:1; /* Inaccessible State (1.4) */ 306 uint8_t anacap_ploss:1; /* Persistent Loss (1.4) */ 307 uint8_t anacap_chg:1; /* Change State (1.4 ) */ 308 uint8_t anacap_rsvd:1; 309 uint8_t anacap_grpns:1; /* ID Changes with NS Attach (1.4) */ 310 uint8_t anacap_grpid:1; /* Supports Group ID (1.4) */ 311 } ap_anacap; 312 uint32_t ap_anagrpmax; /* ANA Group ID Max (1.4) */ 313 uint32_t ap_nanagrpid; /* Number of ANA Group IDs (1.4) */ 314 uint32_t ap_pels; /* Persistent Event Log Size (1.4) */ 315 uint8_t id_rsvd_ac[512 - 356]; 316 317 /* NVM Command Set Attributes */ 318 nvme_idctl_qes_t id_sqes; /* Submission Queue Entry Size */ 319 nvme_idctl_qes_t id_cqes; /* Completion Queue Entry Size */ 320 uint16_t id_maxcmd; /* Max Outstanding Commands (1.3) */ 321 uint32_t id_nn; /* Number of Namespaces */ 322 struct { /* Optional NVM Command Support */ 323 uint16_t on_compare:1; /* Compare */ 324 uint16_t on_wr_unc:1; /* Write Uncorrectable */ 325 uint16_t on_dset_mgmt:1; /* Dataset Management */ 326 uint16_t on_wr_zero:1; /* Write Zeros (1.1) */ 327 uint16_t on_save:1; /* Save/Select in Get/Set Feat (1.1) */ 328 uint16_t on_reserve:1; /* Reservations (1.1) */ 329 uint16_t on_ts:1; /* Timestamp (1.3) */ 330 uint16_t on_verify:1; /* Verify (1.4) */ 331 uint16_t on_rsvd:8; 332 } id_oncs; 333 struct { /* Fused Operation Support */ 334 uint16_t f_cmp_wr:1; /* Compare and Write */ 335 uint16_t f_rsvd:15; 336 } id_fuses; 337 struct { /* Format NVM Attributes */ 338 uint8_t fn_format:1; /* Format applies to all NS */ 339 uint8_t fn_sec_erase:1; /* Secure Erase applies to all NS */ 340 uint8_t fn_crypt_erase:1; /* Cryptographic Erase supported */ 341 uint8_t fn_rsvd:5; 342 } id_fna; 343 struct { /* Volatile Write Cache */ 344 uint8_t vwc_present:1; /* Volatile Write Cache present */ 345 uint8_t vwc_nsflush:2; /* Flush with NS ffffffff (1.4) */ 346 uint8_t rsvd:5; 347 } id_vwc; 348 uint16_t id_awun; /* Atomic Write Unit Normal */ 349 uint16_t id_awupf; /* Atomic Write Unit Power Fail */ 350 struct { /* NVM Vendor Specific Command Conf */ 351 uint8_t nv_spec:1; /* use format from spec */ 352 uint8_t nv_rsvd:7; 353 } id_nvscc; 354 struct { /* Namespace Write Protection Caps */ 355 uint8_t nwpc_base:1; /* Base support (1.4) */ 356 uint8_t nwpc_wpupc:1; /* Write prot until power cycle (1.4) */ 357 uint8_t nwpc_permwp:1; /* Permanent write prot (1.4) */ 358 uint8_t nwpc_rsvd:5; 359 } id_nwpc; 360 uint16_t id_acwu; /* Atomic Compare & Write Unit (1.1) */ 361 uint16_t id_rsvd_nc_3; 362 struct { /* SGL Support (1.1) */ 363 uint16_t sgl_sup:2; /* SGL Supported in NVM cmds (1.3) */ 364 uint16_t sgl_keyed:1; /* Keyed SGL Support (1.2) */ 365 uint16_t sgl_rsvd1:13; 366 uint16_t sgl_bucket:1; /* SGL Bit Bucket supported (1.1) */ 367 uint16_t sgl_balign:1; /* SGL Byte Aligned (1.2) */ 368 uint16_t sgl_sglgtd:1; /* SGL Length Longer than Data (1.2) */ 369 uint16_t sgl_mptr:1; /* SGL MPTR w/ SGL (1.2) */ 370 uint16_t sgl_offset:1; /* SGL Address is offset (1.2) */ 371 uint16_t sgl_tport:1; /* Transport SGL Data Block (1.4) */ 372 uint16_t sgl_rsvd2:10; 373 } id_sgls; 374 uint32_t id_mnam; /* Maximum Number of Allowed NSes */ 375 uint8_t id_rsvd_nc_4[768 - 544]; 376 377 /* I/O Command Set Attributes */ 378 uint8_t id_subnqn[1024 - 768]; /* Subsystem Qualified Name (1.2.1+) */ 379 uint8_t id_rsvd_ioc[1792 - 1024]; 380 uint8_t id_nvmof[2048 - 1792]; /* NVMe over Fabrics */ 381 382 /* Power State Descriptors */ 383 nvme_idctl_psd_t id_psd[32]; 384 385 /* Vendor Specific */ 386 uint8_t id_vs[1024]; 387 } nvme_identify_ctrl_t; 388 389 /* 390 * NVMe Controller Types 391 */ 392 #define NVME_CNTRLTYPE_RSVD 0 393 #define NVME_CNTRLTYPE_IO 1 394 #define NVME_CNTRLTYPE_DISC 2 395 #define NVME_CNTRLTYPE_ADMIN 3 396 397 /* 398 * RPMBS Authentication Types 399 */ 400 #define NVME_RPMBS_AUTH_HMAC_SHA256 0 401 402 /* 403 * NODMMAS Values 404 */ 405 #define NVME_NODMMAS_UNDEF 0x00 406 #define NVME_NODMMAS_NOMOD 0x01 407 #define NVME_NODMMAS_DOMOD 0x02 408 409 /* 410 * VWC NSID flushes 411 */ 412 #define NVME_VWCNS_UNKNOWN 0x00 413 #define NVME_VWCNS_UNSUP 0x02 414 #define NVME_VWCNS_SUP 0x03 415 416 /* 417 * SGL Support Values 418 */ 419 #define NVME_SGL_UNSUP 0x00 420 #define NVME_SGL_SUP_UNALIGN 0x01 421 #define NVME_SGL_SUP_ALIGN 0x02 422 423 /* NVMe Identify Namespace LBA Format */ 424 typedef struct { 425 uint16_t lbaf_ms; /* Metadata Size */ 426 uint8_t lbaf_lbads; /* LBA Data Size */ 427 uint8_t lbaf_rp:2; /* Relative Performance */ 428 uint8_t lbaf_rsvd1:6; 429 } nvme_idns_lbaf_t; 430 431 /* NVMe Identify Namespace Data Structure */ 432 typedef struct { 433 uint64_t id_nsize; /* Namespace Size */ 434 uint64_t id_ncap; /* Namespace Capacity */ 435 uint64_t id_nuse; /* Namespace Utilization */ 436 struct { /* Namespace Features */ 437 uint8_t f_thin:1; /* Thin Provisioning */ 438 uint8_t f_nsabp:1; /* Namespace atomics (1.2) */ 439 uint8_t f_dae:1; /* Deallocated errors supported (1.2) */ 440 uint8_t f_uidreuse:1; /* GUID reuse impossible (1.3) */ 441 uint8_t f_optperf:1; /* Namespace I/O opt (1.4) */ 442 uint8_t f_rsvd:3; 443 } id_nsfeat; 444 uint8_t id_nlbaf; /* Number of LBA formats */ 445 struct { /* Formatted LBA size */ 446 uint8_t lba_format:4; /* LBA format */ 447 uint8_t lba_extlba:1; /* extended LBA (includes metadata) */ 448 uint8_t lba_rsvd:3; 449 } id_flbas; 450 struct { /* Metadata Capabilities */ 451 uint8_t mc_extlba:1; /* extended LBA transfers */ 452 uint8_t mc_separate:1; /* separate metadata transfers */ 453 uint8_t mc_rsvd:6; 454 } id_mc; 455 struct { /* Data Protection Capabilities */ 456 uint8_t dp_type1:1; /* Protection Information Type 1 */ 457 uint8_t dp_type2:1; /* Protection Information Type 2 */ 458 uint8_t dp_type3:1; /* Protection Information Type 3 */ 459 uint8_t dp_first:1; /* first 8 bytes of metadata */ 460 uint8_t dp_last:1; /* last 8 bytes of metadata */ 461 uint8_t dp_rsvd:3; 462 } id_dpc; 463 struct { /* Data Protection Settings */ 464 uint8_t dp_pinfo:3; /* Protection Information enabled */ 465 uint8_t dp_first:1; /* first 8 bytes of metadata */ 466 uint8_t dp_rsvd:4; 467 } id_dps; 468 struct { /* NS Multi-Path/Sharing Cap (1.1) */ 469 uint8_t nm_shared:1; /* NS is shared (1.1) */ 470 uint8_t nm_rsvd:7; 471 } id_nmic; 472 struct { /* Reservation Capabilities (1.1) */ 473 uint8_t rc_persist:1; /* Persist Through Power Loss (1.1) */ 474 uint8_t rc_wr_excl:1; /* Write Exclusive (1.1) */ 475 uint8_t rc_excl:1; /* Exclusive Access (1.1) */ 476 uint8_t rc_wr_excl_r:1; /* Wr Excl - Registrants Only (1.1) */ 477 uint8_t rc_excl_r:1; /* Excl Acc - Registrants Only (1.1) */ 478 uint8_t rc_wr_excl_a:1; /* Wr Excl - All Registrants (1.1) */ 479 uint8_t rc_excl_a:1; /* Excl Acc - All Registrants (1.1) */ 480 uint8_t rc_ign_ekey:1; /* Ignore Existing Key (1.3) */ 481 } id_rescap; 482 struct { /* Format Progress Indicator (1.2) */ 483 uint8_t fpi_remp:7; /* Percent NVM Format Remaining (1.2) */ 484 uint8_t fpi_sup:1; /* Supported (1.2) */ 485 } id_fpi; 486 uint8_t id_dfleat; /* Deallocate Log. Block (1.3) */ 487 uint16_t id_nawun; /* Atomic Write Unit Normal (1.2) */ 488 uint16_t id_nawupf; /* Atomic Write Unit Power Fail (1.2) */ 489 uint16_t id_nacwu; /* Atomic Compare & Write Unit (1.2) */ 490 uint16_t id_nabsn; /* Atomic Boundary Size Normal (1.2) */ 491 uint16_t id_nbao; /* Atomic Boundary Offset (1.2) */ 492 uint16_t id_nabspf; /* Atomic Boundary Size Fail (1.2) */ 493 uint16_t id_noiob; /* Optimal I/O Bondary (1.3) */ 494 nvme_uint128_t id_nvmcap; /* NVM Capacity */ 495 uint16_t id_npwg; /* NS Pref. Write Gran. (1.4) */ 496 uint16_t id_npwa; /* NS Pref. Write Align. (1.4) */ 497 uint16_t id_npdg; /* NS Pref. Deallocate Gran. (1.4) */ 498 uint16_t id_npda; /* NS Pref. Deallocate Align. (1.4) */ 499 uint16_t id_nows; /* NS. Optimal Write Size (1.4) */ 500 uint8_t id_rsvd1[92 - 74]; 501 uint32_t id_anagrpid; /* ANA Group Identifier (1.4) */ 502 uint8_t id_rsvd2[99 - 96]; 503 struct { 504 uint8_t nsa_wprot:1; /* Write Protected (1.4) */ 505 uint8_t nsa_rsvd:7; 506 } id_nsattr; 507 uint16_t id_nvmsetid; /* NVM Set Identifier (1.4) */ 508 uint16_t id_endgid; /* Endurance Group Identifier (1.4) */ 509 uint8_t id_nguid[16]; /* Namespace GUID (1.2) */ 510 uint8_t id_eui64[8]; /* IEEE Extended Unique Id (1.1) */ 511 nvme_idns_lbaf_t id_lbaf[16]; /* LBA Formats */ 512 513 uint8_t id_rsvd3[384 - 192]; 514 515 uint8_t id_vs[4096 - 384]; /* Vendor Specific */ 516 } nvme_identify_nsid_t; 517 518 /* NVMe Identify Primary Controller Capabilities */ 519 typedef struct { 520 uint16_t nipc_cntlid; /* Controller ID */ 521 uint16_t nipc_portid; /* Port Identifier */ 522 uint8_t nipc_crt; /* Controller Resource Types */ 523 uint8_t nipc_rsvd0[32 - 5]; 524 uint32_t nipc_vqfrt; /* VQ Resources Flexible Total */ 525 uint32_t nipc_vqrfa; /* VQ Resources Flexible Assigned */ 526 uint16_t nipc_vqrfap; /* VQ Resources to Primary */ 527 uint16_t nipc_vqprt; /* VQ Resources Private Total */ 528 uint16_t nipc_vqfrsm; /* VQ Resources Secondary Max */ 529 uint16_t nipc_vqgran; /* VQ Flexible Resource Gran */ 530 uint8_t nipc_rvsd1[64 - 48]; 531 uint32_t nipc_vifrt; /* VI Flexible total */ 532 uint32_t nipc_virfa; /* VI Flexible Assigned */ 533 uint16_t nipc_virfap; /* VI Flexible Allocated to Primary */ 534 uint16_t nipc_viprt; /* VI Resources Private Total */ 535 uint16_t nipc_vifrsm; /* VI Resources Secondary Max */ 536 uint16_t nipc_vigran; /* VI Flexible Granularity */ 537 uint8_t nipc_rsvd2[4096 - 80]; 538 } nvme_identify_primary_caps_t; 539 540 /* 541 * NVMe completion queue entry status field 542 */ 543 typedef struct { 544 uint16_t sf_p:1; /* Phase Tag */ 545 uint16_t sf_sc:8; /* Status Code */ 546 uint16_t sf_sct:3; /* Status Code Type */ 547 uint16_t sf_rsvd2:2; 548 uint16_t sf_m:1; /* More */ 549 uint16_t sf_dnr:1; /* Do Not Retry */ 550 } nvme_cqe_sf_t; 551 552 553 /* 554 * NVMe Get Log Page 555 */ 556 #define NVME_LOGPAGE_ERROR 0x1 /* Error Information */ 557 #define NVME_LOGPAGE_HEALTH 0x2 /* SMART/Health Information */ 558 #define NVME_LOGPAGE_FWSLOT 0x3 /* Firmware Slot Information */ 559 560 typedef struct { 561 uint64_t el_count; /* Error Count */ 562 uint16_t el_sqid; /* Submission Queue ID */ 563 uint16_t el_cid; /* Command ID */ 564 nvme_cqe_sf_t el_sf; /* Status Field */ 565 uint8_t el_byte; /* Parameter Error Location byte */ 566 uint8_t el_bit:3; /* Parameter Error Location bit */ 567 uint8_t el_rsvd1:5; 568 uint64_t el_lba; /* Logical Block Address */ 569 uint32_t el_nsid; /* Namespace ID */ 570 uint8_t el_vendor; /* Vendor Specific Information avail */ 571 uint8_t el_rsvd2[64 - 29]; 572 } nvme_error_log_entry_t; 573 574 typedef struct { 575 struct { /* Critical Warning */ 576 uint8_t cw_avail:1; /* available space too low */ 577 uint8_t cw_temp:1; /* temperature too high */ 578 uint8_t cw_reliab:1; /* degraded reliability */ 579 uint8_t cw_readonly:1; /* media is read-only */ 580 uint8_t cw_volatile:1; /* volatile memory backup failed */ 581 uint8_t cw_rsvd:3; 582 } hl_crit_warn; 583 uint16_t hl_temp; /* Temperature */ 584 uint8_t hl_avail_spare; /* Available Spare */ 585 uint8_t hl_avail_spare_thr; /* Available Spare Threshold */ 586 uint8_t hl_used; /* Percentage Used */ 587 uint8_t hl_rsvd1[32 - 6]; 588 nvme_uint128_t hl_data_read; /* Data Units Read */ 589 nvme_uint128_t hl_data_write; /* Data Units Written */ 590 nvme_uint128_t hl_host_read; /* Host Read Commands */ 591 nvme_uint128_t hl_host_write; /* Host Write Commands */ 592 nvme_uint128_t hl_ctrl_busy; /* Controller Busy Time */ 593 nvme_uint128_t hl_power_cycles; /* Power Cycles */ 594 nvme_uint128_t hl_power_on_hours; /* Power On Hours */ 595 nvme_uint128_t hl_unsafe_shutdn; /* Unsafe Shutdowns */ 596 nvme_uint128_t hl_media_errors; /* Media Errors */ 597 nvme_uint128_t hl_errors_logged; /* Number of errors logged */ 598 /* Added in NVMe 1.2 */ 599 uint32_t hl_warn_temp_time; /* Warning Composite Temp Time */ 600 uint32_t hl_crit_temp_time; /* Critical Composite Temp Time */ 601 uint16_t hl_temp_sensor_1; /* Temperature Sensor 1 */ 602 uint16_t hl_temp_sensor_2; /* Temperature Sensor 2 */ 603 uint16_t hl_temp_sensor_3; /* Temperature Sensor 3 */ 604 uint16_t hl_temp_sensor_4; /* Temperature Sensor 4 */ 605 uint16_t hl_temp_sensor_5; /* Temperature Sensor 5 */ 606 uint16_t hl_temp_sensor_6; /* Temperature Sensor 6 */ 607 uint16_t hl_temp_sensor_7; /* Temperature Sensor 7 */ 608 uint16_t hl_temp_sensor_8; /* Temperature Sensor 8 */ 609 /* Added in NVMe 1.3 */ 610 uint32_t hl_tmtemp_1_tc; /* Thermal Mgmt Temp 1 Transition # */ 611 uint32_t hl_tmtemp_2_tc; /* Thermal Mgmt Temp 1 Transition # */ 612 uint32_t hl_tmtemp_1_time; /* Time in Thermal Mgmt Temp 1 */ 613 uint32_t hl_tmtemp_2_time; /* Time in Thermal Mgmt Temp 2 */ 614 uint8_t hl_rsvd2[512 - 232]; 615 } nvme_health_log_t; 616 617 /* 618 * The NVMe spec allows for up to seven firmware slots. 619 */ 620 #define NVME_MAX_FWSLOTS 7 621 #define NVME_FWVER_SZ 8 622 623 typedef struct { 624 /* Active Firmware Slot */ 625 uint8_t fw_afi:3; 626 uint8_t fw_rsvd1:1; 627 /* Next Active Firmware Slot */ 628 uint8_t fw_next:3; 629 uint8_t fw_rsvd2:1; 630 uint8_t fw_rsvd3[7]; 631 /* Firmware Revision / Slot */ 632 char fw_frs[NVME_MAX_FWSLOTS][NVME_FWVER_SZ]; 633 uint8_t fw_rsvd4[512 - 64]; 634 } nvme_fwslot_log_t; 635 636 637 /* 638 * NVMe Format NVM 639 */ 640 #define NVME_FRMT_SES_NONE 0 641 #define NVME_FRMT_SES_USER 1 642 #define NVME_FRMT_SES_CRYPTO 2 643 #define NVME_FRMT_MAX_SES 2 644 645 #define NVME_FRMT_MAX_LBAF 15 646 647 typedef union { 648 struct { 649 uint32_t fm_lbaf:4; /* LBA Format */ 650 uint32_t fm_ms:1; /* Metadata Settings */ 651 uint32_t fm_pi:3; /* Protection Information */ 652 uint32_t fm_pil:1; /* Prot. Information Location */ 653 uint32_t fm_ses:3; /* Secure Erase Settings */ 654 uint32_t fm_resvd:20; 655 } b; 656 uint32_t r; 657 } nvme_format_nvm_t; 658 659 660 /* 661 * NVMe Get / Set Features 662 */ 663 #define NVME_FEAT_ARBITRATION 0x1 /* Command Arbitration */ 664 #define NVME_FEAT_POWER_MGMT 0x2 /* Power Management */ 665 #define NVME_FEAT_LBA_RANGE 0x3 /* LBA Range Type */ 666 #define NVME_FEAT_TEMPERATURE 0x4 /* Temperature Threshold */ 667 #define NVME_FEAT_ERROR 0x5 /* Error Recovery */ 668 #define NVME_FEAT_WRITE_CACHE 0x6 /* Volatile Write Cache */ 669 #define NVME_FEAT_NQUEUES 0x7 /* Number of Queues */ 670 #define NVME_FEAT_INTR_COAL 0x8 /* Interrupt Coalescing */ 671 #define NVME_FEAT_INTR_VECT 0x9 /* Interrupt Vector Configuration */ 672 #define NVME_FEAT_WRITE_ATOM 0xa /* Write Atomicity */ 673 #define NVME_FEAT_ASYNC_EVENT 0xb /* Asynchronous Event Configuration */ 674 #define NVME_FEAT_AUTO_PST 0xc /* Autonomous Power State Transition */ 675 /* (1.1) */ 676 677 #define NVME_FEAT_PROGRESS 0x80 /* Software Progress Marker */ 678 679 /* Arbitration Feature */ 680 typedef union { 681 struct { 682 uint8_t arb_ab:3; /* Arbitration Burst */ 683 uint8_t arb_rsvd:5; 684 uint8_t arb_lpw; /* Low Priority Weight */ 685 uint8_t arb_mpw; /* Medium Priority Weight */ 686 uint8_t arb_hpw; /* High Priority Weight */ 687 } b; 688 uint32_t r; 689 } nvme_arbitration_t; 690 691 /* Power Management Feature */ 692 typedef union { 693 struct { 694 uint32_t pm_ps:5; /* Power State */ 695 uint32_t pm_rsvd:27; 696 } b; 697 uint32_t r; 698 } nvme_power_mgmt_t; 699 700 /* LBA Range Type Feature */ 701 typedef union { 702 struct { 703 uint32_t lr_num:6; /* Number of LBA ranges */ 704 uint32_t lr_rsvd:26; 705 } b; 706 uint32_t r; 707 } nvme_lba_range_type_t; 708 709 typedef struct { 710 uint8_t lr_type; /* Type */ 711 struct { /* Attributes */ 712 uint8_t lr_write:1; /* may be overwritten */ 713 uint8_t lr_hidden:1; /* hidden from OS/EFI/BIOS */ 714 uint8_t lr_rsvd1:6; 715 } lr_attr; 716 uint8_t lr_rsvd2[14]; 717 uint64_t lr_slba; /* Starting LBA */ 718 uint64_t lr_nlb; /* Number of Logical Blocks */ 719 uint8_t lr_guid[16]; /* Unique Identifier */ 720 uint8_t lr_rsvd3[16]; 721 } nvme_lba_range_t; 722 723 #define NVME_LBA_RANGE_BUFSIZE 4096 724 725 /* Temperature Threshold Feature */ 726 typedef union { 727 struct { 728 uint16_t tt_tmpth; /* Temperature Threshold */ 729 uint16_t tt_tmpsel:4; /* Temperature Select */ 730 uint16_t tt_thsel:2; /* Temperature Type */ 731 uint16_t tt_resv:10; 732 } b; 733 uint32_t r; 734 } nvme_temp_threshold_t; 735 736 #define NVME_TEMP_THRESH_MAX_SENSOR 8 737 #define NVME_TEMP_THRESH_ALL 0xf 738 #define NVME_TEMP_THRESH_OVER 0x00 739 #define NVME_TEMP_THRESH_UNDER 0x01 740 741 /* Error Recovery Feature */ 742 typedef union { 743 struct { 744 uint16_t er_tler; /* Time-Limited Error Recovery */ 745 uint16_t er_rsvd; 746 } b; 747 uint32_t r; 748 } nvme_error_recovery_t; 749 750 /* Volatile Write Cache Feature */ 751 typedef union { 752 struct { 753 uint32_t wc_wce:1; /* Volatile Write Cache Enable */ 754 uint32_t wc_rsvd:31; 755 } b; 756 uint32_t r; 757 } nvme_write_cache_t; 758 759 /* Number of Queues Feature */ 760 typedef union { 761 struct { 762 uint16_t nq_nsq; /* Number of Submission Queues */ 763 uint16_t nq_ncq; /* Number of Completion Queues */ 764 } b; 765 uint32_t r; 766 } nvme_nqueues_t; 767 768 /* Interrupt Coalescing Feature */ 769 typedef union { 770 struct { 771 uint8_t ic_thr; /* Aggregation Threshold */ 772 uint8_t ic_time; /* Aggregation Time */ 773 uint16_t ic_rsvd; 774 } b; 775 uint32_t r; 776 } nvme_intr_coal_t; 777 778 /* Interrupt Configuration Features */ 779 typedef union { 780 struct { 781 uint16_t iv_iv; /* Interrupt Vector */ 782 uint16_t iv_cd:1; /* Coalescing Disable */ 783 uint16_t iv_rsvd:15; 784 } b; 785 uint32_t r; 786 } nvme_intr_vect_t; 787 788 /* Write Atomicity Feature */ 789 typedef union { 790 struct { 791 uint32_t wa_dn:1; /* Disable Normal */ 792 uint32_t wa_rsvd:31; 793 } b; 794 uint32_t r; 795 } nvme_write_atomicity_t; 796 797 /* Asynchronous Event Configuration Feature */ 798 typedef union { 799 struct { 800 uint8_t aec_avail:1; /* available space too low */ 801 uint8_t aec_temp:1; /* temperature too high */ 802 uint8_t aec_reliab:1; /* degraded reliability */ 803 uint8_t aec_readonly:1; /* media is read-only */ 804 uint8_t aec_volatile:1; /* volatile memory backup failed */ 805 uint8_t aec_rsvd1:3; 806 uint8_t aec_rsvd2[3]; 807 } b; 808 uint32_t r; 809 } nvme_async_event_conf_t; 810 811 /* Autonomous Power State Transition Feature (1.1) */ 812 typedef union { 813 struct { 814 uint8_t apst_apste:1; /* APST enabled */ 815 uint8_t apst_rsvd:7; 816 } b; 817 uint8_t r; 818 } nvme_auto_power_state_trans_t; 819 820 typedef struct { 821 uint32_t apst_rsvd1:3; 822 uint32_t apst_itps:5; /* Idle Transition Power State */ 823 uint32_t apst_itpt:24; /* Idle Time Prior to Transition */ 824 uint32_t apst_rsvd2; 825 } nvme_auto_power_state_t; 826 827 #define NVME_AUTO_PST_BUFSIZE 256 828 829 /* Software Progress Marker Feature */ 830 typedef union { 831 struct { 832 uint8_t spm_pbslc; /* Pre-Boot Software Load Count */ 833 uint8_t spm_rsvd[3]; 834 } b; 835 uint32_t r; 836 } nvme_software_progress_marker_t; 837 838 /* 839 * Firmware Commit - Command Dword 10 840 */ 841 #define NVME_FWC_SAVE 0x0 /* Save image only */ 842 #define NVME_FWC_SAVE_ACTIVATE 0x1 /* Save and activate at next reset */ 843 #define NVME_FWC_ACTIVATE 0x2 /* Activate slot at next reset */ 844 #define NVME_FWC_ACTIVATE_IMMED 0x3 /* Activate slot immediately */ 845 846 /* 847 * Firmware slot number is only 3 bits, and zero is not allowed. 848 * Valid range is 1 to 7. 849 */ 850 #define NVME_FW_SLOT_MIN 1 /* lowest allowable slot number ... */ 851 #define NVME_FW_SLOT_MAX 7 /* ... and highest */ 852 853 /* 854 * Some constants to make verification of DWORD variables and arguments easier. 855 * A DWORD is 4 bytes. 856 */ 857 #define NVME_DWORD_SHIFT 2 858 #define NVME_DWORD_SIZE (1 << NVME_DWORD_SHIFT) 859 #define NVME_DWORD_MASK (NVME_DWORD_SIZE - 1) 860 861 /* 862 * Maximum offset a firmware image can be load at is the number of 863 * DWORDS in a 32 bit field. Expressed in bytes its is: 864 */ 865 #define NVME_FW_OFFSETB_MAX ((u_longlong_t)UINT32_MAX << NVME_DWORD_SHIFT) 866 867 typedef union { 868 struct { 869 uint32_t fc_slot:3; /* Firmware slot */ 870 uint32_t fc_action:3; /* Commit action */ 871 uint32_t fc_rsvd:26; 872 } b; 873 uint32_t r; 874 } nvme_firmware_commit_dw10_t; 875 876 #pragma pack() /* pack(1) */ 877 878 /* NVMe completion status code type */ 879 #define NVME_CQE_SCT_GENERIC 0 /* Generic Command Status */ 880 #define NVME_CQE_SCT_SPECIFIC 1 /* Command Specific Status */ 881 #define NVME_CQE_SCT_INTEGRITY 2 /* Media and Data Integrity Errors */ 882 #define NVME_CQE_SCT_VENDOR 7 /* Vendor Specific */ 883 884 /* NVMe completion status code (generic) */ 885 #define NVME_CQE_SC_GEN_SUCCESS 0x0 /* Successful Completion */ 886 #define NVME_CQE_SC_GEN_INV_OPC 0x1 /* Invalid Command Opcode */ 887 #define NVME_CQE_SC_GEN_INV_FLD 0x2 /* Invalid Field in Command */ 888 #define NVME_CQE_SC_GEN_ID_CNFL 0x3 /* Command ID Conflict */ 889 #define NVME_CQE_SC_GEN_DATA_XFR_ERR 0x4 /* Data Transfer Error */ 890 #define NVME_CQE_SC_GEN_ABORT_PWRLOSS 0x5 /* Cmds Aborted / Pwr Loss */ 891 #define NVME_CQE_SC_GEN_INTERNAL_ERR 0x6 /* Internal Error */ 892 #define NVME_CQE_SC_GEN_ABORT_REQUEST 0x7 /* Command Abort Requested */ 893 #define NVME_CQE_SC_GEN_ABORT_SQ_DEL 0x8 /* Cmd Aborted / SQ deletion */ 894 #define NVME_CQE_SC_GEN_ABORT_FUSE_FAIL 0x9 /* Cmd Aborted / Failed Fused */ 895 #define NVME_CQE_SC_GEN_ABORT_FUSE_MISS 0xa /* Cmd Aborted / Missing Fusd */ 896 #define NVME_CQE_SC_GEN_INV_NS 0xb /* Inval Namespace or Format */ 897 #define NVME_CQE_SC_GEN_CMD_SEQ_ERR 0xc /* Command Sequence Error */ 898 #define NVME_CQE_SC_GEN_INV_SGL_LAST 0xd /* Inval SGL Last Seg Desc */ 899 #define NVME_CQE_SC_GEN_INV_SGL_NUM 0xe /* Inval Number of SGL Desc */ 900 #define NVME_CQE_SC_GEN_INV_DSGL_LEN 0xf /* Data SGL Length Invalid */ 901 #define NVME_CQE_SC_GEN_INV_MSGL_LEN 0x10 /* Metadata SGL Length Inval */ 902 #define NVME_CQE_SC_GEN_INV_SGL_DESC 0x11 /* SGL Descriptor Type Inval */ 903 #define NVME_CQE_SC_GEN_INV_USE_CMB 0x12 /* Inval use of Ctrl Mem Buf */ 904 #define NVME_CQE_SC_GEN_INV_PRP_OFF 0x13 /* PRP Offset Invalid */ 905 #define NVME_CQE_SC_GEN_AWU_EXCEEDED 0x14 /* Atomic Write Unit Exceeded */ 906 907 /* NVMe completion status code (generic NVM commands) */ 908 #define NVME_CQE_SC_GEN_NVM_LBA_RANGE 0x80 /* LBA Out Of Range */ 909 #define NVME_CQE_SC_GEN_NVM_CAP_EXC 0x81 /* Capacity Exceeded */ 910 #define NVME_CQE_SC_GEN_NVM_NS_NOTRDY 0x82 /* Namespace Not Ready */ 911 #define NVME_CQE_SC_GEN_NVM_RSV_CNFLCT 0x83 /* Reservation Conflict */ 912 913 /* NVMe completion status code (command specific) */ 914 #define NVME_CQE_SC_SPC_INV_CQ 0x0 /* Completion Queue Invalid */ 915 #define NVME_CQE_SC_SPC_INV_QID 0x1 /* Invalid Queue Identifier */ 916 #define NVME_CQE_SC_SPC_MAX_QSZ_EXC 0x2 /* Max Queue Size Exceeded */ 917 #define NVME_CQE_SC_SPC_ABRT_CMD_EXC 0x3 /* Abort Cmd Limit Exceeded */ 918 #define NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC 0x5 /* Async Event Request Limit */ 919 #define NVME_CQE_SC_SPC_INV_FW_SLOT 0x6 /* Invalid Firmware Slot */ 920 #define NVME_CQE_SC_SPC_INV_FW_IMG 0x7 /* Invalid Firmware Image */ 921 #define NVME_CQE_SC_SPC_INV_INT_VECT 0x8 /* Invalid Interrupt Vector */ 922 #define NVME_CQE_SC_SPC_INV_LOG_PAGE 0x9 /* Invalid Log Page */ 923 #define NVME_CQE_SC_SPC_INV_FORMAT 0xa /* Invalid Format */ 924 #define NVME_CQE_SC_SPC_FW_RESET 0xb /* FW Application Reset Reqd */ 925 #define NVME_CQE_SC_SPC_INV_Q_DEL 0xc /* Invalid Queue Deletion */ 926 #define NVME_CQE_SC_SPC_FEAT_SAVE 0xd /* Feature Id Not Saveable */ 927 #define NVME_CQE_SC_SPC_FEAT_CHG 0xe /* Feature Not Changeable */ 928 #define NVME_CQE_SC_SPC_FEAT_NS_SPEC 0xf /* Feature Not Namespace Spec */ 929 #define NVME_CQE_SC_SPC_FW_NSSR 0x10 /* FW Application NSSR Reqd */ 930 #define NVME_CQE_SC_SPC_FW_NEXT_RESET 0x11 /* FW Application Next Reqd */ 931 #define NVME_CQE_SC_SPC_FW_MTFA 0x12 /* FW Application Exceed MTFA */ 932 #define NVME_CQE_SC_SPC_FW_PROHIBITED 0x13 /* FW Application Prohibited */ 933 #define NVME_CQE_SC_SPC_FW_OVERLAP 0x14 /* Overlapping FW ranges */ 934 935 /* NVMe completion status code (NVM command specific */ 936 #define NVME_CQE_SC_SPC_NVM_CNFL_ATTR 0x80 /* Conflicting Attributes */ 937 #define NVME_CQE_SC_SPC_NVM_INV_PROT 0x81 /* Invalid Protection */ 938 #define NVME_CQE_SC_SPC_NVM_READONLY 0x82 /* Write to Read Only Range */ 939 940 /* NVMe completion status code (data / metadata integrity) */ 941 #define NVME_CQE_SC_INT_NVM_WRITE 0x80 /* Write Fault */ 942 #define NVME_CQE_SC_INT_NVM_READ 0x81 /* Unrecovered Read Error */ 943 #define NVME_CQE_SC_INT_NVM_GUARD 0x82 /* Guard Check Error */ 944 #define NVME_CQE_SC_INT_NVM_APPL_TAG 0x83 /* Application Tag Check Err */ 945 #define NVME_CQE_SC_INT_NVM_REF_TAG 0x84 /* Reference Tag Check Err */ 946 #define NVME_CQE_SC_INT_NVM_COMPARE 0x85 /* Compare Failure */ 947 #define NVME_CQE_SC_INT_NVM_ACCESS 0x86 /* Access Denied */ 948 949 #ifdef __cplusplus 950 } 951 #endif 952 953 #endif /* _SYS_NVME_H */ 954