1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2016 Nexenta Systems, Inc. 14 * Copyright 2020 Joyent, Inc. 15 * Copyright 2019 Western Digital Corporation 16 * Copyright 2021 Oxide Computer Company 17 * Copyright 2022 OmniOS Community Edition (OmniOSce) Association. 18 */ 19 20 #ifndef _SYS_NVME_H 21 #define _SYS_NVME_H 22 23 #include <sys/types.h> 24 25 #ifdef _KERNEL 26 #include <sys/types32.h> 27 #else 28 #include <stdint.h> 29 #endif 30 31 /* 32 * Declarations used for communication between nvmeadm(1M) and nvme(7D) 33 */ 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 /* 40 * NVMe ioctl definitions 41 */ 42 43 #define NVME_IOC (('N' << 24) | ('V' << 16) | ('M' << 8)) 44 #define NVME_IOC_IDENTIFY_CTRL (NVME_IOC | 1) 45 #define NVME_IOC_IDENTIFY_NSID (NVME_IOC | 2) 46 #define NVME_IOC_CAPABILITIES (NVME_IOC | 3) 47 #define NVME_IOC_GET_LOGPAGE (NVME_IOC | 4) 48 #define NVME_IOC_GET_FEATURES (NVME_IOC | 5) 49 #define NVME_IOC_INTR_CNT (NVME_IOC | 6) 50 #define NVME_IOC_VERSION (NVME_IOC | 7) 51 #define NVME_IOC_FORMAT (NVME_IOC | 8) 52 #define NVME_IOC_DETACH (NVME_IOC | 9) 53 #define NVME_IOC_ATTACH (NVME_IOC | 10) 54 #define NVME_IOC_FIRMWARE_DOWNLOAD (NVME_IOC | 11) 55 #define NVME_IOC_FIRMWARE_COMMIT (NVME_IOC | 12) 56 #define NVME_IOC_PASSTHRU (NVME_IOC | 13) 57 #define NVME_IOC_MAX NVME_IOC_PASSTHRU 58 59 #define IS_NVME_IOC(x) ((x) > NVME_IOC && (x) <= NVME_IOC_MAX) 60 #define NVME_IOC_CMD(x) ((x) & 0xff) 61 62 typedef struct { 63 size_t n_len; 64 uintptr_t n_buf; 65 uint64_t n_arg; 66 } nvme_ioctl_t; 67 68 #ifdef _KERNEL 69 typedef struct { 70 size32_t n_len; 71 uintptr32_t n_buf; 72 uint64_t n_arg; 73 } nvme_ioctl32_t; 74 #endif 75 76 /* 77 * NVMe capabilities 78 */ 79 typedef struct { 80 uint32_t mpsmax; /* Memory Page Size Maximum */ 81 uint32_t mpsmin; /* Memory Page Size Minimum */ 82 } nvme_capabilities_t; 83 84 /* 85 * NVMe version 86 */ 87 typedef struct { 88 uint16_t v_minor; 89 uint16_t v_major; 90 } nvme_version_t; 91 92 #define NVME_VERSION_ATLEAST(v, maj, min) \ 93 (((v)->v_major) > (maj) || \ 94 ((v)->v_major == (maj) && (v)->v_minor >= (min))) 95 96 #define NVME_VERSION_HIGHER(v, maj, min) \ 97 (((v)->v_major) > (maj) || \ 98 ((v)->v_major == (maj) && (v)->v_minor > (min))) 99 100 101 #pragma pack(1) 102 103 typedef struct { 104 uint64_t lo; 105 uint64_t hi; 106 } nvme_uint128_t; 107 108 /* 109 * NVMe Identify data structures 110 */ 111 112 #define NVME_IDENTIFY_BUFSIZE 4096 /* buffer size for Identify */ 113 114 /* NVMe Queue Entry Size bitfield */ 115 typedef struct { 116 uint8_t qes_min:4; /* minimum entry size */ 117 uint8_t qes_max:4; /* maximum entry size */ 118 } nvme_idctl_qes_t; 119 120 /* NVMe Power State Descriptor */ 121 typedef struct { 122 uint16_t psd_mp; /* Maximum Power */ 123 uint8_t psd_rsvd1; 124 uint8_t psd_mps:1; /* Max Power Scale (1.1) */ 125 uint8_t psd_nops:1; /* Non-Operational State (1.1) */ 126 uint8_t psd_rsvd2:6; 127 uint32_t psd_enlat; /* Entry Latency */ 128 uint32_t psd_exlat; /* Exit Latency */ 129 uint8_t psd_rrt:5; /* Relative Read Throughput */ 130 uint8_t psd_rsvd3:3; 131 uint8_t psd_rrl:5; /* Relative Read Latency */ 132 uint8_t psd_rsvd4:3; 133 uint8_t psd_rwt:5; /* Relative Write Throughput */ 134 uint8_t psd_rsvd5:3; 135 uint8_t psd_rwl:5; /* Relative Write Latency */ 136 uint8_t psd_rsvd6:3; 137 uint16_t psd_idlp; /* Idle Power (1.2) */ 138 uint8_t psd_rsvd7:6; 139 uint8_t psd_ips:2; /* Idle Power Scale (1.2) */ 140 uint8_t psd_rsvd8; 141 uint16_t psd_actp; /* Active Power (1.2) */ 142 uint8_t psd_apw:3; /* Active Power Workload (1.2) */ 143 uint8_t psd_rsvd9:3; 144 uint8_t psd_aps:2; /* Active Power Scale */ 145 uint8_t psd_rsvd10[9]; 146 } nvme_idctl_psd_t; 147 148 #define NVME_SERIAL_SZ 20 149 #define NVME_MODEL_SZ 40 150 151 /* NVMe Identify Controller Data Structure */ 152 typedef struct { 153 /* Controller Capabilities & Features */ 154 uint16_t id_vid; /* PCI vendor ID */ 155 uint16_t id_ssvid; /* PCI subsystem vendor ID */ 156 char id_serial[NVME_SERIAL_SZ]; /* Serial Number */ 157 char id_model[NVME_MODEL_SZ]; /* Model Number */ 158 char id_fwrev[8]; /* Firmware Revision */ 159 uint8_t id_rab; /* Recommended Arbitration Burst */ 160 uint8_t id_oui[3]; /* vendor IEEE OUI */ 161 struct { /* Multi-Interface Capabilities */ 162 uint8_t m_multi_pci:1; /* HW has multiple PCIe interfaces */ 163 uint8_t m_multi_ctrl:1; /* HW has multiple controllers (1.1) */ 164 uint8_t m_sr_iov:1; /* Controller is SR-IOV virt fn (1.1) */ 165 uint8_t m_anar_sup:1; /* ANA Reporting Supported (1.4) */ 166 uint8_t m_rsvd:4; 167 } id_mic; 168 uint8_t id_mdts; /* Maximum Data Transfer Size */ 169 uint16_t id_cntlid; /* Unique Controller Identifier (1.1) */ 170 /* Added in NVMe 1.2 */ 171 uint32_t id_ver; /* Version (1.2) */ 172 uint32_t id_rtd3r; /* RTD3 Resume Latency (1.2) */ 173 uint32_t id_rtd3e; /* RTD3 Entry Latency (1.2) */ 174 struct { 175 uint32_t oaes_rsvd0:8; 176 uint32_t oaes_nsan:1; /* Namespace Attribute Notices (1.2) */ 177 uint32_t oaes_fwact:1; /* Firmware Activation Notices (1.2) */ 178 uint32_t oaes_rsvd1:1; 179 uint32_t oaes_ansacn:1; /* Asymmetric NS Access Change (1.4) */ 180 uint32_t oaes_plat:1; /* Predictable Lat Event Agg. (1.4) */ 181 uint32_t oaes_lbasi:1; /* LBA Status Information (1.4) */ 182 uint32_t oaes_egeal:1; /* Endurance Group Event Agg. (1.4) */ 183 uint32_t oaes_rsvd2:17; 184 } id_oaes; 185 struct { 186 uint32_t ctrat_hid:1; /* 128-bit Host Identifier (1.2) */ 187 uint32_t ctrat_nops:1; /* Non-Operational Power State (1.3) */ 188 uint32_t ctrat_nvmset:1; /* NVMe Sets (1.4) */ 189 uint32_t ctrat_rrl:1; /* Read Recovery Levels (1.4) */ 190 uint32_t ctrat_engrp:1; /* Endurance Groups (1.4) */ 191 uint32_t ctrat_plm:1; /* Predictable Latency Mode (1.4) */ 192 uint32_t ctrat_tbkas:1; /* Traffic Based Keep Alive (1.4) */ 193 uint32_t ctrat_nsg:1; /* Namespace Granularity (1.4) */ 194 uint32_t ctrat_sqass:1; /* SQ Associations (1.4) */ 195 uint32_t ctrat_uuid:1; /* UUID List (1.4) */ 196 uint32_t ctrat_rsvd:22; 197 } id_ctratt; 198 uint16_t id_rrls; /* Read Recovery Levels (1.4) */ 199 uint8_t id_rsvd_cc[111-102]; 200 uint8_t id_cntrltype; /* Controller Type (1.4) */ 201 uint8_t id_frguid[16]; /* FRU GUID (1.3) */ 202 uint16_t id_crdt1; /* Command Retry Delay Time 1 (1.4) */ 203 uint16_t id_crdt2; /* Command Retry Delay Time 2 (1.4) */ 204 uint16_t id_crdt3; /* Command Retry Delay Time 3 (1.4) */ 205 uint8_t id_rsvd2_cc[240 - 134]; 206 uint8_t id_rsvd_nvmemi[253 - 240]; 207 /* NVMe-MI region */ 208 struct { /* NVMe Subsystem Report */ 209 uint8_t nvmsr_nvmesd:1; /* NVMe Storage Device */ 210 uint8_t nvmsr_nvmee:1; /* NVMe Enclosure */ 211 uint8_t nvmsr_rsvd:6; 212 } id_nvmsr; 213 struct { /* VPD Write Cycle Information */ 214 uint8_t vwci_crem:7; /* Write Cycles Remaining */ 215 uint8_t vwci_valid:1; /* Write Cycles Remaining Valid */ 216 } id_vpdwc; 217 struct { /* Management Endpoint Capabilities */ 218 uint8_t mec_smbusme:1; /* SMBus Port Management Endpoint */ 219 uint8_t mec_pcieme:1; /* PCIe Port Management Endpoint */ 220 uint8_t mec_rsvd:6; 221 } id_mec; 222 223 /* Admin Command Set Attributes */ 224 struct { /* Optional Admin Command Support */ 225 uint16_t oa_security:1; /* Security Send & Receive */ 226 uint16_t oa_format:1; /* Format NVM */ 227 uint16_t oa_firmware:1; /* Firmware Activate & Download */ 228 uint16_t oa_nsmgmt:1; /* Namespace Management (1.2) */ 229 uint16_t oa_selftest:1; /* Self Test (1.3) */ 230 uint16_t oa_direct:1; /* Directives (1.3) */ 231 uint16_t oa_nvmemi:1; /* MI-Send/Recv (1.3) */ 232 uint16_t oa_virtmgmt:1; /* Virtualization Management (1.3) */ 233 uint16_t oa_doorbell:1; /* Doorbell Buffer Config (1.3) */ 234 uint16_t oa_lbastat:1; /* LBA Status (1.4) */ 235 uint16_t oa_rsvd:6; 236 } id_oacs; 237 uint8_t id_acl; /* Abort Command Limit */ 238 uint8_t id_aerl; /* Asynchronous Event Request Limit */ 239 struct { /* Firmware Updates */ 240 uint8_t fw_readonly:1; /* Slot 1 is Read-Only */ 241 uint8_t fw_nslot:3; /* number of firmware slots */ 242 uint8_t fw_norst:1; /* Activate w/o reset (1.2) */ 243 uint8_t fw_rsvd:3; 244 } id_frmw; 245 struct { /* Log Page Attributes */ 246 uint8_t lp_smart:1; /* SMART/Health information per NS */ 247 uint8_t lp_cmdeff:1; /* Command Effects (1.2) */ 248 uint8_t lp_extsup:1; /* Extended Get Log Page (1.2) */ 249 uint8_t lp_telemetry:1; /* Telemetry Log Pages (1.3) */ 250 uint8_t lp_persist:1; /* Persistent Log Page (1.4) */ 251 uint8_t lp_rsvd:3; 252 } id_lpa; 253 uint8_t id_elpe; /* Error Log Page Entries */ 254 uint8_t id_npss; /* Number of Power States */ 255 struct { /* Admin Vendor Specific Command Conf */ 256 uint8_t av_spec:1; /* use format from spec */ 257 uint8_t av_rsvd:7; 258 } id_avscc; 259 struct { /* Autonomous Power State Trans (1.1) */ 260 uint8_t ap_sup:1; /* APST supported (1.1) */ 261 uint8_t ap_rsvd:7; 262 } id_apsta; 263 uint16_t ap_wctemp; /* Warning Composite Temp. (1.2) */ 264 uint16_t ap_cctemp; /* Critical Composite Temp. (1.2) */ 265 uint16_t ap_mtfa; /* Maximum Firmware Activation (1.2) */ 266 uint32_t ap_hmpre; /* Host Memory Buf Pref Size (1.2) */ 267 uint32_t ap_hmmin; /* Host Memory Buf Min Size (1.2) */ 268 nvme_uint128_t ap_tnvmcap; /* Total NVM Capacity in Bytes (1.2) */ 269 nvme_uint128_t ap_unvmcap; /* Unallocated NVM Capacity (1.2) */ 270 struct { /* Replay Protected Mem. Block (1.2) */ 271 uint32_t rpmbs_units:3; /* Number of targets */ 272 uint32_t rpmbs_auth:3; /* Auth method */ 273 uint32_t rpmbs_rsvd:10; 274 uint32_t rpmbs_tot:8; /* Total size in 128KB */ 275 uint32_t rpmbs_acc:8; /* Access size in 512B */ 276 } ap_rpmbs; 277 /* Added in NVMe 1.3 */ 278 uint16_t ap_edstt; /* Ext. Device Self-test time (1.3) */ 279 struct { /* Device Self-test Options */ 280 uint8_t dsto_sub:1; /* Subsystem level self-test (1.3) */ 281 uint8_t dsto_rsvd:7; 282 } ap_dsto; 283 uint8_t ap_fwug; /* Firmware Update Granularity (1.3) */ 284 uint16_t ap_kas; /* Keep Alive Support (1.2) */ 285 struct { /* Host Thermal Management (1.3) */ 286 uint16_t hctma_hctm:1; /* Host Controlled (1.3) */ 287 uint16_t hctma_rsvd:15; 288 } ap_hctma; 289 uint16_t ap_mntmt; /* Minimum Thermal Temperature (1.3) */ 290 uint16_t ap_mxtmt; /* Maximum Thermal Temperature (1.3) */ 291 struct { /* Sanitize Caps */ 292 uint32_t san_ces:1; /* Crypto Erase Support (1.3) */ 293 uint32_t san_bes:1; /* Block Erase Support (1.3) */ 294 uint32_t san_ows:1; /* Overwite Support (1.3) */ 295 uint32_t san_rsvd:26; 296 uint32_t san_ndi:1; /* No-deallocate Inhibited (1.4) */ 297 uint32_t san_nodmmas:2; /* No-Deallocate Modifies Media (1.4) */ 298 } ap_sanitize; 299 uint32_t ap_hmminds; /* Host Mem Buf Min Desc Entry (1.4) */ 300 uint16_t ap_hmmaxd; /* How Mem Max Desc Entries (1.4) */ 301 uint16_t ap_nsetidmax; /* Max NVMe set identifier (1.4) */ 302 uint16_t ap_engidmax; /* Max Endurance Group ID (1.4) */ 303 uint8_t ap_anatt; /* ANA Transition Time (1.4) */ 304 struct { /* Asymmetric Namespace Access Caps */ 305 uint8_t anacap_opt:1; /* Optimized State (1.4) */ 306 uint8_t anacap_unopt:1; /* Un-optimized State (1.4) */ 307 uint8_t anacap_inacc:1; /* Inaccessible State (1.4) */ 308 uint8_t anacap_ploss:1; /* Persistent Loss (1.4) */ 309 uint8_t anacap_chg:1; /* Change State (1.4 ) */ 310 uint8_t anacap_rsvd:1; 311 uint8_t anacap_grpns:1; /* ID Changes with NS Attach (1.4) */ 312 uint8_t anacap_grpid:1; /* Supports Group ID (1.4) */ 313 } ap_anacap; 314 uint32_t ap_anagrpmax; /* ANA Group ID Max (1.4) */ 315 uint32_t ap_nanagrpid; /* Number of ANA Group IDs (1.4) */ 316 uint32_t ap_pels; /* Persistent Event Log Size (1.4) */ 317 uint8_t id_rsvd_ac[512 - 356]; 318 319 /* NVM Command Set Attributes */ 320 nvme_idctl_qes_t id_sqes; /* Submission Queue Entry Size */ 321 nvme_idctl_qes_t id_cqes; /* Completion Queue Entry Size */ 322 uint16_t id_maxcmd; /* Max Outstanding Commands (1.3) */ 323 uint32_t id_nn; /* Number of Namespaces */ 324 struct { /* Optional NVM Command Support */ 325 uint16_t on_compare:1; /* Compare */ 326 uint16_t on_wr_unc:1; /* Write Uncorrectable */ 327 uint16_t on_dset_mgmt:1; /* Dataset Management */ 328 uint16_t on_wr_zero:1; /* Write Zeros (1.1) */ 329 uint16_t on_save:1; /* Save/Select in Get/Set Feat (1.1) */ 330 uint16_t on_reserve:1; /* Reservations (1.1) */ 331 uint16_t on_ts:1; /* Timestamp (1.3) */ 332 uint16_t on_verify:1; /* Verify (1.4) */ 333 uint16_t on_rsvd:8; 334 } id_oncs; 335 struct { /* Fused Operation Support */ 336 uint16_t f_cmp_wr:1; /* Compare and Write */ 337 uint16_t f_rsvd:15; 338 } id_fuses; 339 struct { /* Format NVM Attributes */ 340 uint8_t fn_format:1; /* Format applies to all NS */ 341 uint8_t fn_sec_erase:1; /* Secure Erase applies to all NS */ 342 uint8_t fn_crypt_erase:1; /* Cryptographic Erase supported */ 343 uint8_t fn_rsvd:5; 344 } id_fna; 345 struct { /* Volatile Write Cache */ 346 uint8_t vwc_present:1; /* Volatile Write Cache present */ 347 uint8_t vwc_nsflush:2; /* Flush with NS ffffffff (1.4) */ 348 uint8_t rsvd:5; 349 } id_vwc; 350 uint16_t id_awun; /* Atomic Write Unit Normal */ 351 uint16_t id_awupf; /* Atomic Write Unit Power Fail */ 352 struct { /* NVM Vendor Specific Command Conf */ 353 uint8_t nv_spec:1; /* use format from spec */ 354 uint8_t nv_rsvd:7; 355 } id_nvscc; 356 struct { /* Namespace Write Protection Caps */ 357 uint8_t nwpc_base:1; /* Base support (1.4) */ 358 uint8_t nwpc_wpupc:1; /* Write prot until power cycle (1.4) */ 359 uint8_t nwpc_permwp:1; /* Permanent write prot (1.4) */ 360 uint8_t nwpc_rsvd:5; 361 } id_nwpc; 362 uint16_t id_acwu; /* Atomic Compare & Write Unit (1.1) */ 363 uint16_t id_rsvd_nc_3; 364 struct { /* SGL Support (1.1) */ 365 uint16_t sgl_sup:2; /* SGL Supported in NVM cmds (1.3) */ 366 uint16_t sgl_keyed:1; /* Keyed SGL Support (1.2) */ 367 uint16_t sgl_rsvd1:13; 368 uint16_t sgl_bucket:1; /* SGL Bit Bucket supported (1.1) */ 369 uint16_t sgl_balign:1; /* SGL Byte Aligned (1.2) */ 370 uint16_t sgl_sglgtd:1; /* SGL Length Longer than Data (1.2) */ 371 uint16_t sgl_mptr:1; /* SGL MPTR w/ SGL (1.2) */ 372 uint16_t sgl_offset:1; /* SGL Address is offset (1.2) */ 373 uint16_t sgl_tport:1; /* Transport SGL Data Block (1.4) */ 374 uint16_t sgl_rsvd2:10; 375 } id_sgls; 376 uint32_t id_mnam; /* Maximum Number of Allowed NSes */ 377 uint8_t id_rsvd_nc_4[768 - 544]; 378 379 /* I/O Command Set Attributes */ 380 uint8_t id_subnqn[1024 - 768]; /* Subsystem Qualified Name (1.2.1+) */ 381 uint8_t id_rsvd_ioc[1792 - 1024]; 382 uint8_t id_nvmof[2048 - 1792]; /* NVMe over Fabrics */ 383 384 /* Power State Descriptors */ 385 nvme_idctl_psd_t id_psd[32]; 386 387 /* Vendor Specific */ 388 uint8_t id_vs[1024]; 389 } nvme_identify_ctrl_t; 390 391 /* 392 * NVMe Controller Types 393 */ 394 #define NVME_CNTRLTYPE_RSVD 0 395 #define NVME_CNTRLTYPE_IO 1 396 #define NVME_CNTRLTYPE_DISC 2 397 #define NVME_CNTRLTYPE_ADMIN 3 398 399 /* 400 * RPMBS Authentication Types 401 */ 402 #define NVME_RPMBS_AUTH_HMAC_SHA256 0 403 404 /* 405 * NODMMAS Values 406 */ 407 #define NVME_NODMMAS_UNDEF 0x00 408 #define NVME_NODMMAS_NOMOD 0x01 409 #define NVME_NODMMAS_DOMOD 0x02 410 411 /* 412 * VWC NSID flushes 413 */ 414 #define NVME_VWCNS_UNKNOWN 0x00 415 #define NVME_VWCNS_UNSUP 0x02 416 #define NVME_VWCNS_SUP 0x03 417 418 /* 419 * SGL Support Values 420 */ 421 #define NVME_SGL_UNSUP 0x00 422 #define NVME_SGL_SUP_UNALIGN 0x01 423 #define NVME_SGL_SUP_ALIGN 0x02 424 425 /* NVMe Identify Namespace LBA Format */ 426 typedef struct { 427 uint16_t lbaf_ms; /* Metadata Size */ 428 uint8_t lbaf_lbads; /* LBA Data Size */ 429 uint8_t lbaf_rp:2; /* Relative Performance */ 430 uint8_t lbaf_rsvd1:6; 431 } nvme_idns_lbaf_t; 432 433 /* NVMe Identify Namespace Data Structure */ 434 typedef struct { 435 uint64_t id_nsize; /* Namespace Size */ 436 uint64_t id_ncap; /* Namespace Capacity */ 437 uint64_t id_nuse; /* Namespace Utilization */ 438 struct { /* Namespace Features */ 439 uint8_t f_thin:1; /* Thin Provisioning */ 440 uint8_t f_nsabp:1; /* Namespace atomics (1.2) */ 441 uint8_t f_dae:1; /* Deallocated errors supported (1.2) */ 442 uint8_t f_uidreuse:1; /* GUID reuse impossible (1.3) */ 443 uint8_t f_optperf:1; /* Namespace I/O opt (1.4) */ 444 uint8_t f_rsvd:3; 445 } id_nsfeat; 446 uint8_t id_nlbaf; /* Number of LBA formats */ 447 struct { /* Formatted LBA size */ 448 uint8_t lba_format:4; /* LBA format */ 449 uint8_t lba_extlba:1; /* extended LBA (includes metadata) */ 450 uint8_t lba_rsvd:3; 451 } id_flbas; 452 struct { /* Metadata Capabilities */ 453 uint8_t mc_extlba:1; /* extended LBA transfers */ 454 uint8_t mc_separate:1; /* separate metadata transfers */ 455 uint8_t mc_rsvd:6; 456 } id_mc; 457 struct { /* Data Protection Capabilities */ 458 uint8_t dp_type1:1; /* Protection Information Type 1 */ 459 uint8_t dp_type2:1; /* Protection Information Type 2 */ 460 uint8_t dp_type3:1; /* Protection Information Type 3 */ 461 uint8_t dp_first:1; /* first 8 bytes of metadata */ 462 uint8_t dp_last:1; /* last 8 bytes of metadata */ 463 uint8_t dp_rsvd:3; 464 } id_dpc; 465 struct { /* Data Protection Settings */ 466 uint8_t dp_pinfo:3; /* Protection Information enabled */ 467 uint8_t dp_first:1; /* first 8 bytes of metadata */ 468 uint8_t dp_rsvd:4; 469 } id_dps; 470 struct { /* NS Multi-Path/Sharing Cap (1.1) */ 471 uint8_t nm_shared:1; /* NS is shared (1.1) */ 472 uint8_t nm_rsvd:7; 473 } id_nmic; 474 struct { /* Reservation Capabilities (1.1) */ 475 uint8_t rc_persist:1; /* Persist Through Power Loss (1.1) */ 476 uint8_t rc_wr_excl:1; /* Write Exclusive (1.1) */ 477 uint8_t rc_excl:1; /* Exclusive Access (1.1) */ 478 uint8_t rc_wr_excl_r:1; /* Wr Excl - Registrants Only (1.1) */ 479 uint8_t rc_excl_r:1; /* Excl Acc - Registrants Only (1.1) */ 480 uint8_t rc_wr_excl_a:1; /* Wr Excl - All Registrants (1.1) */ 481 uint8_t rc_excl_a:1; /* Excl Acc - All Registrants (1.1) */ 482 uint8_t rc_ign_ekey:1; /* Ignore Existing Key (1.3) */ 483 } id_rescap; 484 struct { /* Format Progress Indicator (1.2) */ 485 uint8_t fpi_remp:7; /* Percent NVM Format Remaining (1.2) */ 486 uint8_t fpi_sup:1; /* Supported (1.2) */ 487 } id_fpi; 488 uint8_t id_dfleat; /* Deallocate Log. Block (1.3) */ 489 uint16_t id_nawun; /* Atomic Write Unit Normal (1.2) */ 490 uint16_t id_nawupf; /* Atomic Write Unit Power Fail (1.2) */ 491 uint16_t id_nacwu; /* Atomic Compare & Write Unit (1.2) */ 492 uint16_t id_nabsn; /* Atomic Boundary Size Normal (1.2) */ 493 uint16_t id_nbao; /* Atomic Boundary Offset (1.2) */ 494 uint16_t id_nabspf; /* Atomic Boundary Size Fail (1.2) */ 495 uint16_t id_noiob; /* Optimal I/O Bondary (1.3) */ 496 nvme_uint128_t id_nvmcap; /* NVM Capacity */ 497 uint16_t id_npwg; /* NS Pref. Write Gran. (1.4) */ 498 uint16_t id_npwa; /* NS Pref. Write Align. (1.4) */ 499 uint16_t id_npdg; /* NS Pref. Deallocate Gran. (1.4) */ 500 uint16_t id_npda; /* NS Pref. Deallocate Align. (1.4) */ 501 uint16_t id_nows; /* NS. Optimal Write Size (1.4) */ 502 uint8_t id_rsvd1[92 - 74]; 503 uint32_t id_anagrpid; /* ANA Group Identifier (1.4) */ 504 uint8_t id_rsvd2[99 - 96]; 505 struct { 506 uint8_t nsa_wprot:1; /* Write Protected (1.4) */ 507 uint8_t nsa_rsvd:7; 508 } id_nsattr; 509 uint16_t id_nvmsetid; /* NVM Set Identifier (1.4) */ 510 uint16_t id_endgid; /* Endurance Group Identifier (1.4) */ 511 uint8_t id_nguid[16]; /* Namespace GUID (1.2) */ 512 uint8_t id_eui64[8]; /* IEEE Extended Unique Id (1.1) */ 513 nvme_idns_lbaf_t id_lbaf[16]; /* LBA Formats */ 514 515 uint8_t id_rsvd3[384 - 192]; 516 517 uint8_t id_vs[4096 - 384]; /* Vendor Specific */ 518 } nvme_identify_nsid_t; 519 520 /* NVMe Identify Primary Controller Capabilities */ 521 typedef struct { 522 uint16_t nipc_cntlid; /* Controller ID */ 523 uint16_t nipc_portid; /* Port Identifier */ 524 uint8_t nipc_crt; /* Controller Resource Types */ 525 uint8_t nipc_rsvd0[32 - 5]; 526 uint32_t nipc_vqfrt; /* VQ Resources Flexible Total */ 527 uint32_t nipc_vqrfa; /* VQ Resources Flexible Assigned */ 528 uint16_t nipc_vqrfap; /* VQ Resources to Primary */ 529 uint16_t nipc_vqprt; /* VQ Resources Private Total */ 530 uint16_t nipc_vqfrsm; /* VQ Resources Secondary Max */ 531 uint16_t nipc_vqgran; /* VQ Flexible Resource Gran */ 532 uint8_t nipc_rvsd1[64 - 48]; 533 uint32_t nipc_vifrt; /* VI Flexible total */ 534 uint32_t nipc_virfa; /* VI Flexible Assigned */ 535 uint16_t nipc_virfap; /* VI Flexible Allocated to Primary */ 536 uint16_t nipc_viprt; /* VI Resources Private Total */ 537 uint16_t nipc_vifrsm; /* VI Resources Secondary Max */ 538 uint16_t nipc_vigran; /* VI Flexible Granularity */ 539 uint8_t nipc_rsvd2[4096 - 80]; 540 } nvme_identify_primary_caps_t; 541 542 /* 543 * NVMe completion queue entry status field 544 */ 545 typedef struct { 546 uint16_t sf_p:1; /* Phase Tag */ 547 uint16_t sf_sc:8; /* Status Code */ 548 uint16_t sf_sct:3; /* Status Code Type */ 549 uint16_t sf_rsvd2:2; 550 uint16_t sf_m:1; /* More */ 551 uint16_t sf_dnr:1; /* Do Not Retry */ 552 } nvme_cqe_sf_t; 553 554 555 /* 556 * NVMe Get Log Page 557 */ 558 #define NVME_LOGPAGE_ERROR 0x1 /* Error Information */ 559 #define NVME_LOGPAGE_HEALTH 0x2 /* SMART/Health Information */ 560 #define NVME_LOGPAGE_FWSLOT 0x3 /* Firmware Slot Information */ 561 #define NVME_LOGPAGE_NSCHANGE 0x4 /* Changed namespace (1.2) */ 562 563 typedef struct { 564 uint64_t el_count; /* Error Count */ 565 uint16_t el_sqid; /* Submission Queue ID */ 566 uint16_t el_cid; /* Command ID */ 567 nvme_cqe_sf_t el_sf; /* Status Field */ 568 uint8_t el_byte; /* Parameter Error Location byte */ 569 uint8_t el_bit:3; /* Parameter Error Location bit */ 570 uint8_t el_rsvd1:5; 571 uint64_t el_lba; /* Logical Block Address */ 572 uint32_t el_nsid; /* Namespace ID */ 573 uint8_t el_vendor; /* Vendor Specific Information avail */ 574 uint8_t el_rsvd2[64 - 29]; 575 } nvme_error_log_entry_t; 576 577 typedef struct { 578 struct { /* Critical Warning */ 579 uint8_t cw_avail:1; /* available space too low */ 580 uint8_t cw_temp:1; /* temperature too high */ 581 uint8_t cw_reliab:1; /* degraded reliability */ 582 uint8_t cw_readonly:1; /* media is read-only */ 583 uint8_t cw_volatile:1; /* volatile memory backup failed */ 584 uint8_t cw_rsvd:3; 585 } hl_crit_warn; 586 uint16_t hl_temp; /* Temperature */ 587 uint8_t hl_avail_spare; /* Available Spare */ 588 uint8_t hl_avail_spare_thr; /* Available Spare Threshold */ 589 uint8_t hl_used; /* Percentage Used */ 590 uint8_t hl_rsvd1[32 - 6]; 591 nvme_uint128_t hl_data_read; /* Data Units Read */ 592 nvme_uint128_t hl_data_write; /* Data Units Written */ 593 nvme_uint128_t hl_host_read; /* Host Read Commands */ 594 nvme_uint128_t hl_host_write; /* Host Write Commands */ 595 nvme_uint128_t hl_ctrl_busy; /* Controller Busy Time */ 596 nvme_uint128_t hl_power_cycles; /* Power Cycles */ 597 nvme_uint128_t hl_power_on_hours; /* Power On Hours */ 598 nvme_uint128_t hl_unsafe_shutdn; /* Unsafe Shutdowns */ 599 nvme_uint128_t hl_media_errors; /* Media Errors */ 600 nvme_uint128_t hl_errors_logged; /* Number of errors logged */ 601 /* Added in NVMe 1.2 */ 602 uint32_t hl_warn_temp_time; /* Warning Composite Temp Time */ 603 uint32_t hl_crit_temp_time; /* Critical Composite Temp Time */ 604 uint16_t hl_temp_sensor_1; /* Temperature Sensor 1 */ 605 uint16_t hl_temp_sensor_2; /* Temperature Sensor 2 */ 606 uint16_t hl_temp_sensor_3; /* Temperature Sensor 3 */ 607 uint16_t hl_temp_sensor_4; /* Temperature Sensor 4 */ 608 uint16_t hl_temp_sensor_5; /* Temperature Sensor 5 */ 609 uint16_t hl_temp_sensor_6; /* Temperature Sensor 6 */ 610 uint16_t hl_temp_sensor_7; /* Temperature Sensor 7 */ 611 uint16_t hl_temp_sensor_8; /* Temperature Sensor 8 */ 612 /* Added in NVMe 1.3 */ 613 uint32_t hl_tmtemp_1_tc; /* Thermal Mgmt Temp 1 Transition # */ 614 uint32_t hl_tmtemp_2_tc; /* Thermal Mgmt Temp 1 Transition # */ 615 uint32_t hl_tmtemp_1_time; /* Time in Thermal Mgmt Temp 1 */ 616 uint32_t hl_tmtemp_2_time; /* Time in Thermal Mgmt Temp 2 */ 617 uint8_t hl_rsvd2[512 - 232]; 618 } nvme_health_log_t; 619 620 /* 621 * The NVMe spec allows for up to seven firmware slots. 622 */ 623 #define NVME_MAX_FWSLOTS 7 624 #define NVME_FWVER_SZ 8 625 626 typedef struct { 627 /* Active Firmware Slot */ 628 uint8_t fw_afi:3; 629 uint8_t fw_rsvd1:1; 630 /* Next Active Firmware Slot */ 631 uint8_t fw_next:3; 632 uint8_t fw_rsvd2:1; 633 uint8_t fw_rsvd3[7]; 634 /* Firmware Revision / Slot */ 635 char fw_frs[NVME_MAX_FWSLOTS][NVME_FWVER_SZ]; 636 uint8_t fw_rsvd4[512 - 64]; 637 } nvme_fwslot_log_t; 638 639 /* 640 * The NVMe spec specifies that the changed namespace list contains up to 641 * 1024 entries. 642 */ 643 #define NVME_NSCHANGE_LIST_SIZE 1024 644 645 typedef struct { 646 uint32_t nscl_ns[NVME_NSCHANGE_LIST_SIZE]; 647 } __packed nvme_nschange_list_t; 648 649 /* CSTYLED */ 650 _Static_assert(sizeof (nvme_nschange_list_t) == 4096, "bad size for nvme_nschange_list_t"); 651 652 /* 653 * NVMe Format NVM 654 */ 655 #define NVME_FRMT_SES_NONE 0 656 #define NVME_FRMT_SES_USER 1 657 #define NVME_FRMT_SES_CRYPTO 2 658 #define NVME_FRMT_MAX_SES 2 659 660 #define NVME_FRMT_MAX_LBAF 15 661 662 typedef union { 663 struct { 664 uint32_t fm_lbaf:4; /* LBA Format */ 665 uint32_t fm_ms:1; /* Metadata Settings */ 666 uint32_t fm_pi:3; /* Protection Information */ 667 uint32_t fm_pil:1; /* Prot. Information Location */ 668 uint32_t fm_ses:3; /* Secure Erase Settings */ 669 uint32_t fm_resvd:20; 670 } b; 671 uint32_t r; 672 } nvme_format_nvm_t; 673 674 675 /* 676 * NVMe Get / Set Features 677 */ 678 #define NVME_FEAT_ARBITRATION 0x1 /* Command Arbitration */ 679 #define NVME_FEAT_POWER_MGMT 0x2 /* Power Management */ 680 #define NVME_FEAT_LBA_RANGE 0x3 /* LBA Range Type */ 681 #define NVME_FEAT_TEMPERATURE 0x4 /* Temperature Threshold */ 682 #define NVME_FEAT_ERROR 0x5 /* Error Recovery */ 683 #define NVME_FEAT_WRITE_CACHE 0x6 /* Volatile Write Cache */ 684 #define NVME_FEAT_NQUEUES 0x7 /* Number of Queues */ 685 #define NVME_FEAT_INTR_COAL 0x8 /* Interrupt Coalescing */ 686 #define NVME_FEAT_INTR_VECT 0x9 /* Interrupt Vector Configuration */ 687 #define NVME_FEAT_WRITE_ATOM 0xa /* Write Atomicity */ 688 #define NVME_FEAT_ASYNC_EVENT 0xb /* Asynchronous Event Configuration */ 689 #define NVME_FEAT_AUTO_PST 0xc /* Autonomous Power State Transition */ 690 /* (1.1) */ 691 692 #define NVME_FEAT_PROGRESS 0x80 /* Software Progress Marker */ 693 694 /* Arbitration Feature */ 695 typedef union { 696 struct { 697 uint8_t arb_ab:3; /* Arbitration Burst */ 698 uint8_t arb_rsvd:5; 699 uint8_t arb_lpw; /* Low Priority Weight */ 700 uint8_t arb_mpw; /* Medium Priority Weight */ 701 uint8_t arb_hpw; /* High Priority Weight */ 702 } b; 703 uint32_t r; 704 } nvme_arbitration_t; 705 706 /* Power Management Feature */ 707 typedef union { 708 struct { 709 uint32_t pm_ps:5; /* Power State */ 710 uint32_t pm_rsvd:27; 711 } b; 712 uint32_t r; 713 } nvme_power_mgmt_t; 714 715 /* LBA Range Type Feature */ 716 typedef union { 717 struct { 718 uint32_t lr_num:6; /* Number of LBA ranges */ 719 uint32_t lr_rsvd:26; 720 } b; 721 uint32_t r; 722 } nvme_lba_range_type_t; 723 724 typedef struct { 725 uint8_t lr_type; /* Type */ 726 struct { /* Attributes */ 727 uint8_t lr_write:1; /* may be overwritten */ 728 uint8_t lr_hidden:1; /* hidden from OS/EFI/BIOS */ 729 uint8_t lr_rsvd1:6; 730 } lr_attr; 731 uint8_t lr_rsvd2[14]; 732 uint64_t lr_slba; /* Starting LBA */ 733 uint64_t lr_nlb; /* Number of Logical Blocks */ 734 uint8_t lr_guid[16]; /* Unique Identifier */ 735 uint8_t lr_rsvd3[16]; 736 } nvme_lba_range_t; 737 738 #define NVME_LBA_RANGE_BUFSIZE 4096 739 740 /* Temperature Threshold Feature */ 741 typedef union { 742 struct { 743 uint16_t tt_tmpth; /* Temperature Threshold */ 744 uint16_t tt_tmpsel:4; /* Temperature Select */ 745 uint16_t tt_thsel:2; /* Temperature Type */ 746 uint16_t tt_resv:10; 747 } b; 748 uint32_t r; 749 } nvme_temp_threshold_t; 750 751 #define NVME_TEMP_THRESH_MAX_SENSOR 8 752 #define NVME_TEMP_THRESH_ALL 0xf 753 #define NVME_TEMP_THRESH_OVER 0x00 754 #define NVME_TEMP_THRESH_UNDER 0x01 755 756 /* Error Recovery Feature */ 757 typedef union { 758 struct { 759 uint16_t er_tler; /* Time-Limited Error Recovery */ 760 uint16_t er_rsvd; 761 } b; 762 uint32_t r; 763 } nvme_error_recovery_t; 764 765 /* Volatile Write Cache Feature */ 766 typedef union { 767 struct { 768 uint32_t wc_wce:1; /* Volatile Write Cache Enable */ 769 uint32_t wc_rsvd:31; 770 } b; 771 uint32_t r; 772 } nvme_write_cache_t; 773 774 /* Number of Queues Feature */ 775 typedef union { 776 struct { 777 uint16_t nq_nsq; /* Number of Submission Queues */ 778 uint16_t nq_ncq; /* Number of Completion Queues */ 779 } b; 780 uint32_t r; 781 } nvme_nqueues_t; 782 783 /* Interrupt Coalescing Feature */ 784 typedef union { 785 struct { 786 uint8_t ic_thr; /* Aggregation Threshold */ 787 uint8_t ic_time; /* Aggregation Time */ 788 uint16_t ic_rsvd; 789 } b; 790 uint32_t r; 791 } nvme_intr_coal_t; 792 793 /* Interrupt Configuration Features */ 794 typedef union { 795 struct { 796 uint16_t iv_iv; /* Interrupt Vector */ 797 uint16_t iv_cd:1; /* Coalescing Disable */ 798 uint16_t iv_rsvd:15; 799 } b; 800 uint32_t r; 801 } nvme_intr_vect_t; 802 803 /* Write Atomicity Feature */ 804 typedef union { 805 struct { 806 uint32_t wa_dn:1; /* Disable Normal */ 807 uint32_t wa_rsvd:31; 808 } b; 809 uint32_t r; 810 } nvme_write_atomicity_t; 811 812 /* Asynchronous Event Configuration Feature */ 813 typedef union { 814 struct { 815 uint8_t aec_avail:1; /* Available space too low */ 816 uint8_t aec_temp:1; /* Temperature too high */ 817 uint8_t aec_reliab:1; /* Degraded reliability */ 818 uint8_t aec_readonly:1; /* Media is read-only */ 819 uint8_t aec_volatile:1; /* Volatile memory backup failed */ 820 uint8_t aec_rsvd1:3; 821 uint8_t aec_nsan:1; /* Namespace attribute notices (1.2) */ 822 uint8_t aec_fwact:1; /* Firmware activation notices (1.2) */ 823 uint8_t aec_telln:1; /* Telemetry log notices (1.3) */ 824 uint8_t aec_ansacn:1; /* Asymm. NS access change (1.4) */ 825 uint8_t aec_plat:1; /* Predictable latency ev. agg. (1.4) */ 826 uint8_t aec_lbasi:1; /* LBA status information (1.4) */ 827 uint8_t aec_egeal:1; /* Endurance group ev. agg. (1.4) */ 828 uint8_t aec_rsvd2:1; 829 uint8_t aec_rsvd3[2]; 830 } b; 831 uint32_t r; 832 } nvme_async_event_conf_t; 833 834 /* Autonomous Power State Transition Feature (1.1) */ 835 typedef union { 836 struct { 837 uint8_t apst_apste:1; /* APST enabled */ 838 uint8_t apst_rsvd:7; 839 } b; 840 uint8_t r; 841 } nvme_auto_power_state_trans_t; 842 843 typedef struct { 844 uint32_t apst_rsvd1:3; 845 uint32_t apst_itps:5; /* Idle Transition Power State */ 846 uint32_t apst_itpt:24; /* Idle Time Prior to Transition */ 847 uint32_t apst_rsvd2; 848 } nvme_auto_power_state_t; 849 850 #define NVME_AUTO_PST_BUFSIZE 256 851 852 /* Software Progress Marker Feature */ 853 typedef union { 854 struct { 855 uint8_t spm_pbslc; /* Pre-Boot Software Load Count */ 856 uint8_t spm_rsvd[3]; 857 } b; 858 uint32_t r; 859 } nvme_software_progress_marker_t; 860 861 /* 862 * Firmware Commit - Command Dword 10 863 */ 864 #define NVME_FWC_SAVE 0x0 /* Save image only */ 865 #define NVME_FWC_SAVE_ACTIVATE 0x1 /* Save and activate at next reset */ 866 #define NVME_FWC_ACTIVATE 0x2 /* Activate slot at next reset */ 867 #define NVME_FWC_ACTIVATE_IMMED 0x3 /* Activate slot immediately */ 868 869 /* 870 * Firmware slot number is only 3 bits, and zero is not allowed. 871 * Valid range is 1 to 7. 872 */ 873 #define NVME_FW_SLOT_MIN 1 /* lowest allowable slot number ... */ 874 #define NVME_FW_SLOT_MAX 7 /* ... and highest */ 875 876 /* 877 * Some constants to make verification of DWORD variables and arguments easier. 878 * A DWORD is 4 bytes. 879 */ 880 #define NVME_DWORD_SHIFT 2 881 #define NVME_DWORD_SIZE (1 << NVME_DWORD_SHIFT) 882 #define NVME_DWORD_MASK (NVME_DWORD_SIZE - 1) 883 884 /* 885 * Maximum offset a firmware image can be load at is the number of 886 * DWORDS in a 32 bit field. Expressed in bytes its is: 887 */ 888 #define NVME_FW_OFFSETB_MAX ((u_longlong_t)UINT32_MAX << NVME_DWORD_SHIFT) 889 890 typedef union { 891 struct { 892 uint32_t fc_slot:3; /* Firmware slot */ 893 uint32_t fc_action:3; /* Commit action */ 894 uint32_t fc_rsvd:26; 895 } b; 896 uint32_t r; 897 } nvme_firmware_commit_dw10_t; 898 899 #pragma pack() /* pack(1) */ 900 901 /* NVMe completion status code type */ 902 #define NVME_CQE_SCT_GENERIC 0 /* Generic Command Status */ 903 #define NVME_CQE_SCT_SPECIFIC 1 /* Command Specific Status */ 904 #define NVME_CQE_SCT_INTEGRITY 2 /* Media and Data Integrity Errors */ 905 #define NVME_CQE_SCT_VENDOR 7 /* Vendor Specific */ 906 907 /* NVMe completion status code (generic) */ 908 #define NVME_CQE_SC_GEN_SUCCESS 0x0 /* Successful Completion */ 909 #define NVME_CQE_SC_GEN_INV_OPC 0x1 /* Invalid Command Opcode */ 910 #define NVME_CQE_SC_GEN_INV_FLD 0x2 /* Invalid Field in Command */ 911 #define NVME_CQE_SC_GEN_ID_CNFL 0x3 /* Command ID Conflict */ 912 #define NVME_CQE_SC_GEN_DATA_XFR_ERR 0x4 /* Data Transfer Error */ 913 #define NVME_CQE_SC_GEN_ABORT_PWRLOSS 0x5 /* Cmds Aborted / Pwr Loss */ 914 #define NVME_CQE_SC_GEN_INTERNAL_ERR 0x6 /* Internal Error */ 915 #define NVME_CQE_SC_GEN_ABORT_REQUEST 0x7 /* Command Abort Requested */ 916 #define NVME_CQE_SC_GEN_ABORT_SQ_DEL 0x8 /* Cmd Aborted / SQ deletion */ 917 #define NVME_CQE_SC_GEN_ABORT_FUSE_FAIL 0x9 /* Cmd Aborted / Failed Fused */ 918 #define NVME_CQE_SC_GEN_ABORT_FUSE_MISS 0xa /* Cmd Aborted / Missing Fusd */ 919 #define NVME_CQE_SC_GEN_INV_NS 0xb /* Inval Namespace or Format */ 920 #define NVME_CQE_SC_GEN_CMD_SEQ_ERR 0xc /* Command Sequence Error */ 921 #define NVME_CQE_SC_GEN_INV_SGL_LAST 0xd /* Inval SGL Last Seg Desc */ 922 #define NVME_CQE_SC_GEN_INV_SGL_NUM 0xe /* Inval Number of SGL Desc */ 923 #define NVME_CQE_SC_GEN_INV_DSGL_LEN 0xf /* Data SGL Length Invalid */ 924 #define NVME_CQE_SC_GEN_INV_MSGL_LEN 0x10 /* Metadata SGL Length Inval */ 925 #define NVME_CQE_SC_GEN_INV_SGL_DESC 0x11 /* SGL Descriptor Type Inval */ 926 #define NVME_CQE_SC_GEN_INV_USE_CMB 0x12 /* Inval use of Ctrl Mem Buf */ 927 #define NVME_CQE_SC_GEN_INV_PRP_OFF 0x13 /* PRP Offset Invalid */ 928 #define NVME_CQE_SC_GEN_AWU_EXCEEDED 0x14 /* Atomic Write Unit Exceeded */ 929 930 /* NVMe completion status code (generic NVM commands) */ 931 #define NVME_CQE_SC_GEN_NVM_LBA_RANGE 0x80 /* LBA Out Of Range */ 932 #define NVME_CQE_SC_GEN_NVM_CAP_EXC 0x81 /* Capacity Exceeded */ 933 #define NVME_CQE_SC_GEN_NVM_NS_NOTRDY 0x82 /* Namespace Not Ready */ 934 #define NVME_CQE_SC_GEN_NVM_RSV_CNFLCT 0x83 /* Reservation Conflict */ 935 936 /* NVMe completion status code (command specific) */ 937 #define NVME_CQE_SC_SPC_INV_CQ 0x0 /* Completion Queue Invalid */ 938 #define NVME_CQE_SC_SPC_INV_QID 0x1 /* Invalid Queue Identifier */ 939 #define NVME_CQE_SC_SPC_MAX_QSZ_EXC 0x2 /* Max Queue Size Exceeded */ 940 #define NVME_CQE_SC_SPC_ABRT_CMD_EXC 0x3 /* Abort Cmd Limit Exceeded */ 941 #define NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC 0x5 /* Async Event Request Limit */ 942 #define NVME_CQE_SC_SPC_INV_FW_SLOT 0x6 /* Invalid Firmware Slot */ 943 #define NVME_CQE_SC_SPC_INV_FW_IMG 0x7 /* Invalid Firmware Image */ 944 #define NVME_CQE_SC_SPC_INV_INT_VECT 0x8 /* Invalid Interrupt Vector */ 945 #define NVME_CQE_SC_SPC_INV_LOG_PAGE 0x9 /* Invalid Log Page */ 946 #define NVME_CQE_SC_SPC_INV_FORMAT 0xa /* Invalid Format */ 947 #define NVME_CQE_SC_SPC_FW_RESET 0xb /* FW Application Reset Reqd */ 948 #define NVME_CQE_SC_SPC_INV_Q_DEL 0xc /* Invalid Queue Deletion */ 949 #define NVME_CQE_SC_SPC_FEAT_SAVE 0xd /* Feature Id Not Saveable */ 950 #define NVME_CQE_SC_SPC_FEAT_CHG 0xe /* Feature Not Changeable */ 951 #define NVME_CQE_SC_SPC_FEAT_NS_SPEC 0xf /* Feature Not Namespace Spec */ 952 #define NVME_CQE_SC_SPC_FW_NSSR 0x10 /* FW Application NSSR Reqd */ 953 #define NVME_CQE_SC_SPC_FW_NEXT_RESET 0x11 /* FW Application Next Reqd */ 954 #define NVME_CQE_SC_SPC_FW_MTFA 0x12 /* FW Application Exceed MTFA */ 955 #define NVME_CQE_SC_SPC_FW_PROHIBITED 0x13 /* FW Application Prohibited */ 956 #define NVME_CQE_SC_SPC_FW_OVERLAP 0x14 /* Overlapping FW ranges */ 957 958 /* NVMe completion status code (NVM command specific */ 959 #define NVME_CQE_SC_SPC_NVM_CNFL_ATTR 0x80 /* Conflicting Attributes */ 960 #define NVME_CQE_SC_SPC_NVM_INV_PROT 0x81 /* Invalid Protection */ 961 #define NVME_CQE_SC_SPC_NVM_READONLY 0x82 /* Write to Read Only Range */ 962 963 /* NVMe completion status code (data / metadata integrity) */ 964 #define NVME_CQE_SC_INT_NVM_WRITE 0x80 /* Write Fault */ 965 #define NVME_CQE_SC_INT_NVM_READ 0x81 /* Unrecovered Read Error */ 966 #define NVME_CQE_SC_INT_NVM_GUARD 0x82 /* Guard Check Error */ 967 #define NVME_CQE_SC_INT_NVM_APPL_TAG 0x83 /* Application Tag Check Err */ 968 #define NVME_CQE_SC_INT_NVM_REF_TAG 0x84 /* Reference Tag Check Err */ 969 #define NVME_CQE_SC_INT_NVM_COMPARE 0x85 /* Compare Failure */ 970 #define NVME_CQE_SC_INT_NVM_ACCESS 0x86 /* Access Denied */ 971 972 /* Flags for NVMe passthru commands. */ 973 #define NVME_PASSTHRU_READ 0x1 /* Read from device */ 974 #define NVME_PASSTHRU_WRITE 0x2 /* Write to device */ 975 976 /* Error codes for NVMe passthru command validation. */ 977 /* Must be sizeof(nvme_passthru_cmd_t) */ 978 #define NVME_PASSTHRU_ERR_CMD_SIZE 0x01 979 #define NVME_PASSTHRU_ERR_NOT_SUPPORTED 0x02 /* Not supported on device */ 980 #define NVME_PASSTHRU_ERR_INVALID_OPCODE 0x03 981 #define NVME_PASSTHRU_ERR_READ_AND_WRITE 0x04 /* Must read ^ write */ 982 #define NVME_PASSTHRU_ERR_INVALID_TIMEOUT 0x05 983 984 /* 985 * Must be 986 * - multiple of 4 bytes in length 987 * - non-null iff length is non-zero 988 * - null if neither reading nor writing 989 * - non-null if either reading or writing 990 * - <= `nvme_vendor_specific_admin_cmd_size` in length, 16 MiB 991 * - <= UINT32_MAX in length 992 */ 993 #define NVME_PASSTHRU_ERR_INVALID_BUFFER 0x06 994 995 996 /* Generic struct for passing through vendor-unique commands to a device. */ 997 typedef struct { 998 uint8_t npc_opcode; /* Command opcode. */ 999 uint8_t npc_status; /* Command completion status code. */ 1000 uint8_t npc_err; /* Error-code if validation fails. */ 1001 uint8_t npc_rsvd0; /* Align to 4 bytes */ 1002 uint32_t npc_timeout; /* Command timeout, in seconds. */ 1003 uint32_t npc_flags; /* Flags for the command. */ 1004 uint32_t npc_cdw0; /* Command-specific result DWord 0 */ 1005 uint32_t npc_cdw12; /* Command-specific DWord 12 */ 1006 uint32_t npc_cdw13; /* Command-specific DWord 13 */ 1007 uint32_t npc_cdw14; /* Command-specific DWord 14 */ 1008 uint32_t npc_cdw15; /* Command-specific DWord 15 */ 1009 size_t npc_buflen; /* Size of npc_buf. */ 1010 uintptr_t npc_buf; /* I/O source or destination */ 1011 } nvme_passthru_cmd_t; 1012 1013 #ifdef _KERNEL 1014 typedef struct { 1015 uint8_t npc_opcode; /* Command opcode. */ 1016 uint8_t npc_status; /* Command completion status code. */ 1017 uint8_t npc_err; /* Error-code if validation fails. */ 1018 uint8_t npc_rsvd0; /* Align to 4 bytes */ 1019 uint32_t npc_timeout; /* Command timeout, in seconds. */ 1020 uint32_t npc_flags; /* Flags for the command. */ 1021 uint32_t npc_cdw0; /* Command-specific result DWord 0 */ 1022 uint32_t npc_cdw12; /* Command-specific DWord 12 */ 1023 uint32_t npc_cdw13; /* Command-specific DWord 13 */ 1024 uint32_t npc_cdw14; /* Command-specific DWord 14 */ 1025 uint32_t npc_cdw15; /* Command-specific DWord 15 */ 1026 size32_t npc_buflen; /* Size of npc_buf. */ 1027 uintptr32_t npc_buf; /* I/O source or destination */ 1028 } nvme_passthru_cmd32_t; 1029 #endif 1030 1031 #ifdef __cplusplus 1032 } 1033 #endif 1034 1035 #endif /* _SYS_NVME_H */ 1036