1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2016 Nexenta Systems, Inc. 14 * Copyright 2020 Joyent, Inc. 15 * Copyright 2019 Western Digital Corporation 16 * Copyright 2024 Oxide Computer Company 17 * Copyright 2022 OmniOS Community Edition (OmniOSce) Association. 18 */ 19 20 #ifndef _SYS_NVME_H 21 #define _SYS_NVME_H 22 23 #include <sys/types.h> 24 #include <sys/debug.h> 25 #include <sys/stddef.h> 26 27 #ifdef _KERNEL 28 #include <sys/types32.h> 29 #else 30 #include <sys/uuid.h> 31 #include <stdint.h> 32 #endif 33 34 /* 35 * Declarations used for communication between nvmeadm(8) and nvme(4D) 36 */ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* 43 * NVMe ioctl definitions 44 */ 45 46 #define NVME_IOC (('N' << 24) | ('V' << 16) | ('M' << 8)) 47 #define NVME_IOC_CTRL_INFO (NVME_IOC | 0) 48 #define NVME_IOC_IDENTIFY (NVME_IOC | 1) 49 #define NVME_IOC_GET_LOGPAGE (NVME_IOC | 2) 50 #define NVME_IOC_GET_FEATURE (NVME_IOC | 3) 51 #define NVME_IOC_FORMAT (NVME_IOC | 4) 52 #define NVME_IOC_DETACH (NVME_IOC | 5) 53 #define NVME_IOC_ATTACH (NVME_IOC | 6) 54 #define NVME_IOC_FIRMWARE_DOWNLOAD (NVME_IOC | 7) 55 #define NVME_IOC_FIRMWARE_COMMIT (NVME_IOC | 8) 56 #define NVME_IOC_PASSTHRU (NVME_IOC | 9) 57 #define NVME_IOC_NS_INFO (NVME_IOC | 10) 58 #define NVME_IOC_LOCK (NVME_IOC | 11) 59 #define NVME_IOC_UNLOCK (NVME_IOC | 12) 60 #define NVME_IOC_MAX NVME_IOC_NS_INFO 61 62 #define IS_NVME_IOC(x) ((x) > NVME_IOC && (x) <= NVME_IOC_MAX) 63 #define NVME_IOC_CMD(x) ((x) & 0xff) 64 65 /* 66 * This represents the set of all possible errors that can be returned from an 67 * ioctl. Our general rule of thumb is that we only will use an errno value to 68 * indicate that certain processing failed: a lack of privileges, bad minor, or 69 * failure to copy in and out the initial ioctl structure. However, if we get 70 * far enough that there is any other failure (including a failure to copy in 71 * and out nested data such as the identify command payload) then we will issue 72 * an error here. Put differently, our basic promise is that there should be a 73 * single straightforward meaning for any errno returned and instead all the 74 * nuance is here. Our goal is that no one should guess what of two dozen things 75 * an EINVAL might have referred to. 76 * 77 * When we are dealing with field parameters, there are three general classes of 78 * errors that we define that are common across all request structures: 79 * 80 * <REQ>_<FIELD>_RANGE RANGE class errors indicate that the value 81 * passed in is outside the range that the device 82 * supports. The range may vary based on the 83 * specification. This is used both for issues like 84 * bad alignment in a value (e.g. not 4-byte 85 * aligned) or a value that is larger than the 86 * maximum possible size. Because the namespace ID 87 * is shared in every request in the controller and 88 * is part of our standard ioctl handling, we use a 89 * single set of errors for that. 90 * 91 * <REQ>_<FIELD>_UNSUP This indicates that the controller cannot 92 * support any value in the given field. This is 93 * either because the field was introduced in an 94 * NVMe specification later than the controller 95 * supports or because there is an explicit feature 96 * bit that indicates whether or not this field is 97 * valid. Entries here may or may not have a 98 * namespace unsupported entry due to the fact that 99 * this is command specific. 100 * 101 * <REQ>_<FIELD>_UNUSE This class is perhaps the weirdest. This 102 * represents a case where a given field cannot be 103 * set because it is not used based on the 104 * specifics of the request. For example, if you're 105 * getting the health log page, you may not set the 106 * LSP or LSI for that log page, even if you have 107 * an NVMe 1.4 controller that supports both fields 108 * because they have no meaning. A similar example 109 * would be setting a controller ID when it has no 110 * meaning in a particular identify request. 111 * 112 * While every field will have a RANGE class error, some fields will not have an 113 * UNSUP or UNUSE class error depending on the specifics. A field that has 114 * always been present since NVMe 1.0 and is always valid, such as say the log 115 * page ID field for a get log page request or the length of a firmware download 116 * request, currently are always valid. It is possible that future revisions to 117 * the specification or our logic may change this. 118 */ 119 typedef enum { 120 /* 121 * Indicates that the command actually completed successfully. 122 */ 123 NVME_IOCTL_E_OK = 0, 124 /* 125 * Indicates that the controller failed the command and the controller 126 * specific (SC/SCT) are available. For all other errors, those fields 127 * are reserved. 128 */ 129 NVME_IOCTL_E_CTRL_ERROR, 130 /* 131 * Indicates that the controller is considered "dead" by the system and 132 * therefore is unusable. Separately, the controller may have been 133 * removed from the system due to hotplug or related. In that case, the 134 * gone variant is used to distinguish this. 135 */ 136 NVME_IOCTL_E_CTRL_DEAD, 137 NVME_IOCTL_E_CTRL_GONE, 138 /* 139 * Indicates that a bad namespace was requested. This would generally 140 * happen when referring to a namespace that is outside of controller's 141 * range. 142 */ 143 NVME_IOCTL_E_NS_RANGE, 144 /* 145 * Indicates that a namespace is not usable in this context. 146 */ 147 NVME_IOCTL_E_NS_UNUSE, 148 /* 149 * Indicates that the requested namespace could not be used because we 150 * are operating on a namespace minor and asked to operate on a 151 * different namespace. 152 */ 153 NVME_IOCTL_E_MINOR_WRONG_NS, 154 /* 155 * Indicates that the requested ioctl can only operate on the controller 156 * minor and we were on a namespace minor. This is not used for when a 157 * namespace is incorrectly requested otherwise. 158 */ 159 NVME_IOCTL_E_NOT_CTRL, 160 /* 161 * Indicates that we were asked to operate on the broadcast namespace 162 * either because it was specified or that was how the request was 163 * transformed and the broadcast namespace is not supported for this 164 * operation. 165 */ 166 NVME_IOCTL_E_NO_BCAST_NS, 167 /* 168 * Indicates that the operation failed because the operation requires a 169 * controller or namespace write lock and the caller did not have it. 170 */ 171 NVME_IOCTL_E_NEED_CTRL_WRLOCK, 172 NVME_IOCTL_E_NEED_NS_WRLOCK, 173 /* 174 * Indicates that the operation could not proceed because someone else 175 * has exclusive access currently to the controller or namespace and 176 * therefore this request (which does not require exclusive access) 177 * could not proceed. 178 */ 179 NVME_IOCTL_E_CTRL_LOCKED, 180 NVME_IOCTL_E_NS_LOCKED, 181 /* 182 * Indicates that a standard log page was requested that the kernel 183 * doesn't know about. 184 */ 185 NVME_IOCTL_E_UNKNOWN_LOG_PAGE, 186 /* 187 * Indicates that the controller does not support the requested log 188 * page; however, the kernel knows about it. 189 */ 190 NVME_IOCTL_E_UNSUP_LOG_PAGE, 191 /* 192 * Indicates that the log page's scope requires operating on something 193 * that isn't what was requested. For example, trying to request the 194 * firmware information page on a namespace. 195 */ 196 NVME_IOCTL_E_BAD_LOG_SCOPE, 197 /* 198 * Log page fields with bad values. 199 */ 200 NVME_IOCTL_E_LOG_CSI_RANGE, 201 NVME_IOCTL_E_LOG_LID_RANGE, 202 NVME_IOCTL_E_LOG_LSP_RANGE, 203 NVME_IOCTL_E_LOG_LSI_RANGE, 204 NVME_IOCTL_E_LOG_RAE_RANGE, 205 NVME_IOCTL_E_LOG_SIZE_RANGE, 206 NVME_IOCTL_E_LOG_OFFSET_RANGE, 207 /* 208 * Log page fields that may not be supported. 209 */ 210 NVME_IOCTL_E_LOG_CSI_UNSUP, 211 NVME_IOCTL_E_LOG_LSP_UNSUP, 212 NVME_IOCTL_E_LOG_LSI_UNSUP, 213 NVME_IOCTL_E_LOG_RAE_UNSUP, 214 NVME_IOCTL_E_LOG_OFFSET_UNSUP, 215 /* 216 * Log page fields that may not be usable, depending on context. 217 */ 218 NVME_IOCTL_E_LOG_LSP_UNUSE, 219 NVME_IOCTL_E_LOG_LSI_UNUSE, 220 NVME_IOCTL_E_LOG_RAE_UNUSE, 221 /* 222 * Indicates that no DMA memory was available for a request. 223 */ 224 NVME_IOCTL_E_NO_DMA_MEM, 225 /* 226 * Indicates that there was no kernel memory avilable for the request. 227 */ 228 NVME_IOCTL_E_NO_KERN_MEM, 229 /* 230 * Indicates that an error occurred while trying to fill out the DMA PRP 231 */ 232 NVME_IOCTL_E_BAD_PRP, 233 /* 234 * Indicates that a pointer to user data to read from or write to was 235 * not valid and generated a fault. Specifically this is for items that 236 * an ioctl structure points to. 237 */ 238 NVME_IOCTL_E_BAD_USER_DATA, 239 /* 240 * Indicates that the kernel does not know about the requested identify 241 * command. 242 */ 243 NVME_IOCTL_E_UNKNOWN_IDENTIFY, 244 /* 245 * Indicates that the controller does not support the requested identify 246 * command. 247 */ 248 NVME_IOCTL_E_UNSUP_IDENTIFY, 249 /* 250 * The following errors indicate either a bad value for a given identify 251 * argument. This would happen because the value is outside the 252 * supported range. There is no CNS or below as those are the 253 * higher-level errors right above this. 254 */ 255 NVME_IOCTL_E_IDENTIFY_CTRLID_RANGE, 256 /* 257 * Next, we have the unsupported and unusable pieces. The nsid was 258 * supported starting in NVMe 1.0, therefore it is never unsupported. 259 * However, the controller ID both requires controller support and is 260 * not usable in several requests. 261 */ 262 NVME_IOCTL_E_IDENTIFY_CTRLID_UNSUP, 263 NVME_IOCTL_E_IDENTIFY_CTRLID_UNUSE, 264 /* 265 * Indicates that the controller does not support the NVMe spec's 266 * general vendor unique command format. 267 */ 268 NVME_IOCTL_E_CTRL_VUC_UNSUP, 269 /* 270 * The following indicate bad values for given NVMe vendor unique 271 * command fields. All of the cdw1[2-5] fields are not part of this 272 * because there is nothing that we can validate. 273 */ 274 NVME_IOCTL_E_VUC_TIMEOUT_RANGE, 275 NVME_IOCTL_E_VUC_OPCODE_RANGE, 276 NVME_IOCTL_E_VUC_FLAGS_RANGE, 277 NVME_IOCTL_E_VUC_IMPACT_RANGE, 278 NVME_IOCTL_E_VUC_NDT_RANGE, 279 /* 280 * These indicate that the VUC data and that the corresponding pair of 281 * fields do not agree with each other. 282 */ 283 NVME_IOCTL_E_INCONSIST_VUC_FLAGS_NDT, 284 NVME_IOCTL_E_INCONSIST_VUC_BUF_NDT, 285 /* 286 * Indicates that the operation in question did not succeed because 287 * blkdev failed to detach. Most often this happens because the device 288 * node is busy. Reasons the device node could be busy include that the 289 * device is in a zpool, a file system is mounted, a process has the 290 * block device open, etc. 291 */ 292 NVME_IOCTL_E_BLKDEV_DETACH, 293 /* 294 * Indicates that the operation in question failed because we were 295 * unable to create and online a new blkdev child. 296 */ 297 NVME_IOCTL_E_BLKDEV_ATTACH, 298 /* 299 * Indicates that the namespace requested for an attach is not supported 300 * by the system. This would happen due to properties of the namespace 301 * itself (e.g. utilizing metadata sectors). 302 */ 303 NVME_IOCTL_E_UNSUP_ATTACH_NS, 304 /* 305 * Indicates that the format operation is not supported by the 306 * controller at all. 307 */ 308 NVME_IOCTL_E_CTRL_FORMAT_UNSUP, 309 /* 310 * Indicates that the controller does not support the ability to perform 311 * a cryptographic secure erase. 312 */ 313 NVME_IOCTL_E_CTRL_CRYPTO_SE_UNSUP, 314 /* 315 * Indicates that a format operation is targeting a namespace, but 316 * cannot be performed because it does not support formatting an 317 * individual namespace or performing a secure-erase of an individual 318 * namespace respectively. 319 */ 320 NVME_IOCTL_E_CTRL_NS_FORMAT_UNSUP, 321 NVME_IOCTL_E_CTRL_NS_SE_UNSUP, 322 /* 323 * The following indicate bad values for a format NVM request. 324 */ 325 NVME_IOCTL_E_FORMAT_LBAF_RANGE, 326 NVME_IOCTL_E_FORMAT_SES_RANGE, 327 /* 328 * Indicates that the requested LBA format is not supported due to its 329 * use of metadata. 330 */ 331 NVME_IOCTL_E_UNSUP_LBAF_META, 332 /* 333 * Indicates that the firmware commands are not supported by the 334 * controller at all. 335 */ 336 NVME_IOCTL_E_CTRL_FW_UNSUP, 337 /* 338 * Indicates that the controller has reported a firmware update 339 * granularity that exceeds the calculated / driver supported maximum 340 * DMA transfer size. As such we cannot perform this operation. 341 */ 342 NVME_IOCTL_E_FW_LOAD_IMPOS_GRAN, 343 /* 344 * The following indicate bad values for a firmware load's length and 345 * offset. 346 */ 347 NVME_IOCTL_E_FW_LOAD_LEN_RANGE, 348 NVME_IOCTL_E_FW_LOAD_OFFSET_RANGE, 349 /* 350 * The following indicate bad values for a firmware commit's slot and 351 * action. 352 */ 353 NVME_IOCTL_E_FW_COMMIT_SLOT_RANGE, 354 NVME_IOCTL_E_FW_COMMIT_ACTION_RANGE, 355 /* 356 * Indicates that an explicit attempt was made to download an image into 357 * a read-only slot. Note, some instances of this cannot be caught prior 358 * to issuing a command to the controller (commit action 0b11 as it can 359 * be used whether there is or isn't a staged image) and will result in 360 * a controller error. 361 */ 362 NVME_IOCTL_E_RO_FW_SLOT, 363 /* 364 * Indicates that the kernel doesn't know about the NVMe feature in 365 * question and therefore cannot proceed. 366 */ 367 NVME_IOCTL_E_UNKNOWN_FEATURE, 368 /* 369 * Indicates that while the system knows about the feature in question, 370 * it is not supported by the controller. 371 */ 372 NVME_IOCTL_E_UNSUP_FEATURE, 373 /* 374 * The following errors indicate a bad value for a given get feature 375 * field. This would happen because the value is outside the supported 376 * range. 377 */ 378 NVME_IOCTL_E_GET_FEAT_SEL_RANGE, 379 NVME_IOCTL_E_GET_FEAT_CDW11_RANGE, 380 NVME_IOCTL_E_GET_FEAT_DATA_RANGE, 381 /* 382 * This set of errors indicate that the field is not supported. This can 383 * happen because a given get feature command doesn't support setting 384 * this value, the field isn't supported in this revision of the 385 * controller, or similar issues. 386 */ 387 NVME_IOCTL_E_GET_FEAT_SEL_UNSUP, 388 /* 389 * Fields that may be circumstantially unusable. 390 */ 391 NVME_IOCTL_E_GET_FEAT_CDW11_UNUSE, 392 NVME_IOCTL_E_GET_FEAT_DATA_UNUSE, 393 /* 394 * The following errors indicate a bad lock type. 395 */ 396 NVME_IOCTL_E_BAD_LOCK_ENTITY, 397 NVME_IOCTL_E_BAD_LOCK_LEVEL, 398 NVME_IOCTL_E_BAD_LOCK_FLAGS, 399 /* 400 * Indicates that a namespace open cannot lock or unlock a controller. 401 */ 402 NVME_IOCTL_E_NS_CANNOT_LOCK_CTRL, 403 NVME_IOCTL_E_NS_CANNOT_UNLOCK_CTRL, 404 /* 405 * Indicates that this lock is already held by the caller. 406 */ 407 NVME_IOCTL_E_LOCK_ALREADY_HELD, 408 /* 409 * Indicates that we cannot take the controller lock, because the 410 * caller already has an active namespace lock. 411 */ 412 NVME_IOCTL_E_LOCK_NO_CTRL_WITH_NS, 413 /* 414 * Indicates that we cannot take a namespace lock because a controller 415 * write lock already exists. 416 */ 417 NVME_IOCTL_LOCK_NO_NS_WITH_CTRL_WRLOCK, 418 /* 419 * Indicates that we cannot take a namespace lock because we already 420 * have one. 421 */ 422 NVME_IOCTL_E_LOCK_NO_2ND_NS, 423 /* 424 * Indicate that a blocking wait for a lock was interrupted due to a 425 * signal. 426 */ 427 NVME_IOCTL_E_LOCK_WAIT_SIGNAL, 428 /* 429 * Indicates that the lock could not be acquired because it was already 430 * held and we were asked not to block on the lock. 431 */ 432 NVME_IOCTL_E_LOCK_WOULD_BLOCK, 433 /* 434 * Indicates that the lock operation could not proceed because the minor 435 * is already blocking on another lock operation. 436 */ 437 NVME_IOCTL_E_LOCK_PENDING, 438 /* 439 * Indicates that the requested lock could not be unlocked because it is 440 * not held. The minor may not hold the lock or it may be blocking for 441 * acquisition. 442 */ 443 NVME_IOCTL_E_LOCK_NOT_HELD, 444 /* 445 * Indicates that the requested lock could not be unlocked because the 446 * namespace requested is not the namespace that is currently locked. 447 */ 448 NVME_IOCTL_E_LOCK_WRONG_NS, 449 /* 450 * Indicates that the request could not proceed because a namespace is 451 * attached to blkdev. This would block a format operation, a vendor 452 * unique command that indicated that it would impact all namespaces, 453 * etc. 454 */ 455 NVME_IOCTL_E_NS_BLKDEV_ATTACH, 456 /* 457 * Indicates that the blkdev address somehow would have overflowed our 458 * internal buffer. 459 */ 460 NVME_IOCTL_E_BD_ADDR_OVER 461 } nvme_ioctl_errno_t; 462 463 /* 464 * This structure is embedded as the first item of every ioctl. It is also used 465 * directly for the attach (NVME_IOC_ATTACH) and detach (NVME_IOC_DETACH) 466 * ioctls. 467 */ 468 typedef struct { 469 /* 470 * This allows one to specify the namespace ID that the ioctl may 471 * target, if it supports it. This field may be left to zero to indicate 472 * that the current open device (whether the controller or a namespace) 473 * should be targeted. If a namespace is open, a value other than 0 or 474 * the current namespace's ID is invalid. 475 */ 476 uint32_t nioc_nsid; 477 /* 478 * These next three values represent a possible error that may have 479 * occurred. On every ioctl nioc_drv_err is set to a value from the 480 * nvme_ioctl_errno_t enumeration. Anything other than NVME_IOCTL_E_OK 481 * indicates a failure of some kind. Some error values will put 482 * supplemental information in sct and sc. For example, 483 * NVME_IOCTL_E_CTRL_ERROR uses that as a way to return the raw error 484 * values from the controller for someone to inspect. Others may use 485 * this for their own well-defined supplemental information. 486 */ 487 uint32_t nioc_drv_err; 488 uint32_t nioc_ctrl_sct; 489 uint32_t nioc_ctrl_sc; 490 } nvme_ioctl_common_t; 491 492 /* 493 * NVMe Identify Command (NVME_IOC_IDENTIFY). 494 */ 495 typedef struct { 496 nvme_ioctl_common_t nid_common; 497 uint32_t nid_cns; 498 uint32_t nid_ctrlid; 499 uintptr_t nid_data; 500 } nvme_ioctl_identify_t; 501 502 /* 503 * The following constants describe the maximum values that may be used in 504 * various identify requests. 505 */ 506 #define NVME_IDENTIFY_MAX_CTRLID 0xffff 507 #define NVME_IDENTIFY_MAX_NSID 0xffffffff 508 #define NVME_IDENTIFY_MAX_CNS_1v2 0xff 509 #define NVME_IDENTIFY_MAX_CNS_1v1 0x3 510 #define NVME_IDENTIFY_MAX_CNS 0x1 511 512 /* 513 * Get a specific feature (NVME_IOC_GET_FEATURE). 514 */ 515 typedef struct { 516 nvme_ioctl_common_t nigf_common; 517 uint32_t nigf_fid; 518 uint32_t nigf_sel; 519 uint32_t nigf_cdw11; 520 uintptr_t nigf_data; 521 uint64_t nigf_len; 522 uint32_t nigf_cdw0; 523 } nvme_ioctl_get_feature_t; 524 525 /* 526 * Feature maximums. 527 */ 528 #define NVME_FEAT_MAX_FID 0xff 529 #define NVME_FEAT_MAX_SEL 0x3 530 531 /* 532 * Get a specific log page (NVME_IOC_GET_LOGPAGE). By default, unused fields 533 * should be left at zero. the input data length is specified by nigl_len, in 534 * bytes. The NVMe specification does not provide a way for a controller to 535 * write less bytes than requested for a log page. It is undefined behavior if a 536 * log page read requests more data than is supported. If this is successful, 537 * nigl_len bytes will be copied out. 538 */ 539 typedef struct { 540 nvme_ioctl_common_t nigl_common; 541 uint32_t nigl_csi; 542 uint32_t nigl_lid; 543 uint32_t nigl_lsp; 544 uint32_t nigl_lsi; 545 uint32_t nigl_rae; 546 uint64_t nigl_len; 547 uint64_t nigl_offset; 548 uintptr_t nigl_data; 549 } nvme_ioctl_get_logpage_t; 550 551 /* 552 * The following constants describe the maximum values for fields that used in 553 * the log page request. Note, some of these change with the version. These 554 * values are inclusive. The default max is the lowest common value. Larger 555 * values are included here. While these values are what the command set 556 * maximums are, the device driver may support smaller minimums (e.g. for size). 557 */ 558 #define NVME_LOG_MAX_LID 0xff 559 #define NVME_LOG_MAX_LSP 0x0f 560 #define NVME_LOG_MAX_LSP_2v0 0x7f 561 #define NVME_LOG_MAX_LSI 0xffff 562 #define NVME_LOG_MAX_UUID 0x7f 563 #define NVME_LOG_MAX_CSI 0xff 564 #define NVME_LOG_MAX_RAE 0x1 565 #define NVME_LOG_MAX_OFFSET UINT64_MAX 566 567 /* 568 * These maximum size values are inclusive like the others. The fields are 12 569 * and 32-bits wide respectively, but are zero based. That is accounted for by 570 * the shifts below. 571 */ 572 #define NVME_LOG_MAX_SIZE ((1ULL << 12ULL) * 4ULL) 573 #define NVME_LOG_MAX_SIZE_1v2 ((1ULL << 32ULL) * 4ULL) 574 575 /* 576 * Inject a vendor-specific admin command (NVME_IOC_PASSTHRU). 577 */ 578 typedef struct { 579 nvme_ioctl_common_t npc_common; /* NSID and status */ 580 uint32_t npc_opcode; /* Command opcode. */ 581 uint32_t npc_timeout; /* Command timeout, in seconds. */ 582 uint32_t npc_flags; /* Flags for the command. */ 583 uint32_t npc_impact; /* Impact information */ 584 uint32_t npc_cdw0; /* Command-specific result DWord 0 */ 585 uint32_t npc_cdw12; /* Command-specific DWord 12 */ 586 uint32_t npc_cdw13; /* Command-specific DWord 13 */ 587 uint32_t npc_cdw14; /* Command-specific DWord 14 */ 588 uint32_t npc_cdw15; /* Command-specific DWord 15 */ 589 uint64_t npc_buflen; /* Size of npc_buf. */ 590 uintptr_t npc_buf; /* I/O source or destination */ 591 } nvme_ioctl_passthru_t; 592 593 /* 594 * Constants for the passthru admin commands. Because the timeout is a kernel 595 * property, we don't include that here. 596 */ 597 #define NVME_PASSTHRU_MIN_ADMIN_OPC 0xc0 598 #define NVME_PASSTHRU_MAX_ADMIN_OPC 0xff 599 600 /* Flags for NVMe passthru commands. */ 601 #define NVME_PASSTHRU_READ 0x1 /* Read from device */ 602 #define NVME_PASSTHRU_WRITE 0x2 /* Write to device */ 603 604 /* 605 * Impact information for NVMe passthru commands. The current impact flags are 606 * defined as follows: 607 * 608 * NVME_IMPACT_NS This implies that one or all of the namespaces may be 609 * changed. This command will rescan all namespace after 610 * this occurs and update our state as a result. However, 611 * this requires that all such namespaces not be attached 612 * to blkdev to continue. 613 */ 614 #define NVME_IMPACT_NS 0x01 615 616 617 /* 618 * Firmware download (NVME_IOC_FIRMWARE_DOWNLOAD). 619 */ 620 typedef struct { 621 nvme_ioctl_common_t fwl_common; 622 uintptr_t fwl_buf; 623 uint64_t fwl_len; 624 uint64_t fwl_off; 625 } nvme_ioctl_fw_load_t; 626 627 /* 628 * Firmware commit (NVME_IOC_FIRMWARE_COMMIT). This was previously called 629 * firmware activate in earlier specification revisions. 630 */ 631 typedef struct { 632 nvme_ioctl_common_t fwc_common; 633 uint32_t fwc_slot; 634 uint32_t fwc_action; 635 } nvme_ioctl_fw_commit_t; 636 637 /* 638 * Format NVM command (NVME_IOC_FORMAT) 639 */ 640 typedef struct { 641 nvme_ioctl_common_t nif_common; 642 uint32_t nif_lbaf; 643 uint32_t nif_ses; 644 } nvme_ioctl_format_t; 645 646 typedef enum { 647 NVME_LOCK_E_CTRL = 1, 648 NVME_LOCK_E_NS 649 } nvme_lock_ent_t; 650 651 typedef enum { 652 NVME_LOCK_L_READ = 1, 653 NVME_LOCK_L_WRITE 654 } nvme_lock_level_t; 655 656 typedef enum { 657 NVME_LOCK_F_DONT_BLOCK = 1 << 0 658 } nvme_lock_flags_t; 659 660 /* 661 * Lock structure (NVME_IOC_LOCK). 662 */ 663 typedef struct { 664 nvme_ioctl_common_t nil_common; 665 nvme_lock_ent_t nil_ent; 666 nvme_lock_level_t nil_level; 667 nvme_lock_flags_t nil_flags; 668 } nvme_ioctl_lock_t; 669 670 /* 671 * Unlock structure (NVME_IOC_UNLOCK). 672 */ 673 typedef struct { 674 nvme_ioctl_common_t niu_common; 675 nvme_lock_ent_t niu_ent; 676 } nvme_ioctl_unlock_t; 677 678 /* 679 * 32-bit ioctl structures. These must be packed to be 4 bytes to get the proper 680 * ILP32 sizing. 681 */ 682 #if defined(_KERNEL) && defined(_SYSCALL32) 683 #pragma pack(4) 684 typedef struct { 685 nvme_ioctl_common_t nid_common; 686 uint32_t nid_cns; 687 uint32_t nid_ctrlid; 688 uintptr32_t nid_data; 689 } nvme_ioctl_identify32_t; 690 691 typedef struct { 692 nvme_ioctl_common_t nigf_common; 693 uint32_t nigf_fid; 694 uint32_t nigf_sel; 695 uint32_t nigf_cdw11; 696 uintptr32_t nigf_data; 697 uint64_t nigf_len; 698 uint32_t nigf_cdw0; 699 } nvme_ioctl_get_feature32_t; 700 701 typedef struct { 702 nvme_ioctl_common_t nigl_common; 703 uint32_t nigl_csi; 704 uint32_t nigl_lid; 705 uint32_t nigl_lsp; 706 uint32_t nigl_lsi; 707 uint32_t nigl_rae; 708 uint64_t nigl_len; 709 uint64_t nigl_offset; 710 uintptr32_t nigl_data; 711 } nvme_ioctl_get_logpage32_t; 712 713 typedef struct { 714 nvme_ioctl_common_t npc_common; /* NSID and status */ 715 uint32_t npc_opcode; /* Command opcode. */ 716 uint32_t npc_timeout; /* Command timeout, in seconds. */ 717 uint32_t npc_flags; /* Flags for the command. */ 718 uint32_t npc_impact; /* Impact information */ 719 uint32_t npc_cdw0; /* Command-specific result DWord 0 */ 720 uint32_t npc_cdw12; /* Command-specific DWord 12 */ 721 uint32_t npc_cdw13; /* Command-specific DWord 13 */ 722 uint32_t npc_cdw14; /* Command-specific DWord 14 */ 723 uint32_t npc_cdw15; /* Command-specific DWord 15 */ 724 uint64_t npc_buflen; /* Size of npc_buf. */ 725 uintptr32_t npc_buf; /* I/O source or destination */ 726 } nvme_ioctl_passthru32_t; 727 728 typedef struct { 729 nvme_ioctl_common_t fwl_common; 730 uintptr32_t fwl_buf; 731 uint64_t fwl_len; 732 uint64_t fwl_off; 733 } nvme_ioctl_fw_load32_t; 734 #pragma pack() /* pack(4) */ 735 #endif /* _KERNEL && _SYSCALL32 */ 736 737 /* 738 * NVMe capabilities. This is a set of fields that come from the controller's 739 * PCIe register space. 740 */ 741 typedef struct { 742 uint32_t cap_mpsmax; /* Memory Page Size Maximum */ 743 uint32_t cap_mpsmin; /* Memory Page Size Minimum */ 744 } nvme_capabilities_t; 745 746 /* 747 * NVMe version 748 */ 749 typedef struct { 750 uint16_t v_minor; 751 uint16_t v_major; 752 } nvme_version_t; 753 754 #define NVME_VERSION_ATLEAST(v, maj, min) \ 755 (((v)->v_major) > (maj) || \ 756 ((v)->v_major == (maj) && (v)->v_minor >= (min))) 757 758 #define NVME_VERSION_HIGHER(v, maj, min) \ 759 (((v)->v_major) > (maj) || \ 760 ((v)->v_major == (maj) && (v)->v_minor > (min))) 761 762 /* 763 * NVMe Namespace related constants. The maximum NSID is determined by the 764 * identify controller data structure. 765 */ 766 #define NVME_NSID_MIN 1 767 #define NVME_NSID_BCAST 0xffffffff 768 769 #pragma pack(1) 770 771 typedef struct { 772 uint64_t lo; 773 uint64_t hi; 774 } nvme_uint128_t; 775 776 /* 777 * NVMe Identify data structures 778 */ 779 780 #define NVME_IDENTIFY_BUFSIZE 4096 /* buffer size for Identify */ 781 782 /* NVMe Identify parameters (cdw10) */ 783 #define NVME_IDENTIFY_NSID 0x0 /* Identify Namespace */ 784 #define NVME_IDENTIFY_CTRL 0x1 /* Identify Controller */ 785 #define NVME_IDENTIFY_NSID_LIST 0x2 /* List Active Namespaces */ 786 #define NVME_IDENTIFY_NSID_DESC 0x3 /* Namespace ID Descriptors */ 787 788 #define NVME_IDENTIFY_NSID_ALLOC_LIST 0x10 /* List Allocated NSID */ 789 #define NVME_IDENTIFY_NSID_ALLOC 0x11 /* Identify Allocated NSID */ 790 #define NVME_IDENTIFY_NSID_CTRL_LIST 0x12 /* List Controllers on NSID */ 791 #define NVME_IDENTIFY_CTRL_LIST 0x13 /* Controller List */ 792 #define NVME_IDENTIFY_PRIMARY_CAPS 0x14 /* Primary Controller Caps */ 793 794 795 /* NVMe Queue Entry Size bitfield */ 796 typedef struct { 797 uint8_t qes_min:4; /* minimum entry size */ 798 uint8_t qes_max:4; /* maximum entry size */ 799 } nvme_idctl_qes_t; 800 801 /* NVMe Power State Descriptor */ 802 typedef struct { 803 uint16_t psd_mp; /* Maximum Power */ 804 uint8_t psd_rsvd1; 805 uint8_t psd_mps:1; /* Max Power Scale (1.1) */ 806 uint8_t psd_nops:1; /* Non-Operational State (1.1) */ 807 uint8_t psd_rsvd2:6; 808 uint32_t psd_enlat; /* Entry Latency */ 809 uint32_t psd_exlat; /* Exit Latency */ 810 uint8_t psd_rrt:5; /* Relative Read Throughput */ 811 uint8_t psd_rsvd3:3; 812 uint8_t psd_rrl:5; /* Relative Read Latency */ 813 uint8_t psd_rsvd4:3; 814 uint8_t psd_rwt:5; /* Relative Write Throughput */ 815 uint8_t psd_rsvd5:3; 816 uint8_t psd_rwl:5; /* Relative Write Latency */ 817 uint8_t psd_rsvd6:3; 818 uint16_t psd_idlp; /* Idle Power (1.2) */ 819 uint8_t psd_rsvd7:6; 820 uint8_t psd_ips:2; /* Idle Power Scale (1.2) */ 821 uint8_t psd_rsvd8; 822 uint16_t psd_actp; /* Active Power (1.2) */ 823 uint8_t psd_apw:3; /* Active Power Workload (1.2) */ 824 uint8_t psd_rsvd9:3; 825 uint8_t psd_aps:2; /* Active Power Scale */ 826 uint8_t psd_rsvd10[9]; 827 } nvme_idctl_psd_t; 828 829 #define NVME_SERIAL_SZ 20 830 #define NVME_MODEL_SZ 40 831 #define NVME_FWVER_SZ 8 832 833 /* NVMe Identify Controller Data Structure */ 834 typedef struct { 835 /* Controller Capabilities & Features */ 836 uint16_t id_vid; /* PCI vendor ID */ 837 uint16_t id_ssvid; /* PCI subsystem vendor ID */ 838 char id_serial[NVME_SERIAL_SZ]; /* Serial Number */ 839 char id_model[NVME_MODEL_SZ]; /* Model Number */ 840 char id_fwrev[NVME_FWVER_SZ]; /* Firmware Revision */ 841 uint8_t id_rab; /* Recommended Arbitration Burst */ 842 uint8_t id_oui[3]; /* vendor IEEE OUI */ 843 struct { /* Multi-Interface Capabilities */ 844 uint8_t m_multi_pci:1; /* HW has multiple PCIe interfaces */ 845 uint8_t m_multi_ctrl:1; /* HW has multiple controllers (1.1) */ 846 uint8_t m_sr_iov:1; /* Controller is SR-IOV virt fn (1.1) */ 847 uint8_t m_anar_sup:1; /* ANA Reporting Supported (1.4) */ 848 uint8_t m_rsvd:4; 849 } id_mic; 850 uint8_t id_mdts; /* Maximum Data Transfer Size */ 851 uint16_t id_cntlid; /* Unique Controller Identifier (1.1) */ 852 /* Added in NVMe 1.2 */ 853 uint32_t id_ver; /* Version (1.2) */ 854 uint32_t id_rtd3r; /* RTD3 Resume Latency (1.2) */ 855 uint32_t id_rtd3e; /* RTD3 Entry Latency (1.2) */ 856 struct { 857 uint32_t oaes_rsvd0:8; 858 uint32_t oaes_nsan:1; /* Namespace Attribute Notices (1.2) */ 859 uint32_t oaes_fwact:1; /* Firmware Activation Notices (1.2) */ 860 uint32_t oaes_rsvd1:1; 861 uint32_t oaes_ansacn:1; /* Asymmetric NS Access Change (1.4) */ 862 uint32_t oaes_plat:1; /* Predictable Lat Event Agg. (1.4) */ 863 uint32_t oaes_lbasi:1; /* LBA Status Information (1.4) */ 864 uint32_t oaes_egeal:1; /* Endurance Group Event Agg. (1.4) */ 865 uint32_t oaes_rsvd2:17; 866 } id_oaes; 867 struct { 868 uint32_t ctrat_hid:1; /* 128-bit Host Identifier (1.2) */ 869 uint32_t ctrat_nops:1; /* Non-Operational Power State (1.3) */ 870 uint32_t ctrat_nvmset:1; /* NVMe Sets (1.4) */ 871 uint32_t ctrat_rrl:1; /* Read Recovery Levels (1.4) */ 872 uint32_t ctrat_engrp:1; /* Endurance Groups (1.4) */ 873 uint32_t ctrat_plm:1; /* Predictable Latency Mode (1.4) */ 874 uint32_t ctrat_tbkas:1; /* Traffic Based Keep Alive (1.4) */ 875 uint32_t ctrat_nsg:1; /* Namespace Granularity (1.4) */ 876 uint32_t ctrat_sqass:1; /* SQ Associations (1.4) */ 877 uint32_t ctrat_uuid:1; /* UUID List (1.4) */ 878 uint32_t ctrat_rsvd:22; 879 } id_ctratt; 880 uint16_t id_rrls; /* Read Recovery Levels (1.4) */ 881 uint8_t id_rsvd_cc[111-102]; 882 uint8_t id_cntrltype; /* Controller Type (1.4) */ 883 uint8_t id_frguid[16]; /* FRU GUID (1.3) */ 884 uint16_t id_crdt1; /* Command Retry Delay Time 1 (1.4) */ 885 uint16_t id_crdt2; /* Command Retry Delay Time 2 (1.4) */ 886 uint16_t id_crdt3; /* Command Retry Delay Time 3 (1.4) */ 887 uint8_t id_rsvd2_cc[240 - 134]; 888 uint8_t id_rsvd_nvmemi[253 - 240]; 889 /* NVMe-MI region */ 890 struct { /* NVMe Subsystem Report */ 891 uint8_t nvmsr_nvmesd:1; /* NVMe Storage Device */ 892 uint8_t nvmsr_nvmee:1; /* NVMe Enclosure */ 893 uint8_t nvmsr_rsvd:6; 894 } id_nvmsr; 895 struct { /* VPD Write Cycle Information */ 896 uint8_t vwci_crem:7; /* Write Cycles Remaining */ 897 uint8_t vwci_valid:1; /* Write Cycles Remaining Valid */ 898 } id_vpdwc; 899 struct { /* Management Endpoint Capabilities */ 900 uint8_t mec_smbusme:1; /* SMBus Port Management Endpoint */ 901 uint8_t mec_pcieme:1; /* PCIe Port Management Endpoint */ 902 uint8_t mec_rsvd:6; 903 } id_mec; 904 905 /* Admin Command Set Attributes */ 906 struct { /* Optional Admin Command Support */ 907 uint16_t oa_security:1; /* Security Send & Receive */ 908 uint16_t oa_format:1; /* Format NVM */ 909 uint16_t oa_firmware:1; /* Firmware Activate & Download */ 910 uint16_t oa_nsmgmt:1; /* Namespace Management (1.2) */ 911 uint16_t oa_selftest:1; /* Self Test (1.3) */ 912 uint16_t oa_direct:1; /* Directives (1.3) */ 913 uint16_t oa_nvmemi:1; /* MI-Send/Recv (1.3) */ 914 uint16_t oa_virtmgmt:1; /* Virtualization Management (1.3) */ 915 uint16_t oa_doorbell:1; /* Doorbell Buffer Config (1.3) */ 916 uint16_t oa_lbastat:1; /* LBA Status (1.4) */ 917 uint16_t oa_rsvd:6; 918 } id_oacs; 919 uint8_t id_acl; /* Abort Command Limit */ 920 uint8_t id_aerl; /* Asynchronous Event Request Limit */ 921 struct { /* Firmware Updates */ 922 uint8_t fw_readonly:1; /* Slot 1 is Read-Only */ 923 uint8_t fw_nslot:3; /* number of firmware slots */ 924 uint8_t fw_norst:1; /* Activate w/o reset (1.2) */ 925 uint8_t fw_rsvd:3; 926 } id_frmw; 927 struct { /* Log Page Attributes */ 928 uint8_t lp_smart:1; /* SMART/Health information per NS */ 929 uint8_t lp_cmdeff:1; /* Command Effects (1.2) */ 930 uint8_t lp_extsup:1; /* Extended Get Log Page (1.2) */ 931 uint8_t lp_telemetry:1; /* Telemetry Log Pages (1.3) */ 932 uint8_t lp_persist:1; /* Persistent Log Page (1.4) */ 933 uint8_t lp_rsvd:3; 934 } id_lpa; 935 uint8_t id_elpe; /* Error Log Page Entries */ 936 uint8_t id_npss; /* Number of Power States */ 937 struct { /* Admin Vendor Specific Command Conf */ 938 uint8_t av_spec:1; /* use format from spec */ 939 uint8_t av_rsvd:7; 940 } id_avscc; 941 struct { /* Autonomous Power State Trans (1.1) */ 942 uint8_t ap_sup:1; /* APST supported (1.1) */ 943 uint8_t ap_rsvd:7; 944 } id_apsta; 945 uint16_t ap_wctemp; /* Warning Composite Temp. (1.2) */ 946 uint16_t ap_cctemp; /* Critical Composite Temp. (1.2) */ 947 uint16_t ap_mtfa; /* Maximum Firmware Activation (1.2) */ 948 uint32_t ap_hmpre; /* Host Memory Buf Pref Size (1.2) */ 949 uint32_t ap_hmmin; /* Host Memory Buf Min Size (1.2) */ 950 nvme_uint128_t ap_tnvmcap; /* Total NVM Capacity in Bytes (1.2) */ 951 nvme_uint128_t ap_unvmcap; /* Unallocated NVM Capacity (1.2) */ 952 struct { /* Replay Protected Mem. Block (1.2) */ 953 uint32_t rpmbs_units:3; /* Number of targets */ 954 uint32_t rpmbs_auth:3; /* Auth method */ 955 uint32_t rpmbs_rsvd:10; 956 uint32_t rpmbs_tot:8; /* Total size in 128KB */ 957 uint32_t rpmbs_acc:8; /* Access size in 512B */ 958 } ap_rpmbs; 959 /* Added in NVMe 1.3 */ 960 uint16_t ap_edstt; /* Ext. Device Self-test time (1.3) */ 961 struct { /* Device Self-test Options */ 962 uint8_t dsto_sub:1; /* Subsystem level self-test (1.3) */ 963 uint8_t dsto_rsvd:7; 964 } ap_dsto; 965 uint8_t ap_fwug; /* Firmware Update Granularity (1.3) */ 966 uint16_t ap_kas; /* Keep Alive Support (1.2) */ 967 struct { /* Host Thermal Management (1.3) */ 968 uint16_t hctma_hctm:1; /* Host Controlled (1.3) */ 969 uint16_t hctma_rsvd:15; 970 } ap_hctma; 971 uint16_t ap_mntmt; /* Minimum Thermal Temperature (1.3) */ 972 uint16_t ap_mxtmt; /* Maximum Thermal Temperature (1.3) */ 973 struct { /* Sanitize Caps */ 974 uint32_t san_ces:1; /* Crypto Erase Support (1.3) */ 975 uint32_t san_bes:1; /* Block Erase Support (1.3) */ 976 uint32_t san_ows:1; /* Overwite Support (1.3) */ 977 uint32_t san_rsvd:26; 978 uint32_t san_ndi:1; /* No-deallocate Inhibited (1.4) */ 979 uint32_t san_nodmmas:2; /* No-Deallocate Modifies Media (1.4) */ 980 } ap_sanitize; 981 uint32_t ap_hmminds; /* Host Mem Buf Min Desc Entry (1.4) */ 982 uint16_t ap_hmmaxd; /* How Mem Max Desc Entries (1.4) */ 983 uint16_t ap_nsetidmax; /* Max NVMe set identifier (1.4) */ 984 uint16_t ap_engidmax; /* Max Endurance Group ID (1.4) */ 985 uint8_t ap_anatt; /* ANA Transition Time (1.4) */ 986 struct { /* Asymmetric Namespace Access Caps */ 987 uint8_t anacap_opt:1; /* Optimized State (1.4) */ 988 uint8_t anacap_unopt:1; /* Un-optimized State (1.4) */ 989 uint8_t anacap_inacc:1; /* Inaccessible State (1.4) */ 990 uint8_t anacap_ploss:1; /* Persistent Loss (1.4) */ 991 uint8_t anacap_chg:1; /* Change State (1.4 ) */ 992 uint8_t anacap_rsvd:1; 993 uint8_t anacap_grpns:1; /* ID Changes with NS Attach (1.4) */ 994 uint8_t anacap_grpid:1; /* Supports Group ID (1.4) */ 995 } ap_anacap; 996 uint32_t ap_anagrpmax; /* ANA Group ID Max (1.4) */ 997 uint32_t ap_nanagrpid; /* Number of ANA Group IDs (1.4) */ 998 uint32_t ap_pels; /* Persistent Event Log Size (1.4) */ 999 uint8_t id_rsvd_ac[512 - 356]; 1000 1001 /* NVM Command Set Attributes */ 1002 nvme_idctl_qes_t id_sqes; /* Submission Queue Entry Size */ 1003 nvme_idctl_qes_t id_cqes; /* Completion Queue Entry Size */ 1004 uint16_t id_maxcmd; /* Max Outstanding Commands (1.3) */ 1005 uint32_t id_nn; /* Number of Namespaces */ 1006 struct { /* Optional NVM Command Support */ 1007 uint16_t on_compare:1; /* Compare */ 1008 uint16_t on_wr_unc:1; /* Write Uncorrectable */ 1009 uint16_t on_dset_mgmt:1; /* Dataset Management */ 1010 uint16_t on_wr_zero:1; /* Write Zeros (1.1) */ 1011 uint16_t on_save:1; /* Save/Select in Get/Set Feat (1.1) */ 1012 uint16_t on_reserve:1; /* Reservations (1.1) */ 1013 uint16_t on_ts:1; /* Timestamp (1.3) */ 1014 uint16_t on_verify:1; /* Verify (1.4) */ 1015 uint16_t on_rsvd:8; 1016 } id_oncs; 1017 struct { /* Fused Operation Support */ 1018 uint16_t f_cmp_wr:1; /* Compare and Write */ 1019 uint16_t f_rsvd:15; 1020 } id_fuses; 1021 struct { /* Format NVM Attributes */ 1022 uint8_t fn_format:1; /* Format applies to all NS */ 1023 uint8_t fn_sec_erase:1; /* Secure Erase applies to all NS */ 1024 uint8_t fn_crypt_erase:1; /* Cryptographic Erase supported */ 1025 uint8_t fn_rsvd:5; 1026 } id_fna; 1027 struct { /* Volatile Write Cache */ 1028 uint8_t vwc_present:1; /* Volatile Write Cache present */ 1029 uint8_t vwc_nsflush:2; /* Flush with NS ffffffff (1.4) */ 1030 uint8_t rsvd:5; 1031 } id_vwc; 1032 uint16_t id_awun; /* Atomic Write Unit Normal */ 1033 uint16_t id_awupf; /* Atomic Write Unit Power Fail */ 1034 struct { /* NVM Vendor Specific Command Conf */ 1035 uint8_t nv_spec:1; /* use format from spec */ 1036 uint8_t nv_rsvd:7; 1037 } id_nvscc; 1038 struct { /* Namespace Write Protection Caps */ 1039 uint8_t nwpc_base:1; /* Base support (1.4) */ 1040 uint8_t nwpc_wpupc:1; /* Write prot until power cycle (1.4) */ 1041 uint8_t nwpc_permwp:1; /* Permanent write prot (1.4) */ 1042 uint8_t nwpc_rsvd:5; 1043 } id_nwpc; 1044 uint16_t id_acwu; /* Atomic Compare & Write Unit (1.1) */ 1045 uint16_t id_rsvd_nc_3; 1046 struct { /* SGL Support (1.1) */ 1047 uint16_t sgl_sup:2; /* SGL Supported in NVM cmds (1.3) */ 1048 uint16_t sgl_keyed:1; /* Keyed SGL Support (1.2) */ 1049 uint16_t sgl_rsvd1:13; 1050 uint16_t sgl_bucket:1; /* SGL Bit Bucket supported (1.1) */ 1051 uint16_t sgl_balign:1; /* SGL Byte Aligned (1.2) */ 1052 uint16_t sgl_sglgtd:1; /* SGL Length Longer than Data (1.2) */ 1053 uint16_t sgl_mptr:1; /* SGL MPTR w/ SGL (1.2) */ 1054 uint16_t sgl_offset:1; /* SGL Address is offset (1.2) */ 1055 uint16_t sgl_tport:1; /* Transport SGL Data Block (1.4) */ 1056 uint16_t sgl_rsvd2:10; 1057 } id_sgls; 1058 uint32_t id_mnan; /* Maximum Number of Allowed NSes */ 1059 uint8_t id_rsvd_nc_4[768 - 544]; 1060 1061 /* I/O Command Set Attributes */ 1062 uint8_t id_subnqn[1024 - 768]; /* Subsystem Qualified Name (1.2.1+) */ 1063 uint8_t id_rsvd_ioc[1792 - 1024]; 1064 uint8_t id_nvmof[2048 - 1792]; /* NVMe over Fabrics */ 1065 1066 /* Power State Descriptors */ 1067 nvme_idctl_psd_t id_psd[32]; 1068 1069 /* Vendor Specific */ 1070 uint8_t id_vs[1024]; 1071 } nvme_identify_ctrl_t; 1072 1073 /* 1074 * NVMe Controller Types 1075 */ 1076 #define NVME_CNTRLTYPE_RSVD 0 1077 #define NVME_CNTRLTYPE_IO 1 1078 #define NVME_CNTRLTYPE_DISC 2 1079 #define NVME_CNTRLTYPE_ADMIN 3 1080 1081 /* 1082 * RPMBS Authentication Types 1083 */ 1084 #define NVME_RPMBS_AUTH_HMAC_SHA256 0 1085 1086 /* 1087 * NODMMAS Values 1088 */ 1089 #define NVME_NODMMAS_UNDEF 0x00 1090 #define NVME_NODMMAS_NOMOD 0x01 1091 #define NVME_NODMMAS_DOMOD 0x02 1092 1093 /* 1094 * VWC NSID flushes 1095 */ 1096 #define NVME_VWCNS_UNKNOWN 0x00 1097 #define NVME_VWCNS_UNSUP 0x02 1098 #define NVME_VWCNS_SUP 0x03 1099 1100 /* 1101 * SGL Support Values 1102 */ 1103 #define NVME_SGL_UNSUP 0x00 1104 #define NVME_SGL_SUP_UNALIGN 0x01 1105 #define NVME_SGL_SUP_ALIGN 0x02 1106 1107 /* NVMe Identify Namespace LBA Format */ 1108 typedef struct { 1109 uint16_t lbaf_ms; /* Metadata Size */ 1110 uint8_t lbaf_lbads; /* LBA Data Size */ 1111 uint8_t lbaf_rp:2; /* Relative Performance */ 1112 uint8_t lbaf_rsvd1:6; 1113 } nvme_idns_lbaf_t; 1114 1115 #define NVME_MAX_LBAF 16 1116 1117 /* NVMe Identify Namespace Data Structure */ 1118 typedef struct { 1119 uint64_t id_nsize; /* Namespace Size */ 1120 uint64_t id_ncap; /* Namespace Capacity */ 1121 uint64_t id_nuse; /* Namespace Utilization */ 1122 struct { /* Namespace Features */ 1123 uint8_t f_thin:1; /* Thin Provisioning */ 1124 uint8_t f_nsabp:1; /* Namespace atomics (1.2) */ 1125 uint8_t f_dae:1; /* Deallocated errors supported (1.2) */ 1126 uint8_t f_uidreuse:1; /* GUID reuse impossible (1.3) */ 1127 uint8_t f_optperf:1; /* Namespace I/O opt (1.4) */ 1128 uint8_t f_rsvd:3; 1129 } id_nsfeat; 1130 uint8_t id_nlbaf; /* Number of LBA formats */ 1131 struct { /* Formatted LBA size */ 1132 uint8_t lba_format:4; /* LBA format */ 1133 uint8_t lba_extlba:1; /* extended LBA (includes metadata) */ 1134 uint8_t lba_rsvd:3; 1135 } id_flbas; 1136 struct { /* Metadata Capabilities */ 1137 uint8_t mc_extlba:1; /* extended LBA transfers */ 1138 uint8_t mc_separate:1; /* separate metadata transfers */ 1139 uint8_t mc_rsvd:6; 1140 } id_mc; 1141 struct { /* Data Protection Capabilities */ 1142 uint8_t dp_type1:1; /* Protection Information Type 1 */ 1143 uint8_t dp_type2:1; /* Protection Information Type 2 */ 1144 uint8_t dp_type3:1; /* Protection Information Type 3 */ 1145 uint8_t dp_first:1; /* first 8 bytes of metadata */ 1146 uint8_t dp_last:1; /* last 8 bytes of metadata */ 1147 uint8_t dp_rsvd:3; 1148 } id_dpc; 1149 struct { /* Data Protection Settings */ 1150 uint8_t dp_pinfo:3; /* Protection Information enabled */ 1151 uint8_t dp_first:1; /* first 8 bytes of metadata */ 1152 uint8_t dp_rsvd:4; 1153 } id_dps; 1154 struct { /* NS Multi-Path/Sharing Cap (1.1) */ 1155 uint8_t nm_shared:1; /* NS is shared (1.1) */ 1156 uint8_t nm_rsvd:7; 1157 } id_nmic; 1158 struct { /* Reservation Capabilities (1.1) */ 1159 uint8_t rc_persist:1; /* Persist Through Power Loss (1.1) */ 1160 uint8_t rc_wr_excl:1; /* Write Exclusive (1.1) */ 1161 uint8_t rc_excl:1; /* Exclusive Access (1.1) */ 1162 uint8_t rc_wr_excl_r:1; /* Wr Excl - Registrants Only (1.1) */ 1163 uint8_t rc_excl_r:1; /* Excl Acc - Registrants Only (1.1) */ 1164 uint8_t rc_wr_excl_a:1; /* Wr Excl - All Registrants (1.1) */ 1165 uint8_t rc_excl_a:1; /* Excl Acc - All Registrants (1.1) */ 1166 uint8_t rc_ign_ekey:1; /* Ignore Existing Key (1.3) */ 1167 } id_rescap; 1168 struct { /* Format Progress Indicator (1.2) */ 1169 uint8_t fpi_remp:7; /* Percent NVM Format Remaining (1.2) */ 1170 uint8_t fpi_sup:1; /* Supported (1.2) */ 1171 } id_fpi; 1172 uint8_t id_dfleat; /* Deallocate Log. Block (1.3) */ 1173 uint16_t id_nawun; /* Atomic Write Unit Normal (1.2) */ 1174 uint16_t id_nawupf; /* Atomic Write Unit Power Fail (1.2) */ 1175 uint16_t id_nacwu; /* Atomic Compare & Write Unit (1.2) */ 1176 uint16_t id_nabsn; /* Atomic Boundary Size Normal (1.2) */ 1177 uint16_t id_nbao; /* Atomic Boundary Offset (1.2) */ 1178 uint16_t id_nabspf; /* Atomic Boundary Size Fail (1.2) */ 1179 uint16_t id_noiob; /* Optimal I/O Bondary (1.3) */ 1180 nvme_uint128_t id_nvmcap; /* NVM Capacity */ 1181 uint16_t id_npwg; /* NS Pref. Write Gran. (1.4) */ 1182 uint16_t id_npwa; /* NS Pref. Write Align. (1.4) */ 1183 uint16_t id_npdg; /* NS Pref. Deallocate Gran. (1.4) */ 1184 uint16_t id_npda; /* NS Pref. Deallocate Align. (1.4) */ 1185 uint16_t id_nows; /* NS. Optimal Write Size (1.4) */ 1186 uint8_t id_rsvd1[92 - 74]; 1187 uint32_t id_anagrpid; /* ANA Group Identifier (1.4) */ 1188 uint8_t id_rsvd2[99 - 96]; 1189 struct { 1190 uint8_t nsa_wprot:1; /* Write Protected (1.4) */ 1191 uint8_t nsa_rsvd:7; 1192 } id_nsattr; 1193 uint16_t id_nvmsetid; /* NVM Set Identifier (1.4) */ 1194 uint16_t id_endgid; /* Endurance Group Identifier (1.4) */ 1195 uint8_t id_nguid[16]; /* Namespace GUID (1.2) */ 1196 uint8_t id_eui64[8]; /* IEEE Extended Unique Id (1.1) */ 1197 nvme_idns_lbaf_t id_lbaf[NVME_MAX_LBAF]; /* LBA Formats */ 1198 1199 uint8_t id_rsvd3[384 - 192]; 1200 1201 uint8_t id_vs[4096 - 384]; /* Vendor Specific */ 1202 } nvme_identify_nsid_t; 1203 1204 /* NVMe Identify Namespace ID List */ 1205 typedef struct { 1206 /* Ordered list of Namespace IDs */ 1207 uint32_t nl_nsid[NVME_IDENTIFY_BUFSIZE / sizeof (uint32_t)]; 1208 } nvme_identify_nsid_list_t; 1209 1210 /* NVME Identify Controller ID List */ 1211 typedef struct { 1212 uint16_t cl_nid; /* Number of controller entries */ 1213 /* unique controller identifiers */ 1214 uint16_t cl_ctlid[NVME_IDENTIFY_BUFSIZE / sizeof (uint16_t) - 1]; 1215 } nvme_identify_ctrl_list_t; 1216 1217 /* NVMe Identify Namespace Descriptor */ 1218 typedef struct { 1219 uint8_t nd_nidt; /* Namespace Identifier Type */ 1220 uint8_t nd_nidl; /* Namespace Identifier Length */ 1221 uint8_t nd_resv[2]; 1222 uint8_t nd_nid[]; /* Namespace Identifier */ 1223 } nvme_identify_nsid_desc_t; 1224 1225 #define NVME_NSID_DESC_EUI64 1 1226 #define NVME_NSID_DESC_NGUID 2 1227 #define NVME_NSID_DESC_NUUID 3 1228 #define NVME_NSID_DESC_MIN NVME_NSID_DESC_EUI64 1229 #define NVME_NSID_DESC_MAX NVME_NSID_DESC_NUUID 1230 1231 #define NVME_NSID_DESC_LEN_EUI64 8 1232 #define NVME_NSID_DESC_LEN_NGUID 16 1233 #define NVME_NSID_DESC_LEN_NUUID UUID_LEN 1234 1235 /* NVMe Identify Primary Controller Capabilities */ 1236 typedef struct { 1237 uint16_t nipc_cntlid; /* Controller ID */ 1238 uint16_t nipc_portid; /* Port Identifier */ 1239 uint8_t nipc_crt; /* Controller Resource Types */ 1240 uint8_t nipc_rsvd0[32 - 5]; 1241 uint32_t nipc_vqfrt; /* VQ Resources Flexible Total */ 1242 uint32_t nipc_vqrfa; /* VQ Resources Flexible Assigned */ 1243 uint16_t nipc_vqrfap; /* VQ Resources to Primary */ 1244 uint16_t nipc_vqprt; /* VQ Resources Private Total */ 1245 uint16_t nipc_vqfrsm; /* VQ Resources Secondary Max */ 1246 uint16_t nipc_vqgran; /* VQ Flexible Resource Gran */ 1247 uint8_t nipc_rvsd1[64 - 48]; 1248 uint32_t nipc_vifrt; /* VI Flexible total */ 1249 uint32_t nipc_virfa; /* VI Flexible Assigned */ 1250 uint16_t nipc_virfap; /* VI Flexible Allocated to Primary */ 1251 uint16_t nipc_viprt; /* VI Resources Private Total */ 1252 uint16_t nipc_vifrsm; /* VI Resources Secondary Max */ 1253 uint16_t nipc_vigran; /* VI Flexible Granularity */ 1254 uint8_t nipc_rsvd2[4096 - 80]; 1255 } nvme_identify_primary_caps_t; 1256 1257 /* 1258 * NVMe completion queue entry status field 1259 */ 1260 typedef struct { 1261 uint16_t sf_p:1; /* Phase Tag */ 1262 uint16_t sf_sc:8; /* Status Code */ 1263 uint16_t sf_sct:3; /* Status Code Type */ 1264 uint16_t sf_rsvd2:2; 1265 uint16_t sf_m:1; /* More */ 1266 uint16_t sf_dnr:1; /* Do Not Retry */ 1267 } nvme_cqe_sf_t; 1268 1269 1270 /* 1271 * NVMe Get Log Page 1272 */ 1273 #define NVME_LOGPAGE_SUP 0x00 /* Supported Logs (2.0) */ 1274 #define NVME_LOGPAGE_ERROR 0x01 /* Error Information */ 1275 #define NVME_LOGPAGE_HEALTH 0x02 /* SMART/Health Information */ 1276 #define NVME_LOGPAGE_FWSLOT 0x03 /* Firmware Slot Information */ 1277 #define NVME_LOGPAGE_NSCHANGE 0x04 /* Changed namespace (1.2) */ 1278 #define NVME_LOGPAGE_CMDSUP 0x05 /* Cmds. Supported and Effects (1.3) */ 1279 #define NVME_LOGPAGE_SELFTEST 0x06 /* Device self-test (1.3) */ 1280 #define NVME_LOGPAGE_TELMHOST 0x07 /* Telemetry Host-Initiated */ 1281 #define NVME_LOGPAGE_TELMCTRL 0x08 /* Telemetry Controller-Initiated */ 1282 #define NVME_LOGPAGE_ENDGRP 0x09 /* Endurance Group Information (1.4) */ 1283 #define NVME_LOGPAGE_PLATSET 0x0a /* Predictable Lat. per NVM Set (1.4) */ 1284 #define NVME_LOGPAGE_PLATAGG 0x0b /* Predictable Lat. Event Agg (1.4) */ 1285 #define NVME_LOGPAGE_ASYMNS 0x0c /* Asymmetric Namespace Access (1.4) */ 1286 #define NVME_LOGPAGE_PEVLOG 0x0d /* Persistent Event Log (1.4) */ 1287 #define NVME_LOGPAGE_LBASTS 0x0e /* LBA Status Information (1.4) */ 1288 #define NVME_LOGPAGE_ENDAGG 0x0f /* Endurance Group Event Agg. (1.4) */ 1289 1290 #define NVME_LOGPAGE_VEND_MIN 0xc0 1291 #define NVME_LOGPAGE_VEND_MAX 0xff 1292 1293 /* 1294 * Supported Log Pages (2.0). There is one entry of an nvme_logsup_t that then 1295 * exists on a per-log basis. 1296 */ 1297 1298 /* 1299 * The NVMe Log Identifier specific parameter field. Currently there is only one 1300 * defined field for the persistent event log (pel). 1301 */ 1302 typedef union { 1303 uint16_t nsl_lidsp; /* Raw Value */ 1304 struct { /* Persistent Event Log */ 1305 uint16_t nsl_ec512:1; 1306 uint16_t nsl_pel_rsvd0p1:15; 1307 } nsl_pel; 1308 } nvme_suplog_lidsp_t; 1309 1310 typedef struct { 1311 uint16_t ns_lsupp:1; 1312 uint16_t ns_ios:1; 1313 uint16_t ns_rsvd0p2:14; 1314 nvme_suplog_lidsp_t ns_lidsp; 1315 } nvme_suplog_t; 1316 1317 CTASSERT(sizeof (nvme_suplog_lidsp_t) == 2); 1318 CTASSERT(sizeof (nvme_suplog_t) == 4); 1319 1320 typedef struct { 1321 nvme_suplog_t nl_logs[256]; 1322 } nvme_suplog_log_t; 1323 1324 CTASSERT(sizeof (nvme_suplog_log_t) == 1024); 1325 1326 /* 1327 * SMART / Health information 1328 */ 1329 typedef struct { 1330 uint64_t el_count; /* Error Count */ 1331 uint16_t el_sqid; /* Submission Queue ID */ 1332 uint16_t el_cid; /* Command ID */ 1333 nvme_cqe_sf_t el_sf; /* Status Field */ 1334 uint8_t el_byte; /* Parameter Error Location byte */ 1335 uint8_t el_bit:3; /* Parameter Error Location bit */ 1336 uint8_t el_rsvd1:5; 1337 uint64_t el_lba; /* Logical Block Address */ 1338 uint32_t el_nsid; /* Namespace ID */ 1339 uint8_t el_vendor; /* Vendor Specific Information avail */ 1340 uint8_t el_rsvd2[64 - 29]; 1341 } nvme_error_log_entry_t; 1342 1343 typedef struct { 1344 struct { /* Critical Warning */ 1345 uint8_t cw_avail:1; /* available space too low */ 1346 uint8_t cw_temp:1; /* temperature too high */ 1347 uint8_t cw_reliab:1; /* degraded reliability */ 1348 uint8_t cw_readonly:1; /* media is read-only */ 1349 uint8_t cw_volatile:1; /* volatile memory backup failed */ 1350 uint8_t cw_rsvd:3; 1351 } hl_crit_warn; 1352 uint16_t hl_temp; /* Temperature */ 1353 uint8_t hl_avail_spare; /* Available Spare */ 1354 uint8_t hl_avail_spare_thr; /* Available Spare Threshold */ 1355 uint8_t hl_used; /* Percentage Used */ 1356 uint8_t hl_rsvd1[32 - 6]; 1357 nvme_uint128_t hl_data_read; /* Data Units Read */ 1358 nvme_uint128_t hl_data_write; /* Data Units Written */ 1359 nvme_uint128_t hl_host_read; /* Host Read Commands */ 1360 nvme_uint128_t hl_host_write; /* Host Write Commands */ 1361 nvme_uint128_t hl_ctrl_busy; /* Controller Busy Time */ 1362 nvme_uint128_t hl_power_cycles; /* Power Cycles */ 1363 nvme_uint128_t hl_power_on_hours; /* Power On Hours */ 1364 nvme_uint128_t hl_unsafe_shutdn; /* Unsafe Shutdowns */ 1365 nvme_uint128_t hl_media_errors; /* Media Errors */ 1366 nvme_uint128_t hl_errors_logged; /* Number of errors logged */ 1367 /* Added in NVMe 1.2 */ 1368 uint32_t hl_warn_temp_time; /* Warning Composite Temp Time */ 1369 uint32_t hl_crit_temp_time; /* Critical Composite Temp Time */ 1370 uint16_t hl_temp_sensor_1; /* Temperature Sensor 1 */ 1371 uint16_t hl_temp_sensor_2; /* Temperature Sensor 2 */ 1372 uint16_t hl_temp_sensor_3; /* Temperature Sensor 3 */ 1373 uint16_t hl_temp_sensor_4; /* Temperature Sensor 4 */ 1374 uint16_t hl_temp_sensor_5; /* Temperature Sensor 5 */ 1375 uint16_t hl_temp_sensor_6; /* Temperature Sensor 6 */ 1376 uint16_t hl_temp_sensor_7; /* Temperature Sensor 7 */ 1377 uint16_t hl_temp_sensor_8; /* Temperature Sensor 8 */ 1378 /* Added in NVMe 1.3 */ 1379 uint32_t hl_tmtemp_1_tc; /* Thermal Mgmt Temp 1 Transition # */ 1380 uint32_t hl_tmtemp_2_tc; /* Thermal Mgmt Temp 1 Transition # */ 1381 uint32_t hl_tmtemp_1_time; /* Time in Thermal Mgmt Temp 1 */ 1382 uint32_t hl_tmtemp_2_time; /* Time in Thermal Mgmt Temp 2 */ 1383 uint8_t hl_rsvd2[512 - 232]; 1384 } nvme_health_log_t; 1385 1386 /* 1387 * The NVMe spec allows for up to seven firmware slots. 1388 */ 1389 #define NVME_MAX_FWSLOTS 7 1390 1391 typedef struct { 1392 /* Active Firmware Slot */ 1393 uint8_t fw_afi:3; 1394 uint8_t fw_rsvd1:1; 1395 /* Next Active Firmware Slot */ 1396 uint8_t fw_next:3; 1397 uint8_t fw_rsvd2:1; 1398 uint8_t fw_rsvd3[7]; 1399 /* Firmware Revision / Slot */ 1400 char fw_frs[NVME_MAX_FWSLOTS][NVME_FWVER_SZ]; 1401 uint8_t fw_rsvd4[512 - 64]; 1402 } nvme_fwslot_log_t; 1403 1404 /* 1405 * The NVMe spec specifies that the changed namespace list contains up to 1406 * 1024 entries. 1407 */ 1408 #define NVME_NSCHANGE_LIST_SIZE 1024 1409 1410 typedef struct { 1411 uint32_t nscl_ns[NVME_NSCHANGE_LIST_SIZE]; 1412 } nvme_nschange_list_t; 1413 1414 /* 1415 * Commands Supported and Effects log page and information structure. This was 1416 * an optional log page added in NVMe 1.2. 1417 */ 1418 typedef struct { 1419 uint8_t cmd_csupp:1; /* Command supported */ 1420 uint8_t cmd_lbcc:1; /* Logical block content change */ 1421 uint8_t cmd_ncc:1; /* Namespace capability change */ 1422 uint8_t cmd_nic:1; /* Namespace inventory change */ 1423 uint8_t cmd_ccc:1; /* Controller capability change */ 1424 uint8_t cmd_rsvd0p5:3; 1425 uint8_t cmd_rsvd1; 1426 uint16_t cmd_cse:3; /* Command submission and execution */ 1427 uint16_t cmd_uuid:1; /* UUID select supported, 1.4 */ 1428 uint16_t cmd_csp:12; /* Command Scope, 2.0 */ 1429 } nvme_cmdeff_t; 1430 1431 CTASSERT(sizeof (nvme_cmdeff_t) == 4); 1432 1433 typedef enum { 1434 NVME_CMDEFF_CSP_NS = 1 << 0, 1435 NVME_CMDEFF_CSP_CTRL = 1 << 1, 1436 NVME_CMDEFF_CSP_SET = 1 << 2, 1437 NVME_CMDEFF_CSP_ENDURANCE = 1 << 3, 1438 NVME_CMDEFF_CSP_DOMAIN = 1 << 4, 1439 NVME_CMDEFF_CSP_NVM = 1 << 5 1440 } nvme_cmdeff_csp_t; 1441 1442 typedef enum { 1443 NVME_CMDEFF_CSE_NONE = 0, 1444 NVME_CMDEFF_CSE_NS, 1445 NVME_CMDEFF_CSE_CTRL 1446 } nvme_cmdeff_cse_t; 1447 1448 typedef struct { 1449 nvme_cmdeff_t cme_admin[256]; 1450 nvme_cmdeff_t cme_io[256]; 1451 uint8_t cme_rsvd2048[2048]; 1452 } nvme_cmdeff_log_t; 1453 1454 CTASSERT(sizeof (nvme_cmdeff_log_t) == 4096); 1455 CTASSERT(offsetof(nvme_cmdeff_log_t, cme_rsvd2048) == 2048); 1456 1457 /* 1458 * NVMe Format NVM 1459 */ 1460 #define NVME_FRMT_SES_NONE 0 1461 #define NVME_FRMT_SES_USER 1 1462 #define NVME_FRMT_SES_CRYPTO 2 1463 #define NVME_FRMT_MAX_SES 2 1464 1465 #define NVME_FRMT_MAX_LBAF 15 1466 1467 typedef union { 1468 struct { 1469 uint32_t fm_lbaf:4; /* LBA Format */ 1470 uint32_t fm_ms:1; /* Metadata Settings */ 1471 uint32_t fm_pi:3; /* Protection Information */ 1472 uint32_t fm_pil:1; /* Prot. Information Location */ 1473 uint32_t fm_ses:3; /* Secure Erase Settings */ 1474 uint32_t fm_resvd:20; 1475 } b; 1476 uint32_t r; 1477 } nvme_format_nvm_t; 1478 1479 1480 /* 1481 * NVMe Get / Set Features 1482 */ 1483 #define NVME_FEAT_ARBITRATION 0x1 /* Command Arbitration */ 1484 #define NVME_FEAT_POWER_MGMT 0x2 /* Power Management */ 1485 #define NVME_FEAT_LBA_RANGE 0x3 /* LBA Range Type */ 1486 #define NVME_FEAT_TEMPERATURE 0x4 /* Temperature Threshold */ 1487 #define NVME_FEAT_ERROR 0x5 /* Error Recovery */ 1488 #define NVME_FEAT_WRITE_CACHE 0x6 /* Volatile Write Cache */ 1489 #define NVME_FEAT_NQUEUES 0x7 /* Number of Queues */ 1490 #define NVME_FEAT_INTR_COAL 0x8 /* Interrupt Coalescing */ 1491 #define NVME_FEAT_INTR_VECT 0x9 /* Interrupt Vector Configuration */ 1492 #define NVME_FEAT_WRITE_ATOM 0xa /* Write Atomicity */ 1493 #define NVME_FEAT_ASYNC_EVENT 0xb /* Asynchronous Event Configuration */ 1494 #define NVME_FEAT_AUTO_PST 0xc /* Autonomous Power State Transition */ 1495 /* (1.1) */ 1496 1497 #define NVME_FEAT_PROGRESS 0x80 /* Software Progress Marker */ 1498 1499 /* 1500 * This enumeration represents the capabilities in the Get Features select / Set 1501 * Features save options. This was introduced in NVMe 1.1 and the values below 1502 * match the specification. An optional feature in the identify controller data 1503 * structure is set to indicate that this is supported (id_oncs.on_save). 1504 */ 1505 typedef enum { 1506 NVME_FEATURE_SEL_CURRENT = 0, 1507 NVME_FEATURE_SEL_DEFAULT, 1508 NVME_FEATURE_SEL_SAVED, 1509 NVME_FEATURE_SEL_SUPPORTED 1510 } nvme_feature_sel_t; 1511 1512 typedef union { 1513 struct { 1514 uint32_t gt_fid:8; /* Feature ID */ 1515 uint32_t gt_sel:3; /* Select */ 1516 uint32_t gt_rsvd:21; 1517 } b; 1518 uint32_t r; 1519 } nvme_get_features_dw10_t; 1520 1521 /* Arbitration Feature */ 1522 typedef union { 1523 struct { 1524 uint8_t arb_ab:3; /* Arbitration Burst */ 1525 uint8_t arb_rsvd:5; 1526 uint8_t arb_lpw; /* Low Priority Weight */ 1527 uint8_t arb_mpw; /* Medium Priority Weight */ 1528 uint8_t arb_hpw; /* High Priority Weight */ 1529 } b; 1530 uint32_t r; 1531 } nvme_arbitration_t; 1532 1533 /* Power Management Feature */ 1534 typedef union { 1535 struct { 1536 uint32_t pm_ps:5; /* Power State */ 1537 uint32_t pm_rsvd:27; 1538 } b; 1539 uint32_t r; 1540 } nvme_power_mgmt_t; 1541 1542 /* LBA Range Type Feature */ 1543 typedef union { 1544 struct { 1545 uint32_t lr_num:6; /* Number of LBA ranges */ 1546 uint32_t lr_rsvd:26; 1547 } b; 1548 uint32_t r; 1549 } nvme_lba_range_type_t; 1550 1551 typedef struct { 1552 uint8_t lr_type; /* Type */ 1553 struct { /* Attributes */ 1554 uint8_t lr_write:1; /* may be overwritten */ 1555 uint8_t lr_hidden:1; /* hidden from OS/EFI/BIOS */ 1556 uint8_t lr_rsvd1:6; 1557 } lr_attr; 1558 uint8_t lr_rsvd2[14]; 1559 uint64_t lr_slba; /* Starting LBA */ 1560 uint64_t lr_nlb; /* Number of Logical Blocks */ 1561 uint8_t lr_guid[16]; /* Unique Identifier */ 1562 uint8_t lr_rsvd3[16]; 1563 } nvme_lba_range_t; 1564 1565 #define NVME_LBA_RANGE_BUFSIZE 4096 1566 1567 /* Temperature Threshold Feature */ 1568 typedef union { 1569 struct { 1570 uint16_t tt_tmpth; /* Temperature Threshold */ 1571 uint16_t tt_tmpsel:4; /* Temperature Select */ 1572 uint16_t tt_thsel:2; /* Temperature Type */ 1573 uint16_t tt_resv:10; 1574 } b; 1575 uint32_t r; 1576 } nvme_temp_threshold_t; 1577 1578 #define NVME_TEMP_THRESH_MAX_SENSOR 8 1579 #define NVME_TEMP_THRESH_ALL 0xf 1580 #define NVME_TEMP_THRESH_OVER 0x00 1581 #define NVME_TEMP_THRESH_UNDER 0x01 1582 1583 /* Error Recovery Feature */ 1584 typedef union { 1585 struct { 1586 uint16_t er_tler; /* Time-Limited Error Recovery */ 1587 uint16_t er_rsvd; 1588 } b; 1589 uint32_t r; 1590 } nvme_error_recovery_t; 1591 1592 /* Volatile Write Cache Feature */ 1593 typedef union { 1594 struct { 1595 uint32_t wc_wce:1; /* Volatile Write Cache Enable */ 1596 uint32_t wc_rsvd:31; 1597 } b; 1598 uint32_t r; 1599 } nvme_write_cache_t; 1600 1601 /* Number of Queues Feature */ 1602 typedef union { 1603 struct { 1604 uint16_t nq_nsq; /* Number of Submission Queues */ 1605 uint16_t nq_ncq; /* Number of Completion Queues */ 1606 } b; 1607 uint32_t r; 1608 } nvme_nqueues_t; 1609 1610 /* Interrupt Coalescing Feature */ 1611 typedef union { 1612 struct { 1613 uint8_t ic_thr; /* Aggregation Threshold */ 1614 uint8_t ic_time; /* Aggregation Time */ 1615 uint16_t ic_rsvd; 1616 } b; 1617 uint32_t r; 1618 } nvme_intr_coal_t; 1619 1620 /* Interrupt Configuration Features */ 1621 typedef union { 1622 struct { 1623 uint16_t iv_iv; /* Interrupt Vector */ 1624 uint16_t iv_cd:1; /* Coalescing Disable */ 1625 uint16_t iv_rsvd:15; 1626 } b; 1627 uint32_t r; 1628 } nvme_intr_vect_t; 1629 1630 /* Write Atomicity Feature */ 1631 typedef union { 1632 struct { 1633 uint32_t wa_dn:1; /* Disable Normal */ 1634 uint32_t wa_rsvd:31; 1635 } b; 1636 uint32_t r; 1637 } nvme_write_atomicity_t; 1638 1639 /* Asynchronous Event Configuration Feature */ 1640 typedef union { 1641 struct { 1642 uint8_t aec_avail:1; /* Available space too low */ 1643 uint8_t aec_temp:1; /* Temperature too high */ 1644 uint8_t aec_reliab:1; /* Degraded reliability */ 1645 uint8_t aec_readonly:1; /* Media is read-only */ 1646 uint8_t aec_volatile:1; /* Volatile memory backup failed */ 1647 uint8_t aec_rsvd1:3; 1648 uint8_t aec_nsan:1; /* Namespace attribute notices (1.2) */ 1649 uint8_t aec_fwact:1; /* Firmware activation notices (1.2) */ 1650 uint8_t aec_telln:1; /* Telemetry log notices (1.3) */ 1651 uint8_t aec_ansacn:1; /* Asymm. NS access change (1.4) */ 1652 uint8_t aec_plat:1; /* Predictable latency ev. agg. (1.4) */ 1653 uint8_t aec_lbasi:1; /* LBA status information (1.4) */ 1654 uint8_t aec_egeal:1; /* Endurance group ev. agg. (1.4) */ 1655 uint8_t aec_rsvd2:1; 1656 uint8_t aec_rsvd3[2]; 1657 } b; 1658 uint32_t r; 1659 } nvme_async_event_conf_t; 1660 1661 /* Autonomous Power State Transition Feature (1.1) */ 1662 typedef union { 1663 struct { 1664 uint32_t apst_apste:1; /* APST enabled */ 1665 uint32_t apst_rsvd:31; 1666 } b; 1667 uint32_t r; 1668 } nvme_auto_power_state_trans_t; 1669 1670 typedef struct { 1671 uint32_t apst_rsvd1:3; 1672 uint32_t apst_itps:5; /* Idle Transition Power State */ 1673 uint32_t apst_itpt:24; /* Idle Time Prior to Transition */ 1674 uint32_t apst_rsvd2; 1675 } nvme_auto_power_state_t; 1676 1677 #define NVME_AUTO_PST_BUFSIZE 256 1678 1679 /* Software Progress Marker Feature */ 1680 typedef union { 1681 struct { 1682 uint8_t spm_pbslc; /* Pre-Boot Software Load Count */ 1683 uint8_t spm_rsvd[3]; 1684 } b; 1685 uint32_t r; 1686 } nvme_software_progress_marker_t; 1687 1688 /* 1689 * Firmware Commit - Command Dword 10 1690 */ 1691 #define NVME_FWC_SAVE 0x0 /* Save image only */ 1692 #define NVME_FWC_SAVE_ACTIVATE 0x1 /* Save and activate at next reset */ 1693 #define NVME_FWC_ACTIVATE 0x2 /* Activate slot at next reset */ 1694 #define NVME_FWC_ACTIVATE_IMMED 0x3 /* Activate slot immediately */ 1695 1696 /* 1697 * Firmware slot number is only 3 bits, and zero is not allowed. 1698 * Valid range is 1 to 7. 1699 */ 1700 #define NVME_FW_SLOT_MIN 1U /* lowest allowable slot number ... */ 1701 #define NVME_FW_SLOT_MAX 7U /* ... and highest */ 1702 1703 /* 1704 * Some constants to make verification of DWORD variables and arguments easier. 1705 * A DWORD is 4 bytes. 1706 */ 1707 #define NVME_DWORD_SHIFT 2 1708 #define NVME_DWORD_SIZE (1 << NVME_DWORD_SHIFT) 1709 #define NVME_DWORD_MASK (NVME_DWORD_SIZE - 1) 1710 1711 /* 1712 * Maximum offset a firmware image can be load at is the number of 1713 * DWORDS in a 32 bit field. Expressed in bytes its is: 1714 */ 1715 #define NVME_FW_OFFSETB_MAX ((u_longlong_t)UINT32_MAX << NVME_DWORD_SHIFT) 1716 1717 typedef union { 1718 struct { 1719 uint32_t fc_slot:3; /* Firmware slot */ 1720 uint32_t fc_action:3; /* Commit action */ 1721 uint32_t fc_rsvd:26; 1722 } b; 1723 uint32_t r; 1724 } nvme_firmware_commit_dw10_t; 1725 1726 #pragma pack() /* pack(1) */ 1727 1728 /* NVMe completion status code type */ 1729 #define NVME_CQE_SCT_GENERIC 0 /* Generic Command Status */ 1730 #define NVME_CQE_SCT_SPECIFIC 1 /* Command Specific Status */ 1731 #define NVME_CQE_SCT_INTEGRITY 2 /* Media and Data Integrity Errors */ 1732 #define NVME_CQE_SCT_PATH 3 /* Path Related Status (1.4) */ 1733 #define NVME_CQE_SCT_VENDOR 7 /* Vendor Specific */ 1734 1735 /* 1736 * Status code ranges 1737 */ 1738 #define NVME_CQE_SC_GEN_MIN 0x00 1739 #define NVME_CQE_SC_GEN_MAX 0x7f 1740 #define NVME_CQE_SC_CSI_MIN 0x80 1741 #define NVME_CQE_SC_CSI_MAX 0xbf 1742 #define NVME_CQE_SC_VEND_MIN 0xc0 1743 #define NVME_CQE_SC_VEND_MAX 0xff 1744 1745 /* NVMe completion status code (generic) */ 1746 #define NVME_CQE_SC_GEN_SUCCESS 0x0 /* Successful Completion */ 1747 #define NVME_CQE_SC_GEN_INV_OPC 0x1 /* Invalid Command Opcode */ 1748 #define NVME_CQE_SC_GEN_INV_FLD 0x2 /* Invalid Field in Command */ 1749 #define NVME_CQE_SC_GEN_ID_CNFL 0x3 /* Command ID Conflict */ 1750 #define NVME_CQE_SC_GEN_DATA_XFR_ERR 0x4 /* Data Transfer Error */ 1751 #define NVME_CQE_SC_GEN_ABORT_PWRLOSS 0x5 /* Cmds Aborted / Pwr Loss */ 1752 #define NVME_CQE_SC_GEN_INTERNAL_ERR 0x6 /* Internal Error */ 1753 #define NVME_CQE_SC_GEN_ABORT_REQUEST 0x7 /* Command Abort Requested */ 1754 #define NVME_CQE_SC_GEN_ABORT_SQ_DEL 0x8 /* Cmd Aborted / SQ deletion */ 1755 #define NVME_CQE_SC_GEN_ABORT_FUSE_FAIL 0x9 /* Cmd Aborted / Failed Fused */ 1756 #define NVME_CQE_SC_GEN_ABORT_FUSE_MISS 0xa /* Cmd Aborted / Missing Fusd */ 1757 #define NVME_CQE_SC_GEN_INV_NS 0xb /* Inval Namespace or Format */ 1758 #define NVME_CQE_SC_GEN_CMD_SEQ_ERR 0xc /* Command Sequence Error */ 1759 #define NVME_CQE_SC_GEN_INV_SGL_LAST 0xd /* Inval SGL Last Seg Desc */ 1760 #define NVME_CQE_SC_GEN_INV_SGL_NUM 0xe /* Inval Number of SGL Desc */ 1761 #define NVME_CQE_SC_GEN_INV_DSGL_LEN 0xf /* Data SGL Length Invalid */ 1762 #define NVME_CQE_SC_GEN_INV_MSGL_LEN 0x10 /* Metadata SGL Length Inval */ 1763 #define NVME_CQE_SC_GEN_INV_SGL_DESC 0x11 /* SGL Descriptor Type Inval */ 1764 /* Added in NVMe 1.2 */ 1765 #define NVME_CQE_SC_GEN_INV_USE_CMB 0x12 /* Inval use of Ctrl Mem Buf */ 1766 #define NVME_CQE_SC_GEN_INV_PRP_OFF 0x13 /* PRP Offset Invalid */ 1767 #define NVME_CQE_SC_GEN_AWU_EXCEEDED 0x14 /* Atomic Write Unit Exceeded */ 1768 #define NVME_CQE_SC_GEN_OP_DENIED 0x15 /* Operation Denied */ 1769 #define NVME_CQE_SC_GEN_INV_SGL_OFF 0x16 /* SGL Offset Invalid */ 1770 #define NVME_CQE_SC_GEN_INV_SGL_ST 0x17 /* SGL Sub type Invalid */ 1771 #define NVME_CQE_SC_GEN_INCON_HOSTID 0x18 /* Host ID Inconsistent fmt */ 1772 #define NVME_CQE_SC_GEN_KA_EXP 0x19 /* Keep Alive Timer Expired */ 1773 #define NVME_CQE_SC_GEN_INV_KA_TO 0x1a /* Keep Alive Timeout Invalid */ 1774 /* Added in NVMe 1.3 */ 1775 #define NVME_CQE_SC_GEN_ABORT_PREEMPT 0x1b /* Cmd aborted due to preempt */ 1776 #define NVME_CQE_SC_GEN_SANITIZE_FAIL 0x1c /* Sanitize Failed */ 1777 #define NVME_CQE_SC_GEN_SANITIZING 0x1d /* Sanitize in Progress */ 1778 #define NVME_CQE_SC_GEN_INV_SGL_GRAN 0x1e /* SGL Data Block Gran. Inval */ 1779 #define NVME_CQE_SC_GEN_NO_CMD_Q_CMD 0x1f /* Command not sup for CMB Q */ 1780 /* Added in NVMe 1.4 */ 1781 #define NVME_CQE_SC_GEN_NS_RDONLY 0x20 /* Namespace is write prot. */ 1782 #define NVME_CQE_SC_GEN_CMD_INTR 0x21 /* Command Interrupted */ 1783 #define NVME_CQE_SC_GEN_TRANSIENT 0x22 /* Transient Transport Error */ 1784 /* Added in NVMe 2.0 */ 1785 #define NVME_CQE_SC_GEN_CMD_LOCK 0x23 /* Command/Feature Lockdown */ 1786 #define NVME_CQE_SC_ADM_MEDIA_NR 0x24 /* Admin Cmd Media Not Ready */ 1787 1788 /* NVMe completion status code (generic NVM commands) */ 1789 #define NVME_CQE_SC_GEN_NVM_LBA_RANGE 0x80 /* LBA Out Of Range */ 1790 #define NVME_CQE_SC_GEN_NVM_CAP_EXC 0x81 /* Capacity Exceeded */ 1791 #define NVME_CQE_SC_GEN_NVM_NS_NOTRDY 0x82 /* Namespace Not Ready */ 1792 #define NVME_CQE_SC_GEN_NVM_RSV_CNFLCT 0x83 /* Reservation Conflict */ 1793 #define NVME_CQE_SC_GEN_NVM_FORMATTING 0x84 /* Format in progress (1.2) */ 1794 /* Added in NVMe 2.0 */ 1795 #define NVME_CQE_SC_GEN_KEY_INV_VAL 0x85 /* Invalid value size */ 1796 #define NVME_CQE_SC_GEN_KEY_INV_KEY 0x86 /* Invalid key size */ 1797 #define NVME_CQE_SC_GEN_KEY_ENOENT 0x87 /* KV Key Does Not Exist */ 1798 #define NVME_CQE_SC_GEN_KEY_UNRECOV 0x88 /* Unrecovered Error */ 1799 #define NVME_CQE_SC_GEN_KEY_EXISTS 0x89 /* Key already exists */ 1800 1801 /* NVMe completion status code (command specific) */ 1802 #define NVME_CQE_SC_SPC_INV_CQ 0x0 /* Completion Queue Invalid */ 1803 #define NVME_CQE_SC_SPC_INV_QID 0x1 /* Invalid Queue Identifier */ 1804 #define NVME_CQE_SC_SPC_MAX_QSZ_EXC 0x2 /* Max Queue Size Exceeded */ 1805 #define NVME_CQE_SC_SPC_ABRT_CMD_EXC 0x3 /* Abort Cmd Limit Exceeded */ 1806 #define NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC 0x5 /* Async Event Request Limit */ 1807 #define NVME_CQE_SC_SPC_INV_FW_SLOT 0x6 /* Invalid Firmware Slot */ 1808 #define NVME_CQE_SC_SPC_INV_FW_IMG 0x7 /* Invalid Firmware Image */ 1809 #define NVME_CQE_SC_SPC_INV_INT_VECT 0x8 /* Invalid Interrupt Vector */ 1810 #define NVME_CQE_SC_SPC_INV_LOG_PAGE 0x9 /* Invalid Log Page */ 1811 #define NVME_CQE_SC_SPC_INV_FORMAT 0xa /* Invalid Format */ 1812 #define NVME_CQE_SC_SPC_FW_RESET 0xb /* FW Application Reset Reqd */ 1813 #define NVME_CQE_SC_SPC_INV_Q_DEL 0xc /* Invalid Queue Deletion */ 1814 #define NVME_CQE_SC_SPC_FEAT_SAVE 0xd /* Feature Id Not Saveable */ 1815 #define NVME_CQE_SC_SPC_FEAT_CHG 0xe /* Feature Not Changeable */ 1816 #define NVME_CQE_SC_SPC_FEAT_NS_SPEC 0xf /* Feature Not Namespace Spec */ 1817 /* Added in NVMe 1.2 */ 1818 #define NVME_CQE_SC_SPC_FW_NSSR 0x10 /* FW Application NSSR Reqd */ 1819 #define NVME_CQE_SC_SPC_FW_NEXT_RESET 0x11 /* FW Application Next Reqd */ 1820 #define NVME_CQE_SC_SPC_FW_MTFA 0x12 /* FW Application Exceed MTFA */ 1821 #define NVME_CQE_SC_SPC_FW_PROHIBITED 0x13 /* FW Application Prohibited */ 1822 #define NVME_CQE_SC_SPC_FW_OVERLAP 0x14 /* Overlapping FW ranges */ 1823 #define NVME_CQE_SC_SPC_NS_INSUF_CAP 0x15 /* NS Insufficient Capacity */ 1824 #define NVME_CQE_SC_SPC_NS_NO_ID 0x16 /* NS ID Unavailable */ 1825 /* 0x17 is reserved */ 1826 #define NVME_CQE_SC_SPC_NS_ATTACHED 0x18 /* NS Already Attached */ 1827 #define NVME_CQE_SC_SPC_NS_PRIV 0x19 /* NS is private */ 1828 #define NVME_CQE_SC_SPC_NS_NOT_ATTACH 0x1a /* NS Not Attached */ 1829 #define NVME_CQE_SC_SPC_THIN_ENOTSUP 0x1b /* Thin Provisioning ENOTSUP */ 1830 #define NVME_CQE_SC_SPC_INV_CTRL_LIST 0x1c /* Controller list invalid */ 1831 /* Added in NVMe 1.3 */ 1832 #define NVME_CQE_SC_SPC_SELF_TESTING 0x1d /* Self-test in progress */ 1833 #define NVME_CQE_SC_SPC_NO_BP_WRITE 0x1e /* No Boot Partition Write */ 1834 #define NVME_CQE_SC_SPC_INV_CTRL_ID 0x1f /* Invalid Controller Id */ 1835 #define NVME_CQE_SC_SPC_INV_SEC_CTRL 0x20 /* Invalid Sec. Ctrl state */ 1836 #define NVME_CQE_SC_SPC_INV_CTRL_NRSRC 0x21 /* Inv. # Ctrl Resources */ 1837 #define NVME_CQE_SC_SPC_INV_RSRC_ID 0x22 /* Inv. Resource ID */ 1838 /* Added in NVMe 1.4 */ 1839 #define NVME_CQE_SC_SPC_NO_SAN_PMR 0x23 /* Sanitize prohib. w/ pmem */ 1840 #define NVME_CQE_SC_SPC_INV_ANA_GID 0x24 /* Invalid ANA group ID */ 1841 #define NVME_CQE_SC_SPC_ANA_ATTACH 0x25 /* ANA Attach Failed */ 1842 /* Added in NVMe 2.0 */ 1843 #define NVME_CQE_SC_SPC_INSUF_CAP 0x26 /* Insufficient Capacity */ 1844 #define NVME_CQE_SC_SPC_NS_ATTACH_LIM 0x27 /* NS Attach Limit Exceeded */ 1845 #define NVME_CQE_SC_SPC_LOCKDOWN_UNSUP 0x28 /* Prohib Cmd Exec Not Sup */ 1846 #define NVME_CQE_SC_SPC_UNSUP_IO_CMD 0x29 /* I/O Command set not sup */ 1847 #define NVME_CQE_SC_SPC_DIS_IO_CMD 0x2a /* I/O Command set not enab */ 1848 #define NVME_CQE_SC_SPC_INV_CMD_COMBO 0x2b /* I/O command set combo rej */ 1849 #define NVME_CQE_SC_SPC_INV_IO_CMD 0x2c /* Invalid I/O command set */ 1850 #define NVME_CQE_SC_SPC_UNAVAIL_ID 0x2d /* Unavailable ID */ 1851 1852 1853 /* NVMe completion status code (I/O command specific) */ 1854 #define NVME_CQE_SC_SPC_NVM_CNFL_ATTR 0x80 /* Conflicting Attributes */ 1855 #define NVME_CQE_SC_SPC_NVM_INV_PROT 0x81 /* Invalid Protection */ 1856 #define NVME_CQE_SC_SPC_NVM_READONLY 0x82 /* Write to Read Only Range */ 1857 /* Added in 2.0 */ 1858 #define NVME_CQE_SC_SPC_IO_LIMIT 0x83 /* Cmd Size Limit Exceeded */ 1859 /* 0x84 to 0xb7 are reserved */ 1860 #define NVME_CQE_SC_SPC_ZONE_BDRY_ERR 0xb8 /* Zoned Boundary Error */ 1861 #define NVME_CQE_SC_SPC_ZONE_FULL 0xb9 /* Zone is Full */ 1862 #define NVME_CQE_SC_SPC_ZONE_RDONLY 0xba /* Zone is Read Only */ 1863 #define NVME_CQE_SC_SPC_ZONE_OFFLINE 0xbb /* Zone is Offline */ 1864 #define NVME_CQE_SC_SPC_ZONE_INV_WRITE 0xbc /* Zone Invalid Write */ 1865 #define NVME_CQE_SC_SPC_ZONE_ACT 0xbd /* Too May Active Zones */ 1866 #define NVME_CQE_SC_SPC_ZONE_OPEN 0xbe /* Too May Open Zones */ 1867 #define NVME_CQE_SC_SPC_INV_ZONE_TRANS 0xbf /* Invalid Zone State Trans */ 1868 1869 /* NVMe completion status code (data / metadata integrity) */ 1870 #define NVME_CQE_SC_INT_NVM_WRITE 0x80 /* Write Fault */ 1871 #define NVME_CQE_SC_INT_NVM_READ 0x81 /* Unrecovered Read Error */ 1872 #define NVME_CQE_SC_INT_NVM_GUARD 0x82 /* Guard Check Error */ 1873 #define NVME_CQE_SC_INT_NVM_APPL_TAG 0x83 /* Application Tag Check Err */ 1874 #define NVME_CQE_SC_INT_NVM_REF_TAG 0x84 /* Reference Tag Check Err */ 1875 #define NVME_CQE_SC_INT_NVM_COMPARE 0x85 /* Compare Failure */ 1876 #define NVME_CQE_SC_INT_NVM_ACCESS 0x86 /* Access Denied */ 1877 /* Added in 1.2 */ 1878 #define NVME_CQE_SC_INT_NVM_DEALLOC 0x87 /* Dealloc Log Block */ 1879 /* Added in 2.0 */ 1880 #define NVME_CQE_SC_INT_NVM_TAG 0x88 /* End-to-End Storage Tag Err */ 1881 1882 /* NVMe completion status code (path related) */ 1883 /* Added in NVMe 1.4 */ 1884 #define NVME_CQE_SC_PATH_INT_ERR 0x00 /* Internal Path Error */ 1885 #define NVME_CQE_SC_PATH_AA_PLOSS 0x01 /* Asym Access Pers Loss */ 1886 #define NVME_CQE_SC_PATH_AA_INACC 0x02 /* Asym Access Inaccessible */ 1887 #define NVME_CQE_SC_PATH_AA_TRANS 0x03 /* Asym Access Transition */ 1888 #define NVME_CQE_SC_PATH_CTRL_ERR 0x60 /* Controller Path Error */ 1889 #define NVME_CQE_SC_PATH_HOST_ERR 0x70 /* Host Path Error */ 1890 #define NVME_CQE_SC_PATH_HOST_ABRT 0x71 /* Cmd aborted by host */ 1891 1892 /* 1893 * Controller information (NVME_IOC_CTRL_INFO). This is a consolidation of misc. 1894 * information that we want to know about a controller. 1895 */ 1896 typedef struct { 1897 nvme_ioctl_common_t nci_common; 1898 nvme_identify_ctrl_t nci_ctrl_id; 1899 nvme_identify_nsid_t nci_common_ns; 1900 nvme_version_t nci_vers; 1901 nvme_capabilities_t nci_caps; 1902 uint32_t nci_nintrs; 1903 } nvme_ioctl_ctrl_info_t; 1904 1905 /* 1906 * NVME namespace state flags. 1907 * 1908 * The values are defined entirely by the driver. Some states correspond to 1909 * namespace states described by the NVMe specification r1.3 section 6.1, others 1910 * are specific to the implementation of this driver. These are present in the 1911 * nvme_ns_kinfo_t that is used with the NVME_IOC_NS_INFO ioctl. 1912 * 1913 * The states are as follows: 1914 * - ALLOCATED: the namespace exists in the controller as per the NVMe spec 1915 * - ACTIVE: the namespace exists and is attached to this controller as per the 1916 * NVMe spec. Any namespace that is ACTIVE is also ALLOCATED. This must not be 1917 * confused with the ATTACHED state. 1918 * - ATTACHED: the driver has attached a blkdev(4D) instance to this namespace. 1919 * This state can be changed by userspace with the ioctls NVME_IOC_ATTACH and 1920 * NVME_IOC_DETACH. A namespace can only be ATTACHED when it is not IGNORED. 1921 * - IGNORED: the driver ignores this namespace, it never attaches a blkdev(4D). 1922 * Namespaces are IGNORED when they are not ACTIVE, or if they are ACTIVE but 1923 * have certain properties that the driver cannot handle. 1924 */ 1925 typedef enum { 1926 NVME_NS_STATE_ALLOCATED = 1 << 0, 1927 NVME_NS_STATE_ACTIVE = 1 << 1, 1928 NVME_NS_STATE_ATTACHED = 1 << 2, 1929 NVME_NS_STATE_IGNORED = 1 << 3 1930 } nvme_ns_state_t; 1931 1932 /* 1933 * This is the maximum length of the NVMe namespace's blkdev address. This is 1934 * only valid in the structure with the NVME_NS_STATE_ATTACHED flag is set. 1935 * Otherwise the entry will be all zeros. This is useful when you need to 1936 * determine what the corresponding blkdev instance in libdevinfo for the 1937 * device. 1938 */ 1939 #define NVME_BLKDEV_NAMELEN 128 1940 1941 /* 1942 * Namespace Information (NVME_IOC_NS_INFO). 1943 */ 1944 typedef struct { 1945 nvme_ioctl_common_t nni_common; 1946 nvme_ns_state_t nni_state; 1947 char nni_addr[NVME_BLKDEV_NAMELEN]; 1948 nvme_identify_nsid_t nni_id; 1949 } nvme_ioctl_ns_info_t; 1950 1951 /* 1952 * NVMe Command Set Identifiers. This was added in NVMe 2.0, but in all the 1953 * places it was required to be specified, the default value of 0 indicates the 1954 * traditional NVM command set. 1955 */ 1956 typedef enum { 1957 NVME_CSI_NVM = 0, 1958 NVME_CSI_KV, 1959 NVME_CSI_ZNS 1960 } nvme_csi_t; 1961 1962 #ifdef __cplusplus 1963 } 1964 #endif 1965 1966 #endif /* _SYS_NVME_H */ 1967