1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_IB_ADAPTERS_HERMON_HW_H 28 #define _SYS_IB_ADAPTERS_HERMON_HW_H 29 30 /* 31 * hermon_hw.h 32 * Contains all the structure definitions and #defines for all Hermon 33 * hardware resources and registers (as defined by the Hermon register 34 * specification). Wherever possible, the names in the Hermon spec 35 * have been preserved in the structure and field names below. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/conf.h> 40 #include <sys/ddi.h> 41 #include <sys/sunddi.h> 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 48 /* 49 * PCI IDs for supported chipsets 50 */ 51 #define PCI_VENID_MLX 0x15b3 52 #define PCI_DEVID_HERMON_SDR 0x6340 /* Mellanox MT25208-SDR PCIe Gen1 */ 53 #define PCI_DEVID_HERMON_DDR 0x634A /* Mellanox MT25208-DDR PCIe Gen1 */ 54 #define PCI_DEVID_HERMON_DDRG2 0x6732 /* Mellanox MT25208-DDR PCIe Gen2 */ 55 #define PCI_DEVID_HERMON_QDRG2 0x673C /* Mellanox MT25208-QDR PCIe Gen2 */ 56 #define PCI_DEVID_HERMON_MAINT 0x0191 /* Maintenance/Mem Controller Mode */ 57 58 /* 59 * Native page size of the adapter 60 */ 61 #define HERMON_PAGESIZE 0x1000 /* 4Kb */ 62 #define HERMON_PAGEMASK (HERMON_PAGESIZE - 1) 63 #define HERMON_PAGESHIFT 0xC /* 12 */ 64 65 /* 66 * MACROS to make some page stuff easier 67 */ 68 69 /* given a value, return a value that's the next higher power of 2 */ 70 #define HERMON_POW2(x) (1 << highbit(x)) 71 /* 72 * given a size in bytes, return the minimum number of 73 * *HCA PAGES* needed to hold it 74 */ 75 #define HERMON_HCA_PAGES(x) \ 76 (((x + HERMON_PAGESIZE) & HERMON_PAGEMASK) >> HERMON_PAGESHIFT) 77 78 /* 79 * given a size in bytes, return the power of two number of 80 * *HCA PAGES* needed to hold it 81 */ 82 #define HERMON_HCA_POW2_PAGES(x) (HERMON_POW2(HERMON_HCA_PAGES(x))) 83 /* 84 * Offsets into the CMD BAR (BAR 0) for many of the more interesting hardware 85 * registers. These registers include the HCR (more below), and the software 86 * reset register (SW_RESET). 87 */ 88 #define HERMON_CMD_HCR_OFFSET 0x80680 /* PRM */ 89 #define HERMON_CMD_SW_RESET_OFFSET 0xF0010 /* PRM */ 90 #define HERMON_CMD_SW_SEMAPHORE_OFFSET 0xF03FC /* PRM */ 91 #define HERMON_CMD_OFFSET_MASK 0xFFFFF /* per MLX instruction */ 92 93 94 /* 95 * Ownership flags used to define hardware or software ownership for 96 * various Hermon resources 97 */ 98 #define HERMON_HW_OWNER 0x1 99 #define HERMON_SW_OWNER 0x0 100 101 /* 102 * Determines whether or not virtual-to-physical address translation is 103 * required. Several of the Hermon hardware structures can be optionally 104 * accessed by Hermon without going through the TPT address translation 105 * tables. 106 */ 107 #define HERMON_VA2PA_XLAT_ENABLED 0x1 108 #define HERMON_VA2PA_XLAT_DISABLED 0x0 109 110 /* 111 * HCA Command Register (HCR) 112 * The HCR command interface provides privileged access to the HCA in 113 * order to query, configure and modify HCA execution. It is the 114 * primary mechanism through which mailboxes may be posted to Hermon 115 * firmware. To use this interface software fills the HCR with pointers 116 * to input and output mailboxes. Some commands support immediate 117 * parameters, however, and for these commands the HCR will contain the 118 * input or output parameters. Command execution completion can be 119 * detected either by the software polling the HCR or by waiting for a 120 * command completion event. 121 */ 122 struct hermon_hw_hcr_s { 123 uint32_t in_param0; 124 uint32_t in_param1; 125 uint32_t input_modifier; 126 uint32_t out_param0; 127 uint32_t out_param1; 128 uint32_t token; 129 uint32_t cmd; 130 }; 131 #define HERMON_HCR_TOKEN_MASK 0xFFFF0000 132 #define HERMON_HCR_TOKEN_SHIFT 16 133 134 #define HERMON_HCR_CMD_STATUS_MASK 0xFF000000 135 #define HERMON_HCR_CMD_GO_MASK 0x00800000 136 #define HERMON_HCR_CMD_E_MASK 0x00400000 137 #define HERMON_HCR_CMD_T_MASK 0x00200000 138 #define HERMON_HCR_CMD_OPMOD_MASK 0x0000F000 139 #define HERMON_HCR_CMD_OPCODE_MASK 0x00000FFF 140 #define HERMON_HCR_CMD_STATUS_SHFT 24 141 #define HERMON_HCR_CMD_GO_SHFT 23 142 #define HERMON_HCR_CMD_E_SHFT 22 143 #define HERMON_HCR_CMD_T_SHFT 21 144 #define HERMON_HCR_CMD_OPMOD_SHFT 12 145 146 /* 147 * Arbel "QUERY_DEV_LIM" command - Hermon, "QUERY_DEV_CAP" - Same hex code 148 * same function as tavor/arbel QUERY_DEV_LIM, just renamed (whatever). 149 * The QUERY_DEV_LIM command returns the device limits and capabilities 150 * supported by the Hermon device. This command must be run before 151 * running the INIT_HCA command (below) in order to determine the maximum 152 * capabilities of the device and which optional features are supported. 153 */ 154 #ifdef _LITTLE_ENDIAN 155 struct hermon_hw_querydevlim_s { 156 uint32_t rsrv0[4]; 157 158 uint32_t log_max_scqs :4; 159 uint32_t :4; 160 uint32_t num_rsvd_scqs :6; 161 uint32_t :2; 162 uint32_t log_max_srq :5; 163 uint32_t :7; 164 uint32_t log_rsvd_srq :4; 165 166 uint32_t log_max_qp :5; 167 uint32_t :3; 168 uint32_t log_rsvd_qp :4; 169 uint32_t :4; 170 uint32_t log_max_qp_sz :8; 171 uint32_t log_max_srq_sz :8; 172 173 uint32_t log_max_eq :4; 174 uint32_t :4; 175 uint32_t num_rsvd_eq :4; 176 uint32_t :4; 177 uint32_t log_max_dmpt :6; 178 uint32_t :2; 179 uint32_t log_max_eq_sz :8; 180 181 uint32_t log_max_cq :5; 182 uint32_t :3; 183 uint32_t log_rsvd_cq :4; 184 uint32_t :4; 185 uint32_t log_max_cq_sz :8; 186 uint32_t :8; 187 188 189 uint32_t :32; 190 191 uint32_t log_max_mtt :6; 192 uint32_t :2; 193 uint32_t log_rsvd_dmpt :4; 194 uint32_t :4; 195 uint32_t log_max_mrw_sz :8; 196 uint32_t :4; 197 uint32_t log_rsvd_mtt :4; 198 199 uint32_t log_max_ra_glob :6; 200 uint32_t :2; 201 uint32_t log_max_rss_tbl_sz :4; 202 uint32_t rss_toep :1; /* rss toeplitz hashing */ 203 uint32_t rss_xor :1; /* rss xor hashing */ 204 uint32_t :2; 205 uint32_t log_max_gso_sz :5; /* Lge Send Offload */ 206 uint32_t :11; /* new w/ 0.35, RSS info */ 207 208 uint32_t log_max_ra_res_qp :6; 209 uint32_t :10; 210 uint32_t log_max_ra_req_qp :6; 211 uint32_t :10; 212 213 uint32_t num_ports :4; 214 uint32_t :12; 215 uint32_t ca_ack_delay :5; 216 uint32_t :11; 217 218 uint32_t mod_wr_srq :1; 219 uint32_t :31; 220 221 uint32_t :4; 222 uint32_t :12; 223 uint32_t stat_rate_sup :16; 224 225 uint32_t :4; 226 uint32_t :12; 227 uint32_t :8; 228 uint32_t log_max_msg :5; 229 uint32_t :3; 230 231 uint32_t rc :1; 232 uint32_t uc :1; 233 uint32_t ud :1; 234 uint32_t xrc :1; 235 uint32_t rcm :1; 236 uint32_t fcoib :1; 237 uint32_t srq :1; 238 uint32_t ipoib_cksm :1; 239 uint32_t pkey_v :1; 240 uint32_t qkey_v :1; 241 uint32_t vmm :1; 242 uint32_t :5; 243 uint32_t mem_win :1; 244 uint32_t apm :1; 245 uint32_t atomic :1; 246 uint32_t raw_multi :1; 247 uint32_t avp :1; 248 uint32_t ud_multi :1; 249 uint32_t :2; 250 uint32_t pg_on_demand :1; 251 uint32_t router :1; 252 uint32_t :6; 253 254 uint32_t :32; 255 256 uint32_t log_max_bf_page :6; 257 uint32_t :2; 258 uint32_t log_max_bf_req_ppg :6; 259 uint32_t :2; 260 uint32_t log_bf_reg_sz :5; 261 uint32_t :10; 262 uint32_t blu_flm :1; 263 264 uint32_t log_pg_sz :8; 265 uint32_t :8; 266 uint32_t log_max_uar_sz :6; 267 uint32_t :6; 268 uint32_t num_rsvd_uar :4; 269 270 uint32_t max_desc_sz_rq :16; 271 uint32_t max_sg_rq :8; 272 uint32_t :8; 273 274 uint32_t max_desc_sz_sq :16; 275 uint32_t max_sg_sq :8; 276 uint32_t :8; 277 278 uint32_t rsvd_fcoib[2]; 279 280 uint32_t log_max_srcd :4; 281 uint32_t :8; 282 uint32_t num_rsvd_srcds :4; 283 uint32_t log_max_pd :5; 284 uint32_t :7; 285 uint32_t num_rsvd_pd :4; 286 287 uint32_t log_max_mcg :8; 288 uint32_t num_rsvd_mcg :4; 289 uint32_t :4; 290 uint32_t log_max_qp_mcg :8; 291 uint32_t :8; 292 293 uint32_t rsrv2[6]; 294 295 uint32_t altc_entry_sz :16; 296 uint32_t aux_entry_sz :16; 297 298 uint32_t qpc_entry_sz :16; 299 uint32_t rdmardc_entry_sz :16; 300 301 uint32_t cmpt_entry_sz :16; 302 uint32_t srq_entry_sz :16; 303 304 uint32_t cqc_entry_sz :16; 305 uint32_t eqc_entry_sz :16; 306 307 uint32_t bmme :1; 308 uint32_t win_type :1; 309 uint32_t mps :1; 310 uint32_t bl :1; 311 uint32_t zb :1; 312 uint32_t lif :1; 313 uint32_t local_inv :1; 314 uint32_t remote_inv :1; 315 uint32_t :1; 316 uint32_t win_type2 :1; 317 uint32_t reserved_lkey :1; 318 uint32_t fast_reg_wr :1; 319 uint32_t :20; 320 321 uint32_t dmpt_entry_sz :16; 322 uint32_t mtt_entry_sz :16; 323 324 uint32_t :32; 325 326 uint32_t rsv_lkey; 327 328 uint64_t max_icm_size; 329 330 uint32_t rsrv3[22]; 331 }; 332 333 #else /* BIG ENDIAN */ 334 335 struct hermon_hw_querydevlim_s { 336 uint32_t rsrv0[4]; 337 338 uint32_t log_max_srq_sz :8; 339 uint32_t log_max_qp_sz :8; 340 uint32_t :4; 341 uint32_t log_rsvd_qp :4; 342 uint32_t :3; 343 uint32_t log_max_qp :5; 344 345 uint32_t log_rsvd_srq :4; 346 uint32_t :7; 347 uint32_t log_max_srq :5; 348 uint32_t :2; 349 uint32_t num_rsvd_scqs :6; 350 uint32_t :4; 351 uint32_t log_max_scqs :4; 352 353 uint32_t :8; 354 uint32_t log_max_cq_sz :8; 355 uint32_t :4; 356 uint32_t log_rsvd_cq :4; 357 uint32_t :3; 358 uint32_t log_max_cq :5; 359 360 uint32_t log_max_eq_sz :8; 361 uint32_t :2; 362 uint32_t log_max_dmpt :6; 363 uint32_t :4; 364 uint32_t num_rsvd_eq :4; 365 uint32_t :4; 366 uint32_t log_max_eq :4; 367 368 uint32_t log_rsvd_mtt :4; 369 uint32_t :4; 370 uint32_t log_max_mrw_sz :8; 371 uint32_t :4; 372 uint32_t log_rsvd_dmpt :4; 373 uint32_t :2; 374 uint32_t log_max_mtt :6; 375 376 uint32_t :32; 377 378 uint32_t :10; 379 uint32_t log_max_ra_req_qp :6; 380 uint32_t :10; 381 uint32_t log_max_ra_res_qp :6; 382 383 uint32_t :11; /* new w/ 0.35, RSS info */ 384 uint32_t log_max_gso_sz :5; /* Lge Send Offload */ 385 uint32_t :2; 386 uint32_t rss_xor :1; /* rss xor hashing */ 387 uint32_t rss_toep :1; /* rss toeplitz hashing */ 388 uint32_t log_max_rss_tbl_sz :4; 389 uint32_t :2; 390 uint32_t log_max_ra_glob :6; 391 392 uint32_t :31; 393 uint32_t mod_wr_srq :1; 394 395 uint32_t :11; 396 uint32_t ca_ack_delay :5; 397 /* PRM 0.35, stuff moved to per port info */ 398 uint32_t :12; 399 uint32_t num_ports :4; 400 401 uint32_t :3; 402 uint32_t log_max_msg :5; 403 uint32_t :8; 404 uint32_t :12; 405 uint32_t :4; 406 407 uint32_t stat_rate_sup :16; 408 uint32_t :12; 409 uint32_t :4; 410 411 uint32_t :32; 412 413 uint32_t :6; 414 uint32_t router :1; 415 uint32_t pg_on_demand :1; 416 uint32_t :2; 417 uint32_t ud_multi :1; 418 uint32_t avp :1; 419 uint32_t raw_multi :1; 420 uint32_t atomic :1; 421 uint32_t apm :1; 422 uint32_t mem_win :1; 423 uint32_t :5; 424 uint32_t vmm :1; 425 uint32_t qkey_v :1; 426 uint32_t pkey_v :1; 427 uint32_t ipoib_cksm :1; 428 uint32_t srq :1; 429 uint32_t fcoib :1; 430 uint32_t rcm :1; 431 uint32_t xrc :1; 432 uint32_t ud :1; 433 uint32_t uc :1; 434 uint32_t rc :1; 435 436 uint32_t num_rsvd_uar :4; 437 uint32_t :6; 438 uint32_t log_max_uar_sz :6; 439 uint32_t :8; 440 uint32_t log_pg_sz :8; 441 442 uint32_t blu_flm :1; 443 uint32_t :10; 444 uint32_t log_bf_reg_sz :5; 445 uint32_t :2; 446 uint32_t log_max_bf_req_ppg :6; 447 uint32_t :2; 448 uint32_t log_max_bf_page :6; 449 450 uint32_t :8; 451 uint32_t max_sg_sq :8; 452 uint32_t max_desc_sz_sq :16; 453 454 uint32_t :8; 455 uint32_t max_sg_rq :8; 456 uint32_t max_desc_sz_rq :16; 457 458 uint32_t rsvd_fcoib[2]; 459 460 uint32_t :8; 461 uint32_t log_max_qp_mcg :8; 462 uint32_t :4; 463 uint32_t num_rsvd_mcg :4; 464 uint32_t log_max_mcg :8; 465 466 uint32_t num_rsvd_pd :4; 467 uint32_t :7; 468 uint32_t log_max_pd :5; 469 uint32_t num_rsvd_srcds :4; 470 uint32_t :8; 471 uint32_t log_max_srcd :4; 472 473 uint32_t rsrv2[6]; 474 475 uint32_t rdmardc_entry_sz :16; 476 uint32_t qpc_entry_sz :16; 477 478 uint32_t aux_entry_sz :16; 479 uint32_t altc_entry_sz :16; 480 481 uint32_t eqc_entry_sz :16; 482 uint32_t cqc_entry_sz :16; 483 484 uint32_t srq_entry_sz :16; 485 uint32_t cmpt_entry_sz :16; 486 487 uint32_t mtt_entry_sz :16; 488 uint32_t dmpt_entry_sz :16; 489 490 uint32_t :20; 491 uint32_t fast_reg_wr :1; 492 uint32_t reserved_lkey :1; 493 uint32_t win_type2 :1; 494 uint32_t :1; 495 uint32_t remote_inv :1; 496 uint32_t local_inv :1; 497 uint32_t lif :1; 498 uint32_t zb :1; 499 uint32_t bl :1; 500 uint32_t mps :1; 501 uint32_t win_type :1; 502 uint32_t bmme :1; 503 504 uint32_t rsv_lkey; 505 506 uint32_t :32; 507 508 uint64_t max_icm_size; 509 510 uint32_t rsrv3[22]; 511 }; 512 #endif 513 514 515 516 /* 517 * Hermon "QUERY_FW" command 518 * The QUERY_FW command retrieves the firmware revision and the Command 519 * Interface revision. The command also returns the HCA attached local 520 * memory area (DDR) which is used by the firmware. Below we also 521 * include some defines which are used to enforce a minimum firmware 522 * version check (see hermon_fw_version_check() for more details). 523 */ 524 525 #ifdef _LITTLE_ENDIAN 526 struct hermon_hw_queryfw_s { 527 uint32_t fw_rev_minor :16; 528 uint32_t fw_rev_subminor :16; 529 530 uint32_t fw_rev_major :16; 531 uint32_t fw_pages :16; 532 533 uint32_t log_max_cmd :8; 534 uint32_t :23; 535 uint32_t dbg_trace :1; 536 537 uint32_t cmd_intf_rev :16; 538 uint32_t :16; 539 540 uint32_t fw_day :8; 541 uint32_t fw_month :8; 542 uint32_t fw_year :16; 543 544 uint32_t :1; 545 uint32_t ccq :1; 546 uint32_t :6; 547 uint32_t fw_sec :8; 548 uint32_t fw_min :8; 549 uint32_t fw_hour :8; 550 551 uint32_t rsrv0[2]; 552 553 uint64_t clr_intr_offs; 554 555 uint32_t :32; 556 557 uint32_t :30; 558 uint32_t clr_int_bar :2; 559 560 uint64_t error_buf_addr; 561 562 uint32_t :30; 563 uint32_t err_buf_bar :2; 564 565 uint32_t error_buf_sz; 566 567 uint32_t rsrv2[48]; 568 }; 569 #else 570 struct hermon_hw_queryfw_s { 571 uint32_t fw_pages :16; 572 uint32_t fw_rev_major :16; 573 574 uint32_t fw_rev_subminor :16; 575 uint32_t fw_rev_minor :16; 576 577 uint32_t :16; 578 uint32_t cmd_intf_rev :16; 579 580 uint32_t dbg_trace :1; 581 uint32_t :23; 582 uint32_t log_max_cmd :8; 583 584 uint32_t fw_hour :8; 585 uint32_t fw_min :8; 586 uint32_t fw_sec :8; 587 uint32_t :6; 588 uint32_t ccq :1; 589 uint32_t :1; 590 591 uint32_t fw_year :16; 592 uint32_t fw_month :8; 593 uint32_t fw_day :8; 594 595 uint32_t rsrv1[2]; 596 597 uint64_t clr_intr_offs; 598 599 uint32_t clr_int_bar :2; 600 uint32_t :30; 601 602 uint32_t :32; 603 604 uint64_t error_buf_addr; 605 606 uint32_t error_buf_sz; 607 608 uint32_t err_buf_bar :2; 609 uint32_t :30; 610 611 uint32_t rsrv2[48]; 612 }; 613 #endif 614 615 /* 616 * need to have min 2.3.0 to include config_spec_qp and SMA in FW 617 */ 618 619 #define HERMON_FW_VER_MAJOR 0x0002 /* TBD for Hermon */ 620 #define HERMON_FW_VER_MINOR 0x0005 621 #define HERMON_FW_VER_SUBMINOR 0x0000 622 623 /* 624 * Hermon "QUERY_ADAPTER" command 625 * The QUERY_ADAPTER command retrieves adapter specific parameters. The 626 * command also retrieves the PCI(X) interrupt pin routing for each of 627 * the INTx# pins supported by the device. This information is used by 628 * the driver during interrupt processing in order to clear the appropriate 629 * interrupt bit. 630 */ 631 #ifdef _LITTLE_ENDIAN 632 struct hermon_hw_queryadapter_s { 633 uint32_t rsrv0[4]; 634 635 uint32_t :32; 636 637 uint32_t :24; 638 uint32_t inta_pin :8; 639 640 uint32_t vsd_vend_id :16; /* added v35 hermon */ 641 uint32_t :16; 642 643 uint32_t :32; 644 645 uint32_t vsd[52]; 646 uint32_t psid[4]; 647 }; 648 #else 649 struct hermon_hw_queryadapter_s { 650 uint32_t rsrv0[4]; 651 652 uint32_t inta_pin :8; 653 uint32_t :24; 654 655 uint32_t :32; 656 657 uint32_t :32; 658 659 uint32_t :16; 660 uint32_t vsd_vend_id :16; /* added v35 hermon */ 661 662 uint32_t vsd[52]; 663 uint32_t psid[4]; 664 }; 665 #endif 666 #define HERMON_REV_A0 0xA0 667 #define HERMON_REV_A1 0xA1 668 669 /* 670 * Virtual physical mapping structure for: MAP_FA, MAP_ICM_AUX, and 671 * MAP_ICM commands. 672 */ 673 674 #ifdef _LITTLE_ENDIAN 675 struct hermon_hw_vpm_s { 676 uint32_t :12; 677 uint32_t vaddr_l :20; 678 uint32_t vaddr_h; 679 680 uint32_t log2sz :5; 681 uint32_t :7; 682 uint32_t paddr_l :20; 683 uint32_t paddr_h; 684 }; 685 #else 686 struct hermon_hw_vpm_s { 687 uint32_t vaddr_h; 688 uint32_t vaddr_l :20; 689 uint32_t :12; 690 691 uint32_t paddr_h; 692 uint32_t paddr_l :20; 693 uint32_t :7; 694 uint32_t log2sz :5; 695 }; 696 #endif 697 698 699 700 701 /* 702 * Hermon "INIT_HCA" and "QUERY_HCA" commands 703 * The INIT_HCA command configures all HCA resources in HCA attached local 704 * memory and some system relevant information. The same mailbox output 705 * format is used by the QUERY_HCA command. All parameters, which are 706 * specifically the output of the QUERY_HCA command are marked as 707 * "QUERY_HCA only". These parameters are not configurable through the 708 * INIT_HCA command, but can be retrieved as read-only through the 709 * QUERY_HCA command. 710 * 711 * Below we first define several structures which help make up the whole 712 * of the INIT_HCA/QUERY_HCA command. These are: 713 * hermon_hw_qp_ee_cq_eq_rdb_t for "QPC/EEC/CQC/EQC/RDB Parameters", 714 * hermon_udav_mem_param_t for "Memory Access Parameters for UDAV Table", 715 * hermon_multicast_param_t for "Multicast Support Parameters", 716 * hermon_tpt_param_t for "Translation and Protection Table Parameters", 717 * and hermon_uar_param_t for Hermon "UAR Parameters". 718 */ 719 720 /* 721 * need to consider removing any ref to "ee", hermon doesn't support 722 * ee/rd stuff, and they've taken away the pretense 723 */ 724 725 726 #ifdef _LITTLE_ENDIAN 727 typedef struct hermon_hw_qp_ee_cq_eq_rdb_s { 728 uint32_t rsrv0[4]; 729 730 uint32_t log_num_qp :5; 731 uint32_t qpc_baseaddr_l :27; 732 uint32_t qpc_baseaddr_h; 733 734 uint32_t rsrv1[4]; 735 736 uint32_t log_num_srq :5; 737 uint32_t srqc_baseaddr_l :27; 738 uint32_t srqc_baseaddr_h; 739 740 uint32_t log_num_cq :5; 741 uint32_t cqc_baseaddr_l :27; 742 uint32_t cqc_baseaddr_h; 743 744 uint32_t rsrv2[2]; 745 746 uint64_t altc_baseaddr; 747 748 uint32_t rsrv3[2]; 749 750 uint64_t auxc_baseaddr; 751 752 uint32_t rsrv4[2]; 753 754 uint32_t log_num_eq :5; 755 uint32_t eqc_baseaddr_l :27; 756 uint32_t eqc_baseaddr_h; 757 758 uint32_t rsv5[2]; 759 760 uint32_t log_num_rdmardc :3; 761 uint32_t :2; 762 uint32_t rdmardc_baseaddr_l :27; 763 uint32_t rdmardc_baseaddr_h; 764 765 uint32_t rsrv6[2]; 766 } hermon_hw_qp_ee_cq_eq_rdb_t; 767 #else 768 typedef struct hermon_hw_qp_ee_cq_eq_rdb_s { 769 uint32_t rsrv0[4]; 770 771 uint32_t qpc_baseaddr_h; 772 uint32_t qpc_baseaddr_l :27; 773 uint32_t log_num_qp :5; 774 775 uint32_t rsrv1[4]; 776 777 uint32_t srqc_baseaddr_h; 778 uint32_t srqc_baseaddr_l :27; 779 uint32_t log_num_srq :5; 780 781 uint32_t cqc_baseaddr_h; 782 uint32_t cqc_baseaddr_l :27; 783 uint32_t log_num_cq :5; 784 785 uint32_t rsrv2[2]; 786 787 uint64_t altc_baseaddr; 788 789 uint32_t rsrv3[2]; 790 791 uint64_t auxc_baseaddr; 792 793 uint32_t rsrv4[2]; 794 795 uint32_t eqc_baseaddr_h; 796 uint32_t eqc_baseaddr_l :27; 797 uint32_t log_num_eq :5; 798 799 uint32_t rsv5[2]; 800 801 uint32_t rdmardc_baseaddr_h; 802 uint32_t rdmardc_baseaddr_l :27; 803 uint32_t :2; 804 uint32_t log_num_rdmardc :3; 805 806 uint32_t rsrv6[2]; 807 } hermon_hw_qp_ee_cq_eq_rdb_t; 808 #endif 809 810 811 812 813 #ifdef _LITTLE_ENDIAN 814 typedef struct hermon_multicast_param_s { 815 uint64_t mc_baseaddr; 816 817 uint32_t rsrv0[2]; 818 819 uint32_t log_mc_tbl_hash_sz :5; 820 uint32_t :27; 821 822 uint32_t log_mc_tbl_ent :5; 823 uint32_t :27; 824 825 uint32_t :32; 826 827 uint32_t log_mc_tbl_sz :5; 828 uint32_t :19; 829 uint32_t mc_hash_fn :3; 830 uint32_t :5; 831 } hermon_multicast_param_t; 832 #else 833 typedef struct hermon_multicast_param_s { 834 uint64_t mc_baseaddr; 835 836 uint32_t rsrv0[2]; 837 838 uint32_t :27; 839 uint32_t log_mc_tbl_ent :5; 840 841 uint32_t :27; 842 uint32_t log_mc_tbl_hash_sz :5; 843 844 uint32_t :5; 845 uint32_t mc_hash_fn :3; 846 uint32_t :19; 847 uint32_t log_mc_tbl_sz :5; 848 849 uint32_t :32; 850 } hermon_multicast_param_t; 851 #endif 852 853 #define HERMON_MCG_DEFAULT_HASH_FN 0x0 854 855 #ifdef _LITTLE_ENDIAN 856 typedef struct hermon_tpt_param_s { 857 uint64_t dmpt_baseaddr; 858 859 uint32_t :32; 860 uint32_t log_dmpt_sz :6; 861 uint32_t :2; 862 uint32_t pgfault_rnr_to :5; 863 uint32_t :19; 864 865 uint64_t mtt_baseaddr; 866 867 uint64_t cmpt_baseaddr; 868 } hermon_tpt_param_t; 869 #else 870 typedef struct hermon_tpt_param_s { 871 uint64_t dmpt_baseaddr; 872 873 uint32_t :19; 874 uint32_t pgfault_rnr_to :5; 875 uint32_t :2; 876 uint32_t log_dmpt_sz :6; 877 uint32_t :32; 878 879 uint64_t mtt_baseaddr; 880 881 uint64_t cmpt_baseaddr; 882 } hermon_tpt_param_t; 883 #endif 884 885 886 #ifdef _LITTLE_ENDIAN 887 typedef struct hermon_uar_param_s { 888 uint32_t rsvd0[2]; 889 890 uint32_t :32; 891 892 uint32_t uar_pg_sz :8; 893 uint32_t log_max_uars :4; 894 uint32_t :20; 895 896 uint32_t resvd1[4]; 897 } hermon_uar_param_t; 898 #else 899 typedef struct hermon_uar_param_s { 900 uint32_t rsvd0[2]; 901 902 uint32_t :20; 903 uint32_t log_max_uars :4; 904 uint32_t uar_pg_sz :8; 905 906 uint32_t :32; 907 908 uint32_t resvd1[4]; 909 } hermon_uar_param_t; 910 #endif 911 912 /* 913 * NEW for Hermon 914 * QP Allocation Params 915 * 916 */ 917 918 #ifdef _LITTLE_ENDIAN 919 typedef struct hermon_qp_alloc_param_s { 920 uint32_t :32; 921 922 uint32_t ccq_base :24; 923 uint32_t log2ccqs :5; 924 uint32_t :2; 925 uint32_t ccq_en :1; 926 927 uint32_t rsvd[6]; /* but 0x14 def'd for fibre channel */ 928 } hermon_qp_alloc_param_t; 929 #else /* BIG ENDIAN */ 930 typedef struct hermon_qp_alloc_param_s { 931 uint32_t ccq_en :1; 932 uint32_t :2; 933 uint32_t log2ccqs :5; 934 uint32_t ccq_base :24; 935 936 uint32_t :32; 937 938 uint32_t rsvd[6]; /* but 0x14 def'd for fibre channel */ 939 } hermon_qp_alloc_param_t; 940 #endif 941 942 #ifdef _LITTLE_ENDIAN 943 struct hermon_hw_initqueryhca_s { 944 uint32_t :32; 945 946 uint32_t :24; 947 uint32_t version :8; 948 949 uint32_t :13; 950 uint32_t log2_cacheline :3; 951 uint32_t hca_core_clock :16; /* QUERY_HCA only */ 952 953 uint32_t :32; 954 955 uint32_t udav_port_chk :1; 956 uint32_t big_endian :1; 957 uint32_t :1; 958 uint32_t chsum_en :1; 959 uint32_t :28; 960 961 uint32_t router_qp :24; 962 uint32_t :5; 963 uint32_t ipr2 :1; 964 uint32_t ipr1 :1; 965 uint32_t router_en :1; 966 967 uint32_t rsrv1[2]; 968 969 hermon_hw_qp_ee_cq_eq_rdb_t context; 970 971 uint32_t rsrv2[8]; 972 973 hermon_multicast_param_t multi; 974 975 uint32_t rsrv3[4]; 976 977 hermon_tpt_param_t tpt; 978 979 uint32_t rsrv4[4]; 980 981 hermon_uar_param_t uar; 982 983 uint32_t rsrv5[4]; 984 985 hermon_qp_alloc_param_t qp_alloc; 986 987 uint32_t rsrv6[100]; /* from 0x16c to 0x2fc offsets */ 988 }; 989 #else /* BIG ENDIAN */ 990 struct hermon_hw_initqueryhca_s { 991 uint32_t version :8; 992 uint32_t :24; 993 994 uint32_t :32; 995 996 uint32_t :32; 997 998 uint32_t hca_core_clock :16; /* QUERY_HCA only */ 999 uint32_t log2_cacheline :3; 1000 uint32_t :13; 1001 1002 uint32_t router_en :1; 1003 uint32_t ipr1 :1; 1004 uint32_t ipr2 :1; 1005 uint32_t :5; 1006 uint32_t router_qp :24; 1007 1008 uint32_t :28; 1009 uint32_t chsum_en :1; 1010 uint32_t :1; 1011 uint32_t big_endian :1; 1012 uint32_t udav_port_chk :1; 1013 1014 uint32_t rsrv1[2]; 1015 1016 hermon_hw_qp_ee_cq_eq_rdb_t context; 1017 1018 uint32_t rsrv2[8]; 1019 1020 hermon_multicast_param_t multi; 1021 1022 uint32_t rsrv3[4]; 1023 1024 hermon_tpt_param_t tpt; 1025 1026 uint32_t rsrv4[4]; 1027 1028 hermon_uar_param_t uar; 1029 1030 uint32_t rsrv5[4]; 1031 1032 hermon_qp_alloc_param_t qp_alloc; 1033 1034 uint32_t rsrv6[100]; /* from 0x16c to 0x2fc offsets */ 1035 }; 1036 #endif 1037 #define HERMON_UDAV_PROTECT_DISABLED 0x0 1038 #define HERMON_UDAV_PROTECT_ENABLED 0x1 1039 #define HERMON_UDAV_PORTCHK_DISABLED 0x0 1040 #define HERMON_UDAV_PORTCHK_ENABLED 0x1 1041 1042 1043 /* 1044 * Hermon "INIT_IB"/"INIT_PORT" command 1045 * The INIT_IB/INIT_PORT command enables the physical layer of an IB port. 1046 * It provides control over the IB port attributes. The capabilities 1047 * requested here should not exceed the device limits, as retrieved by 1048 * the QUERY_DEV_LIM/CAP command (above). To query information about the IB 1049 * port or node, the driver may submit GetPortInfo or GetNodeInfo MADs 1050 * through the Hermon MAD_IFC command. 1051 * 1052 * Changed name to initport, but operates similar to initib - but as of 1053 * PRM v0.35c the initport just does that, and the params set previously 1054 * by initib are now set in SET_PORT 1055 */ 1056 1057 1058 1059 1060 /* 1061 * HERMON query_port and set_port commands. QUERY_PORT is new for hermon, 1062 * doing some of what used to be done in the QUERY_DEV_CAP command. It is 1063 * introduced in PRM v0.35 and will need to be added to the list of 1064 * supported HCA commands 1065 * 1066 * SET_PORT is similar to the SET_IB command from tavor and arbel. Here, 1067 * tho, it's more extensive and will be easier to deal with I suspect by 1068 * making it a structure and filling it in and then doing the copy to the 1069 * mailbox (instead of just writing the minimal information to the mailbox 1070 * directly as was done for the previous HCAs). 1071 */ 1072 1073 #ifdef _LITTLE_ENDIAN 1074 struct hermon_hw_query_port_s { 1075 uint32_t log_max_pkey :4; /* pkey table size */ 1076 uint32_t log_max_gid :4; /* max gids / port */ 1077 /* was max_port_width arbel: long list of values */ 1078 uint32_t ib_port_wid :4; 1079 uint32_t :4; 1080 uint32_t :4; /* other types possibly */ 1081 uint32_t :4; 1082 /* 1083 * 0x1=2.5G, 0x3=2.5 or 5.0G, 0x5=2.5 or 10G 1084 * 0x7=2.5, 5.0, or 10G, others rsvd 1085 */ 1086 uint32_t ib_link_spd :4; 1087 1088 uint32_t :4; 1089 1090 uint32_t :16; /* used for other types (?) */ 1091 uint32_t ib_mtu :4; 1092 /* 1093 * 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 1094 * 0x5=4096, others rsvd 1095 */ 1096 uint32_t :4; 1097 uint32_t port_type :8; /* 0x00, 0x01 IB, others TBD */ 1098 1099 uint32_t :32; 1100 /* max vl's supported (not incl vl_15) */ 1101 uint32_t max_vl :4; 1102 uint32_t :4; 1103 uint32_t :8; /* but others possibly */ 1104 uint32_t :16; 1105 1106 uint32_t rsvd0[2]; /* but for other types */ 1107 uint32_t rsvd1[504]; 1108 }; 1109 #else /* BIG ENDIAN */ 1110 struct hermon_hw_query_port_s { 1111 uint32_t port_type :8; /* 0x00, 0x01 IB, others TBD */ 1112 uint32_t :4; 1113 /* 1114 * 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 1115 * 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 1116 */ 1117 uint32_t ib_mtu :4; 1118 /* 0x5=4096, others rsvd */ 1119 uint32_t :16; /* used for other types (?) */ 1120 1121 uint32_t :4; 1122 uint32_t ib_link_spd :4; 1123 /* 1124 * 0x1=2.5G, 0x3=2.5 or 5.0G, 0x5=2.5 or 10G 1125 * 0x7=2.5, 5.0, or 10G, others rsvd 1126 */ 1127 uint32_t :4; 1128 uint32_t :4; /* other types possibly */ 1129 uint32_t :4; 1130 /* was max_port_width arbel: long list of values */ 1131 uint32_t ib_port_wid :4; 1132 uint32_t log_max_gid :4; /* max gids / port */ 1133 uint32_t log_max_pkey :4; /* pkey table size */ 1134 1135 uint32_t :16; 1136 uint32_t :8; /* but others possibly */ 1137 uint32_t :4; 1138 /* max vl's supported (not incl vl_15) */ 1139 uint32_t max_vl :4; 1140 1141 uint32_t :32; 1142 1143 uint32_t rsvd0[2]; /* but for other types */ 1144 uint32_t rsvd1[504]; 1145 1146 }; 1147 #endif 1148 1149 #ifdef _LITTLE_ENDIAN 1150 struct hermon_hw_set_port_s { 1151 uint32_t cap_mask; 1152 1153 uint32_t rqk :1; /* reset qkey violation cntr */ 1154 uint32_t rcm :1; /* reset capability mask */ 1155 uint32_t :2; 1156 uint32_t vl_cap :4; 1157 uint32_t :4; 1158 uint32_t mtu_cap :4; 1159 uint32_t g0 :1; /* set port GUID0 */ 1160 uint32_t ng :1; /* set node GUID (all ports) */ 1161 uint32_t sig :1; /* set sys image */ 1162 uint32_t mg :1; /* change GID table */ 1163 uint32_t mp :1; /* change pkey table size */ 1164 uint32_t mvc :1; /* change vl_cap */ 1165 uint32_t mmc :1; /* change mtu_cap */ 1166 uint32_t :9; 1167 1168 uint64_t sys_img_guid; 1169 1170 uint64_t guid0; 1171 1172 uint64_t node_guid; 1173 1174 uint32_t sniff_qpn_base :24; 1175 uint32_t ge :1; /* glob egress sniff enabled */ 1176 uint32_t gi :1; /* glob ingress sniff enabled */ 1177 uint32_t qe :1; /* qp-egress sniff enable */ 1178 uint32_t qi :1; /* qp-ingress sniff enabled */ 1179 uint32_t :4; 1180 1181 uint32_t router_qpn_base :24; 1182 uint32_t routermode :1; 1183 uint32_t :7; 1184 1185 uint32_t :32; 1186 1187 uint32_t max_guid :16; /* valid if noted above */ 1188 uint32_t max_pkey :16; /* valid if noted above */ 1189 1190 uint32_t rsrd0[500]; 1191 }; 1192 #else /* BIG ENDIAN */ 1193 struct hermon_hw_set_port_s { 1194 uint32_t :9; 1195 uint32_t mmc :1; /* change mtu_cap */ 1196 uint32_t mvc :1; /* change vl_cap */ 1197 uint32_t mp :1; /* change pkey table size */ 1198 uint32_t mg :1; /* change GID table size */ 1199 uint32_t sig :1; /* set sys image GUID */ 1200 uint32_t ng :1; /* set node GUID (all ports) */ 1201 uint32_t g0 :1; /* set port GUID0 */ 1202 uint32_t mtu_cap :4; 1203 uint32_t :4; 1204 uint32_t vl_cap :4; 1205 uint32_t :2; 1206 uint32_t rcm :1; /* reset capability mask */ 1207 uint32_t rqk :1; /* reset qkey violation cntr */ 1208 1209 uint32_t cap_mask; 1210 1211 uint64_t sys_img_guid; 1212 1213 uint64_t guid0; 1214 1215 uint64_t node_guid; 1216 1217 uint32_t :7; 1218 uint32_t routermode :1; 1219 uint32_t router_qpn_base :24; 1220 1221 uint32_t :4; 1222 uint32_t qi :1; /* qp-ingress sniff enabled */ 1223 uint32_t qe :1; /* qp-egress sniff enable */ 1224 uint32_t gi :1; /* glob ingress sniff enabled */ 1225 uint32_t ge :1; /* glob egress sniff enabled */ 1226 uint32_t sniff_qpn_base :24; 1227 1228 uint32_t max_pkey :16; /* valid if noted above */ 1229 uint32_t max_guid :16; /* valid if noted above */ 1230 1231 uint32_t :32; 1232 1233 uint32_t rsrd0[500]; 1234 }; 1235 #endif 1236 1237 1238 1239 1240 /* 1241 * Hermon Memory Protection Table (MPT) entries 1242 * 1243 * The Memory Protection Table (MPT) contains the information associated 1244 * with all the regions and windows. The MPT table resides in a virtually- 1245 * contiguous area in ICM, and the memory key (R_Key or L_Key) is used to 1246 * calculate the physical address for accessing the entries in the table. 1247 * 1248 * 1249 * The SW2HW_MPT command transfers ownership of an MPT entry from software 1250 * to hardware. The command takes the MPT entry from the input mailbox and 1251 * stores it in the MPT in the hardware. The command will fail if the 1252 * requested MPT entry is already owned by the hardware or if the MPT index 1253 * given in the command is inconsistent with the MPT entry memory key. 1254 * The QUERY_MPT command retrieves a snapshot of an MPT entry. The command 1255 * takes the current state of an MPT entry from the hardware and stores it 1256 * in the output mailbox. The command will fail if the requested MPT entry 1257 * is already owned by software. 1258 * Finally, the HW2SW_MPT command transfers ownership of an MPT entry from 1259 * the hardware to the software. The command takes the MPT entry from the 1260 * hardware, invalidates it, and stores it in the output mailbox. The 1261 * command will fail if the requested entry is already owned by software. 1262 * The command will also fail if the MPT entry in question is a Memory 1263 * Region which has Memory Windows currently bound to it. 1264 * 1265 * The following structure is used in the SW2HW_MPT, QUERY_MPT, and 1266 * HW2SW_MPT commands, and ONLY for the dMPT - for data. 1267 */ 1268 1269 #ifdef _LITTLE_ENDIAN 1270 struct hermon_hw_dmpt_s { 1271 uint32_t :7; 1272 uint32_t bnd_qp :1; 1273 uint32_t qpn :24; /* dw 1, byte 4-7 */ 1274 1275 uint32_t :8; 1276 uint32_t reg_win :1; 1277 uint32_t phys_addr :1; 1278 uint32_t lr :1; 1279 uint32_t lw :1; 1280 uint32_t rr :1; 1281 uint32_t rw :1; 1282 uint32_t atomic :1; 1283 uint32_t en_bind :1; 1284 uint32_t atc_req :1; 1285 uint32_t atc_xlat :1; 1286 uint32_t :1; 1287 uint32_t no_snoop :1; 1288 uint32_t :8; 1289 uint32_t status :4; /* dw 0, byte 0-3 */ 1290 1291 uint32_t pd :24; 1292 uint32_t ren_inval :1; 1293 uint32_t en_inval :1; 1294 uint32_t net_cache :1; 1295 uint32_t fast_reg_en :1; 1296 uint32_t rem_acc_en :1; 1297 uint32_t w_dif :1; 1298 uint32_t m_dif :1; 1299 uint32_t :1; /* dw 2, byte 0xc-f */ 1300 1301 uint32_t mem_key; 1302 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1303 1304 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1305 1306 uint32_t win_cnt :24; 1307 uint32_t :8; /* dw 9, byte 0x24-27 */ 1308 1309 uint32_t lkey; /* dw 8, byte 0x20-23 */ 1310 1311 uint32_t mtt_addr_h :8; 1312 uint32_t :24; /* dw 11, byte 0x2c-2f */ 1313 1314 uint32_t mtt_rep :4; 1315 uint32_t :17; 1316 uint32_t blk_mode :1; 1317 uint32_t len_b64 :1; /* bit 64 of length */ 1318 uint32_t fbo_en :1; 1319 uint32_t :8; /* dw 10, byte 0x28-2b */ 1320 1321 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1322 1323 uint32_t :3; 1324 uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */ 1325 1326 uint32_t mtt_fbo :21; 1327 uint32_t :11; /* dw 15, byte 0x3c-3f */ 1328 1329 uint32_t entity_sz :21; 1330 uint32_t :11; /* dw 14, byte 0x38-3b */ 1331 #ifdef HERMON_NOTIMPL 1332 uint32_t dif_m_atag :16; 1333 uint32_t :16; /* dw 17, 0x44-47 */ 1334 1335 uint32_t dif_a_msk :16; 1336 uint32_t dif_v_msk :2; 1337 uint32_t dif_rep :2; 1338 uint32_t :9; 1339 uint32_t dif_err :3; /* dw 16, 0x40-43 */ 1340 1341 uint32_t dif_w_atag :16; 1342 uint32_t :16; /* dw 19, 0x4c-4f */ 1343 1344 uint32_t dif_m_rtagb; /* dw 18, 0x48-4b */ 1345 1346 uint32_t :32; 1347 1348 uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */ 1349 #endif /* HERMON_NOTIMPL */ 1350 }; 1351 1352 #else /* BIG ENDIAN */ 1353 struct hermon_hw_dmpt_s { 1354 uint32_t status :4; 1355 uint32_t :8; 1356 uint32_t no_snoop :1; 1357 uint32_t :1; 1358 uint32_t atc_xlat :1; 1359 uint32_t atc_req :1; 1360 uint32_t en_bind :1; 1361 uint32_t atomic :1; 1362 uint32_t rw :1; 1363 uint32_t rr :1; 1364 uint32_t lw :1; 1365 uint32_t lr :1; 1366 uint32_t phys_addr :1; 1367 uint32_t reg_win :1; 1368 uint32_t :8; /* dw 0, byte 0x0-3 */ 1369 1370 uint32_t qpn :24; 1371 uint32_t bnd_qp :1; 1372 uint32_t :7; /* dw 1, byte 0x4-7 */ 1373 1374 uint32_t mem_key; /* dw 2, byte 0x8-b */ 1375 1376 uint32_t :1; 1377 uint32_t m_dif :1; 1378 uint32_t w_dif :1; 1379 uint32_t rem_acc_en :1; 1380 uint32_t fast_reg_en :1; 1381 uint32_t net_cache :1; 1382 uint32_t en_inval :1; 1383 uint32_t ren_inavl :1; 1384 uint32_t pd :24; /* dw 3, byte 0xc-f */ 1385 1386 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1387 1388 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1389 1390 uint32_t lkey; /* dw 8, bytd 0x20-23 */ 1391 1392 uint32_t :8; 1393 uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */ 1394 1395 uint32_t :8; 1396 uint32_t fbo_en :1; 1397 uint32_t len_b64 :1; /* bit 64 of length */ 1398 uint32_t blk_mode :1; 1399 uint32_t :17; 1400 uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */ 1401 1402 uint32_t :24; 1403 uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */ 1404 1405 uint32_t mtt_addr_l :29; 1406 uint32_t :3; /* dw 12, byte 0x30-33 */ 1407 1408 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1409 1410 uint32_t :11; 1411 uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */ 1412 1413 uint32_t :11; 1414 uint32_t mtt_fbo :21; /* dw 15, byte 0x3c-3f */ 1415 #ifdef HERMON_NOTIMPL 1416 1417 uint32_t dif_err :3; 1418 uint32_t :9; 1419 uint32_t dif_rep :2; 1420 uint32_t dif_v_msk :2; 1421 uint32_t dif_a_msk :16; /* dw 16, 0x40-43 */ 1422 1423 uint32_t :16; 1424 uint32_t dif_m_atag :16; /* dw 17, 0x44-47 */ 1425 1426 uint32_t dif_m_rtagb; /* dw 18, 0x48-4b */ 1427 1428 uint32_t :16; 1429 uint32_t dif_w_atag :16; /* dw 19, 0x4c-4f */ 1430 1431 uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */ 1432 1433 uint32_t :32; 1434 #endif /* HERMON_NOTIMPL */ 1435 }; 1436 #endif 1437 1438 /* 1439 * The following structure is for the CMPTs. This is NEVER actually built and 1440 * passed to the hardware - we use it to track information needed for the 1441 * context entries, and to facilitate the alloc tracking. It differs from 1442 * the dMPT sturcture above in that it does not have/need the "dif" stuff. 1443 * 1444 */ 1445 1446 1447 1448 #ifdef _LITTLE_ENDIAN 1449 struct hermon_hw_cmpt_s { 1450 uint32_t :7; 1451 uint32_t bnd_qp :1; 1452 uint32_t qpn :24; /* dw 1, byte 4-7 */ 1453 1454 uint32_t :8; 1455 uint32_t reg_win :1; 1456 uint32_t phys_addr :1; 1457 uint32_t lr :1; 1458 uint32_t lw :1; 1459 uint32_t rr :1; 1460 uint32_t rw :1; 1461 uint32_t atomic :1; 1462 uint32_t en_bind :1; 1463 uint32_t atc_req :1; 1464 uint32_t atc_xlat :1; 1465 uint32_t :1; 1466 uint32_t no_snoop :1; 1467 uint32_t :8; 1468 uint32_t status :4; /* dw 0, byte 0-3 */ 1469 1470 uint32_t pd :24; 1471 uint32_t ren_inval :1; 1472 uint32_t en_inval :1; 1473 uint32_t net_cache :1; 1474 uint32_t fast_reg_en :1; 1475 uint32_t rem_acc_en :1; 1476 uint32_t w_dif :1; 1477 uint32_t m_dif :1; 1478 uint32_t :1; /* dw 2, byte 0xc-f */ 1479 1480 uint32_t mem_key; 1481 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1482 1483 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1484 1485 uint32_t win_cnt :24; 1486 uint32_t :8; /* dw 9, byte 0x24-27 */ 1487 1488 uint32_t lkey; /* dw 8, byte 0x20-23 */ 1489 1490 uint32_t mtt_addr_h :8; 1491 uint32_t :24; /* dw 11, byte 0x2c-2f */ 1492 1493 uint32_t mtt_rep :4; 1494 uint32_t :17; 1495 uint32_t blk_mode :1; 1496 uint32_t len_b64 :1; /* bit 64 of length */ 1497 uint32_t fbo_en :1; 1498 uint32_t :8; /* dw 10, byte 0x28-2b */ 1499 1500 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1501 1502 uint32_t :3; 1503 uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */ 1504 1505 uint32_t mtt_fbo :21; 1506 uint32_t :11; /* dw 15, byte 0x3c-3f */ 1507 1508 uint32_t entity_sz :21; 1509 uint32_t :11; /* dw 14, byte 0x38-3b */ 1510 1511 }; 1512 1513 1514 #else /* BIG ENDIAN */ 1515 struct hermon_hw_cmpt_s { 1516 uint32_t status :4; 1517 uint32_t :8; 1518 uint32_t no_snoop :1; 1519 uint32_t :1; 1520 uint32_t atc_xlat :1; 1521 uint32_t atc_req :1; 1522 uint32_t en_bind :1; 1523 uint32_t atomic :1; 1524 uint32_t rw :1; 1525 uint32_t rr :1; 1526 uint32_t lw :1; 1527 uint32_t lr :1; 1528 uint32_t phys_addr :1; 1529 uint32_t reg_win :1; 1530 uint32_t :8; /* dw 0, byte 0x0-3 */ 1531 1532 uint32_t qpn :24; 1533 uint32_t bnd_qp :1; 1534 uint32_t :7; /* dw 1, byte 0x4-7 */ 1535 1536 uint32_t mem_key; /* dw 2, byte 0x8-b */ 1537 1538 uint32_t :1; 1539 uint32_t m_dif :1; 1540 uint32_t w_dif :1; 1541 uint32_t rem_acc_en :1; 1542 uint32_t fast_reg_en :1; 1543 uint32_t net_cache :1; 1544 uint32_t en_inval :1; 1545 uint32_t ren_inavl :1; 1546 uint32_t pd :24; /* dw 3, byte 0xc-f */ 1547 1548 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1549 1550 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1551 1552 uint32_t lkey; /* dw 8, bytd 0x20-23 */ 1553 1554 uint32_t :8; 1555 uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */ 1556 1557 uint32_t :8; 1558 uint32_t fbo_en :1; 1559 uint32_t len_b64 :1; /* bit 64 of length */ 1560 uint32_t blk_mode :1; 1561 uint32_t :17; 1562 uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */ 1563 1564 uint32_t :24; 1565 uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */ 1566 1567 uint32_t mtt_addr_l :29; 1568 uint32_t :3; /* dw 12, byte 0x30-33 */ 1569 1570 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1571 1572 uint32_t :11; 1573 uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */ 1574 }; 1575 #endif 1576 1577 1578 #define HERMON_MEM_CYCLE_GENERATE 0x1 1579 #define HERMON_IO_CYCLE_GENERATE 0x0 1580 1581 #define HERMON_MPT_IS_WINDOW 0x0 1582 #define HERMON_MPT_IS_REGION 0x1 1583 1584 #define HERMON_MPT_DEFAULT_VERSION 0x0 1585 1586 #define HERMON_UNLIMITED_WIN_BIND 0x0 1587 1588 #define HERMON_PHYSADDR_ENABLED 0x1 1589 #define HERMON_PHYSADDR_DISABLED 0x0 1590 1591 1592 /* 1593 * Hermon Memory Translation Table (MTT) entries 1594 * After accessing the MPT table (above) and validating the access rights 1595 * to the region/window, Hermon address translation moves to the next step 1596 * where it translates the virtual address to a physical address. This 1597 * translation is performed using the Memory Translation Table entries 1598 * (MTT). Note: The MTT in hardware is organized into segments and each 1599 * segment contains multiple address translation pages (MTT entries). 1600 * Each memory region (MPT above) points to the first segment in the MTT 1601 * that corresponds to that region. 1602 */ 1603 1604 #ifdef _LITTLE_ENDIAN 1605 struct hermon_hw_mtt_s { 1606 uint32_t present :1; 1607 uint32_t :2; 1608 uint32_t ptag_l :29; 1609 1610 uint32_t ptag_h; 1611 }; 1612 #else /* BIG_ENDIAN */ 1613 struct hermon_hw_mtt_s { 1614 uint32_t ptag_h; 1615 1616 uint32_t ptag_l :29; 1617 uint32_t :2; 1618 uint32_t present :1; 1619 }; 1620 1621 #endif 1622 #define HERMON_MTT_ENTRY_NOTPRESENT 0x0 1623 #define HERMON_MTT_ENTRY_PRESENT 0x1 1624 1625 1626 /* 1627 * Hermon Event Queue Context Table (EQC) entries 1628 * Hermon supports 512 Event Queues, and the status of Event Queues is stored 1629 * in the Event Queue Context (EQC) table. The EQC table is a virtually- 1630 * contiguous memory structure in the ICM. Each EQC 1631 * table entry contains Event Queue status and information required by 1632 * the hardware in order to access the event queue. 1633 * NOTE that in Hermon (as opposed to earlier HCAs), 1634 * you have to allocate ICM for 2**32 (or about 16 M), even though 1635 * it doesn't support that many. See PRM v35. Also, some set of them 1636 * will be available for each domain in a virtual environment, needing to 1637 * rething the allocation and usage model for EQs - in the future. 1638 * 1639 * The following structure is used in the SW2HW_EQ, QUERY_EQ, and HW2SW_EQ 1640 * commands. 1641 * The SW2HW_EQ command transfers ownership of an EQ context from software 1642 * to hardware. The command takes the EQC entry from the input mailbox and 1643 * stores it in the EQC in the hardware. The command will fail if the 1644 * requested EQC entry is already owned by the hardware. NOTE: the 1645 * initialization of the cMPT for the EQC occurs implicitly as a result 1646 * of executing this command, and MR has/had to be adjusted for it. 1647 * The QUERY_EQ command retrieves a snapshot of an EQC entry. The command 1648 * stores the snapshot in the output mailbox. The EQC state and its values 1649 * are not affected by the QUERY_EQ command. 1650 * Finally, the HW2SW_EQ command transfers ownership of an EQC entry from 1651 * the hardware to the software. The command takes the EQC entry from the 1652 * hardware and stores it in the output mailbox. The EQC entry will be 1653 * invalidated as a result of the command. It is the responsibility of the 1654 * software to unmap all the events, which might have been previously 1655 * mapped to the EQ, prior to issuing the HW2SW_EQ command. 1656 */ 1657 1658 1659 #ifdef _LITTLE_ENDIAN 1660 struct hermon_hw_eqc_s { 1661 uint32_t :32; 1662 1663 uint32_t :8; 1664 uint32_t state :4; 1665 uint32_t :5; 1666 uint32_t overrun_ignore :1; 1667 uint32_t ev_coalesc :1; 1668 uint32_t :9; 1669 uint32_t status :4; 1670 1671 uint32_t :24; 1672 uint32_t log_eq_sz :5; 1673 uint32_t :3; 1674 1675 uint32_t :5; 1676 uint32_t pg_offs :7; 1677 uint32_t :20; 1678 1679 uint32_t intr :10; 1680 uint32_t :22; 1681 1682 uint32_t eq_max_cnt :16; 1683 uint32_t eq_period :16; 1684 1685 uint32_t :3; 1686 uint32_t mtt_base_addrl :29; 1687 1688 uint32_t mtt_base_addrh :8; 1689 uint32_t :16; 1690 uint32_t log2_pgsz :6; /* in 4K pages */ 1691 uint32_t :2; 1692 1693 uint32_t rsrv0[2]; 1694 1695 uint32_t prod_indx :24; 1696 uint32_t :8; 1697 1698 uint32_t cons_indx :24; 1699 uint32_t :8; 1700 1701 uint64_t rsrv1[2]; /* force it to 8b alignment */ 1702 }; 1703 #else /* BIG ENDIAN */ 1704 struct hermon_hw_eqc_s { 1705 uint32_t status :4; 1706 uint32_t :9; 1707 uint32_t ev_coalesc :1; 1708 uint32_t overrun_ignore :1; 1709 uint32_t :5; 1710 uint32_t state :4; 1711 uint32_t :8; 1712 1713 uint32_t :32; 1714 1715 uint32_t :20; 1716 uint32_t pg_offs :7; 1717 uint32_t :5; 1718 1719 uint32_t :3; 1720 uint32_t log_eq_sz :5; 1721 uint32_t :24; 1722 1723 uint32_t eq_period :16; 1724 uint32_t eq_max_cnt :16; 1725 1726 uint32_t :22; 1727 uint32_t intr :10; 1728 1729 uint32_t :2; 1730 uint32_t log2_pgsz :6; /* in 4K pages */ 1731 uint32_t :16; 1732 uint32_t mtt_base_addrh :8; 1733 1734 uint32_t mtt_base_addrl :29; 1735 uint32_t :3; 1736 1737 uint32_t rsrv0[2]; 1738 1739 uint32_t :8; 1740 uint32_t cons_indx :24; 1741 1742 uint32_t :8; 1743 uint32_t prod_indx :24; 1744 1745 uint64_t rsrv1[2]; /* force it to 8b alignment */ 1746 }; 1747 #endif 1748 #define HERMON_EQ_STATUS_OK 0x0 1749 #define HERMON_EQ_STATUS_OVERFLOW 0x9 1750 #define HERMON_EQ_STATUS_WRITE_FAILURE 0xA 1751 1752 #define HERMON_EQ_ARMED 0x9 1753 #define HERMON_EQ_FIRED 0xA 1754 #define HERMON_EQ_ALWAYS_ARMED 0xB 1755 1756 1757 /* 1758 * Hermon Event Queue Entries (EQE) 1759 * Each EQE contains enough information for the software to identify the 1760 * source of the event. The following structures are used to define each 1761 * of the various kinds of events that the Hermon hardware will generate. 1762 * Note: The hermon_hw_eqe_t below is the generic "Event Queue Entry". All 1763 * other EQEs differ only in the contents of their "event_data" field. 1764 * 1765 * Below we first define several structures which define the contents of 1766 * the "event_data" fields: 1767 * hermon_hw_eqe_cq_t for "Completion Queue Events" 1768 * hermon_hw_eqe_qp_evt_t for "Queue Pair Events" such as Path Migration 1769 * Succeeded, Path Migration Failed, Communication Established, Send 1770 * Queue Drained, Local WQ Catastrophic Error, Invalid Request Local 1771 * WQ Error, and Local Access Violation WQ Error. 1772 * hermon_hw_eqe_cqerr_t for "Completion Queue Error Events" 1773 * hermon_hw_eqe_portstate_t for "Port State Change Events" 1774 * hermon_hw_eqe_gpio_t for "GPIO State Change Events" 1775 * hermon_hw_eqe_cmdcmpl_t for "Command Interface Completion Events" 1776 * hermon_hw_eqe_operr_t for "Operational and Catastrophic Error Events" 1777 * such as EQ Overflow, Misbehaved UAR page, Internal Parity Error, 1778 * Uplink bus error, and DDR data error. 1779 * hermon_hw_eqe_pgflt_t for "Not-present Page Fault on WQE or Data 1780 * Buffer Access". (Note: Currently, this event is unsupported). 1781 * 1782 * Note also: The following structures are not #define'd with both 1783 * little-endian and big-endian definitions. This is because their 1784 * individual fields are not directly accessed except through the macros 1785 * defined below. 1786 */ 1787 1788 1789 typedef struct hermon_hw_eqe_cq_s { 1790 uint32_t :8; 1791 uint32_t cqn :24; 1792 uint32_t rsrv0[5]; 1793 } hermon_hw_eqe_cq_t; 1794 1795 1796 1797 typedef struct hermon_hw_eqe_qp_evt_s { 1798 uint32_t :8; 1799 uint32_t qpn :24; 1800 1801 uint32_t rsrv0[5]; 1802 } hermon_hw_eqe_qpevt_t; 1803 1804 1805 typedef struct hermon_hw_eqe_cqerr_s { 1806 uint32_t :8; 1807 uint32_t cqn :24; 1808 1809 uint32_t :32; 1810 1811 uint32_t :24; 1812 uint32_t syndrome :8; 1813 1814 uint32_t rsrv0[3]; 1815 } hermon_hw_eqe_cqerr_t; 1816 #define HERMON_CQERR_OVERFLOW 0x1 1817 #define HERMON_CQERR_ACCESS_VIOLATION 0x2 1818 1819 1820 typedef struct hermon_hw_eqe_portstate_s { 1821 uint32_t rsrv0[2]; 1822 1823 uint32_t :2; 1824 uint32_t port :2; 1825 uint32_t :28; 1826 1827 uint32_t rsrv1[3]; 1828 } hermon_hw_eqe_portstate_t; 1829 #define HERMON_PORT_LINK_ACTIVE 0x4 1830 #define HERMON_PORT_LINK_DOWN 0x1 1831 1832 1833 typedef struct hermon_hw_eqe_gpio_s { 1834 uint32_t rsrv0[3]; 1835 1836 uint32_t gpio_ev0; 1837 1838 uint32_t gpio_ev1; 1839 1840 uint32_t :32; 1841 } hermon_hw_eqe_gpio_t; 1842 1843 1844 typedef struct hermon_hw_eqe_cmdcmpl_s { 1845 uint32_t :16; 1846 uint32_t token :16; 1847 1848 uint32_t :32; 1849 1850 uint32_t :24; 1851 uint32_t status :8; 1852 1853 uint32_t out_param0; 1854 1855 uint32_t out_param1; 1856 1857 uint32_t :32; 1858 } hermon_hw_eqe_cmdcmpl_t; 1859 1860 1861 typedef struct hermon_hw_eqe_operr_s { 1862 uint32_t rsrv0[2]; 1863 1864 uint32_t :24; 1865 uint32_t error_type :8; 1866 1867 uint32_t data; 1868 1869 uint32_t rsrv1[2]; 1870 } hermon_hw_eqe_operr_t; 1871 #define HERMON_ERREVT_EQ_OVERFLOW 0x1 1872 #define HERMON_ERREVT_BAD_UARPG 0x2 1873 #define HERMON_ERREVT_UPLINK_BUSERR 0x3 1874 #define HERMON_ERREVT_DDR_DATAERR 0x4 1875 #define HERMON_ERREVT_INTERNAL_PARITY 0x5 1876 1877 1878 typedef struct hermon_hw_eqe_pgflt_s { 1879 uint32_t rsrv0[2]; 1880 uint32_t :24; 1881 uint32_t fault_type :4; 1882 uint32_t wqv :1; 1883 uint32_t wqe_data :1; 1884 uint32_t rem_loc :1; 1885 uint32_t snd_rcv :1; 1886 uint32_t vaddr_h; 1887 uint32_t vaddr_l; 1888 uint32_t mem_key; 1889 } hermon_hw_eqe_pgflt_t; 1890 #define HERMON_PGFLT_PG_NOTPRESENT 0x8 1891 #define HERMON_PGFLT_PG_WRACC_VIOL 0xA 1892 #define HERMON_PGFLT_UNSUP_NOTPRESENT 0xE 1893 #define HERMON_PGFLT_UNSUP_WRACC_VIOL 0xF 1894 #define HERMON_PGFLT_WQE_CAUSED 0x1 1895 #define HERMON_PGFLT_DATA_CAUSED 0x0 1896 #define HERMON_PGFLT_REMOTE_CAUSED 0x1 1897 #define HERMON_PGFLT_LOCAL_CAUSED 0x0 1898 #define HERMON_PGFLT_SEND_CAUSED 0x1 1899 #define HERMON_PGFLT_RECV_CAUSED 0x0 1900 #define HERMON_PGFLT_DESC_CONSUMED 0x1 1901 #define HERMON_PGFLT_DESC_NOTCONSUMED 0x0 1902 1903 struct hermon_hw_eqe_s { 1904 uint32_t :8; 1905 uint32_t event_type :8; 1906 uint32_t :8; 1907 uint32_t event_subtype :8; 1908 union { 1909 hermon_hw_eqe_cq_t eqe_cq; 1910 hermon_hw_eqe_qpevt_t eqe_qpevt; 1911 hermon_hw_eqe_cqerr_t eqe_cqerr; 1912 hermon_hw_eqe_portstate_t eqe_portstate; 1913 hermon_hw_eqe_gpio_t eqe_gpio; 1914 hermon_hw_eqe_cmdcmpl_t eqe_cmdcmpl; 1915 hermon_hw_eqe_operr_t eqe_operr; 1916 hermon_hw_eqe_pgflt_t eqe_pgflt; 1917 } event_data; 1918 uint32_t :24; 1919 uint32_t owner :1; 1920 uint32_t :7; 1921 }; 1922 #define eqe_cq event_data.eqe_cq 1923 #define eqe_qpevt event_data.eqe_qpevt 1924 #define eqe_cqerr event_data.eqe_cqerr 1925 #define eqe_portstate event_data.eqe_portstate 1926 #define eqe_gpio event_data.eqe_gpio 1927 #define eqe_cmdcmpl event_data.eqe_cmdcmpl 1928 #define eqe_operr event_data.eqe_operr 1929 #define eqe_pgflt event_data.eqe_pgflt 1930 1931 /* 1932 * The following macros are used for extracting (and in some cases filling in) 1933 * information from EQEs 1934 */ 1935 #define HERMON_EQE_CQNUM_MASK 0x00FFFFFF 1936 #define HERMON_EQE_CQNUM_SHIFT 0 1937 #define HERMON_EQE_QPNUM_MASK 0x00FFFFFF 1938 #define HERMON_EQE_QPNUM_SHIFT 0 1939 #define HERMON_EQE_PORTNUM_MASK 0x30 1940 #define HERMON_EQE_PORTNUM_SHIFT 4 1941 #define HERMON_EQE_OWNER_MASK 0x00000080 1942 #define HERMON_EQE_OWNER_SHIFT 7 1943 1944 #define HERMON_EQE_EVTTYPE_GET(eq, eqe) \ 1945 (((uint8_t *)(eqe))[1]) 1946 #define HERMON_EQE_EVTSUBTYPE_GET(eq, eqe) \ 1947 (((uint8_t *)(eqe))[3]) 1948 #define HERMON_EQE_CQNUM_GET(eq, eqe) \ 1949 ((htonl(((uint32_t *)(eqe))[1]) & HERMON_EQE_CQNUM_MASK) >> \ 1950 HERMON_EQE_CQNUM_SHIFT) 1951 #define HERMON_EQE_QPNUM_GET(eq, eqe) \ 1952 ((htonl(((uint32_t *)(eqe))[1]) & HERMON_EQE_QPNUM_MASK) >> \ 1953 HERMON_EQE_QPNUM_SHIFT) 1954 #define HERMON_EQE_PORTNUM_GET(eq, eqe) \ 1955 (((((uint8_t *)(eqe))[12]) & HERMON_EQE_PORTNUM_MASK) >> \ 1956 HERMON_EQE_PORTNUM_SHIFT) 1957 #define HERMON_EQE_CMDTOKEN_GET(eq, eqe) \ 1958 htons(((uint16_t *)(eqe))[3]) 1959 #define HERMON_EQE_CMDSTATUS_GET(eq, eqe) \ 1960 (((uint8_t *)(eqe))[0xf]) 1961 #define HERMON_EQE_CMDOUTP0_GET(eq, eqe) \ 1962 htonl(((uint32_t *)(eqe))[4]) 1963 #define HERMON_EQE_CMDOUTP1_GET(eq, eqe) \ 1964 htonl(((uint32_t *)(eqe))[5]) 1965 #define HERMON_EQE_OPERRTYPE_GET(eq, eqe) \ 1966 (((uint8_t *)(eqe))[0xf]) 1967 #define HERMON_EQE_OPERRDATA_GET(eq, eqe) \ 1968 htonl(((uint32_t *)(eqe))[4]) 1969 /* 1970 * Hermon does ownership of CQ and EQ differently from Arbel & Tavor. 1971 * Now, you keep track of the TOTAL number of CQE's or EQE's that have been 1972 * processed, and the sense of the ownership bit changes each time through. 1973 * That is, if the size of the queue is 16, so 4 bits [3:0] are the index 1974 * number, then bit [4] is the ownership bit in the count. So you mask that 1975 * bit and compare it to the owner bit in the entry - if the same, then the 1976 * entry is in SW onwership. Otherwise, it's in hardware and the driver 1977 * does not consume it. 1978 */ 1979 1980 #define HERMON_EQE_OWNER_IS_SW(eq, eqe) \ 1981 ((((uint8_t *)(eqe))[0x1f] & HERMON_EQE_OWNER_MASK) == \ 1982 (((eq->eq_nexteqe) & eq->eq_bufsz) >> \ 1983 (eq->eq_log_eqsz - HERMON_EQE_OWNER_SHIFT))) 1984 1985 /* 1986 * Hermon Completion Queue Context Table (CQC) entries 1987 * The CQC table is a virtually-contiguous memory area residing in HCA's 1988 * ICM. Each CQC table entry contains information 1989 * required by the hardware to access the completion queue to post 1990 * completions (CQE). 1991 * 1992 * The following structure is used in the SW2HW_CQ, QUERY_CQ, RESIZE_CQ, 1993 * and HW2SW_CQ commands. 1994 * The SW2HW_CQ command transfers ownership of an CQ context from software 1995 * to hardware. The command takes the CQC entry from the input mailbox and 1996 * stores it in the CQC in the hardware. The command will fail if the 1997 * requested CQC entry is already owned by the hardware. 1998 * The QUERY_CQ command retrieves a snapshot of a CQC entry. The command 1999 * stores the snapshot in the output mailbox. The CQC state and its values 2000 * are not affected by the QUERY_CQ command. 2001 * Finally, the HW2SW_CQ command transfers ownership of a CQC entry from 2002 * the hardware to the software. The command takes the CQC entry from the 2003 * hardware and stores it in the output mailbox. The CQC entry will be 2004 * invalidated as a result of the command. 2005 */ 2006 2007 2008 #ifdef _LITTLE_ENDIAN 2009 struct hermon_hw_cqc_s { 2010 uint32_t :32; 2011 2012 uint32_t :8; 2013 uint32_t state :4; 2014 uint32_t :5; 2015 uint32_t overrun_ignore :1; 2016 uint32_t cqe_coalesc :1; 2017 uint32_t :9; 2018 uint32_t status :4; 2019 2020 uint32_t usr_page :24; 2021 uint32_t log_cq_sz :5; 2022 uint32_t :3; 2023 2024 uint32_t :5; 2025 uint32_t pg_offs :7; 2026 uint32_t :20; 2027 2028 uint32_t c_eqn :9; 2029 uint32_t :23; 2030 2031 uint32_t cq_max_cnt :16; 2032 uint32_t cq_period :16; 2033 2034 uint32_t :3; 2035 uint32_t mtt_base_addl :29; 2036 2037 uint32_t mtt_base_addh :8; 2038 uint32_t :16; 2039 uint32_t log2_pgsz :6; 2040 uint32_t :2; 2041 2042 uint32_t solicit_prod_indx :24; 2043 uint32_t :8; 2044 2045 uint32_t last_notified_indx :24; 2046 uint32_t :8; 2047 2048 uint32_t prod_cntr :24; /* producer counter */ 2049 uint32_t :8; 2050 2051 uint32_t cons_cntr :24; /* consumer counter */ 2052 uint32_t :8; 2053 2054 uint32_t rsrv0[2]; 2055 2056 uint32_t :3; 2057 uint32_t dbr_addrl :29; 2058 2059 uint32_t dbr_addrh; 2060 2061 uint64_t rsrv1[8]; /* hermon, match DEV_CAP size */ 2062 }; 2063 #else 2064 struct hermon_hw_cqc_s { 2065 uint32_t status :4; 2066 uint32_t :9; 2067 uint32_t cqe_coalesc :1; 2068 uint32_t overrun_ignore :1; 2069 uint32_t :5; 2070 uint32_t state :4; 2071 uint32_t :8; 2072 2073 uint32_t :32; 2074 2075 uint32_t :20; 2076 uint32_t pg_offs :7; 2077 uint32_t :5; 2078 2079 uint32_t :3; 2080 uint32_t log_cq_sz :5; 2081 uint32_t usr_page :24; 2082 2083 uint32_t cq_period :16; 2084 uint32_t cq_max_cnt :16; 2085 2086 uint32_t :23; 2087 uint32_t c_eqn :9; 2088 2089 uint32_t :2; 2090 uint32_t log2_pgsz :6; 2091 uint32_t :16; 2092 uint32_t mtt_base_addh :8; 2093 2094 uint32_t mtt_base_addl :29; 2095 uint32_t :3; 2096 2097 uint32_t :8; 2098 uint32_t last_notified_indx :24; 2099 2100 uint32_t :8; 2101 uint32_t solicit_prod_indx :24; 2102 2103 uint32_t :8; 2104 uint32_t cons_cntr :24; /* consumer counter */ 2105 2106 uint32_t :8; 2107 uint32_t prod_cntr :24; /* priducer counter */ 2108 2109 uint32_t rsrv0[2]; 2110 2111 uint32_t dbr_addrh; 2112 2113 uint32_t dbr_addrl :29; 2114 uint32_t :3; 2115 2116 uint64_t rsrv1[8]; /* hermon, match DEV_CAP size */ 2117 }; 2118 #endif 2119 #define HERMON_CQ_STATUS_OK 0x0 2120 #define HERMON_CQ_STATUS_OVERFLOW 0x9 2121 #define HERMON_CQ_STATUS_WRITE_FAILURE 0xA 2122 2123 #define HERMON_CQ_DISARMED 0x0 2124 #define HERMON_CQ_ARMED 0x1 2125 #define HERMON_CQ_ARMED_SOLICITED 0x4 2126 #define HERMON_CQ_FIRED 0xA 2127 2128 /* 2129 * Hermon Completion Queue Entries (CQE) 2130 * Each CQE contains enough information for the software to associate the 2131 * completion with the Work Queue Element (WQE) to which it corresponds. 2132 * 2133 * Note: The following structure is not #define'd with both little-endian 2134 * and big-endian definitions. This is because each CQE's individual 2135 * fields are not directly accessed except through the macros defined below. 2136 */ 2137 2138 2139 struct hermon_hw_cqe_s { 2140 uint32_t dife :1; 2141 uint32_t :2; 2142 uint32_t fl :1; 2143 uint32_t fccrc_sd :1; 2144 uint32_t d2s :1; 2145 uint32_t :2; 2146 uint32_t my_qpn :24; 2147 2148 uint32_t immed_rss_val_key; 2149 2150 uint32_t grh :1; 2151 uint32_t ml_path :7; 2152 uint32_t srq_rqpn :24; 2153 2154 uint32_t sl :4; 2155 uint32_t :12; 2156 uint32_t slid :16; 2157 2158 uint32_t ipoib_status; 2159 2160 uint32_t byte_cnt; 2161 2162 uint32_t wqe_cntr :16; 2163 uint32_t checksum :16; 2164 2165 uint32_t :8; 2166 uint32_t :16; 2167 uint32_t owner :1; 2168 uint32_t send_or_recv :1; 2169 uint32_t inline_scatter :1; 2170 uint32_t opcode :5; 2171 }; 2172 #define HERMON_COMPLETION_RECV 0x0 2173 #define HERMON_COMPLETION_SEND 0x1 2174 2175 #define HERMON_CQE_DEFAULT_VERSION 0x0 2176 2177 /* 2178 * The following macros are used for extracting (and in some cases filling in) 2179 * information from CQEs 2180 */ 2181 #define HERMON_CQE_QPNUM_MASK 0x00FFFFFF 2182 #define HERMON_CQE_QPNUM_SHIFT 0 2183 2184 2185 #define HERMON_CQE_DQPN_MASK 0x00FFFFFF 2186 #define HERMON_CQE_DQPN_SHIFT 0 2187 2188 2189 #define HERMON_CQE_SL_SHIFT 4 2190 #define HERMON_CQE_GRH_MASK 0x80 2191 #define HERMON_CQE_PATHBITS_MASK 0x7F 2192 #define HERMON_CQE_SLID_15_8 0xe 2193 #define HERMON_CQE_SLID_7_0 0xf 2194 #define HERMON_CQE_OPCODE_MASK 0x1F 2195 #define HERMON_CQE_SENDRECV_MASK 0x40 2196 #define HERMON_CQE_SENDRECV_SHIFT 6 2197 #define HERMON_CQE_OWNER_MASK 0x80 2198 #define HERMON_CQE_OWNER_SHIFT 7 2199 #define HERMON_CQE_WQECNTR_15_8 0x18 2200 #define HERMON_CQE_WQECNTR_7_0 0x19 2201 /* Byte offsets for IPoIB Checksum Offload fields */ 2202 #define HERMON_CQE_CKSUM_15_8 0x1a 2203 #define HERMON_CQE_CKSUM_7_0 0x1b 2204 #define HERMON_CQE_IPOK 0x10 /* byte 0x10 in cqe */ 2205 #define HERMON_CQE_IPOK_BIT 0x10 /* bitmask for OK bit */ 2206 2207 #define HERMON_CQE_IS_IPOK(cq, cqe) \ 2208 (((uint8_t *)(cqe))[HERMON_CQE_IPOK] & HERMON_CQE_IPOK_BIT) 2209 2210 #define HERMON_CQE_CKSUM(cq, cqe) \ 2211 ((((uint8_t *)(cqe))[HERMON_CQE_CKSUM_15_8] << 8) | \ 2212 (((uint8_t *)(cqe))[HERMON_CQE_CKSUM_7_0])) 2213 2214 #define HERMON_CQE_IPOIB_STATUS(cq, cqe) \ 2215 htonl((((uint32_t *)(cqe)))[4]) 2216 2217 #define HERMON_CQE_QPNUM_GET(cq, cqe) \ 2218 ((htonl((((uint32_t *)(cqe)))[0]) & HERMON_CQE_QPNUM_MASK) >> \ 2219 HERMON_CQE_QPNUM_SHIFT) 2220 2221 #define HERMON_CQE_IMM_ETH_PKEY_CRED_GET(cq, cqe) \ 2222 htonl(((uint32_t *)(cqe))[1]) 2223 2224 #define HERMON_CQE_DQPN_GET(cq, cqe) \ 2225 ((htonl(((uint32_t *)(cqe))[2]) & HERMON_CQE_DQPN_MASK) >> \ 2226 HERMON_CQE_DQPN_SHIFT) 2227 2228 #define HERMON_CQE_GRH_GET(cq, cqe) \ 2229 (((uint8_t *)(cqe))[8] & HERMON_CQE_GRH_MASK) 2230 2231 #define HERMON_CQE_PATHBITS_GET(cq, cqe) \ 2232 (((uint8_t *)(cqe))[8] & HERMON_CQE_PATHBITS_MASK) 2233 2234 #define HERMON_CQE_DLID_GET(cq, cqe) \ 2235 ((((uint8_t *)(cqe))[HERMON_CQE_SLID_15_8] << 8) | \ 2236 (((uint8_t *)(cqe))[HERMON_CQE_SLID_7_0])) 2237 2238 #define HERMON_CQE_SL_GET(cq, cqe) \ 2239 ((((uint8_t *)(cqe))[12]) >> HERMON_CQE_SL_SHIFT) 2240 2241 #define HERMON_CQE_BYTECNT_GET(cq, cqe) \ 2242 htonl(((uint32_t *)(cqe))[5]) 2243 2244 #define HERMON_CQE_WQECNTR_GET(cq, cqe) \ 2245 ((((uint8_t *)(cqe))[HERMON_CQE_WQECNTR_15_8] << 8) | \ 2246 (((uint8_t *)(cqe))[HERMON_CQE_WQECNTR_7_0])) 2247 2248 #define HERMON_CQE_ERROR_SYNDROME_GET(cq, cqe) \ 2249 (((uint8_t *)(cqe))[27]) 2250 2251 #define HERMON_CQE_OPCODE_GET(cq, cqe) \ 2252 ((((uint8_t *)(cqe))[31]) & HERMON_CQE_OPCODE_MASK) 2253 2254 #define HERMON_CQE_SENDRECV_GET(cq, cqe) \ 2255 (((((uint8_t *)(cqe))[31]) & HERMON_CQE_SENDRECV_MASK) >> \ 2256 HERMON_CQE_SENDRECV_SHIFT) 2257 2258 /* See Comment above for EQE - ownership of CQE is handled the same */ 2259 2260 #define HERMON_CQE_OWNER_IS_SW(cq, cqe, considx) \ 2261 (((((uint8_t *)(cqe))[31] & HERMON_CQE_OWNER_MASK) >> \ 2262 HERMON_CQE_OWNER_SHIFT) == \ 2263 (((considx) & cq->cq_bufsz) >> cq->cq_log_cqsz)) 2264 2265 /* 2266 * Hermon Shared Receive Queue (SRQ) Context Entry Format 2267 */ 2268 2269 #ifdef _LITTLE_ENDIAN 2270 struct hermon_hw_srqc_s { 2271 uint32_t xrc_domain :16; 2272 uint32_t :8; 2273 uint32_t log_rq_stride :3; 2274 uint32_t :5; 2275 2276 uint32_t srqn :24; 2277 uint32_t log_srq_size :4; 2278 uint32_t state :4; 2279 2280 uint32_t :32; 2281 2282 uint32_t cqn_xrc :24; 2283 uint32_t :2; 2284 uint32_t page_offs :6; 2285 2286 uint32_t :3; 2287 uint32_t mtt_base_addrl :29; 2288 2289 uint32_t mtt_base_addrh :8; 2290 uint32_t :16; 2291 uint32_t log2_pgsz :6; 2292 uint32_t :2; 2293 2294 uint32_t wqe_cnt :16; 2295 uint32_t lwm :16; 2296 2297 uint32_t pd :24; 2298 uint32_t :8; 2299 2300 uint32_t :32; 2301 2302 uint32_t srq_wqe_cntr :16; 2303 uint32_t :16; 2304 2305 uint32_t :2; 2306 uint32_t dbr_addrl :30; 2307 2308 uint32_t dbr_addrh; 2309 2310 uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */ 2311 2312 }; 2313 #else 2314 struct hermon_hw_srqc_s { 2315 uint32_t state :4; 2316 uint32_t log_srq_size :4; 2317 uint32_t srqn :24; 2318 2319 uint32_t :5; 2320 uint32_t log_rq_stride :3; 2321 uint32_t :8; 2322 uint32_t xrc_domain :16; 2323 2324 uint32_t page_offs :6; 2325 uint32_t :2; 2326 uint32_t cqn_xrc :24; 2327 2328 uint32_t :32; 2329 2330 uint32_t :2; 2331 uint32_t log2_pgsz :6; 2332 uint32_t :16; 2333 uint32_t mtt_base_addrh :8; 2334 2335 uint32_t mtt_base_addrl :29; 2336 uint32_t :3; 2337 2338 uint32_t :8; 2339 uint32_t pd :24; 2340 2341 uint32_t lwm :16; 2342 uint32_t wqe_cnt :16; 2343 2344 uint32_t :16; 2345 uint32_t srq_wqe_cntr :16; 2346 2347 uint32_t :32; 2348 2349 uint32_t dbr_addrh; 2350 2351 uint32_t dbr_addrl :30; 2352 uint32_t :2; 2353 2354 uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */ 2355 }; 2356 #endif 2357 2358 /* 2359 * Hermon MOD_STAT_CFG input mailbox structure 2360 */ 2361 2362 2363 #ifdef _LITTLE_ENDIAN 2364 struct hermon_hw_mod_stat_cfg_s { 2365 uint32_t rsvd0; 2366 2367 uint32_t :14; 2368 uint32_t dife :1; 2369 uint32_t dife_m :1; 2370 uint32_t rx_options :4; 2371 uint32_t :3; 2372 uint32_t rx_options_m :1; 2373 uint32_t tx_options :4; 2374 uint32_t :3; 2375 uint32_t tx_options_m :1; 2376 2377 uint32_t lid :16; 2378 uint32_t lid_m :1; 2379 uint32_t :3; 2380 uint32_t port_en :1; 2381 uint32_t port_en_m :1; 2382 uint32_t :10; 2383 2384 uint32_t rsvd1; 2385 2386 uint32_t guid_hi; 2387 2388 uint32_t :31; 2389 uint32_t guid_hi_m :1; 2390 2391 uint32_t guid_lo; 2392 uint32_t :31; 2393 2394 uint32_t guid_lo_m :1; 2395 2396 uint32_t rsvd[4]; 2397 2398 uint32_t inbuf_ind_en :3; 2399 uint32_t :1; 2400 uint32_t sd_main :4; 2401 uint32_t :4; 2402 uint32_t sd_equal :4; 2403 uint32_t :4; 2404 uint32_t sd_mux_main :2; 2405 uint32_t :2; 2406 uint32_t mux_eq :2; 2407 uint32_t :2; 2408 uint32_t sigdet_th :3; 2409 uint32_t :1; 2410 2411 uint32_t ob_preemp_pre :5; 2412 uint32_t :3; 2413 uint32_t op_preemp_post :5; 2414 uint32_t :3; 2415 uint32_t ob_preemp_main :5; 2416 uint32_t :3; 2417 uint32_t ob_preemp :5; 2418 uint32_t :2; 2419 uint32_t serdes_m :1; 2420 2421 uint32_t reserved[50]; 2422 }; 2423 #else /* BIG ENDIAN */ 2424 struct hermon_hw_mod_stat_cfg_s { 2425 uint32_t tx_options_m :1; 2426 uint32_t :3; 2427 uint32_t tx_options :4; 2428 uint32_t rx_options_m :1; 2429 uint32_t :3; 2430 uint32_t rx_options :4; 2431 uint32_t dife_m :1; 2432 uint32_t dife :1; 2433 uint32_t :14; 2434 2435 uint32_t rsvd0; 2436 2437 uint32_t rsvd1; 2438 2439 uint32_t :10; 2440 uint32_t port_en_m :1; 2441 uint32_t port_en :1; 2442 uint32_t :3; 2443 uint32_t lid_m :1; 2444 uint32_t lid :16; 2445 2446 uint32_t guid_hi_m :1; 2447 uint32_t :31; 2448 2449 uint32_t guid_hi; 2450 2451 uint32_t guid_lo_m :1; 2452 uint32_t :31; 2453 2454 uint32_t guid_lo; 2455 2456 uint32_t rsvd[4]; 2457 2458 uint32_t serdes_m :1; 2459 uint32_t :2; 2460 uint32_t ob_preemp :5; 2461 uint32_t :3; 2462 uint32_t ob_preemp_main :5; 2463 uint32_t :3; 2464 uint32_t op_preemp_post :5; 2465 uint32_t :3; 2466 uint32_t ob_preemp_pre :5; 2467 2468 uint32_t :1; 2469 uint32_t sigdet_th :3; 2470 uint32_t :2; 2471 uint32_t mux_eq :2; 2472 uint32_t :2; 2473 uint32_t sd_mux_main :2; 2474 uint32_t :4; 2475 uint32_t sd_equal :4; 2476 uint32_t :4; 2477 uint32_t sd_main :4; 2478 uint32_t :1; 2479 uint32_t inbuf_ind_en :3; 2480 2481 uint32_t reserved[50]; 2482 }; 2483 #endif 2484 2485 2486 /* 2487 * Hermon MOD_STAT_CFG input modifier structure 2488 */ 2489 struct hermon_hw_msg_in_mod_s { 2490 #ifdef _LITTLE_ENDIAN 2491 uint32_t offset :8; 2492 uint32_t port_num :8; 2493 uint32_t lane_num :4; 2494 uint32_t link_speed :3; 2495 uint32_t auto_neg :1; 2496 uint32_t :8; 2497 #else 2498 uint32_t :8; 2499 uint32_t auto_neg :1; 2500 uint32_t link_speed :3; 2501 uint32_t lane_num :4; 2502 uint32_t port_num :8; 2503 uint32_t offset :8; 2504 #endif 2505 }; 2506 2507 2508 /* 2509 * Hermon UD Address Vector (UDAV) 2510 * Hermon UDAV are used in conjunction with Unreliable Datagram (UD) send 2511 * WQEs. Each UD send message contains an address vector in in the datagram 2512 * segment. The verbs consumer must use special verbs to create and modify 2513 * address handles, each of which contains a UDAV structure. When posting 2514 * send WQEs to UD QP, the verbs consumer must supply a valid address 2515 * handle/UDAV. 2516 */ 2517 2518 2519 #ifdef _LITTLE_ENDIAN 2520 struct hermon_hw_udav_s { 2521 uint32_t rlid :16; 2522 uint32_t ml_path :7; 2523 uint32_t grh :1; 2524 uint32_t :8; 2525 2526 uint32_t pd :24; 2527 uint32_t portnum :2; 2528 uint32_t :5; 2529 uint32_t force_lp :1; 2530 2531 uint32_t flow_label :20; 2532 uint32_t tclass :8; 2533 uint32_t sl :4; 2534 2535 uint32_t hop_limit :8; 2536 uint32_t max_stat_rate :4; 2537 uint32_t :4; 2538 uint32_t mgid_index :7; 2539 uint32_t :9; 2540 2541 uint64_t rgid_h; 2542 uint64_t rgid_l; 2543 }; 2544 #else 2545 struct hermon_hw_udav_s { 2546 uint32_t force_lb :1; 2547 uint32_t :5; 2548 uint32_t portnum :2; 2549 uint32_t pd :24; 2550 2551 uint32_t :8; 2552 uint32_t grh :1; 2553 uint32_t ml_path :7; 2554 uint32_t rlid :16; 2555 2556 uint32_t :9; 2557 uint32_t mgid_index :7; 2558 uint32_t :4; 2559 uint32_t max_stat_rate :4; 2560 uint32_t hop_limit :8; 2561 2562 uint32_t sl :4; 2563 uint32_t tclass :8; 2564 uint32_t flow_label :20; 2565 2566 uint64_t rgid_h; 2567 uint64_t rgid_l; 2568 }; 2569 #endif 2570 #define HERMON_UDAV_MODIFY_MASK0 0xFCFFFFFFFF000000ULL 2571 #define HERMON_UDAV_MODIFY_MASK1 0xFF80F00000000000ULL 2572 2573 2574 /* 2575 * Hermon Queue Pair Context Table (QPC) entries 2576 * The QPC table is a virtually-contiguous memory area residing in HCA 2577 * ICM. Each QPC entry is accessed for reads and writes 2578 * by the HCA while executing work requests on the associated QP. 2579 * 2580 * The following structure is used in the RST2INIT_QP, INIT2INIT_QP, 2581 * INIT2RTR_QP, RTR2RTS_QP, RTS2RTS_QP, SQERR2RTS_QP, TOERR_QP, RTS2SQD_QP, 2582 * SQD2RTS_QP, TORST_QP, and QUERY_QP commands. 2583 * With the exception of the QUERY_QP command, each of these commands reads 2584 * from some portion of the QPC in the input mailbox and modified the QPC 2585 * stored in the hardware. The QUERY_QP command retrieves a snapshot of a 2586 * QPC entry. The command stores the snapshot in the output mailbox. The 2587 * QPC state and its values are not affected by the QUERY_QP command. 2588 * 2589 * Below we first define the hermon_hw_addr_path_t or "Hermon Address Path" 2590 * structure. This structure is used to provide address path information 2591 * (both primary and secondary) for each QP context. Note: Since this 2592 * structure is _very_ similar to the hermon_hw_udav_t structure above, 2593 * we are able to leverage the similarity with filling in and reading from 2594 * the two types of structures. See hermon_get_addr_path() and 2595 * hermon_set_addr_path() in hermon_misc.c for more details. 2596 */ 2597 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2598 #pragma pack(4) 2599 #endif 2600 2601 #ifdef _LITTLE_ENDIAN 2602 struct hermon_hw_addr_path_s { 2603 uint32_t rlid :16; 2604 uint32_t mlid :7; 2605 uint32_t grh :1; 2606 uint32_t cntr_idx :8; 2607 2608 uint32_t pkey_indx :7; 2609 uint32_t :22; 2610 uint32_t :2; /* but may be used for enet */ 2611 uint32_t force_lb :1; 2612 2613 uint32_t flow_label :20; 2614 uint32_t tclass :8; 2615 uint32_t :4; 2616 2617 uint32_t hop_limit :8; 2618 uint32_t max_stat_rate :4; 2619 uint32_t :4; 2620 uint32_t mgid_index :7; 2621 uint32_t :4; 2622 uint32_t ack_timeout :5; 2623 2624 uint64_t rgid_h; 2625 uint64_t rgid_l; 2626 2627 uint32_t :32; /* but may be used for enet */ 2628 2629 uint32_t :12; /* but may be used for enet */ 2630 uint32_t fsip :1; 2631 uint32_t :3; 2632 uint32_t :7; 2633 uint32_t :1; 2634 uint32_t sched_q :8; 2635 2636 2637 uint32_t :32; 2638 }; 2639 #else 2640 struct hermon_hw_addr_path_s { 2641 uint32_t force_lb :1; 2642 uint32_t :2; /* but may be used for enet */ 2643 uint32_t :22; 2644 uint32_t pkey_indx :7; 2645 2646 uint32_t cntr_idx :8; 2647 uint32_t grh :1; 2648 uint32_t mlid :7; 2649 uint32_t rlid :16; 2650 2651 uint32_t ack_timeout :5; 2652 uint32_t :4; 2653 uint32_t mgid_index :7; 2654 uint32_t :4; 2655 uint32_t max_stat_rate :4; 2656 uint32_t hop_limit :8; 2657 2658 uint32_t :4; 2659 uint32_t tclass :8; 2660 uint32_t flow_label :20; 2661 2662 uint64_t rgid_h; 2663 uint64_t rgid_l; 2664 2665 uint32_t sched_q :8; 2666 uint32_t :1; 2667 uint32_t :7; 2668 uint32_t :3; 2669 uint32_t fsip :1; 2670 uint32_t :12; /* but may be used for enet */ 2671 2672 uint32_t :32; /* but may be used for enet */ 2673 2674 uint32_t :32; 2675 }; 2676 #endif /* LITTLE ENDIAN */ 2677 2678 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2679 #pragma pack() 2680 #endif 2681 2682 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2683 #pragma pack(4) 2684 #endif 2685 #ifdef _LITTLE_ENDIAN 2686 struct hermon_hw_qpc_s { 2687 uint32_t pd :24; 2688 uint32_t :8; 2689 2690 uint32_t :11; 2691 uint32_t pm_state :2; 2692 uint32_t rss :1; 2693 uint32_t :2; 2694 uint32_t serv_type :8; 2695 uint32_t :4; 2696 uint32_t state :4; 2697 2698 uint32_t usr_page :24; 2699 uint32_t :8; 2700 2701 uint32_t :4; 2702 uint32_t rlky :1; 2703 uint32_t :3; 2704 uint32_t log_sq_stride :3; 2705 uint32_t log_sq_size :4; 2706 uint32_t sq_no_prefetch :1; 2707 uint32_t log_rq_stride :3; 2708 uint32_t log_rq_size :4; 2709 uint32_t :1; 2710 uint32_t msg_max :5; 2711 uint32_t mtu :3; 2712 2713 uint32_t rem_qpn :24; 2714 uint32_t :8; 2715 2716 uint32_t loc_qpn :24; 2717 uint32_t :8; 2718 2719 hermon_hw_addr_path_t pri_addr_path; 2720 2721 hermon_hw_addr_path_t alt_addr_path; 2722 2723 uint32_t :32; 2724 2725 uint32_t :5; 2726 uint32_t cur_retry_cnt :3; 2727 uint32_t cur_rnr_retry :3; 2728 uint32_t fre :1; 2729 uint32_t :1; 2730 uint32_t rnr_retry :3; 2731 uint32_t retry_cnt :3; 2732 uint32_t :2; 2733 uint32_t sra_max :3; 2734 uint32_t :4; 2735 uint32_t ack_req_freq :4; 2736 2737 uint32_t cqn_snd :24; 2738 uint32_t :8; 2739 2740 uint32_t next_snd_psn :24; 2741 uint32_t :8; 2742 2743 uint32_t :32; 2744 2745 uint32_t :32; 2746 2747 uint32_t ssn :24; 2748 uint32_t :8; 2749 2750 uint32_t last_acked_psn :24; 2751 uint32_t :8; 2752 2753 uint32_t next_rcv_psn :24; 2754 uint32_t min_rnr_nak :5; 2755 uint32_t :3; 2756 2757 uint32_t :4; 2758 uint32_t ric :1; 2759 uint32_t :1; 2760 uint32_t page_offs :6; 2761 uint32_t :1; 2762 uint32_t rae :1; 2763 uint32_t rwe :1; 2764 uint32_t rre :1; 2765 uint32_t :5; 2766 uint32_t rra_max :3; 2767 uint32_t :8; 2768 2769 uint32_t cqn_rcv :24; 2770 uint32_t :8; 2771 2772 uint32_t srcd :16; 2773 uint32_t :16; 2774 2775 uint32_t :2; 2776 uint32_t dbr_addrl :30; 2777 2778 uint32_t dbr_addrh :32; 2779 2780 uint32_t srq_number :24; 2781 uint32_t srq_en :1; 2782 uint32_t :7; 2783 2784 uint32_t qkey; 2785 2786 uint32_t sq_wqe_counter :16; 2787 uint32_t rq_wqe_counter :16; 2788 2789 uint32_t rmsn :24; 2790 uint32_t :8; 2791 2792 uint32_t rsrv0[2]; 2793 2794 /* new w/ hermon */ 2795 2796 uint32_t base_mkey :24; /* bits 32-8, low 7 m/b 0 */ 2797 uint32_t num_rmc_peers :8; 2798 2799 uint32_t rmc_parent_qpn :24; 2800 uint32_t header_sep :1; 2801 uint32_t inline_scatter :1; /* m/b 0 for srq */ 2802 uint32_t :1; 2803 uint32_t rmc_enable :2; 2804 uint32_t :2; /* may use one bit for enet */ 2805 uint32_t mkey_remap :1; 2806 2807 uint32_t :3; 2808 uint32_t mtt_base_addrl :29; 2809 2810 uint32_t mtt_base_addrh :8; 2811 uint32_t :16; 2812 uint32_t log2_pgsz :6; 2813 uint32_t :2; 2814 2815 uint32_t rsvd[12]; /* may/will be used for FCoIB */ 2816 }; 2817 #else /* BIG ENDIAN */ 2818 struct hermon_hw_qpc_s { 2819 uint32_t state :4; 2820 uint32_t :4; 2821 uint32_t serv_type :8; 2822 uint32_t :2; 2823 uint32_t rss :1; 2824 uint32_t pm_state :2; 2825 uint32_t :11; 2826 2827 uint32_t :8; 2828 uint32_t pd :24; 2829 2830 uint32_t mtu :3; 2831 uint32_t msg_max :5; 2832 uint32_t :1; 2833 uint32_t log_rq_size :4; 2834 uint32_t log_rq_stride :3; 2835 uint32_t sq_no_prefetch :1; 2836 uint32_t log_sq_size :4; 2837 uint32_t log_sq_stride :3; 2838 uint32_t :3; 2839 uint32_t rlky :1; 2840 uint32_t :4; 2841 2842 uint32_t :8; 2843 uint32_t usr_page :24; 2844 2845 uint32_t :8; 2846 uint32_t loc_qpn :24; 2847 2848 uint32_t :8; 2849 uint32_t rem_qpn :24; 2850 2851 hermon_hw_addr_path_t pri_addr_path; 2852 2853 hermon_hw_addr_path_t alt_addr_path; 2854 2855 uint32_t ack_req_freq :4; 2856 uint32_t :4; 2857 uint32_t sra_max :3; 2858 uint32_t :2; 2859 uint32_t retry_cnt :3; 2860 uint32_t rnr_retry :3; 2861 uint32_t :1; 2862 uint32_t fre :1; 2863 uint32_t cur_rnr_retry :3; 2864 uint32_t cur_retry_cnt :3; 2865 uint32_t :5; 2866 2867 uint32_t :32; 2868 2869 uint32_t :8; 2870 uint32_t next_snd_psn :24; 2871 2872 uint32_t :8; 2873 uint32_t cqn_snd :24; 2874 2875 uint32_t :32; 2876 2877 uint32_t :32; 2878 2879 uint32_t :8; 2880 uint32_t last_acked_psn :24; 2881 2882 uint32_t :8; 2883 uint32_t ssn :24; 2884 2885 uint32_t :8; 2886 uint32_t rra_max :3; 2887 uint32_t :5; 2888 uint32_t rre :1; 2889 uint32_t rwe :1; 2890 uint32_t rae :1; 2891 uint32_t :1; 2892 uint32_t page_offs :6; 2893 uint32_t :1; 2894 uint32_t ric :1; 2895 uint32_t :4; 2896 2897 uint32_t :3; 2898 uint32_t min_rnr_nak :5; 2899 uint32_t next_rcv_psn :24; 2900 2901 uint32_t :16; 2902 uint32_t srcd :16; 2903 2904 uint32_t :8; 2905 uint32_t cqn_rcv :24; 2906 2907 uint32_t dbr_addrh :32; 2908 2909 uint32_t dbr_addrl :30; 2910 uint32_t :2; 2911 2912 uint32_t qkey; 2913 2914 uint32_t :7; 2915 uint32_t srq_en :1; 2916 uint32_t srq_number :24; 2917 2918 uint32_t :8; 2919 uint32_t rmsn :24; 2920 2921 uint32_t rq_wqe_counter :16; 2922 uint32_t sq_wqe_counter :16; 2923 2924 uint32_t rsrv0[2]; 2925 2926 /* new w/ hermon */ 2927 2928 uint32_t mkey_remap :1; 2929 uint32_t :2; /* may use one bit for enet */ 2930 uint32_t rmc_enable :2; 2931 uint32_t :1; 2932 uint32_t inline_scatter :1; /* m/b 0 for srq */ 2933 uint32_t header_sep :1; 2934 uint32_t rmc_parent_qpn :24; 2935 2936 uint32_t num_rmc_peers :8; 2937 uint32_t base_mkey :24; /* bits 32-8, low 7 m/b 0 */ 2938 2939 uint32_t :2; 2940 uint32_t log2_pgsz :6; 2941 uint32_t :16; 2942 uint32_t mtt_base_addrh :8; 2943 2944 uint32_t mtt_base_addrl :29; 2945 uint32_t :3; 2946 2947 uint32_t rsvd[12]; /* may/will be used for FCoIB */ 2948 }; 2949 #endif /* LITTLE ENDIAN */ 2950 2951 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2952 #pragma pack() 2953 #endif 2954 2955 #define HERMON_QP_RESET 0x0 2956 #define HERMON_QP_INIT 0x1 2957 #define HERMON_QP_RTR 0x2 2958 #define HERMON_QP_RTS 0x3 2959 #define HERMON_QP_SQERR 0x4 2960 #define HERMON_QP_SQD 0x5 2961 #define HERMON_QP_ERR 0x6 2962 #define HERMON_QP_SQDRAINING 0x7 2963 2964 #define HERMON_QP_RC 0x0 2965 #define HERMON_QP_UC 0x1 2966 #define HERMON_QP_UD 0x3 2967 #define HERMON_QP_MLX 0x7 2968 2969 #define HERMON_QP_PMSTATE_MIGRATED 0x3 2970 #define HERMON_QP_PMSTATE_ARMED 0x0 2971 #define HERMON_QP_PMSTATE_REARM 0x1 2972 2973 #define HERMON_QP_DESC_EVT_DISABLED 0x0 2974 #define HERMON_QP_DESC_EVT_ENABLED 0x1 2975 2976 #define HERMON_QP_FLIGHT_LIM_UNLIMITED 0xF 2977 2978 #define HERMON_QP_SQ_ALL_SIGNALED 0x1 2979 #define HERMON_QP_SQ_WR_SIGNALED 0x0 2980 #define HERMON_QP_RQ_ALL_SIGNALED 0x1 2981 #define HERMON_QP_RQ_WR_SIGNALED 0x0 2982 2983 #define HERMON_QP_SRQ_ENABLED 0x1 2984 #define HERMON_QP_SRQ_DISABLED 0x0 2985 2986 #define HERMON_QP_WQE_BASE_SHIFT 0x6 2987 2988 /* 2989 * Hermon Multicast Group Member (MCG) 2990 * Hermon MCG are organized in a virtually-contiguous memory table (the 2991 * Multicast Group Table) in the ICM. This table is 2992 * actually comprised of two consecutive tables: the Multicast Group Hash 2993 * Table (MGHT) and the Additional Multicast Group Members Table (AMGM). 2994 * Each such entry contains an MGID and a list of QPs that are attached to 2995 * the multicast group. Each such entry may also include an index to an 2996 * Additional Multicast Group Member Table (AMGM) entry. The AMGMs are 2997 * used to form a linked list of MCG entries that all map to the same hash 2998 * value. The MCG entry size is configured through the INIT_HCA command. 2999 * Note: An MCG actually consists of a single hermon_hw_mcg_t and some 3000 * number of hermon_hw_mcg_qp_list_t (such that the combined structure is a 3001 * power-of-2). 3002 * 3003 * The following structures are used in the READ_MGM and WRITE_MGM commands. 3004 * The READ_MGM command reads an MCG entry from the multicast table and 3005 * returns it in the output mailbox. Note: This operation does not affect 3006 * the MCG entry state or values. 3007 * The WRITE_MGM command retrieves an MCG entry from the input mailbox and 3008 * stores it in the multicast group table at the index specified in the 3009 * command. Once the command has finished execution, the multicast group 3010 * table is updated. The old entry contents are lost. 3011 */ 3012 #ifdef _LITTLE_ENDIAN 3013 struct hermon_hw_mcg_s { 3014 uint32_t member_cnt :24; 3015 uint32_t :8; 3016 3017 uint32_t :6; 3018 uint32_t next_gid_indx :26; 3019 3020 uint32_t :32; 3021 uint32_t :32; 3022 3023 uint64_t mgid_h; 3024 uint64_t mgid_l; 3025 }; 3026 #else 3027 struct hermon_hw_mcg_s { 3028 uint32_t next_gid_indx :26; 3029 uint32_t :6; 3030 3031 uint32_t :8; 3032 uint32_t member_cnt :24; 3033 3034 uint32_t :32; 3035 uint32_t :32; 3036 3037 uint64_t mgid_h; 3038 uint64_t mgid_l; 3039 }; 3040 #endif 3041 3042 3043 /* Multicast Group Member - QP List entries */ 3044 #ifdef _LITTLE_ENDIAN 3045 struct hermon_hw_mcg_qp_list_s { 3046 uint32_t qpn :24; 3047 uint32_t :6; 3048 uint32_t blk_lb :1; 3049 uint32_t :1; 3050 }; 3051 #else 3052 struct hermon_hw_mcg_qp_list_s { 3053 uint32_t :1; 3054 uint32_t blk_lb :1; 3055 uint32_t :6; 3056 uint32_t qpn :24; 3057 }; 3058 #endif 3059 3060 #define HERMON_MCG_QPN_BLOCK_LB 0x40000000 3061 3062 /* 3063 * Structure for getting the peformance counters from the HCA 3064 */ 3065 3066 #ifdef _LITTLE_ENDIAN 3067 struct hermon_hw_sm_perfcntr_s { 3068 uint32_t linkdown :8; 3069 uint32_t linkerrrec :8; 3070 uint32_t symerr :16; 3071 3072 uint32_t cntrsel :16; 3073 uint32_t portsel :8; 3074 uint32_t :8; 3075 3076 uint32_t portxmdiscard :16; 3077 uint32_t portrcvswrelay :16; 3078 3079 uint32_t portrcvrem :16; 3080 uint32_t portrcv :16; 3081 3082 uint32_t vl15drop :16; 3083 uint32_t :16; 3084 3085 uint32_t xsbuffovrun :4; 3086 uint32_t locallinkint :4; 3087 uint32_t :8; 3088 uint32_t portrcconstr :8; 3089 uint32_t portxmconstr :8; 3090 3091 uint32_t portrcdata; 3092 3093 uint32_t portxmdata; 3094 3095 uint32_t portrcpkts; 3096 3097 uint32_t portxmpkts; 3098 3099 uint32_t reserved; 3100 3101 uint32_t portxmwait; 3102 }; 3103 #else /* BIG ENDIAN */ 3104 struct hermon_hw_sm_perfcntr_s { 3105 uint32_t :8; 3106 uint32_t portsel :8; 3107 uint32_t cntrsel :16; 3108 3109 uint32_t symerr :16; 3110 uint32_t linkerrrec :8; 3111 uint32_t linkdown :8; 3112 3113 uint32_t portrcv :16; 3114 uint32_t portrcvrem :16; 3115 3116 uint32_t portrcvswrelay :16; 3117 uint32_t portxmdiscard :16; 3118 3119 uint32_t portxmconstr :8; 3120 uint32_t portrcconstr :8; 3121 uint32_t :8; 3122 uint32_t locallinkint :4; 3123 uint32_t xsbuffovrun :4; 3124 3125 uint32_t :16; 3126 uint32_t vl15drop :16; 3127 3128 uint32_t portxmdata; 3129 3130 uint32_t portrcdata; 3131 3132 uint32_t portxmpkts; 3133 3134 uint32_t portrcpkts; 3135 3136 uint32_t portxmwait; 3137 3138 uint32_t reserved; 3139 }; 3140 #endif 3141 3142 /* 3143 * Structure for getting the extended peformance counters from the HCA 3144 */ 3145 3146 #ifdef _LITTLE_ENDIAN 3147 struct hermon_hw_sm_extperfcntr_s { 3148 uint32_t rsvd; 3149 uint32_t cntrsel :16; 3150 uint32_t portsel :8; 3151 uint32_t :8; 3152 3153 uint64_t portxmdata; 3154 3155 uint64_t portrcdata; 3156 3157 uint64_t portxmpkts; 3158 3159 uint64_t portrcpkts; 3160 3161 uint64_t portunicastxmpkts; 3162 3163 uint64_t portunicastrcpkts; 3164 3165 uint64_t portmulticastxmpkts; 3166 3167 uint64_t portmulticastrcpkts; 3168 }; 3169 #else /* BIG ENDIAN */ 3170 struct hermon_hw_sm_extperfcntr_s { 3171 uint32_t :8; 3172 uint32_t portsel :8; 3173 uint32_t cntrsel :16; 3174 uint32_t rsvd; 3175 3176 uint64_t portxmdata; 3177 3178 uint64_t portrcdata; 3179 3180 uint64_t portxmpkts; 3181 3182 uint64_t portrcpkts; 3183 3184 uint64_t portunicastxmpkts; 3185 3186 uint64_t portunicastrcpkts; 3187 3188 uint64_t portmulticastxmpkts; 3189 3190 uint64_t portmulticastrcpkts; 3191 }; 3192 #endif 3193 3194 3195 /* 3196 * Hermon User Access Region (UAR) 3197 * 3198 * JBDB : writeup on the UAR for memfree 3199 * 3200 * JBDB : writeup on the structures 3201 * UAR page 3202 * DB register 3203 * DB record 3204 * UCE 3205 * 3206 * [es] and change it even further for hermon 3207 * the whole UAR and doorbell record (dbr) approach is changed again 3208 * from arbel, and needs commenting 3209 * 3210 * -- Tavor comment 3211 * 3212 * 3213 * Tavor doorbells are each rung by writing to the doorbell registers that 3214 * form a User Access Region (UAR). A doorbell is a write-only hardware 3215 * register which enables passing information from software to hardware 3216 * with minimum software latency. A write operation from the host software 3217 * to these doorbell registers passes information about the HCA resources 3218 * and initiates processing of the doorbell data. There are 6 types of 3219 * doorbells in Tavor. 3220 * 3221 * "Send Doorbell" for synchronizing the attachment of a WQE (or a chain 3222 * of WQEs) to the send queue. 3223 * "RD Send Doorbell" (Same as above, except for RD QPs) is not supported. 3224 * "Receive Doorbell" for synchronizing the attachment of a WQE (or a chain 3225 * of WQEs) to the receive queue. 3226 * "CQ Doorbell" for updating the CQ consumer index and requesting 3227 * completion notifications. 3228 * "EQ Doorbell" for updating the EQ consumer index, arming interrupt 3229 * triggering, and disarming CQ notification requests. 3230 * "InfiniBlast" (which would have enabled access to the "InfiniBlast 3231 * buffer") is not supported. 3232 * 3233 * Note: The tavor_hw_uar_t below is the container for all of the various 3234 * doorbell types. Below we first define several structures which make up 3235 * the contents of those doorbell types. 3236 * 3237 * Note also: The following structures are not #define'd with both little- 3238 * endian and big-endian definitions. This is because each doorbell type 3239 * is not directly accessed except through a single ddi_put64() operation 3240 * (see tavor_qp_send_doorbell, tavor_qp_recv_doorbell, tavor_cq_doorbell, 3241 * or tavor_eq_doorbell) 3242 */ 3243 3244 /* 3245 * Send doorbell register structure 3246 */ 3247 typedef struct hermon_hw_send_db_reg_s { 3248 uint32_t :32; 3249 3250 uint32_t snd_q_num :24; 3251 uint32_t :8; 3252 } hermon_hw_send_db_reg_t; 3253 3254 #define HERMON_QPSNDDB_QPN_SHIFT 0x8 3255 3256 /* Max descriptors per Hermon doorbell */ 3257 #define HERMON_QP_MAXDESC_PER_DB 256 3258 3259 /* 3260 * CQ doorbell register structure 3261 */ 3262 typedef struct hermon_hw_cq_db_reg_s { 3263 uint32_t :2; 3264 uint32_t cmd_sn :2; 3265 uint32_t :2; 3266 uint32_t cmd :2; 3267 uint32_t cqn :24; 3268 3269 uint32_t :8; 3270 /* consumer cntr of last polled completion */ 3271 uint32_t cq_ci :24; 3272 } hermon_hw_cq_db_reg_t; 3273 3274 #define HERMON_CQDB_CMD_SHIFT 0x18 /* dec 24 */ 3275 #define HERMON_CQDB_CMDSN_SHIFT 0x1C /* dec 28 */ 3276 3277 3278 #define HERMON_CQDB_NOTIFY_CQ 0x02 3279 #define HERMON_CQDB_NOTIFY_CQ_SOLICIT 0x01 3280 3281 /* Default value for use in NOTIFY_CQ doorbell */ 3282 #define HERMON_CQDB_DEFAULT_PARAM 0xFFFFFFFF 3283 3284 typedef struct hermon_hw_guest_eq_ci_s { /* guest op eq consumer index */ 3285 uint32_t armed :1; 3286 uint32_t :7; 3287 uint32_t guestos_ci :24; 3288 3289 uint32_t :32; 3290 } hermon_hw_guest_eq_ci_t; 3291 3292 3293 3294 /* 3295 * UAR page structure, containing all doorbell registers 3296 */ 3297 struct hermon_hw_uar_s { 3298 uint32_t rsrv0[4]; 3299 3300 hermon_hw_send_db_reg_t send; 3301 3302 uint32_t rsrv1[2]; 3303 3304 hermon_hw_cq_db_reg_t cq; 3305 3306 uint32_t rsrv2[502]; /* next is at offset 0x800 */ 3307 3308 hermon_hw_guest_eq_ci_t g_eq0; 3309 hermon_hw_guest_eq_ci_t g_eq1; 3310 hermon_hw_guest_eq_ci_t g_eq2; 3311 hermon_hw_guest_eq_ci_t g_eq3; 3312 3313 uint32_t rsrv3[504]; /* end of page */ 3314 }; 3315 3316 /* 3317 * QP (RQ, SRQ) doorbell record-specific data 3318 * Note that this structure is NOT in ICM, but just kept in host memory 3319 * and managed independently of PRM or other constraints. Also, though 3320 * the qp/srq doorbell need to be only 4 bytes, it is 8 bytes in memory for 3321 * ease of management. Hermon defines its usage in the QP chapter. 3322 */ 3323 typedef struct hermon_hw_qp_db_s { 3324 uint32_t :16; 3325 uint32_t rcv_wqe_cntr :16; /* wqe_counter */ 3326 3327 uint32_t :32; 3328 } hermon_hw_qp_db_t; 3329 3330 /* 3331 * CQ (ARM and SET_CI) doorbell record-specific data 3332 * See comment above re: QP doorbell. This dbr is 8 bytes long, and its 3333 * usage is defined in PRM chapter on Completion Queues 3334 */ 3335 typedef struct hermon_hw_cq_arm_db_s { 3336 uint32_t :8; 3337 uint32_t update_ci :24; 3338 3339 uint32_t :2; 3340 /* sequence number of the doorbell ring % 4 */ 3341 uint32_t cmd_sn :2; 3342 uint32_t :1; 3343 uint32_t cmd :3; /* command */ 3344 uint32_t cq_ci :24; 3345 } hermon_hw_cq_db_t; 3346 3347 #define HERMON_CQ_DB_CMD_SOLICTED 0x01 3348 #define HERMON_CQ_DB_CMD_NEXT 0x02 3349 3350 3351 /* 3352 * Hermon Blue Flame (BF) 3353 * Hermon has the ability to do a low-latency write of successive WQEs 3354 * for the HCA. This utilizes part of the memory area behind the 3355 * same BAR as the UAR page (see above) - half the area is devoted to 3356 * UAR pages, the other half to BlueFlame (though in fairness, the return 3357 * information from QUERY_DEV_CAP should be consulted _in case_ they ever 3358 * decide to change it. 3359 * 3360 * We define the structures to access them below. 3361 */ 3362 3363 3364 /* 3365 * Hermon Send Work Queue Element (WQE) 3366 * A Hermon Send WQE is built of the following segments, each of which is a 3367 * multiple of 16 bytes. Note: Each individual WQE may contain only a 3368 * subset of these segments described below (according to the operation type 3369 * and transport type of the QP). 3370 * 3371 * The first 16 bytes of ever WQE are formed from the "Ctrl" segment. 3372 * This segment contains the address of the next WQE to be executed and the 3373 * information required in order to allocate the resources to execute the 3374 * next WQE. The "Ctrl" part of this segment contains the control 3375 * information required to execute the WQE, including the opcode and other 3376 * control information. 3377 * The "Datagram" segment contains address information required in order to 3378 * form a UD message. 3379 * The "Bind" segment contains the parameters required for a Bind Memory 3380 * Window operation. 3381 * The "Remote Address" segment is present only in RDMA or Atomic WQEs and 3382 * specifies remote virtual addresses and RKey, respectively. Length of 3383 * the remote access is calculated from the scatter/gather list (for 3384 * RDMA-write/RDMA-read) or set to eight (for Atomic). 3385 * The "Atomic" segment is present only in Atomic WQEs and specifies 3386 * Swap/Add and Compare data. 3387 * 3388 * Note: The following structures are not #define'd with both little-endian 3389 * and big-endian definitions. This is because their individual fields are 3390 * not directly accessed except through macros defined below. 3391 */ 3392 3393 3394 struct hermon_hw_snd_wqe_ctrl_s { 3395 uint32_t owner :1; 3396 /* NOTE: some/many may be used by enet */ 3397 uint32_t :26; 3398 uint32_t opcode :5; 3399 /* NOTE: some will be used by enet */ 3400 uint32_t :25; 3401 uint32_t fence :1; 3402 /* WQE size in octowords */ 3403 uint32_t ds :6; 3404 /* SRC remote buffer if impl */ 3405 uint32_t src_rem_buf :24; 3406 uint32_t so :1; 3407 uint32_t :1; /* FCoIB only */ 3408 uint32_t tcp_udp :1; /* Checksumming */ 3409 uint32_t ip :1; /* Checksumming */ 3410 uint32_t cq_gen :2; /* 00=no cqe, 11= gen cqe */ 3411 /* set means solicit bit in last packet */ 3412 uint32_t s :1; 3413 uint32_t force_lb :1; 3414 3415 uint32_t immediate :32; 3416 }; 3417 3418 struct hermon_hw_srq_wqe_next_s { 3419 uint32_t :16; 3420 uint32_t next_wqe_idx :16; 3421 3422 uint32_t rsvd[3]; 3423 }; 3424 3425 3426 #define HERMON_WQE_SEND_FENCE_MASK 0x40 3427 3428 #define HERMON_WQE_SEND_NOPCODE_NOP 0x00 3429 #define HERMON_WQE_SEND_NOPCODE_SND_INV 0x01 3430 #define HERMON_WQE_SEND_NOPCODE_RDMAW 0x8 3431 #define HERMON_WQE_SEND_NOPCODE_RDMAWI 0x9 3432 #define HERMON_WQE_SEND_NOPCODE_SEND 0xA 3433 #define HERMON_WQE_SEND_NOPCODE_SENDI 0xB 3434 #define HERMON_WQE_SEND_NOPCODE_LSO 0xE 3435 #define HERMON_WQE_SEND_NOPCODE_RDMAR 0x10 3436 #define HERMON_WQE_SEND_NOPCODE_ATMCS 0x11 3437 #define HERMON_WQE_SEND_NOPCODE_ATMFA 0x12 3438 #define HERMON_WQE_SEND_NOPCODE_ATMCSE 0x14 3439 #define HERMON_WQE_SEND_NOPCODE_ATMFAE 0x15 3440 #define HERMON_WQE_SEND_NOPCODE_BIND 0x18 3441 #define HERMON_WQE_SEND_NOPCODE_FRWR 0x19 3442 #define HERMON_WQE_SEND_NOPCODE_LCL_INV 0x1B 3443 #define HERMON_WQE_SEND_NOPCODE_CONFIG 0x1F /* for ccq only */ 3444 3445 #define HERMON_WQE_SEND_SIGNALED_MASK 0x0000000C00000000ull 3446 #define HERMON_WQE_SEND_SOLICIT_MASK 0x0000000200000000ull 3447 #define HERMON_WQE_SEND_IMMEDIATE_MASK 0x0000000100000000ull 3448 3449 struct hermon_hw_snd_wqe_ud_s { 3450 struct hermon_hw_udav_s ud_addr_v; 3451 3452 uint32_t :8; 3453 uint32_t dest_qp :24; 3454 uint32_t qkey :32; 3455 uint32_t :32; 3456 uint32_t :32; 3457 }; 3458 #define HERMON_WQE_SENDHDR_UD_AV_MASK 0xFFFFFFFFFFFFFFE0ull 3459 #define HERMON_WQE_SENDHDR_UD_DQPN_MASK 0xFFFFFF 3460 3461 struct hermon_hw_snd_wqe_bind_s { 3462 uint32_t ae :1; 3463 uint32_t rw :1; 3464 uint32_t rr :1; 3465 uint32_t :3; 3466 uint32_t l_64 :1; 3467 uint32_t :25; 3468 3469 uint32_t win_t :1; 3470 uint32_t z_base :1; 3471 uint32_t :30; 3472 3473 uint32_t new_rkey; 3474 uint32_t reg_lkey; 3475 uint64_t addr; 3476 uint64_t len; 3477 }; 3478 #define HERMON_WQE_SENDHDR_BIND_ATOM 0x8000000000000000ull 3479 #define HERMON_WQE_SENDHDR_BIND_WR 0x4000000000000000ull 3480 #define HERMON_WQE_SENDHDR_BIND_RD 0x2000000000000000ull 3481 3482 struct hermon_hw_snd_wqe_remaddr_s { 3483 uint64_t vaddr; 3484 uint32_t rkey; 3485 uint32_t :32; 3486 }; 3487 3488 struct hermon_hw_snd_wqe_atomic_s { 3489 uint64_t swap_add; 3490 uint64_t compare; 3491 }; 3492 3493 struct hermon_hw_snd_wqe_atomic_ext_s { 3494 uint64_t swap_add; 3495 uint64_t compare; 3496 uint64_t swapmask; 3497 uint64_t cmpmask; 3498 }; 3499 3500 3501 3502 struct hermon_hw_snd_wqe_local_inv_s { 3503 uint32_t :6; 3504 uint32_t atc_shoot :1; 3505 uint32_t :25; 3506 3507 uint32_t :32; 3508 3509 uint32_t mkey; 3510 3511 uint32_t :25; 3512 uint32_t guest_id :7; /* for atc shootdown */ 3513 3514 uint32_t rsrv0[6]; 3515 3516 uint32_t p_addrh; 3517 uint32_t p_addrl :23; 3518 uint32_t :9; 3519 }; 3520 3521 struct hermon_hw_snd_wqe_frwr_s { 3522 uint32_t rem_atomic :1; 3523 uint32_t rem_write :1; 3524 uint32_t rem_read :1; 3525 uint32_t loc_write :1; 3526 uint32_t loc_read :1; 3527 uint32_t fbo_en :1; 3528 uint32_t len_64 :1; 3529 uint32_t :3; /* but some for FCoIB */ 3530 uint32_t bind_en :1; 3531 uint32_t blk_pg_mode :1; 3532 uint32_t mtt_rep :4; 3533 uint32_t :16; 3534 3535 uint32_t mkey; /* swapped w/ addrh relative to arbel */ 3536 3537 uint32_t pbl_addrh; 3538 3539 uint32_t pbl_addrl :26; 3540 uint32_t :6; 3541 3542 uint64_t start_addr; 3543 3544 uint64_t reg_len; /* w/ len_64 allows 65 bits of length */ 3545 3546 uint32_t :11; 3547 uint32_t fbo :21; 3548 3549 uint32_t :11; 3550 uint32_t pge_blk_sz :21; 3551 3552 uint32_t rsrv0[2]; 3553 }; 3554 3555 /* 3556 * NOTE: Some hermon-PRM defined Send WQE segments are not defined here 3557 * because they will not be used initially: they should be added and 3558 * used later on: 3559 * FCP-3 init 3560 * FCP-3 Control 3561 * Large Send Offload 3562 * 3563 */ 3564 3565 /* 3566 * Hermon "MLX transport" Work Queue Element (WQE) 3567 * The format of the MLX WQE is similar to that of the Send WQE (above) 3568 * with the following exceptions. MLX WQEs are used for sending MADs on 3569 * special QPs 0 and 1. Everything following the "Next/Ctrl" header 3570 * (defined below) consists of scatter-gather list entries. The contents 3571 * of these SGLs (also defined below) will be put on the wire exactly as 3572 * they appear in the buffers. In addition, the VCRC and the ICRC of each 3573 * sent packet can be modified by changing values in the following header 3574 * or in the payload of the packet itself. 3575 */ 3576 3577 3578 struct hermon_hw_mlx_wqe_nextctrl_s { 3579 uint32_t owner :1; 3580 uint32_t :23; 3581 uint32_t :3; 3582 uint32_t opcode :5; /* is 0x0A (send) for MLX */ 3583 3584 uint32_t :26; 3585 uint32_t ds :6; /* WQE size in octowords */ 3586 3587 uint32_t :14; 3588 uint32_t vl15 :1; 3589 uint32_t slr :1; 3590 uint32_t max_srate :4; 3591 uint32_t sl :4; 3592 uint32_t :3; /* FCoIB usage */ 3593 uint32_t icrc :1; /* 1==don't replace icrc fld */ 3594 uint32_t cq_gen :2; /* 00= no cqe, 11==cqe */ 3595 uint32_t :1; 3596 uint32_t force_lb :1; 3597 3598 uint32_t rlid :16; 3599 uint32_t :16; 3600 }; 3601 3602 3603 #define HERMON_WQE_MLXHDR_VL15_MASK 0x0002000000000000ull 3604 #define HERMON_WQE_MLXHDR_SLR_MASK 0x0001000000000000ull 3605 #define HERMON_WQE_MLXHDR_SRATE_SHIFT 44 3606 #define HERMON_WQE_MLXHDR_SL_SHIFT 40 3607 #define HERMON_WQE_MLXHDR_SIGNALED_MASK 0x0000000800000000ull 3608 #define HERMON_WQE_MLXHDR_RLID_SHIFT 16 3609 3610 3611 /* 3612 * Hermon Receive Work Queue Element (WQE) 3613 * Unlike the Send WQE, the Receive WQE is built ONLY of 16-byte segments. A 3614 * "Next/Ctrl" segment is no longer needed, because of the fixed 3615 * receive queue stride (RQ.STRIDE). It contains just 3616 * some number of scatter list entries for the incoming message. 3617 * 3618 * The format of the scatter-gather list entries is shown below. For 3619 * Receive WQEs the "inline_data" field must be cleared (i.e. data segments 3620 * cannot contain inline data). 3621 */ 3622 3623 3624 struct hermon_hw_wqe_sgl_s { 3625 uint32_t inline_data :1; 3626 uint32_t byte_cnt :31; 3627 3628 uint32_t lkey; 3629 3630 uint64_t addr; 3631 }; 3632 #define HERMON_WQE_SGL_BYTE_CNT_MASK 0x7FFFFFFF 3633 #define HERMON_WQE_SGL_INLINE_MASK 0x80000000 3634 3635 /* 3636 * The following defines are used when building descriptors for special QP 3637 * work requests (i.e. MLX transport WQEs). Note: Because Hermon MLX transport 3638 * requires the driver to build actual IB packet headers, we use these defines 3639 * for the most common fields in those headers. 3640 */ 3641 3642 3643 #define HERMON_MLX_VL15_LVER 0xF0000000 3644 #define HERMON_MLX_VL0_LVER 0x00000000 3645 #define HERMON_MLX_IPVER_TC_FLOW 0x60000000 3646 #define HERMON_MLX_TC_SHIFT 20 3647 #define HERMON_MLX_DEF_PKEY 0xFFFF 3648 #define HERMON_MLX_GSI_QKEY 0x80010000 3649 #define HERMON_MLX_UDSEND_OPCODE 0x64000000 3650 #define HERMON_MLX_DQPN_MASK 0xFFFFFF 3651 3652 /* 3653 * The following macros are used for building each of the individual 3654 * segments that can make up a Hermon WQE. Note: We try not to use the 3655 * structures (with their associated bitfields) here, instead opting to 3656 * build and put 64-bit or 32-bit chunks to the WQEs as appropriate, 3657 * primarily because using the bitfields appears to force more read-modify- 3658 * write operations. 3659 * 3660 * HERMON_WQE_BUILD_UD - Builds Unreliable Datagram Segment 3661 * 3662 * HERMON_WQE_BUILD_REMADDR - Builds Remote Address Segment using 3663 * RDMA info from the work request 3664 * HERMON_WQE_BUILD_RC_ATOMIC_REMADDR - Builds Remote Address Segment 3665 * for RC Atomic work requests 3666 * HERMON_WQE_BUILD_ATOMIC - Builds Atomic Segment using atomic 3667 * info from the work request 3668 * HERMON_WQE_BUILD_BIND - Builds the Bind Memory Window 3669 * Segment using bind info from the 3670 * work request 3671 * HERMON_WQE_BUILD_DATA_SEG - Builds the individual Data Segments 3672 * for Send, Receive, and MLX WQEs 3673 * HERMON_WQE_BUILD_INLINE - Builds an "inline" Data Segment 3674 * (primarily for MLX transport) 3675 * HERMON_WQE_BUILD_INLINE_ICRC - Also builds an "inline" Data Segment 3676 * (but used primarily in the ICRC 3677 * portion of MLX transport WQEs) 3678 * HERMON_WQE_LINKNEXT - Links the current WQE to the 3679 * previous one 3680 * HERMON_WQE_LINKFIRST - Links the first WQE on the current 3681 * chain to the previous WQE 3682 * HERMON_WQE_BUILD_MLX_LRH - Builds the inline LRH header for 3683 * MLX transport MADs 3684 * HERMON_WQE_BUILD_MLX_GRH - Builds the inline GRH header for 3685 * MLX transport MADs 3686 * HERMON_WQE_BUILD_MLX_BTH - Builds the inline BTH header for 3687 * MLX transport MADs 3688 * HERMON_WQE_BUILD_MLX_DETH - Builds the inline DETH header for 3689 * MLX transport MADs 3690 */ 3691 #define HERMON_WQE_BUILD_UD(qp, ud, ah, dest) \ 3692 { \ 3693 uint64_t *tmp; \ 3694 uint64_t *udav; \ 3695 \ 3696 tmp = (uint64_t *)(ud); \ 3697 udav = (uint64_t *)(ah)->ah_udav; \ 3698 tmp[0] = ntohll(udav[0]); \ 3699 tmp[1] = ntohll(udav[1]); \ 3700 tmp[2] = ntohll(udav[2]); \ 3701 tmp[3] = ntohll(udav[3]); \ 3702 tmp[4] = ntohll((((uint64_t)((dest)->ud_dst_qpn & \ 3703 HERMON_WQE_SENDHDR_UD_DQPN_MASK) << 32) | \ 3704 (dest)->ud_qkey)); \ 3705 tmp[5] = 0; \ 3706 } 3707 3708 #define HERMON_WQE_BUILD_LSO(qp, ds, mss, hdr_sz) \ 3709 *(uint32_t *)(ds) = htonl(((mss) << 16) | hdr_sz); 3710 3711 #define HERMON_WQE_BUILD_REMADDR(qp, ra, wr_rdma) \ 3712 { \ 3713 uint64_t *tmp; \ 3714 \ 3715 tmp = (uint64_t *)(ra); \ 3716 tmp[0] = htonll((wr_rdma)->rdma_raddr); \ 3717 tmp[1] = htonll((uint64_t)(wr_rdma)->rdma_rkey << 32); \ 3718 } 3719 3720 #define HERMON_WQE_BUILD_RC_ATOMIC_REMADDR(qp, rc, wr) \ 3721 { \ 3722 uint64_t *tmp; \ 3723 \ 3724 tmp = (uint64_t *)(rc); \ 3725 tmp[0] = htonll((wr)->wr.rc.rcwr.atomic->atom_raddr); \ 3726 tmp[1] = htonll((uint64_t)(wr)->wr.rc.rcwr.atomic->atom_rkey << 32); \ 3727 } 3728 3729 #define HERMON_WQE_BUILD_ATOMIC(qp, at, wr_atom) \ 3730 { \ 3731 uint64_t *tmp; \ 3732 \ 3733 tmp = (uint64_t *)(at); \ 3734 tmp[0] = htonll((wr_atom)->atom_arg2); \ 3735 tmp[1] = htonll((wr_atom)->atom_arg1); \ 3736 } 3737 3738 #define HERMON_WQE_BUILD_BIND(qp, bn, wr_bind) \ 3739 { \ 3740 uint64_t *tmp; \ 3741 uint64_t bn0_tmp; \ 3742 ibt_bind_flags_t bind_flags; \ 3743 \ 3744 tmp = (uint64_t *)(bn); \ 3745 bind_flags = (wr_bind)->bind_flags; \ 3746 bn0_tmp = (bind_flags & IBT_WR_BIND_ATOMIC) ? \ 3747 HERMON_WQE_SENDHDR_BIND_ATOM : 0; \ 3748 bn0_tmp |= (bind_flags & IBT_WR_BIND_WRITE) ? \ 3749 HERMON_WQE_SENDHDR_BIND_WR : 0; \ 3750 bn0_tmp |= (bind_flags & IBT_WR_BIND_READ) ? \ 3751 HERMON_WQE_SENDHDR_BIND_RD : 0; \ 3752 tmp[0] = htonll(bn0_tmp); \ 3753 tmp[1] = htonll(((uint64_t)(wr_bind)->bind_rkey_out << 32) | \ 3754 (wr_bind)->bind_lkey); \ 3755 tmp[2] = htonll((wr_bind)->bind_va); \ 3756 tmp[3] = htonll((wr_bind)->bind_len); \ 3757 } 3758 3759 #define HERMON_WQE_BUILD_DATA_SEG_RECV(ds, sgl) \ 3760 { \ 3761 uint64_t *tmp; \ 3762 \ 3763 tmp = (uint64_t *)(ds); \ 3764 tmp[0] = htonll((((uint64_t)((sgl)->ds_len & \ 3765 HERMON_WQE_SGL_BYTE_CNT_MASK) << 32) | (sgl)->ds_key)); \ 3766 tmp[1] = htonll((sgl)->ds_va); \ 3767 } 3768 #define HERMON_WQE_BUILD_DATA_SEG_SEND(ds, sgl) \ 3769 { \ 3770 ((uint64_t *)(ds))[1] = htonll((sgl)->ds_va); \ 3771 ((uint32_t *)(ds))[1] = htonl((sgl)->ds_key); \ 3772 membar_producer(); \ 3773 ((uint32_t *)(ds))[0] = \ 3774 htonl((sgl)->ds_len & HERMON_WQE_SGL_BYTE_CNT_MASK); \ 3775 } 3776 3777 #define HERMON_WQE_BUILD_INLINE(qp, ds, sz) \ 3778 *(uint32_t *)(ds) = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz)) 3779 3780 #define HERMON_WQE_BUILD_INLINE_ICRC(qp, ds, sz, icrc) \ 3781 { \ 3782 uint32_t *tmp; \ 3783 \ 3784 tmp = (uint32_t *)(ds); \ 3785 tmp[0] = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz)); \ 3786 tmp[1] = htonl(icrc); \ 3787 } 3788 3789 #define HERMON_WQE_SET_CTRL_SEGMENT(desc, desc_sz, fence, \ 3790 imm, sol, sig, ip_cksum, qp) \ 3791 { \ 3792 uint32_t *tmp; \ 3793 uint32_t cntr_tmp; \ 3794 \ 3795 /* do not set the first dword (owner/opcode) here */ \ 3796 tmp = (uint32_t *)desc; \ 3797 cntr_tmp = (fence << 6) | desc_sz; \ 3798 tmp[1] = ntohl(cntr_tmp); \ 3799 cntr_tmp = 0; \ 3800 if ((sol) != 0) cntr_tmp |= 0x02; \ 3801 if ((sig) != 0) cntr_tmp |= 0x0C; \ 3802 /*LINTED*/ \ 3803 if (ip_cksum) cntr_tmp |= 0x30; \ 3804 tmp[2] = ntohl(cntr_tmp); \ 3805 tmp[3] = ntohl(imm); \ 3806 } 3807 3808 #define HERMON_WQE_SET_MLX_CTRL_SEGMENT(desc, desc_sz, sig, maxstat, \ 3809 lid, qp, sl) \ 3810 { \ 3811 uint32_t *tmp; \ 3812 uint32_t cntr_tmp; \ 3813 \ 3814 tmp = (uint32_t *)desc; \ 3815 cntr_tmp = htonl(tmp[0]); \ 3816 cntr_tmp &= 0x80000000; \ 3817 cntr_tmp |= HERMON_WQE_SEND_NOPCODE_SEND; \ 3818 tmp[0] = ntohl(cntr_tmp); \ 3819 tmp[1] = ntohl(desc_sz); \ 3820 cntr_tmp = ((maxstat << 4) | (sl & 0xff)) << 8; \ 3821 if (qp->qp_is_special == HERMON_QP_SMI) \ 3822 cntr_tmp |= (0x02 << 16); \ 3823 if (lid == IB_LID_PERMISSIVE) \ 3824 cntr_tmp |= (0x01 << 16); \ 3825 if ((sig) != 0) \ 3826 cntr_tmp |= 0xC; \ 3827 tmp[2] = ntohl(cntr_tmp); \ 3828 tmp[3] = ntohl((lid) << 16); \ 3829 } 3830 3831 #define HERMON_WQE_BUILD_MLX_LRH(lrh, qp, udav, pktlen) \ 3832 { \ 3833 uint32_t *tmp; \ 3834 uint32_t lrh_tmp; \ 3835 \ 3836 tmp = (uint32_t *)(void *)(lrh); \ 3837 \ 3838 if ((qp)->qp_is_special == HERMON_QP_SMI) { \ 3839 lrh_tmp = HERMON_MLX_VL15_LVER; \ 3840 } else { \ 3841 lrh_tmp = HERMON_MLX_VL0_LVER | ((udav)->sl << 20); \ 3842 } \ 3843 if ((udav)->grh) { \ 3844 lrh_tmp |= (IB_LRH_NEXT_HDR_GRH << 16); \ 3845 } else { \ 3846 lrh_tmp |= (IB_LRH_NEXT_HDR_BTH << 16); \ 3847 } \ 3848 lrh_tmp |= (udav)->rlid; \ 3849 tmp[0] = htonl(lrh_tmp); \ 3850 \ 3851 lrh_tmp = (pktlen) << 16; \ 3852 if ((udav)->rlid == IB_LID_PERMISSIVE) { \ 3853 lrh_tmp |= IB_LID_PERMISSIVE; \ 3854 } else { \ 3855 lrh_tmp |= (udav)->ml_path; \ 3856 } \ 3857 tmp[1] = htonl(lrh_tmp); \ 3858 } 3859 3860 /* 3861 * Note: The GRH payload length, calculated below, is the overall packet 3862 * length (in bytes) minus LRH header and GRH headers. 3863 * 3864 * Also note: Filling in the GIDs in the way we do below is helpful because 3865 * it avoids potential alignment restrictions and/or conflicts. 3866 */ 3867 #define HERMON_WQE_BUILD_MLX_GRH(state, grh, qp, udav, pktlen) \ 3868 { \ 3869 uint32_t *tmp; \ 3870 uint32_t grh_tmp; \ 3871 ib_gid_t sgid; \ 3872 \ 3873 tmp = (uint32_t *)(grh); \ 3874 \ 3875 grh_tmp = HERMON_MLX_IPVER_TC_FLOW; \ 3876 grh_tmp |= (udav)->tclass << HERMON_MLX_TC_SHIFT; \ 3877 grh_tmp |= (udav)->flow_label; \ 3878 tmp[0] = htonl(grh_tmp); \ 3879 \ 3880 grh_tmp = (((pktlen) << 2) - (sizeof (ib_lrh_hdr_t) + \ 3881 sizeof (ib_grh_t))) << 16; \ 3882 grh_tmp |= (IB_GRH_NEXT_HDR_BTH << 8); \ 3883 grh_tmp |= (udav)->hop_limit; \ 3884 tmp[1] = htonl(grh_tmp); \ 3885 \ 3886 sgid.gid_prefix = (state)->hs_sn_prefix[(qp)->qp_portnum]; \ 3887 sgid.gid_guid = (state)->hs_guid[(qp)->qp_portnum] \ 3888 [(udav)->mgid_index]; \ 3889 bcopy(&sgid, &tmp[2], sizeof (ib_gid_t)); \ 3890 bcopy(&(udav)->rgid_h, &tmp[6], sizeof (ib_gid_t)); \ 3891 } 3892 3893 #define HERMON_WQE_BUILD_MLX_BTH(state, bth, qp, wr) \ 3894 { \ 3895 uint32_t *tmp; \ 3896 uint32_t bth_tmp; \ 3897 \ 3898 tmp = (uint32_t *)(bth); \ 3899 \ 3900 bth_tmp = HERMON_MLX_UDSEND_OPCODE; \ 3901 if ((wr)->wr_flags & IBT_WR_SEND_SOLICIT) { \ 3902 bth_tmp |= (IB_BTH_SOLICITED_EVENT_MASK << 16); \ 3903 } \ 3904 if (qp->qp_is_special == HERMON_QP_SMI) { \ 3905 bth_tmp |= HERMON_MLX_DEF_PKEY; \ 3906 } else { \ 3907 bth_tmp |= (state)->hs_pkey[(qp)->qp_portnum] \ 3908 [(qp)->qp_pkeyindx]; \ 3909 } \ 3910 tmp[0] = htonl(bth_tmp); \ 3911 tmp[1] = htonl((wr)->wr.ud.udwr_dest->ud_dst_qpn & \ 3912 HERMON_MLX_DQPN_MASK); \ 3913 tmp[2] = 0x0; \ 3914 } 3915 3916 #define HERMON_WQE_BUILD_MLX_DETH(deth, qp) \ 3917 { \ 3918 uint32_t *tmp; \ 3919 \ 3920 tmp = (uint32_t *)(deth); \ 3921 \ 3922 if ((qp)->qp_is_special == HERMON_QP_SMI) { \ 3923 tmp[0] = 0x0; \ 3924 tmp[1] = 0x0; \ 3925 } else { \ 3926 tmp[0] = htonl(HERMON_MLX_GSI_QKEY); \ 3927 tmp[1] = htonl(0x1); \ 3928 } \ 3929 } 3930 3931 3932 3933 3934 3935 3936 /* 3937 * Flash interface: 3938 * Below we have PCI config space space offsets for flash interface 3939 * access, offsets within Hermon CR space for accessing flash-specific 3940 * information or settings, masks used for flash settings, and 3941 * timeout values for flash operations. 3942 */ 3943 #define HERMON_HW_FLASH_CFG_HWREV 8 3944 #define HERMON_HW_FLASH_CFG_ADDR 88 3945 #define HERMON_HW_FLASH_CFG_DATA 92 3946 3947 #define HERMON_HW_FLASH_RESET_AMD 0xF0 3948 #define HERMON_HW_FLASH_RESET_INTEL 0xFF 3949 #define HERMON_HW_FLASH_CPUMODE 0xF0150 3950 #define HERMON_HW_FLASH_ADDR 0xF01A4 3951 #define HERMON_HW_FLASH_DATA 0xF01A8 3952 #define HERMON_HW_FLASH_GPIO_SEMA 0xF03FC 3953 #define HERMON_HW_FLASH_WRCONF_SEMA 0xF0380 3954 #define HERMON_HW_FLASH_GPIO_DATA 0xF0040 3955 #define HERMON_HW_FLASH_GPIO_MOD1 0xF004C 3956 #define HERMON_HW_FLASH_GPIO_MOD0 0xF0050 3957 #define HERMON_HW_FLASH_GPIO_DATACLEAR 0xF00D4 3958 #define HERMON_HW_FLASH_GPIO_DATASET 0xF00DC 3959 #define HERMON_HW_FLASH_GPIO_LOCK 0xF0048 3960 #define HERMON_HW_FLASH_GPIO_UNLOCK_VAL 0xD42F 3961 #define HERMON_HW_FLASH_GPIO_PIN_ENABLE 0x1E000000 3962 3963 #define HERMON_HW_FLASH_CPU_MASK 0xC0000000 3964 #define HERMON_HW_FLASH_CPU_SHIFT 30 3965 #define HERMON_HW_FLASH_ADDR_MASK 0x0007FFFC 3966 #define HERMON_HW_FLASH_CMD_MASK 0xE0000000 3967 #define HERMON_HW_FLASH_BANK_MASK 0xFFF80000 3968 3969 #define HERMON_HW_FLASH_SPI_BUSY 0x40000000 3970 #define HERMON_HW_FLASH_SPI_WIP 0x01000000 3971 #define HERMON_HW_FLASH_SPI_READ_OP 0x00000001 3972 #define HERMON_HW_FLASH_SPI_USE_INSTR 0x00000040 3973 #define HERMON_HW_FLASH_SPI_NO_ADDR 0x00000020 3974 #define HERMON_HW_FLASH_SPI_NO_DATA 0x00000010 3975 #define HERMON_HW_FLASH_SPI_TRANS_SZ_4B 0x00000200 3976 3977 #define HERMON_HW_FLASH_SPI_SECTOR_ERASE 0xD8 3978 #define HERMON_HW_FLASH_SPI_READ 0x03 3979 #define HERMON_HW_FLASH_SPI_PAGE_PROGRAM 0x02 3980 #define HERMON_HW_FLASH_SPI_READ_STATUS_REG 0x05 3981 #define HERMON_HW_FLASH_SPI_WRITE_ENABLE 0x06 3982 #define HERMON_HW_FLASH_SPI_READ_ESIGNATURE 0xAB 3983 3984 #define HERMON_HW_FLASH_SPI_GW 0xF0400 3985 #define HERMON_HW_FLASH_SPI_ADDR 0xF0404 3986 #define HERMON_HW_FLASH_SPI_DATA 0xF0410 3987 #define HERMON_HW_FLASH_SPI_DATA4 0xF0414 3988 #define HERMON_HW_FLASH_SPI_DATA8 0xF0418 3989 #define HERMON_HW_FLASH_SPI_DATA12 0xF041C 3990 #define HERMON_HW_FLASH_SPI_ADDR_MASK 0x00FFFFFF 3991 #define HERMON_HW_FLASH_SPI_INSTR_PHASE_OFF 0x04 3992 #define HERMON_HW_FLASH_SPI_ADDR_PHASE_OFF 0x08 3993 #define HERMON_HW_FLASH_SPI_DATA_PHASE_OFF 0x10 3994 #define HERMON_HW_FLASH_SPI_ENABLE_OFF 0x2000 3995 #define HERMON_HW_FLASH_SPI_CS_OFF 0x800 3996 #define HERMON_HW_FLASH_SPI_INSTR_OFF 0x10000 3997 #define HERMON_HW_FLASH_SPI_INSTR_SHIFT 0x10 3998 #define HERMON_HW_FLASH_SPI_BOOT_ADDR_REG 0xF0000 3999 4000 #define HERMON_HW_FLASH_TIMEOUT_WRITE 300 4001 #define HERMON_HW_FLASH_TIMEOUT_ERASE 1000000 4002 #define HERMON_HW_FLASH_TIMEOUT_GPIO_SEMA 1000 4003 #define HERMON_HW_FLASH_TIMEOUT_CONFIG 50 4004 4005 #define HERMON_HW_FLASH_ICS_ERASE 0x20 4006 #define HERMON_HW_FLASH_ICS_ERROR 0x3E 4007 #define HERMON_HW_FLASH_ICS_WRITE 0x40 4008 #define HERMON_HW_FLASH_ICS_STATUS 0x70 4009 #define HERMON_HW_FLASH_ICS_READY 0x80 4010 #define HERMON_HW_FLASH_ICS_CONFIRM 0xD0 4011 #define HERMON_HW_FLASH_ICS_READ 0xFF 4012 4013 #ifdef __cplusplus 4014 } 4015 #endif 4016 4017 #endif /* _SYS_IB_ADAPTERS_HERMON_HW_H */ 4018