1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 #ifndef _SYS_IB_ADAPTERS_HERMON_HW_H 27 #define _SYS_IB_ADAPTERS_HERMON_HW_H 28 29 /* 30 * hermon_hw.h 31 * Contains all the structure definitions and #defines for all Hermon 32 * hardware resources and registers (as defined by the Hermon register 33 * specification). Wherever possible, the names in the Hermon spec 34 * have been preserved in the structure and field names below. 35 */ 36 37 #include <sys/types.h> 38 #include <sys/conf.h> 39 #include <sys/ddi.h> 40 #include <sys/sunddi.h> 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 47 /* 48 * PCI IDs for supported chipsets 49 */ 50 #define PCI_VENID_MLX 0x15b3 51 #define PCI_DEVID_HERMON_SDR 0x6340 /* Mellanox MT25208-SDR PCIe Gen1 */ 52 #define PCI_DEVID_HERMON_DDR 0x634A /* Mellanox MT25208-DDR PCIe Gen1 */ 53 #define PCI_DEVID_HERMON_DDRG2 0x6732 /* Mellanox MT25208-DDR PCIe Gen2 */ 54 #define PCI_DEVID_HERMON_QDRG2 0x673C /* Mellanox MT25208-QDR PCIe Gen2 */ 55 #define PCI_DEVID_HERMON_QDRG2V 0x6746 /* Mellanox MT25208-QDR PCIe Gen2 */ 56 #define PCI_DEVID_HERMON_MAINT 0x0191 /* Maintenance/Mem Controller Mode */ 57 58 /* 59 * Native page size of the adapter 60 */ 61 #define HERMON_PAGESIZE 0x1000 /* 4Kb */ 62 #define HERMON_PAGEOFFSET (HERMON_PAGESIZE - 1) 63 #define HERMON_PAGEMASK (~HERMON_PAGEOFFSET) 64 #define HERMON_PAGESHIFT 0xC /* 12 */ 65 66 /* 67 * Offsets into the CMD BAR (BAR 0) for many of the more interesting hardware 68 * registers. These registers include the HCR (more below), and the software 69 * reset register (SW_RESET). 70 */ 71 #define HERMON_CMD_HCR_OFFSET 0x80680 /* PRM */ 72 #define HERMON_CMD_SW_RESET_OFFSET 0xF0010 /* PRM */ 73 #define HERMON_CMD_SW_SEMAPHORE_OFFSET 0xF03FC /* PRM */ 74 #define HERMON_CMD_OFFSET_MASK 0xFFFFF /* per MLX instruction */ 75 76 77 /* 78 * Ownership flags used to define hardware or software ownership for 79 * various Hermon resources 80 */ 81 #define HERMON_HW_OWNER 0x1 82 #define HERMON_SW_OWNER 0x0 83 84 /* 85 * Determines whether or not virtual-to-physical address translation is 86 * required. Several of the Hermon hardware structures can be optionally 87 * accessed by Hermon without going through the TPT address translation 88 * tables. 89 */ 90 #define HERMON_VA2PA_XLAT_ENABLED 0x1 91 #define HERMON_VA2PA_XLAT_DISABLED 0x0 92 93 /* 94 * HCA Command Register (HCR) 95 * The HCR command interface provides privileged access to the HCA in 96 * order to query, configure and modify HCA execution. It is the 97 * primary mechanism through which mailboxes may be posted to Hermon 98 * firmware. To use this interface software fills the HCR with pointers 99 * to input and output mailboxes. Some commands support immediate 100 * parameters, however, and for these commands the HCR will contain the 101 * input or output parameters. Command execution completion can be 102 * detected either by the software polling the HCR or by waiting for a 103 * command completion event. 104 */ 105 struct hermon_hw_hcr_s { 106 uint32_t in_param0; 107 uint32_t in_param1; 108 uint32_t input_modifier; 109 uint32_t out_param0; 110 uint32_t out_param1; 111 uint32_t token; 112 uint32_t cmd; 113 }; 114 #define HERMON_HCR_TOKEN_MASK 0xFFFF0000 115 #define HERMON_HCR_TOKEN_SHIFT 16 116 117 #define HERMON_HCR_CMD_STATUS_MASK 0xFF000000 118 #define HERMON_HCR_CMD_GO_MASK 0x00800000 119 #define HERMON_HCR_CMD_E_MASK 0x00400000 120 #define HERMON_HCR_CMD_T_MASK 0x00200000 121 #define HERMON_HCR_CMD_OPMOD_MASK 0x0000F000 122 #define HERMON_HCR_CMD_OPCODE_MASK 0x00000FFF 123 #define HERMON_HCR_CMD_STATUS_SHFT 24 124 #define HERMON_HCR_CMD_GO_SHFT 23 125 #define HERMON_HCR_CMD_E_SHFT 22 126 #define HERMON_HCR_CMD_T_SHFT 21 127 #define HERMON_HCR_CMD_OPMOD_SHFT 12 128 129 /* 130 * Arbel "QUERY_DEV_LIM" command - Hermon, "QUERY_DEV_CAP" - Same hex code 131 * same function as tavor/arbel QUERY_DEV_LIM, just renamed (whatever). 132 * The QUERY_DEV_LIM command returns the device limits and capabilities 133 * supported by the Hermon device. This command must be run before 134 * running the INIT_HCA command (below) in order to determine the maximum 135 * capabilities of the device and which optional features are supported. 136 */ 137 #ifdef _LITTLE_ENDIAN 138 struct hermon_hw_querydevlim_s { 139 uint32_t rsrv0[4]; 140 141 uint32_t log_max_scqs :4; 142 uint32_t :4; 143 uint32_t num_rsvd_scqs :6; 144 uint32_t :2; 145 uint32_t log_max_srq :5; 146 uint32_t :7; 147 uint32_t log_rsvd_srq :4; 148 149 uint32_t log_max_qp :5; 150 uint32_t :3; 151 uint32_t log_rsvd_qp :4; 152 uint32_t :4; 153 uint32_t log_max_qp_sz :8; 154 uint32_t log_max_srq_sz :8; 155 156 uint32_t log_max_eq :4; 157 uint32_t :4; 158 uint32_t num_rsvd_eq :4; 159 uint32_t :4; 160 uint32_t log_max_dmpt :6; 161 uint32_t :2; 162 uint32_t log_max_eq_sz :8; 163 164 uint32_t log_max_cq :5; 165 uint32_t :3; 166 uint32_t log_rsvd_cq :4; 167 uint32_t :4; 168 uint32_t log_max_cq_sz :8; 169 uint32_t :8; 170 171 172 uint32_t :32; 173 174 uint32_t log_max_mtt :6; 175 uint32_t :2; 176 uint32_t log_rsvd_dmpt :4; 177 uint32_t :4; 178 uint32_t log_max_mrw_sz :8; 179 uint32_t :4; 180 uint32_t log_rsvd_mtt :4; 181 182 uint32_t log_max_ra_glob :6; 183 uint32_t :2; 184 uint32_t log_max_rss_tbl_sz :4; 185 uint32_t rss_toep :1; /* rss toeplitz hashing */ 186 uint32_t rss_xor :1; /* rss xor hashing */ 187 uint32_t :2; 188 uint32_t log_max_gso_sz :5; /* Lge Send Offload */ 189 uint32_t :11; /* new w/ 0.35, RSS info */ 190 191 uint32_t log_max_ra_res_qp :6; 192 uint32_t :10; 193 uint32_t log_max_ra_req_qp :6; 194 uint32_t :10; 195 196 uint32_t num_ports :4; 197 uint32_t :12; 198 uint32_t ca_ack_delay :5; 199 uint32_t :11; 200 201 uint32_t mod_wr_srq :1; 202 uint32_t :31; 203 204 uint32_t :4; 205 uint32_t :12; 206 uint32_t stat_rate_sup :16; 207 208 uint32_t :4; 209 uint32_t :12; 210 uint32_t :8; 211 uint32_t log_max_msg :5; 212 uint32_t :3; 213 214 uint32_t rc :1; 215 uint32_t uc :1; 216 uint32_t ud :1; 217 uint32_t xrc :1; 218 uint32_t rcm :1; 219 uint32_t fcoib :1; 220 uint32_t srq :1; 221 uint32_t ipoib_cksm :1; 222 uint32_t pkey_v :1; 223 uint32_t qkey_v :1; 224 uint32_t vmm :1; 225 uint32_t :5; 226 uint32_t mem_win :1; 227 uint32_t apm :1; 228 uint32_t atomic :1; 229 uint32_t raw_multi :1; 230 uint32_t avp :1; 231 uint32_t ud_multi :1; 232 uint32_t :2; 233 uint32_t pg_on_demand :1; 234 uint32_t router :1; 235 uint32_t :6; 236 237 uint32_t :32; 238 239 uint32_t log_max_bf_page :6; 240 uint32_t :2; 241 uint32_t log_max_bf_req_ppg :6; 242 uint32_t :2; 243 uint32_t log_bf_reg_sz :5; 244 uint32_t :10; 245 uint32_t blu_flm :1; 246 247 uint32_t log_pg_sz :8; 248 uint32_t :8; 249 uint32_t log_max_uar_sz :6; 250 uint32_t :6; 251 uint32_t num_rsvd_uar :4; 252 253 uint32_t max_desc_sz_rq :16; 254 uint32_t max_sg_rq :8; 255 uint32_t :8; 256 257 uint32_t max_desc_sz_sq :16; 258 uint32_t max_sg_sq :8; 259 uint32_t :8; 260 261 uint32_t rsvd_fcoib[2]; 262 263 uint32_t log_max_srcd :4; 264 uint32_t :8; 265 uint32_t num_rsvd_srcds :4; 266 uint32_t log_max_pd :5; 267 uint32_t :7; 268 uint32_t num_rsvd_pd :4; 269 270 uint32_t log_max_mcg :8; 271 uint32_t num_rsvd_mcg :4; 272 uint32_t :4; 273 uint32_t log_max_qp_mcg :8; 274 uint32_t :8; 275 276 uint32_t rsrv2[6]; 277 278 uint32_t altc_entry_sz :16; 279 uint32_t aux_entry_sz :16; 280 281 uint32_t qpc_entry_sz :16; 282 uint32_t rdmardc_entry_sz :16; 283 284 uint32_t cmpt_entry_sz :16; 285 uint32_t srq_entry_sz :16; 286 287 uint32_t cqc_entry_sz :16; 288 uint32_t eqc_entry_sz :16; 289 290 uint32_t bmme :1; 291 uint32_t win_type :1; 292 uint32_t mps :1; 293 uint32_t bl :1; 294 uint32_t zb :1; 295 uint32_t lif :1; 296 uint32_t local_inv :1; 297 uint32_t remote_inv :1; 298 uint32_t :1; 299 uint32_t win_type2 :1; 300 uint32_t reserved_lkey :1; 301 uint32_t fast_reg_wr :1; 302 uint32_t :20; 303 304 uint32_t dmpt_entry_sz :16; 305 uint32_t mtt_entry_sz :16; 306 307 uint32_t :32; 308 309 uint32_t rsv_lkey; 310 311 uint64_t max_icm_size; 312 313 uint32_t rsrv3[22]; 314 }; 315 316 #else /* BIG ENDIAN */ 317 318 struct hermon_hw_querydevlim_s { 319 uint32_t rsrv0[4]; 320 321 uint32_t log_max_srq_sz :8; 322 uint32_t log_max_qp_sz :8; 323 uint32_t :4; 324 uint32_t log_rsvd_qp :4; 325 uint32_t :3; 326 uint32_t log_max_qp :5; 327 328 uint32_t log_rsvd_srq :4; 329 uint32_t :7; 330 uint32_t log_max_srq :5; 331 uint32_t :2; 332 uint32_t num_rsvd_scqs :6; 333 uint32_t :4; 334 uint32_t log_max_scqs :4; 335 336 uint32_t :8; 337 uint32_t log_max_cq_sz :8; 338 uint32_t :4; 339 uint32_t log_rsvd_cq :4; 340 uint32_t :3; 341 uint32_t log_max_cq :5; 342 343 uint32_t log_max_eq_sz :8; 344 uint32_t :2; 345 uint32_t log_max_dmpt :6; 346 uint32_t :4; 347 uint32_t num_rsvd_eq :4; 348 uint32_t :4; 349 uint32_t log_max_eq :4; 350 351 uint32_t log_rsvd_mtt :4; 352 uint32_t :4; 353 uint32_t log_max_mrw_sz :8; 354 uint32_t :4; 355 uint32_t log_rsvd_dmpt :4; 356 uint32_t :2; 357 uint32_t log_max_mtt :6; 358 359 uint32_t :32; 360 361 uint32_t :10; 362 uint32_t log_max_ra_req_qp :6; 363 uint32_t :10; 364 uint32_t log_max_ra_res_qp :6; 365 366 uint32_t :11; /* new w/ 0.35, RSS info */ 367 uint32_t log_max_gso_sz :5; /* Lge Send Offload */ 368 uint32_t :2; 369 uint32_t rss_xor :1; /* rss xor hashing */ 370 uint32_t rss_toep :1; /* rss toeplitz hashing */ 371 uint32_t log_max_rss_tbl_sz :4; 372 uint32_t :2; 373 uint32_t log_max_ra_glob :6; 374 375 uint32_t :31; 376 uint32_t mod_wr_srq :1; 377 378 uint32_t :11; 379 uint32_t ca_ack_delay :5; 380 /* PRM 0.35, stuff moved to per port info */ 381 uint32_t :12; 382 uint32_t num_ports :4; 383 384 uint32_t :3; 385 uint32_t log_max_msg :5; 386 uint32_t :8; 387 uint32_t :12; 388 uint32_t :4; 389 390 uint32_t stat_rate_sup :16; 391 uint32_t :12; 392 uint32_t :4; 393 394 uint32_t :32; 395 396 uint32_t :6; 397 uint32_t router :1; 398 uint32_t pg_on_demand :1; 399 uint32_t :2; 400 uint32_t ud_multi :1; 401 uint32_t avp :1; 402 uint32_t raw_multi :1; 403 uint32_t atomic :1; 404 uint32_t apm :1; 405 uint32_t mem_win :1; 406 uint32_t :5; 407 uint32_t vmm :1; 408 uint32_t qkey_v :1; 409 uint32_t pkey_v :1; 410 uint32_t ipoib_cksm :1; 411 uint32_t srq :1; 412 uint32_t fcoib :1; 413 uint32_t rcm :1; 414 uint32_t xrc :1; 415 uint32_t ud :1; 416 uint32_t uc :1; 417 uint32_t rc :1; 418 419 uint32_t num_rsvd_uar :4; 420 uint32_t :6; 421 uint32_t log_max_uar_sz :6; 422 uint32_t :8; 423 uint32_t log_pg_sz :8; 424 425 uint32_t blu_flm :1; 426 uint32_t :10; 427 uint32_t log_bf_reg_sz :5; 428 uint32_t :2; 429 uint32_t log_max_bf_req_ppg :6; 430 uint32_t :2; 431 uint32_t log_max_bf_page :6; 432 433 uint32_t :8; 434 uint32_t max_sg_sq :8; 435 uint32_t max_desc_sz_sq :16; 436 437 uint32_t :8; 438 uint32_t max_sg_rq :8; 439 uint32_t max_desc_sz_rq :16; 440 441 uint32_t rsvd_fcoib[2]; 442 443 uint32_t :8; 444 uint32_t log_max_qp_mcg :8; 445 uint32_t :4; 446 uint32_t num_rsvd_mcg :4; 447 uint32_t log_max_mcg :8; 448 449 uint32_t num_rsvd_pd :4; 450 uint32_t :7; 451 uint32_t log_max_pd :5; 452 uint32_t num_rsvd_srcds :4; 453 uint32_t :8; 454 uint32_t log_max_srcd :4; 455 456 uint32_t rsrv2[6]; 457 458 uint32_t rdmardc_entry_sz :16; 459 uint32_t qpc_entry_sz :16; 460 461 uint32_t aux_entry_sz :16; 462 uint32_t altc_entry_sz :16; 463 464 uint32_t eqc_entry_sz :16; 465 uint32_t cqc_entry_sz :16; 466 467 uint32_t srq_entry_sz :16; 468 uint32_t cmpt_entry_sz :16; 469 470 uint32_t mtt_entry_sz :16; 471 uint32_t dmpt_entry_sz :16; 472 473 uint32_t :20; 474 uint32_t fast_reg_wr :1; 475 uint32_t reserved_lkey :1; 476 uint32_t win_type2 :1; 477 uint32_t :1; 478 uint32_t remote_inv :1; 479 uint32_t local_inv :1; 480 uint32_t lif :1; 481 uint32_t zb :1; 482 uint32_t bl :1; 483 uint32_t mps :1; 484 uint32_t win_type :1; 485 uint32_t bmme :1; 486 487 uint32_t rsv_lkey; 488 489 uint32_t :32; 490 491 uint64_t max_icm_size; 492 493 uint32_t rsrv3[22]; 494 }; 495 #endif 496 497 498 499 /* 500 * Hermon "QUERY_FW" command 501 * The QUERY_FW command retrieves the firmware revision and the Command 502 * Interface revision. The command also returns the HCA attached local 503 * memory area (DDR) which is used by the firmware. Below we also 504 * include some defines which are used to enforce a minimum firmware 505 * version check (see hermon_fw_version_check() for more details). 506 */ 507 508 #ifdef _LITTLE_ENDIAN 509 struct hermon_hw_queryfw_s { 510 uint32_t fw_rev_minor :16; 511 uint32_t fw_rev_subminor :16; 512 513 uint32_t fw_rev_major :16; 514 uint32_t fw_pages :16; 515 516 uint32_t log_max_cmd :8; 517 uint32_t :23; 518 uint32_t dbg_trace :1; 519 520 uint32_t cmd_intf_rev :16; 521 uint32_t :16; 522 523 uint32_t fw_day :8; 524 uint32_t fw_month :8; 525 uint32_t fw_year :16; 526 527 uint32_t :1; 528 uint32_t ccq :1; 529 uint32_t :6; 530 uint32_t fw_sec :8; 531 uint32_t fw_min :8; 532 uint32_t fw_hour :8; 533 534 uint32_t rsrv0[2]; 535 536 uint64_t clr_intr_offs; 537 538 uint32_t :32; 539 540 uint32_t :30; 541 uint32_t clr_int_bar :2; 542 543 uint64_t error_buf_addr; 544 545 uint32_t :30; 546 uint32_t err_buf_bar :2; 547 548 uint32_t error_buf_sz; 549 550 uint32_t rsrv2[48]; 551 }; 552 #else 553 struct hermon_hw_queryfw_s { 554 uint32_t fw_pages :16; 555 uint32_t fw_rev_major :16; 556 557 uint32_t fw_rev_subminor :16; 558 uint32_t fw_rev_minor :16; 559 560 uint32_t :16; 561 uint32_t cmd_intf_rev :16; 562 563 uint32_t dbg_trace :1; 564 uint32_t :23; 565 uint32_t log_max_cmd :8; 566 567 uint32_t fw_hour :8; 568 uint32_t fw_min :8; 569 uint32_t fw_sec :8; 570 uint32_t :6; 571 uint32_t ccq :1; 572 uint32_t :1; 573 574 uint32_t fw_year :16; 575 uint32_t fw_month :8; 576 uint32_t fw_day :8; 577 578 uint32_t rsrv1[2]; 579 580 uint64_t clr_intr_offs; 581 582 uint32_t clr_int_bar :2; 583 uint32_t :30; 584 585 uint32_t :32; 586 587 uint64_t error_buf_addr; 588 589 uint32_t error_buf_sz; 590 591 uint32_t err_buf_bar :2; 592 uint32_t :30; 593 594 uint32_t rsrv2[48]; 595 }; 596 #endif 597 598 /* 599 * 2.6.000 is critical for some performance features, e.g., Reserved_Lkey, 600 * and 2.7.000 is needed for FRWR and FCoIB. Requiring 2.6.000 now so that 601 * existing customers get the performance, but are not required to upgrade 602 * to the latest. Less than 2.6.000 will cause the driver to attach in 603 * maintenance mode, and throw an FMA event about upgrading the firmware. 604 */ 605 606 #define HERMON_FW_VER_MAJOR 0x0002 607 #define HERMON_FW_VER_MINOR 0x0006 608 #define HERMON_FW_VER_SUBMINOR 0x0000 609 610 /* 611 * Hermon "QUERY_ADAPTER" command 612 * The QUERY_ADAPTER command retrieves adapter specific parameters. The 613 * command also retrieves the PCI(X) interrupt pin routing for each of 614 * the INTx# pins supported by the device. This information is used by 615 * the driver during interrupt processing in order to clear the appropriate 616 * interrupt bit. 617 */ 618 #ifdef _LITTLE_ENDIAN 619 struct hermon_hw_queryadapter_s { 620 uint32_t rsrv0[4]; 621 622 uint32_t :32; 623 624 uint32_t :24; 625 uint32_t inta_pin :8; 626 627 uint32_t vsd_vend_id :16; /* added v35 hermon */ 628 uint32_t :16; 629 630 uint32_t :32; 631 632 uint32_t vsd[52]; 633 uint32_t psid[4]; 634 }; 635 #else 636 struct hermon_hw_queryadapter_s { 637 uint32_t rsrv0[4]; 638 639 uint32_t inta_pin :8; 640 uint32_t :24; 641 642 uint32_t :32; 643 644 uint32_t :32; 645 646 uint32_t :16; 647 uint32_t vsd_vend_id :16; /* added v35 hermon */ 648 649 uint32_t vsd[52]; 650 uint32_t psid[4]; 651 }; 652 #endif 653 #define HERMON_REV_A0 0xA0 654 #define HERMON_REV_A1 0xA1 655 656 /* 657 * Virtual physical mapping structure for: MAP_FA, MAP_ICM_AUX, and 658 * MAP_ICM commands. 659 */ 660 661 #ifdef _LITTLE_ENDIAN 662 struct hermon_hw_vpm_s { 663 uint32_t :12; 664 uint32_t vaddr_l :20; 665 uint32_t vaddr_h; 666 667 uint32_t log2sz :5; 668 uint32_t :7; 669 uint32_t paddr_l :20; 670 uint32_t paddr_h; 671 }; 672 #else 673 struct hermon_hw_vpm_s { 674 uint32_t vaddr_h; 675 uint32_t vaddr_l :20; 676 uint32_t :12; 677 678 uint32_t paddr_h; 679 uint32_t paddr_l :20; 680 uint32_t :7; 681 uint32_t log2sz :5; 682 }; 683 #endif 684 685 686 687 688 /* 689 * Hermon "INIT_HCA" and "QUERY_HCA" commands 690 * The INIT_HCA command configures all HCA resources in HCA attached local 691 * memory and some system relevant information. The same mailbox output 692 * format is used by the QUERY_HCA command. All parameters, which are 693 * specifically the output of the QUERY_HCA command are marked as 694 * "QUERY_HCA only". These parameters are not configurable through the 695 * INIT_HCA command, but can be retrieved as read-only through the 696 * QUERY_HCA command. 697 * 698 * Below we first define several structures which help make up the whole 699 * of the INIT_HCA/QUERY_HCA command. These are: 700 * hermon_hw_qp_ee_cq_eq_rdb_t for "QPC/EEC/CQC/EQC/RDB Parameters", 701 * hermon_udav_mem_param_t for "Memory Access Parameters for UDAV Table", 702 * hermon_multicast_param_t for "Multicast Support Parameters", 703 * hermon_tpt_param_t for "Translation and Protection Table Parameters", 704 * and hermon_uar_param_t for Hermon "UAR Parameters". 705 */ 706 707 /* 708 * need to consider removing any ref to "ee", hermon doesn't support 709 * ee/rd stuff, and they've taken away the pretense 710 */ 711 712 713 #ifdef _LITTLE_ENDIAN 714 typedef struct hermon_hw_qp_ee_cq_eq_rdb_s { 715 uint32_t rsrv0[4]; 716 717 uint32_t log_num_qp :5; 718 uint32_t qpc_baseaddr_l :27; 719 uint32_t qpc_baseaddr_h; 720 721 uint32_t rsrv1[4]; 722 723 uint32_t log_num_srq :5; 724 uint32_t srqc_baseaddr_l :27; 725 uint32_t srqc_baseaddr_h; 726 727 uint32_t log_num_cq :5; 728 uint32_t cqc_baseaddr_l :27; 729 uint32_t cqc_baseaddr_h; 730 731 uint32_t rsrv2[2]; 732 733 uint64_t altc_baseaddr; 734 735 uint32_t rsrv3[2]; 736 737 uint64_t auxc_baseaddr; 738 739 uint32_t rsrv4[2]; 740 741 uint32_t log_num_eq :5; 742 uint32_t eqc_baseaddr_l :27; 743 uint32_t eqc_baseaddr_h; 744 745 uint32_t rsv5[2]; 746 747 uint32_t log_num_rdmardc :3; 748 uint32_t :2; 749 uint32_t rdmardc_baseaddr_l :27; 750 uint32_t rdmardc_baseaddr_h; 751 752 uint32_t rsrv6[2]; 753 } hermon_hw_qp_ee_cq_eq_rdb_t; 754 #else 755 typedef struct hermon_hw_qp_ee_cq_eq_rdb_s { 756 uint32_t rsrv0[4]; 757 758 uint32_t qpc_baseaddr_h; 759 uint32_t qpc_baseaddr_l :27; 760 uint32_t log_num_qp :5; 761 762 uint32_t rsrv1[4]; 763 764 uint32_t srqc_baseaddr_h; 765 uint32_t srqc_baseaddr_l :27; 766 uint32_t log_num_srq :5; 767 768 uint32_t cqc_baseaddr_h; 769 uint32_t cqc_baseaddr_l :27; 770 uint32_t log_num_cq :5; 771 772 uint32_t rsrv2[2]; 773 774 uint64_t altc_baseaddr; 775 776 uint32_t rsrv3[2]; 777 778 uint64_t auxc_baseaddr; 779 780 uint32_t rsrv4[2]; 781 782 uint32_t eqc_baseaddr_h; 783 uint32_t eqc_baseaddr_l :27; 784 uint32_t log_num_eq :5; 785 786 uint32_t rsv5[2]; 787 788 uint32_t rdmardc_baseaddr_h; 789 uint32_t rdmardc_baseaddr_l :27; 790 uint32_t :2; 791 uint32_t log_num_rdmardc :3; 792 793 uint32_t rsrv6[2]; 794 } hermon_hw_qp_ee_cq_eq_rdb_t; 795 #endif 796 797 798 799 800 #ifdef _LITTLE_ENDIAN 801 typedef struct hermon_multicast_param_s { 802 uint64_t mc_baseaddr; 803 804 uint32_t rsrv0[2]; 805 806 uint32_t log_mc_tbl_hash_sz :5; 807 uint32_t :27; 808 809 uint32_t log_mc_tbl_ent :5; 810 uint32_t :27; 811 812 uint32_t :32; 813 814 uint32_t log_mc_tbl_sz :5; 815 uint32_t :19; 816 uint32_t mc_hash_fn :3; 817 uint32_t :5; 818 } hermon_multicast_param_t; 819 #else 820 typedef struct hermon_multicast_param_s { 821 uint64_t mc_baseaddr; 822 823 uint32_t rsrv0[2]; 824 825 uint32_t :27; 826 uint32_t log_mc_tbl_ent :5; 827 828 uint32_t :27; 829 uint32_t log_mc_tbl_hash_sz :5; 830 831 uint32_t :5; 832 uint32_t mc_hash_fn :3; 833 uint32_t :19; 834 uint32_t log_mc_tbl_sz :5; 835 836 uint32_t :32; 837 } hermon_multicast_param_t; 838 #endif 839 840 #define HERMON_MCG_DEFAULT_HASH_FN 0x0 841 842 #ifdef _LITTLE_ENDIAN 843 typedef struct hermon_tpt_param_s { 844 uint64_t dmpt_baseaddr; 845 846 uint32_t :32; 847 uint32_t log_dmpt_sz :6; 848 uint32_t :2; 849 uint32_t pgfault_rnr_to :5; 850 uint32_t :19; 851 852 uint64_t mtt_baseaddr; 853 854 uint64_t cmpt_baseaddr; 855 } hermon_tpt_param_t; 856 #else 857 typedef struct hermon_tpt_param_s { 858 uint64_t dmpt_baseaddr; 859 860 uint32_t :19; 861 uint32_t pgfault_rnr_to :5; 862 uint32_t :2; 863 uint32_t log_dmpt_sz :6; 864 uint32_t :32; 865 866 uint64_t mtt_baseaddr; 867 868 uint64_t cmpt_baseaddr; 869 } hermon_tpt_param_t; 870 #endif 871 872 873 #ifdef _LITTLE_ENDIAN 874 typedef struct hermon_uar_param_s { 875 uint32_t rsvd0[2]; 876 877 uint32_t :32; 878 879 uint32_t uar_pg_sz :8; 880 uint32_t log_max_uars :4; 881 uint32_t :20; 882 883 uint32_t resvd1[4]; 884 } hermon_uar_param_t; 885 #else 886 typedef struct hermon_uar_param_s { 887 uint32_t rsvd0[2]; 888 889 uint32_t :20; 890 uint32_t log_max_uars :4; 891 uint32_t uar_pg_sz :8; 892 893 uint32_t :32; 894 895 uint32_t resvd1[4]; 896 } hermon_uar_param_t; 897 #endif 898 899 /* 900 * NEW for Hermon 901 * QP Allocation Params 902 * 903 */ 904 905 #ifdef _LITTLE_ENDIAN 906 typedef struct hermon_qp_alloc_param_s { 907 uint32_t :32; 908 909 uint32_t ccq_base :24; 910 uint32_t log2ccqs :5; 911 uint32_t :2; 912 uint32_t ccq_en :1; 913 914 uint32_t rsvd[6]; /* but 0x14 def'd for fibre channel */ 915 } hermon_qp_alloc_param_t; 916 #else /* BIG ENDIAN */ 917 typedef struct hermon_qp_alloc_param_s { 918 uint32_t ccq_en :1; 919 uint32_t :2; 920 uint32_t log2ccqs :5; 921 uint32_t ccq_base :24; 922 923 uint32_t :32; 924 925 uint32_t rsvd[6]; /* but 0x14 def'd for fibre channel */ 926 } hermon_qp_alloc_param_t; 927 #endif 928 929 #ifdef _LITTLE_ENDIAN 930 struct hermon_hw_initqueryhca_s { 931 uint32_t :32; 932 933 uint32_t :24; 934 uint32_t version :8; 935 936 uint32_t :13; 937 uint32_t log2_cacheline :3; 938 uint32_t hca_core_clock :16; /* QUERY_HCA only */ 939 940 uint32_t :32; 941 942 uint32_t udav_port_chk :1; 943 uint32_t big_endian :1; 944 uint32_t :1; 945 uint32_t chsum_en :1; 946 uint32_t :28; 947 948 uint32_t router_qp :24; 949 uint32_t :5; 950 uint32_t ipr2 :1; 951 uint32_t ipr1 :1; 952 uint32_t router_en :1; 953 954 uint32_t rsrv1[2]; 955 956 hermon_hw_qp_ee_cq_eq_rdb_t context; 957 958 uint32_t rsrv2[8]; 959 960 hermon_multicast_param_t multi; 961 962 uint32_t rsrv3[4]; 963 964 hermon_tpt_param_t tpt; 965 966 uint32_t rsrv4[4]; 967 968 hermon_uar_param_t uar; 969 970 uint32_t rsrv5[4]; 971 972 hermon_qp_alloc_param_t qp_alloc; 973 974 uint32_t rsrv6[100]; /* from 0x16c to 0x2fc offsets */ 975 }; 976 #else /* BIG ENDIAN */ 977 struct hermon_hw_initqueryhca_s { 978 uint32_t version :8; 979 uint32_t :24; 980 981 uint32_t :32; 982 983 uint32_t :32; 984 985 uint32_t hca_core_clock :16; /* QUERY_HCA only */ 986 uint32_t log2_cacheline :3; 987 uint32_t :13; 988 989 uint32_t router_en :1; 990 uint32_t ipr1 :1; 991 uint32_t ipr2 :1; 992 uint32_t :5; 993 uint32_t router_qp :24; 994 995 uint32_t :28; 996 uint32_t chsum_en :1; 997 uint32_t :1; 998 uint32_t big_endian :1; 999 uint32_t udav_port_chk :1; 1000 1001 uint32_t rsrv1[2]; 1002 1003 hermon_hw_qp_ee_cq_eq_rdb_t context; 1004 1005 uint32_t rsrv2[8]; 1006 1007 hermon_multicast_param_t multi; 1008 1009 uint32_t rsrv3[4]; 1010 1011 hermon_tpt_param_t tpt; 1012 1013 uint32_t rsrv4[4]; 1014 1015 hermon_uar_param_t uar; 1016 1017 uint32_t rsrv5[4]; 1018 1019 hermon_qp_alloc_param_t qp_alloc; 1020 1021 uint32_t rsrv6[100]; /* from 0x16c to 0x2fc offsets */ 1022 }; 1023 #endif 1024 #define HERMON_UDAV_PROTECT_DISABLED 0x0 1025 #define HERMON_UDAV_PROTECT_ENABLED 0x1 1026 #define HERMON_UDAV_PORTCHK_DISABLED 0x0 1027 #define HERMON_UDAV_PORTCHK_ENABLED 0x1 1028 1029 1030 /* 1031 * Hermon "INIT_IB"/"INIT_PORT" command 1032 * The INIT_IB/INIT_PORT command enables the physical layer of an IB port. 1033 * It provides control over the IB port attributes. The capabilities 1034 * requested here should not exceed the device limits, as retrieved by 1035 * the QUERY_DEV_LIM/CAP command (above). To query information about the IB 1036 * port or node, the driver may submit GetPortInfo or GetNodeInfo MADs 1037 * through the Hermon MAD_IFC command. 1038 * 1039 * Changed name to initport, but operates similar to initib - but as of 1040 * PRM v0.35c the initport just does that, and the params set previously 1041 * by initib are now set in SET_PORT 1042 */ 1043 1044 1045 1046 1047 /* 1048 * HERMON query_port and set_port commands. QUERY_PORT is new for hermon, 1049 * doing some of what used to be done in the QUERY_DEV_CAP command. It is 1050 * introduced in PRM v0.35 and will need to be added to the list of 1051 * supported HCA commands 1052 * 1053 * SET_PORT is similar to the SET_IB command from tavor and arbel. Here, 1054 * tho, it's more extensive and will be easier to deal with I suspect by 1055 * making it a structure and filling it in and then doing the copy to the 1056 * mailbox (instead of just writing the minimal information to the mailbox 1057 * directly as was done for the previous HCAs). 1058 */ 1059 1060 #ifdef _LITTLE_ENDIAN 1061 struct hermon_hw_query_port_s { 1062 uint32_t log_max_pkey :4; /* pkey table size */ 1063 uint32_t log_max_gid :4; /* max gids / port */ 1064 /* was max_port_width arbel: long list of values */ 1065 uint32_t ib_port_wid :4; 1066 uint32_t :4; 1067 uint32_t :4; /* other types possibly */ 1068 uint32_t :4; 1069 /* 1070 * 0x1=2.5G, 0x3=2.5 or 5.0G, 0x5=2.5 or 10G 1071 * 0x7=2.5, 5.0, or 10G, others rsvd 1072 */ 1073 uint32_t ib_link_spd :4; 1074 1075 uint32_t :4; 1076 1077 uint32_t :16; /* used for other types (?) */ 1078 uint32_t ib_mtu :4; 1079 /* 1080 * 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 1081 * 0x5=4096, others rsvd 1082 */ 1083 uint32_t :4; 1084 uint32_t port_type :8; /* 0x00, 0x01 IB, others TBD */ 1085 1086 uint32_t :32; 1087 /* max vl's supported (not incl vl_15) */ 1088 uint32_t max_vl :4; 1089 uint32_t :4; 1090 uint32_t :8; /* but others possibly */ 1091 uint32_t :16; 1092 1093 uint32_t rsvd0[2]; /* but for other types */ 1094 uint32_t rsvd1[504]; 1095 }; 1096 #else /* BIG ENDIAN */ 1097 struct hermon_hw_query_port_s { 1098 uint32_t port_type :8; /* 0x00, 0x01 IB, others TBD */ 1099 uint32_t :4; 1100 /* 1101 * 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 1102 * 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 1103 */ 1104 uint32_t ib_mtu :4; 1105 /* 0x5=4096, others rsvd */ 1106 uint32_t :16; /* used for other types (?) */ 1107 1108 uint32_t :4; 1109 uint32_t ib_link_spd :4; 1110 /* 1111 * 0x1=2.5G, 0x3=2.5 or 5.0G, 0x5=2.5 or 10G 1112 * 0x7=2.5, 5.0, or 10G, others rsvd 1113 */ 1114 uint32_t :4; 1115 uint32_t :4; /* other types possibly */ 1116 uint32_t :4; 1117 /* was max_port_width arbel: long list of values */ 1118 uint32_t ib_port_wid :4; 1119 uint32_t log_max_gid :4; /* max gids / port */ 1120 uint32_t log_max_pkey :4; /* pkey table size */ 1121 1122 uint32_t :16; 1123 uint32_t :8; /* but others possibly */ 1124 uint32_t :4; 1125 /* max vl's supported (not incl vl_15) */ 1126 uint32_t max_vl :4; 1127 1128 uint32_t :32; 1129 1130 uint32_t rsvd0[2]; /* but for other types */ 1131 uint32_t rsvd1[504]; 1132 1133 }; 1134 #endif 1135 1136 #ifdef _LITTLE_ENDIAN 1137 struct hermon_hw_set_port_s { 1138 uint32_t cap_mask; 1139 1140 uint32_t rqk :1; /* reset qkey violation cntr */ 1141 uint32_t rcm :1; /* reset capability mask */ 1142 uint32_t :2; 1143 uint32_t vl_cap :4; 1144 uint32_t :4; 1145 uint32_t mtu_cap :4; 1146 uint32_t g0 :1; /* set port GUID0 */ 1147 uint32_t ng :1; /* set node GUID (all ports) */ 1148 uint32_t sig :1; /* set sys image */ 1149 uint32_t mg :1; /* change GID table */ 1150 uint32_t mp :1; /* change pkey table size */ 1151 uint32_t mvc :1; /* change vl_cap */ 1152 uint32_t mmc :1; /* change mtu_cap */ 1153 uint32_t :9; 1154 1155 uint64_t sys_img_guid; 1156 1157 uint64_t guid0; 1158 1159 uint64_t node_guid; 1160 1161 uint32_t sniff_qpn_base :24; 1162 uint32_t ge :1; /* glob egress sniff enabled */ 1163 uint32_t gi :1; /* glob ingress sniff enabled */ 1164 uint32_t qe :1; /* qp-egress sniff enable */ 1165 uint32_t qi :1; /* qp-ingress sniff enabled */ 1166 uint32_t :4; 1167 1168 uint32_t router_qpn_base :24; 1169 uint32_t routermode :1; 1170 uint32_t :7; 1171 1172 uint32_t :32; 1173 1174 uint32_t max_guid :16; /* valid if noted above */ 1175 uint32_t max_pkey :16; /* valid if noted above */ 1176 1177 uint32_t rsrd0[500]; 1178 }; 1179 #else /* BIG ENDIAN */ 1180 struct hermon_hw_set_port_s { 1181 uint32_t :9; 1182 uint32_t mmc :1; /* change mtu_cap */ 1183 uint32_t mvc :1; /* change vl_cap */ 1184 uint32_t mp :1; /* change pkey table size */ 1185 uint32_t mg :1; /* change GID table size */ 1186 uint32_t sig :1; /* set sys image GUID */ 1187 uint32_t ng :1; /* set node GUID (all ports) */ 1188 uint32_t g0 :1; /* set port GUID0 */ 1189 uint32_t mtu_cap :4; 1190 uint32_t :4; 1191 uint32_t vl_cap :4; 1192 uint32_t :2; 1193 uint32_t rcm :1; /* reset capability mask */ 1194 uint32_t rqk :1; /* reset qkey violation cntr */ 1195 1196 uint32_t cap_mask; 1197 1198 uint64_t sys_img_guid; 1199 1200 uint64_t guid0; 1201 1202 uint64_t node_guid; 1203 1204 uint32_t :7; 1205 uint32_t routermode :1; 1206 uint32_t router_qpn_base :24; 1207 1208 uint32_t :4; 1209 uint32_t qi :1; /* qp-ingress sniff enabled */ 1210 uint32_t qe :1; /* qp-egress sniff enable */ 1211 uint32_t gi :1; /* glob ingress sniff enabled */ 1212 uint32_t ge :1; /* glob egress sniff enabled */ 1213 uint32_t sniff_qpn_base :24; 1214 1215 uint32_t max_pkey :16; /* valid if noted above */ 1216 uint32_t max_guid :16; /* valid if noted above */ 1217 1218 uint32_t :32; 1219 1220 uint32_t rsrd0[500]; 1221 }; 1222 #endif 1223 1224 1225 1226 1227 /* 1228 * Hermon Memory Protection Table (MPT) entries 1229 * 1230 * The Memory Protection Table (MPT) contains the information associated 1231 * with all the regions and windows. The MPT table resides in a virtually- 1232 * contiguous area in ICM, and the memory key (R_Key or L_Key) is used to 1233 * calculate the physical address for accessing the entries in the table. 1234 * 1235 * 1236 * The SW2HW_MPT command transfers ownership of an MPT entry from software 1237 * to hardware. The command takes the MPT entry from the input mailbox and 1238 * stores it in the MPT in the hardware. The command will fail if the 1239 * requested MPT entry is already owned by the hardware or if the MPT index 1240 * given in the command is inconsistent with the MPT entry memory key. 1241 * The QUERY_MPT command retrieves a snapshot of an MPT entry. The command 1242 * takes the current state of an MPT entry from the hardware and stores it 1243 * in the output mailbox. The command will fail if the requested MPT entry 1244 * is already owned by software. 1245 * Finally, the HW2SW_MPT command transfers ownership of an MPT entry from 1246 * the hardware to the software. The command takes the MPT entry from the 1247 * hardware, invalidates it, and stores it in the output mailbox. The 1248 * command will fail if the requested entry is already owned by software. 1249 * The command will also fail if the MPT entry in question is a Memory 1250 * Region which has Memory Windows currently bound to it. 1251 * 1252 * The following structure is used in the SW2HW_MPT, QUERY_MPT, and 1253 * HW2SW_MPT commands, and ONLY for the dMPT - for data. 1254 */ 1255 1256 #ifdef _LITTLE_ENDIAN 1257 struct hermon_hw_dmpt_s { 1258 uint32_t :7; 1259 uint32_t bnd_qp :1; 1260 uint32_t qpn :24; /* dw 1, byte 4-7 */ 1261 1262 uint32_t :8; 1263 uint32_t reg_win :1; 1264 uint32_t phys_addr :1; 1265 uint32_t lr :1; 1266 uint32_t lw :1; 1267 uint32_t rr :1; 1268 uint32_t rw :1; 1269 uint32_t atomic :1; 1270 uint32_t en_bind :1; 1271 uint32_t atc_req :1; 1272 uint32_t atc_xlat :1; 1273 uint32_t :1; 1274 uint32_t no_snoop :1; 1275 uint32_t :8; 1276 uint32_t status :4; /* dw 0, byte 0-3 */ 1277 1278 uint32_t pd :24; 1279 uint32_t ren_inval :1; 1280 uint32_t en_inval :1; 1281 uint32_t net_cache :1; 1282 uint32_t fast_reg_en :1; 1283 uint32_t rem_acc_en :1; 1284 uint32_t w_dif :1; 1285 uint32_t m_dif :1; 1286 uint32_t :1; /* dw 2, byte 0xc-f */ 1287 1288 uint32_t mem_key; 1289 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1290 1291 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1292 1293 uint32_t win_cnt :24; 1294 uint32_t :8; /* dw 9, byte 0x24-27 */ 1295 1296 uint32_t lkey; /* dw 8, byte 0x20-23 */ 1297 1298 uint32_t mtt_addr_h :8; 1299 uint32_t :24; /* dw 11, byte 0x2c-2f */ 1300 1301 uint32_t mtt_rep :4; 1302 uint32_t :17; 1303 uint32_t blk_mode :1; 1304 uint32_t len_b64 :1; /* bit 64 of length */ 1305 uint32_t fbo_en :1; 1306 uint32_t :8; /* dw 10, byte 0x28-2b */ 1307 1308 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1309 1310 uint32_t :3; 1311 uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */ 1312 1313 uint32_t mtt_fbo :21; 1314 uint32_t :11; /* dw 15, byte 0x3c-3f */ 1315 1316 uint32_t entity_sz :21; 1317 uint32_t :11; /* dw 14, byte 0x38-3b */ 1318 #ifdef HERMON_NOTIMPL 1319 uint32_t dif_m_atag :16; 1320 uint32_t :16; /* dw 17, 0x44-47 */ 1321 1322 uint32_t dif_a_msk :16; 1323 uint32_t dif_v_msk :2; 1324 uint32_t dif_rep :2; 1325 uint32_t :9; 1326 uint32_t dif_err :3; /* dw 16, 0x40-43 */ 1327 1328 uint32_t dif_w_atag :16; 1329 uint32_t :16; /* dw 19, 0x4c-4f */ 1330 1331 uint32_t dif_m_rtagb; /* dw 18, 0x48-4b */ 1332 1333 uint32_t :32; 1334 1335 uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */ 1336 #endif /* HERMON_NOTIMPL */ 1337 }; 1338 1339 #else /* BIG ENDIAN */ 1340 struct hermon_hw_dmpt_s { 1341 uint32_t status :4; 1342 uint32_t :8; 1343 uint32_t no_snoop :1; 1344 uint32_t :1; 1345 uint32_t atc_xlat :1; 1346 uint32_t atc_req :1; 1347 uint32_t en_bind :1; 1348 uint32_t atomic :1; 1349 uint32_t rw :1; 1350 uint32_t rr :1; 1351 uint32_t lw :1; 1352 uint32_t lr :1; 1353 uint32_t phys_addr :1; 1354 uint32_t reg_win :1; 1355 uint32_t :8; /* dw 0, byte 0x0-3 */ 1356 1357 uint32_t qpn :24; 1358 uint32_t bnd_qp :1; 1359 uint32_t :7; /* dw 1, byte 0x4-7 */ 1360 1361 uint32_t mem_key; /* dw 2, byte 0x8-b */ 1362 1363 uint32_t :1; 1364 uint32_t m_dif :1; 1365 uint32_t w_dif :1; 1366 uint32_t rem_acc_en :1; 1367 uint32_t fast_reg_en :1; 1368 uint32_t net_cache :1; 1369 uint32_t en_inval :1; 1370 uint32_t ren_inval :1; 1371 uint32_t pd :24; /* dw 3, byte 0xc-f */ 1372 1373 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1374 1375 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1376 1377 uint32_t lkey; /* dw 8, bytd 0x20-23 */ 1378 1379 uint32_t :8; 1380 uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */ 1381 1382 uint32_t :8; 1383 uint32_t fbo_en :1; 1384 uint32_t len_b64 :1; /* bit 64 of length */ 1385 uint32_t blk_mode :1; 1386 uint32_t :17; 1387 uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */ 1388 1389 uint32_t :24; 1390 uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */ 1391 1392 uint32_t mtt_addr_l :29; 1393 uint32_t :3; /* dw 12, byte 0x30-33 */ 1394 1395 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1396 1397 uint32_t :11; 1398 uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */ 1399 1400 uint32_t :11; 1401 uint32_t mtt_fbo :21; /* dw 15, byte 0x3c-3f */ 1402 #ifdef HERMON_NOTIMPL 1403 1404 uint32_t dif_err :3; 1405 uint32_t :9; 1406 uint32_t dif_rep :2; 1407 uint32_t dif_v_msk :2; 1408 uint32_t dif_a_msk :16; /* dw 16, 0x40-43 */ 1409 1410 uint32_t :16; 1411 uint32_t dif_m_atag :16; /* dw 17, 0x44-47 */ 1412 1413 uint32_t dif_m_rtagb; /* dw 18, 0x48-4b */ 1414 1415 uint32_t :16; 1416 uint32_t dif_w_atag :16; /* dw 19, 0x4c-4f */ 1417 1418 uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */ 1419 1420 uint32_t :32; 1421 #endif /* HERMON_NOTIMPL */ 1422 }; 1423 #endif 1424 1425 /* 1426 * The following structure is for the CMPTs. This is NEVER actually built and 1427 * passed to the hardware - we use it to track information needed for the 1428 * context entries, and to facilitate the alloc tracking. It differs from 1429 * the dMPT sturcture above in that it does not have/need the "dif" stuff. 1430 * 1431 */ 1432 1433 1434 1435 #ifdef _LITTLE_ENDIAN 1436 struct hermon_hw_cmpt_s { 1437 uint32_t :7; 1438 uint32_t bnd_qp :1; 1439 uint32_t qpn :24; /* dw 1, byte 4-7 */ 1440 1441 uint32_t :8; 1442 uint32_t reg_win :1; 1443 uint32_t phys_addr :1; 1444 uint32_t lr :1; 1445 uint32_t lw :1; 1446 uint32_t rr :1; 1447 uint32_t rw :1; 1448 uint32_t atomic :1; 1449 uint32_t en_bind :1; 1450 uint32_t atc_req :1; 1451 uint32_t atc_xlat :1; 1452 uint32_t :1; 1453 uint32_t no_snoop :1; 1454 uint32_t :8; 1455 uint32_t status :4; /* dw 0, byte 0-3 */ 1456 1457 uint32_t pd :24; 1458 uint32_t ren_inval :1; 1459 uint32_t en_inval :1; 1460 uint32_t net_cache :1; 1461 uint32_t fast_reg_en :1; 1462 uint32_t rem_acc_en :1; 1463 uint32_t w_dif :1; 1464 uint32_t m_dif :1; 1465 uint32_t :1; /* dw 2, byte 0xc-f */ 1466 1467 uint32_t mem_key; 1468 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1469 1470 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1471 1472 uint32_t win_cnt :24; 1473 uint32_t :8; /* dw 9, byte 0x24-27 */ 1474 1475 uint32_t lkey; /* dw 8, byte 0x20-23 */ 1476 1477 uint32_t mtt_addr_h :8; 1478 uint32_t :24; /* dw 11, byte 0x2c-2f */ 1479 1480 uint32_t mtt_rep :4; 1481 uint32_t :17; 1482 uint32_t blk_mode :1; 1483 uint32_t len_b64 :1; /* bit 64 of length */ 1484 uint32_t fbo_en :1; 1485 uint32_t :8; /* dw 10, byte 0x28-2b */ 1486 1487 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1488 1489 uint32_t :3; 1490 uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */ 1491 1492 uint32_t mtt_fbo :21; 1493 uint32_t :11; /* dw 15, byte 0x3c-3f */ 1494 1495 uint32_t entity_sz :21; 1496 uint32_t :11; /* dw 14, byte 0x38-3b */ 1497 1498 }; 1499 1500 1501 #else /* BIG ENDIAN */ 1502 struct hermon_hw_cmpt_s { 1503 uint32_t status :4; 1504 uint32_t :8; 1505 uint32_t no_snoop :1; 1506 uint32_t :1; 1507 uint32_t atc_xlat :1; 1508 uint32_t atc_req :1; 1509 uint32_t en_bind :1; 1510 uint32_t atomic :1; 1511 uint32_t rw :1; 1512 uint32_t rr :1; 1513 uint32_t lw :1; 1514 uint32_t lr :1; 1515 uint32_t phys_addr :1; 1516 uint32_t reg_win :1; 1517 uint32_t :8; /* dw 0, byte 0x0-3 */ 1518 1519 uint32_t qpn :24; 1520 uint32_t bnd_qp :1; 1521 uint32_t :7; /* dw 1, byte 0x4-7 */ 1522 1523 uint32_t mem_key; /* dw 2, byte 0x8-b */ 1524 1525 uint32_t :1; 1526 uint32_t m_dif :1; 1527 uint32_t w_dif :1; 1528 uint32_t rem_acc_en :1; 1529 uint32_t fast_reg_en :1; 1530 uint32_t net_cache :1; 1531 uint32_t en_inval :1; 1532 uint32_t ren_inval :1; 1533 uint32_t pd :24; /* dw 3, byte 0xc-f */ 1534 1535 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1536 1537 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1538 1539 uint32_t lkey; /* dw 8, bytd 0x20-23 */ 1540 1541 uint32_t :8; 1542 uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */ 1543 1544 uint32_t :8; 1545 uint32_t fbo_en :1; 1546 uint32_t len_b64 :1; /* bit 64 of length */ 1547 uint32_t blk_mode :1; 1548 uint32_t :17; 1549 uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */ 1550 1551 uint32_t :24; 1552 uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */ 1553 1554 uint32_t mtt_addr_l :29; 1555 uint32_t :3; /* dw 12, byte 0x30-33 */ 1556 1557 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1558 1559 uint32_t :11; 1560 uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */ 1561 }; 1562 #endif 1563 1564 1565 #define HERMON_MEM_CYCLE_GENERATE 0x1 1566 #define HERMON_IO_CYCLE_GENERATE 0x0 1567 1568 #define HERMON_MPT_IS_WINDOW 0x0 1569 #define HERMON_MPT_IS_REGION 0x1 1570 1571 #define HERMON_MPT_DEFAULT_VERSION 0x0 1572 1573 #define HERMON_UNLIMITED_WIN_BIND 0x0 1574 1575 #define HERMON_PHYSADDR_ENABLED 0x1 1576 #define HERMON_PHYSADDR_DISABLED 0x0 1577 1578 1579 /* 1580 * Hermon Memory Translation Table (MTT) entries 1581 * After accessing the MPT table (above) and validating the access rights 1582 * to the region/window, Hermon address translation moves to the next step 1583 * where it translates the virtual address to a physical address. This 1584 * translation is performed using the Memory Translation Table entries 1585 * (MTT). Note: The MTT in hardware is organized into segments and each 1586 * segment contains multiple address translation pages (MTT entries). 1587 * Each memory region (MPT above) points to the first segment in the MTT 1588 * that corresponds to that region. 1589 */ 1590 1591 #ifdef _LITTLE_ENDIAN 1592 struct hermon_hw_mtt_s { 1593 uint32_t present :1; 1594 uint32_t :2; 1595 uint32_t ptag_l :29; 1596 1597 uint32_t ptag_h; 1598 }; 1599 #else /* BIG_ENDIAN */ 1600 struct hermon_hw_mtt_s { 1601 uint32_t ptag_h; 1602 1603 uint32_t ptag_l :29; 1604 uint32_t :2; 1605 uint32_t present :1; 1606 }; 1607 1608 #endif 1609 #define HERMON_MTT_ENTRY_NOTPRESENT 0x0 1610 #define HERMON_MTT_ENTRY_PRESENT 0x1 1611 1612 1613 /* 1614 * Hermon Event Queue Context Table (EQC) entries 1615 * Hermon supports 512 Event Queues, and the status of Event Queues is stored 1616 * in the Event Queue Context (EQC) table. The EQC table is a virtually- 1617 * contiguous memory structure in the ICM. Each EQC 1618 * table entry contains Event Queue status and information required by 1619 * the hardware in order to access the event queue. 1620 * NOTE that in Hermon (as opposed to earlier HCAs), 1621 * you have to allocate ICM for 2**32 (or about 16 M), even though 1622 * it doesn't support that many. See PRM v35. Also, some set of them 1623 * will be available for each domain in a virtual environment, needing to 1624 * rething the allocation and usage model for EQs - in the future. 1625 * 1626 * The following structure is used in the SW2HW_EQ, QUERY_EQ, and HW2SW_EQ 1627 * commands. 1628 * The SW2HW_EQ command transfers ownership of an EQ context from software 1629 * to hardware. The command takes the EQC entry from the input mailbox and 1630 * stores it in the EQC in the hardware. The command will fail if the 1631 * requested EQC entry is already owned by the hardware. NOTE: the 1632 * initialization of the cMPT for the EQC occurs implicitly as a result 1633 * of executing this command, and MR has/had to be adjusted for it. 1634 * The QUERY_EQ command retrieves a snapshot of an EQC entry. The command 1635 * stores the snapshot in the output mailbox. The EQC state and its values 1636 * are not affected by the QUERY_EQ command. 1637 * Finally, the HW2SW_EQ command transfers ownership of an EQC entry from 1638 * the hardware to the software. The command takes the EQC entry from the 1639 * hardware and stores it in the output mailbox. The EQC entry will be 1640 * invalidated as a result of the command. It is the responsibility of the 1641 * software to unmap all the events, which might have been previously 1642 * mapped to the EQ, prior to issuing the HW2SW_EQ command. 1643 */ 1644 1645 1646 #ifdef _LITTLE_ENDIAN 1647 struct hermon_hw_eqc_s { 1648 uint32_t :32; 1649 1650 uint32_t :8; 1651 uint32_t state :4; 1652 uint32_t :5; 1653 uint32_t overrun_ignore :1; 1654 uint32_t ev_coalesc :1; 1655 uint32_t :9; 1656 uint32_t status :4; 1657 1658 uint32_t :24; 1659 uint32_t log_eq_sz :5; 1660 uint32_t :3; 1661 1662 uint32_t :5; 1663 uint32_t pg_offs :7; 1664 uint32_t :20; 1665 1666 uint32_t intr :10; 1667 uint32_t :22; 1668 1669 uint32_t eq_max_cnt :16; 1670 uint32_t eq_period :16; 1671 1672 uint32_t :3; 1673 uint32_t mtt_base_addrl :29; 1674 1675 uint32_t mtt_base_addrh :8; 1676 uint32_t :16; 1677 uint32_t log2_pgsz :6; /* in 4K pages */ 1678 uint32_t :2; 1679 1680 uint32_t rsrv0[2]; 1681 1682 uint32_t prod_indx :24; 1683 uint32_t :8; 1684 1685 uint32_t cons_indx :24; 1686 uint32_t :8; 1687 1688 uint64_t rsrv1[2]; /* force it to 8b alignment */ 1689 }; 1690 #else /* BIG ENDIAN */ 1691 struct hermon_hw_eqc_s { 1692 uint32_t status :4; 1693 uint32_t :9; 1694 uint32_t ev_coalesc :1; 1695 uint32_t overrun_ignore :1; 1696 uint32_t :5; 1697 uint32_t state :4; 1698 uint32_t :8; 1699 1700 uint32_t :32; 1701 1702 uint32_t :20; 1703 uint32_t pg_offs :7; 1704 uint32_t :5; 1705 1706 uint32_t :3; 1707 uint32_t log_eq_sz :5; 1708 uint32_t :24; 1709 1710 uint32_t eq_period :16; 1711 uint32_t eq_max_cnt :16; 1712 1713 uint32_t :22; 1714 uint32_t intr :10; 1715 1716 uint32_t :2; 1717 uint32_t log2_pgsz :6; /* in 4K pages */ 1718 uint32_t :16; 1719 uint32_t mtt_base_addrh :8; 1720 1721 uint32_t mtt_base_addrl :29; 1722 uint32_t :3; 1723 1724 uint32_t rsrv0[2]; 1725 1726 uint32_t :8; 1727 uint32_t cons_indx :24; 1728 1729 uint32_t :8; 1730 uint32_t prod_indx :24; 1731 1732 uint64_t rsrv1[2]; /* force it to 8b alignment */ 1733 }; 1734 #endif 1735 #define HERMON_EQ_STATUS_OK 0x0 1736 #define HERMON_EQ_STATUS_OVERFLOW 0x9 1737 #define HERMON_EQ_STATUS_WRITE_FAILURE 0xA 1738 1739 #define HERMON_EQ_ARMED 0x9 1740 #define HERMON_EQ_FIRED 0xA 1741 #define HERMON_EQ_ALWAYS_ARMED 0xB 1742 1743 1744 /* 1745 * Hermon Event Queue Entries (EQE) 1746 * Each EQE contains enough information for the software to identify the 1747 * source of the event. The following structures are used to define each 1748 * of the various kinds of events that the Hermon hardware will generate. 1749 * Note: The hermon_hw_eqe_t below is the generic "Event Queue Entry". All 1750 * other EQEs differ only in the contents of their "event_data" field. 1751 * 1752 * Below we first define several structures which define the contents of 1753 * the "event_data" fields: 1754 * hermon_hw_eqe_cq_t for "Completion Queue Events" 1755 * hermon_hw_eqe_qp_evt_t for "Queue Pair Events" such as Path Migration 1756 * Succeeded, Path Migration Failed, Communication Established, Send 1757 * Queue Drained, Local WQ Catastrophic Error, Invalid Request Local 1758 * WQ Error, and Local Access Violation WQ Error. 1759 * hermon_hw_eqe_cqerr_t for "Completion Queue Error Events" 1760 * hermon_hw_eqe_portstate_t for "Port State Change Events" 1761 * hermon_hw_eqe_gpio_t for "GPIO State Change Events" 1762 * hermon_hw_eqe_cmdcmpl_t for "Command Interface Completion Events" 1763 * hermon_hw_eqe_operr_t for "Operational and Catastrophic Error Events" 1764 * such as EQ Overflow, Misbehaved UAR page, Internal Parity Error, 1765 * Uplink bus error, and DDR data error. 1766 * hermon_hw_eqe_pgflt_t for "Not-present Page Fault on WQE or Data 1767 * Buffer Access". (Note: Currently, this event is unsupported). 1768 * 1769 * Note also: The following structures are not #define'd with both 1770 * little-endian and big-endian definitions. This is because their 1771 * individual fields are not directly accessed except through the macros 1772 * defined below. 1773 */ 1774 1775 1776 typedef struct hermon_hw_eqe_cq_s { 1777 uint32_t :8; 1778 uint32_t cqn :24; 1779 uint32_t rsrv0[5]; 1780 } hermon_hw_eqe_cq_t; 1781 1782 1783 1784 typedef struct hermon_hw_eqe_qp_evt_s { 1785 uint32_t :8; 1786 uint32_t qpn :24; 1787 1788 uint32_t rsrv0[5]; 1789 } hermon_hw_eqe_qpevt_t; 1790 1791 1792 typedef struct hermon_hw_eqe_cqerr_s { 1793 uint32_t :8; 1794 uint32_t cqn :24; 1795 1796 uint32_t :32; 1797 1798 uint32_t :24; 1799 uint32_t syndrome :8; 1800 1801 uint32_t rsrv0[3]; 1802 } hermon_hw_eqe_cqerr_t; 1803 #define HERMON_CQERR_OVERFLOW 0x1 1804 #define HERMON_CQERR_ACCESS_VIOLATION 0x2 1805 1806 1807 typedef struct hermon_hw_eqe_portstate_s { 1808 uint32_t rsrv0[2]; 1809 1810 uint32_t :2; 1811 uint32_t port :2; 1812 uint32_t :28; 1813 1814 uint32_t rsrv1[3]; 1815 } hermon_hw_eqe_portstate_t; 1816 #define HERMON_PORT_LINK_ACTIVE 0x4 1817 #define HERMON_PORT_LINK_DOWN 0x1 1818 1819 1820 typedef struct hermon_hw_eqe_gpio_s { 1821 uint32_t rsrv0[3]; 1822 1823 uint32_t gpio_ev0; 1824 1825 uint32_t gpio_ev1; 1826 1827 uint32_t :32; 1828 } hermon_hw_eqe_gpio_t; 1829 1830 1831 typedef struct hermon_hw_eqe_cmdcmpl_s { 1832 uint32_t :16; 1833 uint32_t token :16; 1834 1835 uint32_t :32; 1836 1837 uint32_t :24; 1838 uint32_t status :8; 1839 1840 uint32_t out_param0; 1841 1842 uint32_t out_param1; 1843 1844 uint32_t :32; 1845 } hermon_hw_eqe_cmdcmpl_t; 1846 1847 1848 typedef struct hermon_hw_eqe_operr_s { 1849 uint32_t rsrv0[2]; 1850 1851 uint32_t :24; 1852 uint32_t error_type :8; 1853 1854 uint32_t data; 1855 1856 uint32_t rsrv1[2]; 1857 } hermon_hw_eqe_operr_t; 1858 #define HERMON_ERREVT_EQ_OVERFLOW 0x1 1859 #define HERMON_ERREVT_BAD_UARPG 0x2 1860 #define HERMON_ERREVT_UPLINK_BUSERR 0x3 1861 #define HERMON_ERREVT_DDR_DATAERR 0x4 1862 #define HERMON_ERREVT_INTERNAL_PARITY 0x5 1863 1864 1865 typedef struct hermon_hw_eqe_pgflt_s { 1866 uint32_t rsrv0[2]; 1867 uint32_t :24; 1868 uint32_t fault_type :4; 1869 uint32_t wqv :1; 1870 uint32_t wqe_data :1; 1871 uint32_t rem_loc :1; 1872 uint32_t snd_rcv :1; 1873 uint32_t vaddr_h; 1874 uint32_t vaddr_l; 1875 uint32_t mem_key; 1876 } hermon_hw_eqe_pgflt_t; 1877 #define HERMON_PGFLT_PG_NOTPRESENT 0x8 1878 #define HERMON_PGFLT_PG_WRACC_VIOL 0xA 1879 #define HERMON_PGFLT_UNSUP_NOTPRESENT 0xE 1880 #define HERMON_PGFLT_UNSUP_WRACC_VIOL 0xF 1881 #define HERMON_PGFLT_WQE_CAUSED 0x1 1882 #define HERMON_PGFLT_DATA_CAUSED 0x0 1883 #define HERMON_PGFLT_REMOTE_CAUSED 0x1 1884 #define HERMON_PGFLT_LOCAL_CAUSED 0x0 1885 #define HERMON_PGFLT_SEND_CAUSED 0x1 1886 #define HERMON_PGFLT_RECV_CAUSED 0x0 1887 #define HERMON_PGFLT_DESC_CONSUMED 0x1 1888 #define HERMON_PGFLT_DESC_NOTCONSUMED 0x0 1889 1890 struct hermon_hw_eqe_s { 1891 uint32_t :8; 1892 uint32_t event_type :8; 1893 uint32_t :8; 1894 uint32_t event_subtype :8; 1895 union { 1896 hermon_hw_eqe_cq_t eqe_cq; 1897 hermon_hw_eqe_qpevt_t eqe_qpevt; 1898 hermon_hw_eqe_cqerr_t eqe_cqerr; 1899 hermon_hw_eqe_portstate_t eqe_portstate; 1900 hermon_hw_eqe_gpio_t eqe_gpio; 1901 hermon_hw_eqe_cmdcmpl_t eqe_cmdcmpl; 1902 hermon_hw_eqe_operr_t eqe_operr; 1903 hermon_hw_eqe_pgflt_t eqe_pgflt; 1904 } event_data; 1905 uint32_t :24; 1906 uint32_t owner :1; 1907 uint32_t :7; 1908 }; 1909 #define eqe_cq event_data.eqe_cq 1910 #define eqe_qpevt event_data.eqe_qpevt 1911 #define eqe_cqerr event_data.eqe_cqerr 1912 #define eqe_portstate event_data.eqe_portstate 1913 #define eqe_gpio event_data.eqe_gpio 1914 #define eqe_cmdcmpl event_data.eqe_cmdcmpl 1915 #define eqe_operr event_data.eqe_operr 1916 #define eqe_pgflt event_data.eqe_pgflt 1917 1918 /* 1919 * The following macros are used for extracting (and in some cases filling in) 1920 * information from EQEs 1921 */ 1922 #define HERMON_EQE_CQNUM_MASK 0x00FFFFFF 1923 #define HERMON_EQE_CQNUM_SHIFT 0 1924 #define HERMON_EQE_QPNUM_MASK 0x00FFFFFF 1925 #define HERMON_EQE_QPNUM_SHIFT 0 1926 #define HERMON_EQE_PORTNUM_MASK 0x30 1927 #define HERMON_EQE_PORTNUM_SHIFT 4 1928 #define HERMON_EQE_OWNER_MASK 0x00000080 1929 #define HERMON_EQE_OWNER_SHIFT 7 1930 1931 #define HERMON_EQE_EVTTYPE_GET(eq, eqe) \ 1932 (((uint8_t *)(eqe))[1]) 1933 #define HERMON_EQE_EVTSUBTYPE_GET(eq, eqe) \ 1934 (((uint8_t *)(eqe))[3]) 1935 #define HERMON_EQE_CQNUM_GET(eq, eqe) \ 1936 ((htonl(((uint32_t *)(eqe))[1]) & HERMON_EQE_CQNUM_MASK) >> \ 1937 HERMON_EQE_CQNUM_SHIFT) 1938 #define HERMON_EQE_QPNUM_GET(eq, eqe) \ 1939 ((htonl(((uint32_t *)(eqe))[1]) & HERMON_EQE_QPNUM_MASK) >> \ 1940 HERMON_EQE_QPNUM_SHIFT) 1941 #define HERMON_EQE_PORTNUM_GET(eq, eqe) \ 1942 (((((uint8_t *)(eqe))[12]) & HERMON_EQE_PORTNUM_MASK) >> \ 1943 HERMON_EQE_PORTNUM_SHIFT) 1944 #define HERMON_EQE_CMDTOKEN_GET(eq, eqe) \ 1945 htons(((uint16_t *)(eqe))[3]) 1946 #define HERMON_EQE_CMDSTATUS_GET(eq, eqe) \ 1947 (((uint8_t *)(eqe))[0xf]) 1948 #define HERMON_EQE_CMDOUTP0_GET(eq, eqe) \ 1949 htonl(((uint32_t *)(eqe))[4]) 1950 #define HERMON_EQE_CMDOUTP1_GET(eq, eqe) \ 1951 htonl(((uint32_t *)(eqe))[5]) 1952 #define HERMON_EQE_OPERRTYPE_GET(eq, eqe) \ 1953 (((uint8_t *)(eqe))[0xf]) 1954 #define HERMON_EQE_OPERRDATA_GET(eq, eqe) \ 1955 htonl(((uint32_t *)(eqe))[4]) 1956 /* 1957 * Hermon does ownership of CQ and EQ differently from Arbel & Tavor. 1958 * Now, you keep track of the TOTAL number of CQE's or EQE's that have been 1959 * processed, and the sense of the ownership bit changes each time through. 1960 * That is, if the size of the queue is 16, so 4 bits [3:0] are the index 1961 * number, then bit [4] is the ownership bit in the count. So you mask that 1962 * bit and compare it to the owner bit in the entry - if the same, then the 1963 * entry is in SW onwership. Otherwise, it's in hardware and the driver 1964 * does not consume it. 1965 */ 1966 1967 #define HERMON_EQE_OWNER_IS_SW(eq, eqe) \ 1968 ((((uint8_t *)(eqe))[0x1f] & HERMON_EQE_OWNER_MASK) == \ 1969 (((eq->eq_nexteqe) & eq->eq_bufsz) >> \ 1970 (eq->eq_log_eqsz - HERMON_EQE_OWNER_SHIFT))) 1971 1972 /* 1973 * Hermon Completion Queue Context Table (CQC) entries 1974 * The CQC table is a virtually-contiguous memory area residing in HCA's 1975 * ICM. Each CQC table entry contains information 1976 * required by the hardware to access the completion queue to post 1977 * completions (CQE). 1978 * 1979 * The following structure is used in the SW2HW_CQ, QUERY_CQ, RESIZE_CQ, 1980 * and HW2SW_CQ commands. 1981 * The SW2HW_CQ command transfers ownership of an CQ context from software 1982 * to hardware. The command takes the CQC entry from the input mailbox and 1983 * stores it in the CQC in the hardware. The command will fail if the 1984 * requested CQC entry is already owned by the hardware. 1985 * The QUERY_CQ command retrieves a snapshot of a CQC entry. The command 1986 * stores the snapshot in the output mailbox. The CQC state and its values 1987 * are not affected by the QUERY_CQ command. 1988 * Finally, the HW2SW_CQ command transfers ownership of a CQC entry from 1989 * the hardware to the software. The command takes the CQC entry from the 1990 * hardware and stores it in the output mailbox. The CQC entry will be 1991 * invalidated as a result of the command. 1992 */ 1993 1994 1995 #ifdef _LITTLE_ENDIAN 1996 struct hermon_hw_cqc_s { 1997 uint32_t :32; 1998 1999 uint32_t :8; 2000 uint32_t state :4; 2001 uint32_t :5; 2002 uint32_t overrun_ignore :1; 2003 uint32_t cqe_coalesc :1; 2004 uint32_t :9; 2005 uint32_t status :4; 2006 2007 uint32_t usr_page :24; 2008 uint32_t log_cq_sz :5; 2009 uint32_t :3; 2010 2011 uint32_t :5; 2012 uint32_t pg_offs :7; 2013 uint32_t :20; 2014 2015 uint32_t c_eqn :9; 2016 uint32_t :23; 2017 2018 uint32_t cq_max_cnt :16; 2019 uint32_t cq_period :16; 2020 2021 uint32_t :3; 2022 uint32_t mtt_base_addl :29; 2023 2024 uint32_t mtt_base_addh :8; 2025 uint32_t :16; 2026 uint32_t log2_pgsz :6; 2027 uint32_t :2; 2028 2029 uint32_t solicit_prod_indx :24; 2030 uint32_t :8; 2031 2032 uint32_t last_notified_indx :24; 2033 uint32_t :8; 2034 2035 uint32_t prod_cntr :24; /* producer counter */ 2036 uint32_t :8; 2037 2038 uint32_t cons_cntr :24; /* consumer counter */ 2039 uint32_t :8; 2040 2041 uint32_t rsrv0[2]; 2042 2043 uint32_t :3; 2044 uint32_t dbr_addrl :29; 2045 2046 uint32_t dbr_addrh; 2047 2048 uint64_t rsrv1[8]; /* hermon, match DEV_CAP size */ 2049 }; 2050 #else 2051 struct hermon_hw_cqc_s { 2052 uint32_t status :4; 2053 uint32_t :9; 2054 uint32_t cqe_coalesc :1; 2055 uint32_t overrun_ignore :1; 2056 uint32_t :5; 2057 uint32_t state :4; 2058 uint32_t :8; 2059 2060 uint32_t :32; 2061 2062 uint32_t :20; 2063 uint32_t pg_offs :7; 2064 uint32_t :5; 2065 2066 uint32_t :3; 2067 uint32_t log_cq_sz :5; 2068 uint32_t usr_page :24; 2069 2070 uint32_t cq_period :16; 2071 uint32_t cq_max_cnt :16; 2072 2073 uint32_t :23; 2074 uint32_t c_eqn :9; 2075 2076 uint32_t :2; 2077 uint32_t log2_pgsz :6; 2078 uint32_t :16; 2079 uint32_t mtt_base_addh :8; 2080 2081 uint32_t mtt_base_addl :29; 2082 uint32_t :3; 2083 2084 uint32_t :8; 2085 uint32_t last_notified_indx :24; 2086 2087 uint32_t :8; 2088 uint32_t solicit_prod_indx :24; 2089 2090 uint32_t :8; 2091 uint32_t cons_cntr :24; /* consumer counter */ 2092 2093 uint32_t :8; 2094 uint32_t prod_cntr :24; /* priducer counter */ 2095 2096 uint32_t rsrv0[2]; 2097 2098 uint32_t dbr_addrh; 2099 2100 uint32_t dbr_addrl :29; 2101 uint32_t :3; 2102 2103 uint64_t rsrv1[8]; /* hermon, match DEV_CAP size */ 2104 }; 2105 #endif 2106 #define HERMON_CQ_STATUS_OK 0x0 2107 #define HERMON_CQ_STATUS_OVERFLOW 0x9 2108 #define HERMON_CQ_STATUS_WRITE_FAILURE 0xA 2109 2110 #define HERMON_CQ_DISARMED 0x0 2111 #define HERMON_CQ_ARMED 0x1 2112 #define HERMON_CQ_ARMED_SOLICITED 0x4 2113 #define HERMON_CQ_FIRED 0xA 2114 2115 /* 2116 * Hermon Completion Queue Entries (CQE) 2117 * Each CQE contains enough information for the software to associate the 2118 * completion with the Work Queue Element (WQE) to which it corresponds. 2119 * 2120 * Note: The following structure is not #define'd with both little-endian 2121 * and big-endian definitions. This is because each CQE's individual 2122 * fields are not directly accessed except through the macros defined below. 2123 */ 2124 2125 2126 struct hermon_hw_cqe_s { 2127 uint32_t dife :1; 2128 uint32_t :2; 2129 uint32_t fl :1; 2130 uint32_t fccrc_sd :1; 2131 uint32_t d2s :1; 2132 uint32_t :2; 2133 uint32_t my_qpn :24; 2134 2135 uint32_t immed_rss_val_key; 2136 2137 uint32_t grh :1; 2138 uint32_t ml_path :7; 2139 uint32_t srq_rqpn :24; 2140 2141 uint32_t sl :4; 2142 uint32_t :12; 2143 uint32_t slid :16; 2144 2145 uint32_t ipoib_status; 2146 2147 uint32_t byte_cnt; 2148 2149 uint32_t wqe_cntr :16; 2150 uint32_t checksum :16; 2151 2152 uint32_t :8; 2153 uint32_t :16; 2154 uint32_t owner :1; 2155 uint32_t send_or_recv :1; 2156 uint32_t inline_scatter :1; 2157 uint32_t opcode :5; 2158 }; 2159 #define HERMON_COMPLETION_RECV 0x0 2160 #define HERMON_COMPLETION_SEND 0x1 2161 2162 #define HERMON_CQE_DEFAULT_VERSION 0x0 2163 2164 /* 2165 * The following macros are used for extracting (and in some cases filling in) 2166 * information from CQEs 2167 */ 2168 #define HERMON_CQE_QPNUM_MASK 0x00FFFFFF 2169 #define HERMON_CQE_QPNUM_SHIFT 0 2170 2171 2172 #define HERMON_CQE_DQPN_MASK 0x00FFFFFF 2173 #define HERMON_CQE_DQPN_SHIFT 0 2174 2175 2176 #define HERMON_CQE_SL_SHIFT 4 2177 #define HERMON_CQE_GRH_MASK 0x80 2178 #define HERMON_CQE_PATHBITS_MASK 0x7F 2179 #define HERMON_CQE_SLID_15_8 0xe 2180 #define HERMON_CQE_SLID_7_0 0xf 2181 #define HERMON_CQE_OPCODE_MASK 0x1F 2182 #define HERMON_CQE_SENDRECV_MASK 0x40 2183 #define HERMON_CQE_SENDRECV_SHIFT 6 2184 #define HERMON_CQE_OWNER_MASK 0x80 2185 #define HERMON_CQE_OWNER_SHIFT 7 2186 #define HERMON_CQE_WQECNTR_15_8 0x18 2187 #define HERMON_CQE_WQECNTR_7_0 0x19 2188 /* Byte offsets for IPoIB Checksum Offload fields */ 2189 #define HERMON_CQE_CKSUM_15_8 0x1a 2190 #define HERMON_CQE_CKSUM_7_0 0x1b 2191 #define HERMON_CQE_IPOK 0x10 /* byte 0x10 in cqe */ 2192 #define HERMON_CQE_IPOK_BIT 0x10 /* bitmask for OK bit */ 2193 2194 #define HERMON_CQE_IS_IPOK(cq, cqe) \ 2195 (((uint8_t *)(cqe))[HERMON_CQE_IPOK] & HERMON_CQE_IPOK_BIT) 2196 2197 #define HERMON_CQE_CKSUM(cq, cqe) \ 2198 ((((uint8_t *)(cqe))[HERMON_CQE_CKSUM_15_8] << 8) | \ 2199 (((uint8_t *)(cqe))[HERMON_CQE_CKSUM_7_0])) 2200 2201 #define HERMON_CQE_IPOIB_STATUS(cq, cqe) \ 2202 htonl((((uint32_t *)(cqe)))[4]) 2203 2204 #define HERMON_CQE_QPNUM_GET(cq, cqe) \ 2205 ((htonl((((uint32_t *)(cqe)))[0]) & HERMON_CQE_QPNUM_MASK) >> \ 2206 HERMON_CQE_QPNUM_SHIFT) 2207 2208 #define HERMON_CQE_IMM_ETH_PKEY_CRED_GET(cq, cqe) \ 2209 htonl(((uint32_t *)(cqe))[1]) 2210 2211 #define HERMON_CQE_DQPN_GET(cq, cqe) \ 2212 ((htonl(((uint32_t *)(cqe))[2]) & HERMON_CQE_DQPN_MASK) >> \ 2213 HERMON_CQE_DQPN_SHIFT) 2214 2215 #define HERMON_CQE_GRH_GET(cq, cqe) \ 2216 (((uint8_t *)(cqe))[8] & HERMON_CQE_GRH_MASK) 2217 2218 #define HERMON_CQE_PATHBITS_GET(cq, cqe) \ 2219 (((uint8_t *)(cqe))[8] & HERMON_CQE_PATHBITS_MASK) 2220 2221 #define HERMON_CQE_DLID_GET(cq, cqe) \ 2222 ((((uint8_t *)(cqe))[HERMON_CQE_SLID_15_8] << 8) | \ 2223 (((uint8_t *)(cqe))[HERMON_CQE_SLID_7_0])) 2224 2225 #define HERMON_CQE_SL_GET(cq, cqe) \ 2226 ((((uint8_t *)(cqe))[12]) >> HERMON_CQE_SL_SHIFT) 2227 2228 #define HERMON_CQE_BYTECNT_GET(cq, cqe) \ 2229 htonl(((uint32_t *)(cqe))[5]) 2230 2231 #define HERMON_CQE_WQECNTR_GET(cq, cqe) \ 2232 ((((uint8_t *)(cqe))[HERMON_CQE_WQECNTR_15_8] << 8) | \ 2233 (((uint8_t *)(cqe))[HERMON_CQE_WQECNTR_7_0])) 2234 2235 #define HERMON_CQE_ERROR_SYNDROME_GET(cq, cqe) \ 2236 (((uint8_t *)(cqe))[27]) 2237 2238 #define HERMON_CQE_OPCODE_GET(cq, cqe) \ 2239 ((((uint8_t *)(cqe))[31]) & HERMON_CQE_OPCODE_MASK) 2240 2241 #define HERMON_CQE_SENDRECV_GET(cq, cqe) \ 2242 (((((uint8_t *)(cqe))[31]) & HERMON_CQE_SENDRECV_MASK) >> \ 2243 HERMON_CQE_SENDRECV_SHIFT) 2244 2245 /* See Comment above for EQE - ownership of CQE is handled the same */ 2246 2247 #define HERMON_CQE_OWNER_IS_SW(cq, cqe, considx) \ 2248 (((((uint8_t *)(cqe))[31] & HERMON_CQE_OWNER_MASK) >> \ 2249 HERMON_CQE_OWNER_SHIFT) == \ 2250 (((considx) & cq->cq_bufsz) >> cq->cq_log_cqsz)) 2251 2252 /* 2253 * Hermon Shared Receive Queue (SRQ) Context Entry Format 2254 */ 2255 2256 #ifdef _LITTLE_ENDIAN 2257 struct hermon_hw_srqc_s { 2258 uint32_t xrc_domain :16; 2259 uint32_t :8; 2260 uint32_t log_rq_stride :3; 2261 uint32_t :5; 2262 2263 uint32_t srqn :24; 2264 uint32_t log_srq_size :4; 2265 uint32_t state :4; 2266 2267 uint32_t :32; 2268 2269 uint32_t cqn_xrc :24; 2270 uint32_t :2; 2271 uint32_t page_offs :6; 2272 2273 uint32_t :3; 2274 uint32_t mtt_base_addrl :29; 2275 2276 uint32_t mtt_base_addrh :8; 2277 uint32_t :16; 2278 uint32_t log2_pgsz :6; 2279 uint32_t :2; 2280 2281 uint32_t wqe_cnt :16; 2282 uint32_t lwm :16; 2283 2284 uint32_t pd :24; 2285 uint32_t :8; 2286 2287 uint32_t :32; 2288 2289 uint32_t srq_wqe_cntr :16; 2290 uint32_t :16; 2291 2292 uint32_t :2; 2293 uint32_t dbr_addrl :30; 2294 2295 uint32_t dbr_addrh; 2296 2297 uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */ 2298 2299 }; 2300 #else 2301 struct hermon_hw_srqc_s { 2302 uint32_t state :4; 2303 uint32_t log_srq_size :4; 2304 uint32_t srqn :24; 2305 2306 uint32_t :5; 2307 uint32_t log_rq_stride :3; 2308 uint32_t :8; 2309 uint32_t xrc_domain :16; 2310 2311 uint32_t page_offs :6; 2312 uint32_t :2; 2313 uint32_t cqn_xrc :24; 2314 2315 uint32_t :32; 2316 2317 uint32_t :2; 2318 uint32_t log2_pgsz :6; 2319 uint32_t :16; 2320 uint32_t mtt_base_addrh :8; 2321 2322 uint32_t mtt_base_addrl :29; 2323 uint32_t :3; 2324 2325 uint32_t :8; 2326 uint32_t pd :24; 2327 2328 uint32_t lwm :16; 2329 uint32_t wqe_cnt :16; 2330 2331 uint32_t :16; 2332 uint32_t srq_wqe_cntr :16; 2333 2334 uint32_t :32; 2335 2336 uint32_t dbr_addrh; 2337 2338 uint32_t dbr_addrl :30; 2339 uint32_t :2; 2340 2341 uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */ 2342 }; 2343 #endif 2344 2345 /* 2346 * Hermon MOD_STAT_CFG input mailbox structure 2347 */ 2348 2349 2350 #ifdef _LITTLE_ENDIAN 2351 struct hermon_hw_mod_stat_cfg_s { 2352 uint32_t rsvd0; 2353 2354 uint32_t :14; 2355 uint32_t dife :1; 2356 uint32_t dife_m :1; 2357 uint32_t rx_options :4; 2358 uint32_t :3; 2359 uint32_t rx_options_m :1; 2360 uint32_t tx_options :4; 2361 uint32_t :3; 2362 uint32_t tx_options_m :1; 2363 2364 uint32_t lid :16; 2365 uint32_t lid_m :1; 2366 uint32_t :3; 2367 uint32_t port_en :1; 2368 uint32_t port_en_m :1; 2369 uint32_t :10; 2370 2371 uint32_t rsvd1; 2372 2373 uint32_t guid_hi; 2374 2375 uint32_t :31; 2376 uint32_t guid_hi_m :1; 2377 2378 uint32_t guid_lo; 2379 uint32_t :31; 2380 2381 uint32_t guid_lo_m :1; 2382 2383 uint32_t rsvd[4]; 2384 2385 uint32_t inbuf_ind_en :3; 2386 uint32_t :1; 2387 uint32_t sd_main :4; 2388 uint32_t :4; 2389 uint32_t sd_equal :4; 2390 uint32_t :4; 2391 uint32_t sd_mux_main :2; 2392 uint32_t :2; 2393 uint32_t mux_eq :2; 2394 uint32_t :2; 2395 uint32_t sigdet_th :3; 2396 uint32_t :1; 2397 2398 uint32_t ob_preemp_pre :5; 2399 uint32_t :3; 2400 uint32_t op_preemp_post :5; 2401 uint32_t :3; 2402 uint32_t ob_preemp_main :5; 2403 uint32_t :3; 2404 uint32_t ob_preemp :5; 2405 uint32_t :2; 2406 uint32_t serdes_m :1; 2407 2408 uint32_t reserved[50]; 2409 }; 2410 #else /* BIG ENDIAN */ 2411 struct hermon_hw_mod_stat_cfg_s { 2412 uint32_t tx_options_m :1; 2413 uint32_t :3; 2414 uint32_t tx_options :4; 2415 uint32_t rx_options_m :1; 2416 uint32_t :3; 2417 uint32_t rx_options :4; 2418 uint32_t dife_m :1; 2419 uint32_t dife :1; 2420 uint32_t :14; 2421 2422 uint32_t rsvd0; 2423 2424 uint32_t rsvd1; 2425 2426 uint32_t :10; 2427 uint32_t port_en_m :1; 2428 uint32_t port_en :1; 2429 uint32_t :3; 2430 uint32_t lid_m :1; 2431 uint32_t lid :16; 2432 2433 uint32_t guid_hi_m :1; 2434 uint32_t :31; 2435 2436 uint32_t guid_hi; 2437 2438 uint32_t guid_lo_m :1; 2439 uint32_t :31; 2440 2441 uint32_t guid_lo; 2442 2443 uint32_t rsvd[4]; 2444 2445 uint32_t serdes_m :1; 2446 uint32_t :2; 2447 uint32_t ob_preemp :5; 2448 uint32_t :3; 2449 uint32_t ob_preemp_main :5; 2450 uint32_t :3; 2451 uint32_t op_preemp_post :5; 2452 uint32_t :3; 2453 uint32_t ob_preemp_pre :5; 2454 2455 uint32_t :1; 2456 uint32_t sigdet_th :3; 2457 uint32_t :2; 2458 uint32_t mux_eq :2; 2459 uint32_t :2; 2460 uint32_t sd_mux_main :2; 2461 uint32_t :4; 2462 uint32_t sd_equal :4; 2463 uint32_t :4; 2464 uint32_t sd_main :4; 2465 uint32_t :1; 2466 uint32_t inbuf_ind_en :3; 2467 2468 uint32_t reserved[50]; 2469 }; 2470 #endif 2471 2472 2473 /* 2474 * Hermon MOD_STAT_CFG input modifier structure 2475 */ 2476 struct hermon_hw_msg_in_mod_s { 2477 #ifdef _LITTLE_ENDIAN 2478 uint32_t offset :8; 2479 uint32_t port_num :8; 2480 uint32_t lane_num :4; 2481 uint32_t link_speed :3; 2482 uint32_t auto_neg :1; 2483 uint32_t :8; 2484 #else 2485 uint32_t :8; 2486 uint32_t auto_neg :1; 2487 uint32_t link_speed :3; 2488 uint32_t lane_num :4; 2489 uint32_t port_num :8; 2490 uint32_t offset :8; 2491 #endif 2492 }; 2493 2494 2495 /* 2496 * Hermon UD Address Vector (UDAV) 2497 * Hermon UDAV are used in conjunction with Unreliable Datagram (UD) send 2498 * WQEs. Each UD send message contains an address vector in in the datagram 2499 * segment. The verbs consumer must use special verbs to create and modify 2500 * address handles, each of which contains a UDAV structure. When posting 2501 * send WQEs to UD QP, the verbs consumer must supply a valid address 2502 * handle/UDAV. 2503 */ 2504 2505 2506 #ifdef _LITTLE_ENDIAN 2507 struct hermon_hw_udav_s { 2508 uint32_t rlid :16; 2509 uint32_t ml_path :7; 2510 uint32_t grh :1; 2511 uint32_t :8; 2512 2513 uint32_t pd :24; 2514 uint32_t portnum :2; 2515 uint32_t :5; 2516 uint32_t force_lp :1; 2517 2518 uint32_t flow_label :20; 2519 uint32_t tclass :8; 2520 uint32_t sl :4; 2521 2522 uint32_t hop_limit :8; 2523 uint32_t max_stat_rate :4; 2524 uint32_t :4; 2525 uint32_t mgid_index :7; 2526 uint32_t :9; 2527 2528 uint64_t rgid_h; 2529 uint64_t rgid_l; 2530 }; 2531 #else 2532 struct hermon_hw_udav_s { 2533 uint32_t force_lb :1; 2534 uint32_t :5; 2535 uint32_t portnum :2; 2536 uint32_t pd :24; 2537 2538 uint32_t :8; 2539 uint32_t grh :1; 2540 uint32_t ml_path :7; 2541 uint32_t rlid :16; 2542 2543 uint32_t :9; 2544 uint32_t mgid_index :7; 2545 uint32_t :4; 2546 uint32_t max_stat_rate :4; 2547 uint32_t hop_limit :8; 2548 2549 uint32_t sl :4; 2550 uint32_t tclass :8; 2551 uint32_t flow_label :20; 2552 2553 uint64_t rgid_h; 2554 uint64_t rgid_l; 2555 }; 2556 #endif 2557 #define HERMON_UDAV_MODIFY_MASK0 0xFCFFFFFFFF000000ULL 2558 #define HERMON_UDAV_MODIFY_MASK1 0xFF80F00000000000ULL 2559 2560 2561 /* 2562 * Hermon Queue Pair Context Table (QPC) entries 2563 * The QPC table is a virtually-contiguous memory area residing in HCA 2564 * ICM. Each QPC entry is accessed for reads and writes 2565 * by the HCA while executing work requests on the associated QP. 2566 * 2567 * The following structure is used in the RST2INIT_QP, INIT2INIT_QP, 2568 * INIT2RTR_QP, RTR2RTS_QP, RTS2RTS_QP, SQERR2RTS_QP, TOERR_QP, RTS2SQD_QP, 2569 * SQD2RTS_QP, TORST_QP, and QUERY_QP commands. 2570 * With the exception of the QUERY_QP command, each of these commands reads 2571 * from some portion of the QPC in the input mailbox and modified the QPC 2572 * stored in the hardware. The QUERY_QP command retrieves a snapshot of a 2573 * QPC entry. The command stores the snapshot in the output mailbox. The 2574 * QPC state and its values are not affected by the QUERY_QP command. 2575 * 2576 * Below we first define the hermon_hw_addr_path_t or "Hermon Address Path" 2577 * structure. This structure is used to provide address path information 2578 * (both primary and secondary) for each QP context. Note: Since this 2579 * structure is _very_ similar to the hermon_hw_udav_t structure above, 2580 * we are able to leverage the similarity with filling in and reading from 2581 * the two types of structures. See hermon_get_addr_path() and 2582 * hermon_set_addr_path() in hermon_misc.c for more details. 2583 */ 2584 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2585 #pragma pack(4) 2586 #endif 2587 2588 #ifdef _LITTLE_ENDIAN 2589 struct hermon_hw_addr_path_s { 2590 uint32_t rlid :16; 2591 uint32_t mlid :7; 2592 uint32_t grh :1; 2593 uint32_t cntr_idx :8; 2594 2595 uint32_t pkey_indx :7; 2596 uint32_t :22; 2597 uint32_t :2; /* but may be used for enet */ 2598 uint32_t force_lb :1; 2599 2600 uint32_t flow_label :20; 2601 uint32_t tclass :8; 2602 uint32_t :4; 2603 2604 uint32_t hop_limit :8; 2605 uint32_t max_stat_rate :4; 2606 uint32_t :4; 2607 uint32_t mgid_index :7; 2608 uint32_t :4; 2609 uint32_t ack_timeout :5; 2610 2611 uint64_t rgid_h; 2612 uint64_t rgid_l; 2613 2614 uint32_t :32; /* but may be used for enet */ 2615 2616 uint32_t :12; /* but may be used for enet */ 2617 uint32_t fsip :1; 2618 uint32_t :3; 2619 uint32_t :7; 2620 uint32_t :1; 2621 uint32_t sched_q :8; 2622 2623 2624 uint32_t :32; 2625 }; 2626 #else 2627 struct hermon_hw_addr_path_s { 2628 uint32_t force_lb :1; 2629 uint32_t :2; /* but may be used for enet */ 2630 uint32_t :22; 2631 uint32_t pkey_indx :7; 2632 2633 uint32_t cntr_idx :8; 2634 uint32_t grh :1; 2635 uint32_t mlid :7; 2636 uint32_t rlid :16; 2637 2638 uint32_t ack_timeout :5; 2639 uint32_t :4; 2640 uint32_t mgid_index :7; 2641 uint32_t :4; 2642 uint32_t max_stat_rate :4; 2643 uint32_t hop_limit :8; 2644 2645 uint32_t :4; 2646 uint32_t tclass :8; 2647 uint32_t flow_label :20; 2648 2649 uint64_t rgid_h; 2650 uint64_t rgid_l; 2651 2652 uint32_t sched_q :8; 2653 uint32_t :1; 2654 uint32_t :7; 2655 uint32_t :3; 2656 uint32_t fsip :1; 2657 uint32_t :12; /* but may be used for enet */ 2658 2659 uint32_t :32; /* but may be used for enet */ 2660 2661 uint32_t :32; 2662 }; 2663 #endif /* LITTLE ENDIAN */ 2664 2665 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2666 #pragma pack() 2667 #endif 2668 2669 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2670 #pragma pack(4) 2671 #endif 2672 #ifdef _LITTLE_ENDIAN 2673 struct hermon_hw_qpc_s { 2674 uint32_t pd :24; 2675 uint32_t :8; 2676 2677 uint32_t :11; 2678 uint32_t pm_state :2; 2679 uint32_t rss :1; 2680 uint32_t :2; 2681 uint32_t serv_type :8; 2682 uint32_t :4; 2683 uint32_t state :4; 2684 2685 uint32_t usr_page :24; 2686 uint32_t :8; 2687 2688 uint32_t :4; 2689 uint32_t rlky :1; 2690 uint32_t :3; 2691 uint32_t log_sq_stride :3; 2692 uint32_t log_sq_size :4; 2693 uint32_t sq_no_prefetch :1; 2694 uint32_t log_rq_stride :3; 2695 uint32_t log_rq_size :4; 2696 uint32_t :1; 2697 uint32_t msg_max :5; 2698 uint32_t mtu :3; 2699 2700 uint32_t rem_qpn :24; 2701 uint32_t :8; 2702 2703 uint32_t loc_qpn :24; 2704 uint32_t :8; 2705 2706 hermon_hw_addr_path_t pri_addr_path; 2707 2708 hermon_hw_addr_path_t alt_addr_path; 2709 2710 uint32_t :32; 2711 2712 uint32_t :5; 2713 uint32_t cur_retry_cnt :3; 2714 uint32_t cur_rnr_retry :3; 2715 uint32_t fre :1; 2716 uint32_t :1; 2717 uint32_t rnr_retry :3; 2718 uint32_t retry_cnt :3; 2719 uint32_t :2; 2720 uint32_t sra_max :3; 2721 uint32_t :4; 2722 uint32_t ack_req_freq :4; 2723 2724 uint32_t cqn_snd :24; 2725 uint32_t :8; 2726 2727 uint32_t next_snd_psn :24; 2728 uint32_t :8; 2729 2730 uint32_t :32; 2731 2732 uint32_t :32; 2733 2734 uint32_t ssn :24; 2735 uint32_t :8; 2736 2737 uint32_t last_acked_psn :24; 2738 uint32_t :8; 2739 2740 uint32_t next_rcv_psn :24; 2741 uint32_t min_rnr_nak :5; 2742 uint32_t :3; 2743 2744 uint32_t :4; 2745 uint32_t ric :1; 2746 uint32_t :1; 2747 uint32_t page_offs :6; 2748 uint32_t :1; 2749 uint32_t rae :1; 2750 uint32_t rwe :1; 2751 uint32_t rre :1; 2752 uint32_t :5; 2753 uint32_t rra_max :3; 2754 uint32_t :8; 2755 2756 uint32_t cqn_rcv :24; 2757 uint32_t :8; 2758 2759 uint32_t srcd :16; 2760 uint32_t :16; 2761 2762 uint32_t :2; 2763 uint32_t dbr_addrl :30; 2764 2765 uint32_t dbr_addrh :32; 2766 2767 uint32_t srq_number :24; 2768 uint32_t srq_en :1; 2769 uint32_t :7; 2770 2771 uint32_t qkey; 2772 2773 uint32_t sq_wqe_counter :16; 2774 uint32_t rq_wqe_counter :16; 2775 2776 uint32_t rmsn :24; 2777 uint32_t :8; 2778 2779 uint32_t rsrv0[2]; 2780 2781 /* new w/ hermon */ 2782 2783 uint32_t base_mkey :24; /* bits 32-8, low 7 m/b 0 */ 2784 uint32_t num_rmc_peers :8; 2785 2786 uint32_t rmc_parent_qpn :24; 2787 uint32_t header_sep :1; 2788 uint32_t inline_scatter :1; /* m/b 0 for srq */ 2789 uint32_t :1; 2790 uint32_t rmc_enable :2; 2791 uint32_t :2; /* may use one bit for enet */ 2792 uint32_t mkey_remap :1; 2793 2794 uint32_t :3; 2795 uint32_t mtt_base_addrl :29; 2796 2797 uint32_t mtt_base_addrh :8; 2798 uint32_t :16; 2799 uint32_t log2_pgsz :6; 2800 uint32_t :2; 2801 2802 uint32_t rsvd[12]; /* may/will be used for FCoIB */ 2803 }; 2804 #else /* BIG ENDIAN */ 2805 struct hermon_hw_qpc_s { 2806 uint32_t state :4; 2807 uint32_t :4; 2808 uint32_t serv_type :8; 2809 uint32_t :2; 2810 uint32_t rss :1; 2811 uint32_t pm_state :2; 2812 uint32_t :11; 2813 2814 uint32_t :8; 2815 uint32_t pd :24; 2816 2817 uint32_t mtu :3; 2818 uint32_t msg_max :5; 2819 uint32_t :1; 2820 uint32_t log_rq_size :4; 2821 uint32_t log_rq_stride :3; 2822 uint32_t sq_no_prefetch :1; 2823 uint32_t log_sq_size :4; 2824 uint32_t log_sq_stride :3; 2825 uint32_t :3; 2826 uint32_t rlky :1; 2827 uint32_t :4; 2828 2829 uint32_t :8; 2830 uint32_t usr_page :24; 2831 2832 uint32_t :8; 2833 uint32_t loc_qpn :24; 2834 2835 uint32_t :8; 2836 uint32_t rem_qpn :24; 2837 2838 hermon_hw_addr_path_t pri_addr_path; 2839 2840 hermon_hw_addr_path_t alt_addr_path; 2841 2842 uint32_t ack_req_freq :4; 2843 uint32_t :4; 2844 uint32_t sra_max :3; 2845 uint32_t :2; 2846 uint32_t retry_cnt :3; 2847 uint32_t rnr_retry :3; 2848 uint32_t :1; 2849 uint32_t fre :1; 2850 uint32_t cur_rnr_retry :3; 2851 uint32_t cur_retry_cnt :3; 2852 uint32_t :5; 2853 2854 uint32_t :32; 2855 2856 uint32_t :8; 2857 uint32_t next_snd_psn :24; 2858 2859 uint32_t :8; 2860 uint32_t cqn_snd :24; 2861 2862 uint32_t :32; 2863 2864 uint32_t :32; 2865 2866 uint32_t :8; 2867 uint32_t last_acked_psn :24; 2868 2869 uint32_t :8; 2870 uint32_t ssn :24; 2871 2872 uint32_t :8; 2873 uint32_t rra_max :3; 2874 uint32_t :5; 2875 uint32_t rre :1; 2876 uint32_t rwe :1; 2877 uint32_t rae :1; 2878 uint32_t :1; 2879 uint32_t page_offs :6; 2880 uint32_t :1; 2881 uint32_t ric :1; 2882 uint32_t :4; 2883 2884 uint32_t :3; 2885 uint32_t min_rnr_nak :5; 2886 uint32_t next_rcv_psn :24; 2887 2888 uint32_t :16; 2889 uint32_t srcd :16; 2890 2891 uint32_t :8; 2892 uint32_t cqn_rcv :24; 2893 2894 uint32_t dbr_addrh :32; 2895 2896 uint32_t dbr_addrl :30; 2897 uint32_t :2; 2898 2899 uint32_t qkey; 2900 2901 uint32_t :7; 2902 uint32_t srq_en :1; 2903 uint32_t srq_number :24; 2904 2905 uint32_t :8; 2906 uint32_t rmsn :24; 2907 2908 uint32_t rq_wqe_counter :16; 2909 uint32_t sq_wqe_counter :16; 2910 2911 uint32_t rsrv0[2]; 2912 2913 /* new w/ hermon */ 2914 2915 uint32_t mkey_remap :1; 2916 uint32_t :2; /* may use one bit for enet */ 2917 uint32_t rmc_enable :2; 2918 uint32_t :1; 2919 uint32_t inline_scatter :1; /* m/b 0 for srq */ 2920 uint32_t header_sep :1; 2921 uint32_t rmc_parent_qpn :24; 2922 2923 uint32_t num_rmc_peers :8; 2924 uint32_t base_mkey :24; /* bits 32-8, low 7 m/b 0 */ 2925 2926 uint32_t :2; 2927 uint32_t log2_pgsz :6; 2928 uint32_t :16; 2929 uint32_t mtt_base_addrh :8; 2930 2931 uint32_t mtt_base_addrl :29; 2932 uint32_t :3; 2933 2934 uint32_t rsvd[12]; /* may/will be used for FCoIB */ 2935 }; 2936 #endif /* LITTLE ENDIAN */ 2937 2938 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2939 #pragma pack() 2940 #endif 2941 2942 #define HERMON_QP_RESET 0x0 2943 #define HERMON_QP_INIT 0x1 2944 #define HERMON_QP_RTR 0x2 2945 #define HERMON_QP_RTS 0x3 2946 #define HERMON_QP_SQERR 0x4 2947 #define HERMON_QP_SQD 0x5 2948 #define HERMON_QP_ERR 0x6 2949 #define HERMON_QP_SQDRAINING 0x7 2950 2951 #define HERMON_QP_RC 0x0 2952 #define HERMON_QP_UC 0x1 2953 #define HERMON_QP_UD 0x3 2954 #define HERMON_QP_MLX 0x7 2955 2956 #define HERMON_QP_PMSTATE_MIGRATED 0x3 2957 #define HERMON_QP_PMSTATE_ARMED 0x0 2958 #define HERMON_QP_PMSTATE_REARM 0x1 2959 2960 #define HERMON_QP_DESC_EVT_DISABLED 0x0 2961 #define HERMON_QP_DESC_EVT_ENABLED 0x1 2962 2963 #define HERMON_QP_FLIGHT_LIM_UNLIMITED 0xF 2964 2965 #define HERMON_QP_SQ_ALL_SIGNALED 0x1 2966 #define HERMON_QP_SQ_WR_SIGNALED 0x0 2967 #define HERMON_QP_RQ_ALL_SIGNALED 0x1 2968 #define HERMON_QP_RQ_WR_SIGNALED 0x0 2969 2970 #define HERMON_QP_SRQ_ENABLED 0x1 2971 #define HERMON_QP_SRQ_DISABLED 0x0 2972 2973 #define HERMON_QP_WQE_BASE_SHIFT 0x6 2974 2975 /* 2976 * Hermon Multicast Group Member (MCG) 2977 * Hermon MCG are organized in a virtually-contiguous memory table (the 2978 * Multicast Group Table) in the ICM. This table is 2979 * actually comprised of two consecutive tables: the Multicast Group Hash 2980 * Table (MGHT) and the Additional Multicast Group Members Table (AMGM). 2981 * Each such entry contains an MGID and a list of QPs that are attached to 2982 * the multicast group. Each such entry may also include an index to an 2983 * Additional Multicast Group Member Table (AMGM) entry. The AMGMs are 2984 * used to form a linked list of MCG entries that all map to the same hash 2985 * value. The MCG entry size is configured through the INIT_HCA command. 2986 * Note: An MCG actually consists of a single hermon_hw_mcg_t and some 2987 * number of hermon_hw_mcg_qp_list_t (such that the combined structure is a 2988 * power-of-2). 2989 * 2990 * The following structures are used in the READ_MGM and WRITE_MGM commands. 2991 * The READ_MGM command reads an MCG entry from the multicast table and 2992 * returns it in the output mailbox. Note: This operation does not affect 2993 * the MCG entry state or values. 2994 * The WRITE_MGM command retrieves an MCG entry from the input mailbox and 2995 * stores it in the multicast group table at the index specified in the 2996 * command. Once the command has finished execution, the multicast group 2997 * table is updated. The old entry contents are lost. 2998 */ 2999 #ifdef _LITTLE_ENDIAN 3000 struct hermon_hw_mcg_s { 3001 uint32_t member_cnt :24; 3002 uint32_t :8; 3003 3004 uint32_t :6; 3005 uint32_t next_gid_indx :26; 3006 3007 uint32_t :32; 3008 uint32_t :32; 3009 3010 uint64_t mgid_h; 3011 uint64_t mgid_l; 3012 }; 3013 #else 3014 struct hermon_hw_mcg_s { 3015 uint32_t next_gid_indx :26; 3016 uint32_t :6; 3017 3018 uint32_t :8; 3019 uint32_t member_cnt :24; 3020 3021 uint32_t :32; 3022 uint32_t :32; 3023 3024 uint64_t mgid_h; 3025 uint64_t mgid_l; 3026 }; 3027 #endif 3028 3029 3030 /* Multicast Group Member - QP List entries */ 3031 #ifdef _LITTLE_ENDIAN 3032 struct hermon_hw_mcg_qp_list_s { 3033 uint32_t qpn :24; 3034 uint32_t :6; 3035 uint32_t blk_lb :1; 3036 uint32_t :1; 3037 }; 3038 #else 3039 struct hermon_hw_mcg_qp_list_s { 3040 uint32_t :1; 3041 uint32_t blk_lb :1; 3042 uint32_t :6; 3043 uint32_t qpn :24; 3044 }; 3045 #endif 3046 3047 #define HERMON_MCG_QPN_BLOCK_LB 0x40000000 3048 3049 /* 3050 * Structure for getting the peformance counters from the HCA 3051 */ 3052 3053 #ifdef _LITTLE_ENDIAN 3054 struct hermon_hw_sm_perfcntr_s { 3055 uint32_t linkdown :8; 3056 uint32_t linkerrrec :8; 3057 uint32_t symerr :16; 3058 3059 uint32_t cntrsel :16; 3060 uint32_t portsel :8; 3061 uint32_t :8; 3062 3063 uint32_t portxmdiscard :16; 3064 uint32_t portrcvswrelay :16; 3065 3066 uint32_t portrcvrem :16; 3067 uint32_t portrcv :16; 3068 3069 uint32_t vl15drop :16; 3070 uint32_t :16; 3071 3072 uint32_t xsbuffovrun :4; 3073 uint32_t locallinkint :4; 3074 uint32_t :8; 3075 uint32_t portrcconstr :8; 3076 uint32_t portxmconstr :8; 3077 3078 uint32_t portrcdata; 3079 3080 uint32_t portxmdata; 3081 3082 uint32_t portrcpkts; 3083 3084 uint32_t portxmpkts; 3085 3086 uint32_t reserved; 3087 3088 uint32_t portxmwait; 3089 }; 3090 #else /* BIG ENDIAN */ 3091 struct hermon_hw_sm_perfcntr_s { 3092 uint32_t :8; 3093 uint32_t portsel :8; 3094 uint32_t cntrsel :16; 3095 3096 uint32_t symerr :16; 3097 uint32_t linkerrrec :8; 3098 uint32_t linkdown :8; 3099 3100 uint32_t portrcv :16; 3101 uint32_t portrcvrem :16; 3102 3103 uint32_t portrcvswrelay :16; 3104 uint32_t portxmdiscard :16; 3105 3106 uint32_t portxmconstr :8; 3107 uint32_t portrcconstr :8; 3108 uint32_t :8; 3109 uint32_t locallinkint :4; 3110 uint32_t xsbuffovrun :4; 3111 3112 uint32_t :16; 3113 uint32_t vl15drop :16; 3114 3115 uint32_t portxmdata; 3116 3117 uint32_t portrcdata; 3118 3119 uint32_t portxmpkts; 3120 3121 uint32_t portrcpkts; 3122 3123 uint32_t portxmwait; 3124 3125 uint32_t reserved; 3126 }; 3127 #endif 3128 3129 /* 3130 * Structure for getting the extended peformance counters from the HCA 3131 */ 3132 3133 #ifdef _LITTLE_ENDIAN 3134 struct hermon_hw_sm_extperfcntr_s { 3135 uint32_t rsvd; 3136 uint32_t cntrsel :16; 3137 uint32_t portsel :8; 3138 uint32_t :8; 3139 3140 uint64_t portxmdata; 3141 3142 uint64_t portrcdata; 3143 3144 uint64_t portxmpkts; 3145 3146 uint64_t portrcpkts; 3147 3148 uint64_t portunicastxmpkts; 3149 3150 uint64_t portunicastrcpkts; 3151 3152 uint64_t portmulticastxmpkts; 3153 3154 uint64_t portmulticastrcpkts; 3155 }; 3156 #else /* BIG ENDIAN */ 3157 struct hermon_hw_sm_extperfcntr_s { 3158 uint32_t :8; 3159 uint32_t portsel :8; 3160 uint32_t cntrsel :16; 3161 uint32_t rsvd; 3162 3163 uint64_t portxmdata; 3164 3165 uint64_t portrcdata; 3166 3167 uint64_t portxmpkts; 3168 3169 uint64_t portrcpkts; 3170 3171 uint64_t portunicastxmpkts; 3172 3173 uint64_t portunicastrcpkts; 3174 3175 uint64_t portmulticastxmpkts; 3176 3177 uint64_t portmulticastrcpkts; 3178 }; 3179 #endif 3180 3181 3182 /* 3183 * Hermon User Access Region (UAR) 3184 * 3185 * JBDB : writeup on the UAR for memfree 3186 * 3187 * JBDB : writeup on the structures 3188 * UAR page 3189 * DB register 3190 * DB record 3191 * UCE 3192 * 3193 * [es] and change it even further for hermon 3194 * the whole UAR and doorbell record (dbr) approach is changed again 3195 * from arbel, and needs commenting 3196 * 3197 * -- Tavor comment 3198 * 3199 * 3200 * Tavor doorbells are each rung by writing to the doorbell registers that 3201 * form a User Access Region (UAR). A doorbell is a write-only hardware 3202 * register which enables passing information from software to hardware 3203 * with minimum software latency. A write operation from the host software 3204 * to these doorbell registers passes information about the HCA resources 3205 * and initiates processing of the doorbell data. There are 6 types of 3206 * doorbells in Tavor. 3207 * 3208 * "Send Doorbell" for synchronizing the attachment of a WQE (or a chain 3209 * of WQEs) to the send queue. 3210 * "RD Send Doorbell" (Same as above, except for RD QPs) is not supported. 3211 * "Receive Doorbell" for synchronizing the attachment of a WQE (or a chain 3212 * of WQEs) to the receive queue. 3213 * "CQ Doorbell" for updating the CQ consumer index and requesting 3214 * completion notifications. 3215 * "EQ Doorbell" for updating the EQ consumer index, arming interrupt 3216 * triggering, and disarming CQ notification requests. 3217 * "InfiniBlast" (which would have enabled access to the "InfiniBlast 3218 * buffer") is not supported. 3219 * 3220 * Note: The tavor_hw_uar_t below is the container for all of the various 3221 * doorbell types. Below we first define several structures which make up 3222 * the contents of those doorbell types. 3223 * 3224 * Note also: The following structures are not #define'd with both little- 3225 * endian and big-endian definitions. This is because each doorbell type 3226 * is not directly accessed except through a single ddi_put64() operation 3227 * (see tavor_qp_send_doorbell, tavor_qp_recv_doorbell, tavor_cq_doorbell, 3228 * or tavor_eq_doorbell) 3229 */ 3230 3231 /* 3232 * Send doorbell register structure 3233 */ 3234 typedef struct hermon_hw_send_db_reg_s { 3235 uint32_t :32; 3236 3237 uint32_t snd_q_num :24; 3238 uint32_t :8; 3239 } hermon_hw_send_db_reg_t; 3240 3241 #define HERMON_QPSNDDB_QPN_SHIFT 0x8 3242 3243 /* Max descriptors per Hermon doorbell */ 3244 #define HERMON_QP_MAXDESC_PER_DB 256 3245 3246 /* 3247 * CQ doorbell register structure 3248 */ 3249 typedef struct hermon_hw_cq_db_reg_s { 3250 uint32_t :2; 3251 uint32_t cmd_sn :2; 3252 uint32_t :2; 3253 uint32_t cmd :2; 3254 uint32_t cqn :24; 3255 3256 uint32_t :8; 3257 /* consumer cntr of last polled completion */ 3258 uint32_t cq_ci :24; 3259 } hermon_hw_cq_db_reg_t; 3260 3261 #define HERMON_CQDB_CMD_SHIFT 0x18 /* dec 24 */ 3262 #define HERMON_CQDB_CMDSN_SHIFT 0x1C /* dec 28 */ 3263 3264 3265 #define HERMON_CQDB_NOTIFY_CQ 0x02 3266 #define HERMON_CQDB_NOTIFY_CQ_SOLICIT 0x01 3267 3268 /* Default value for use in NOTIFY_CQ doorbell */ 3269 #define HERMON_CQDB_DEFAULT_PARAM 0xFFFFFFFF 3270 3271 typedef struct hermon_hw_guest_eq_ci_s { /* guest op eq consumer index */ 3272 uint32_t armed :1; 3273 uint32_t :7; 3274 uint32_t guestos_ci :24; 3275 3276 uint32_t :32; 3277 } hermon_hw_guest_eq_ci_t; 3278 3279 3280 3281 /* 3282 * UAR page structure, containing all doorbell registers 3283 */ 3284 struct hermon_hw_uar_s { 3285 uint32_t rsrv0[4]; 3286 3287 hermon_hw_send_db_reg_t send; 3288 3289 uint32_t rsrv1[2]; 3290 3291 hermon_hw_cq_db_reg_t cq; 3292 3293 uint32_t rsrv2[502]; /* next is at offset 0x800 */ 3294 3295 hermon_hw_guest_eq_ci_t g_eq0; 3296 hermon_hw_guest_eq_ci_t g_eq1; 3297 hermon_hw_guest_eq_ci_t g_eq2; 3298 hermon_hw_guest_eq_ci_t g_eq3; 3299 3300 uint32_t rsrv3[504]; /* end of page */ 3301 }; 3302 3303 /* 3304 * QP (RQ, SRQ) doorbell record-specific data 3305 * Note that this structure is NOT in ICM, but just kept in host memory 3306 * and managed independently of PRM or other constraints. Also, though 3307 * the qp/srq doorbell need to be only 4 bytes, it is 8 bytes in memory for 3308 * ease of management. Hermon defines its usage in the QP chapter. 3309 */ 3310 typedef struct hermon_hw_qp_db_s { 3311 uint32_t :16; 3312 uint32_t rcv_wqe_cntr :16; /* wqe_counter */ 3313 3314 uint32_t :32; 3315 } hermon_hw_qp_db_t; 3316 3317 /* 3318 * CQ (ARM and SET_CI) doorbell record-specific data 3319 * See comment above re: QP doorbell. This dbr is 8 bytes long, and its 3320 * usage is defined in PRM chapter on Completion Queues 3321 */ 3322 typedef struct hermon_hw_cq_arm_db_s { 3323 uint32_t :8; 3324 uint32_t update_ci :24; 3325 3326 uint32_t :2; 3327 /* sequence number of the doorbell ring % 4 */ 3328 uint32_t cmd_sn :2; 3329 uint32_t :1; 3330 uint32_t cmd :3; /* command */ 3331 uint32_t cq_ci :24; 3332 } hermon_hw_cq_db_t; 3333 3334 #define HERMON_CQ_DB_CMD_SOLICTED 0x01 3335 #define HERMON_CQ_DB_CMD_NEXT 0x02 3336 3337 3338 /* 3339 * Hermon Blue Flame (BF) 3340 * Hermon has the ability to do a low-latency write of successive WQEs 3341 * for the HCA. This utilizes part of the memory area behind the 3342 * same BAR as the UAR page (see above) - half the area is devoted to 3343 * UAR pages, the other half to BlueFlame (though in fairness, the return 3344 * information from QUERY_DEV_CAP should be consulted _in case_ they ever 3345 * decide to change it. 3346 * 3347 * We define the structures to access them below. 3348 */ 3349 3350 3351 /* 3352 * Hermon Send Work Queue Element (WQE) 3353 * A Hermon Send WQE is built of the following segments, each of which is a 3354 * multiple of 16 bytes. Note: Each individual WQE may contain only a 3355 * subset of these segments described below (according to the operation type 3356 * and transport type of the QP). 3357 * 3358 * The first 16 bytes of ever WQE are formed from the "Ctrl" segment. 3359 * This segment contains the address of the next WQE to be executed and the 3360 * information required in order to allocate the resources to execute the 3361 * next WQE. The "Ctrl" part of this segment contains the control 3362 * information required to execute the WQE, including the opcode and other 3363 * control information. 3364 * The "Datagram" segment contains address information required in order to 3365 * form a UD message. 3366 * The "Bind" segment contains the parameters required for a Bind Memory 3367 * Window operation. 3368 * The "Remote Address" segment is present only in RDMA or Atomic WQEs and 3369 * specifies remote virtual addresses and RKey, respectively. Length of 3370 * the remote access is calculated from the scatter/gather list (for 3371 * RDMA-write/RDMA-read) or set to eight (for Atomic). 3372 * The "Atomic" segment is present only in Atomic WQEs and specifies 3373 * Swap/Add and Compare data. 3374 * 3375 * Note: The following structures are not #define'd with both little-endian 3376 * and big-endian definitions. This is because their individual fields are 3377 * not directly accessed except through macros defined below. 3378 */ 3379 3380 3381 struct hermon_hw_snd_wqe_ctrl_s { 3382 uint32_t owner :1; 3383 /* NOTE: some/many may be used by enet */ 3384 uint32_t :26; 3385 uint32_t opcode :5; 3386 /* NOTE: some will be used by enet */ 3387 uint32_t :25; 3388 uint32_t fence :1; 3389 /* WQE size in octowords */ 3390 uint32_t ds :6; 3391 /* SRC remote buffer if impl */ 3392 uint32_t src_rem_buf :24; 3393 uint32_t so :1; 3394 uint32_t :1; /* FCoIB only */ 3395 uint32_t tcp_udp :1; /* Checksumming */ 3396 uint32_t ip :1; /* Checksumming */ 3397 uint32_t cq_gen :2; /* 00=no cqe, 11= gen cqe */ 3398 /* set means solicit bit in last packet */ 3399 uint32_t s :1; 3400 uint32_t force_lb :1; 3401 3402 uint32_t immediate :32; 3403 }; 3404 3405 struct hermon_hw_srq_wqe_next_s { 3406 uint32_t :16; 3407 uint32_t next_wqe_idx :16; 3408 3409 uint32_t rsvd[3]; 3410 }; 3411 3412 3413 #define HERMON_WQE_SEND_FENCE_MASK 0x40 3414 3415 #define HERMON_WQE_SEND_NOPCODE_NOP 0x00 3416 #define HERMON_WQE_SEND_NOPCODE_SND_INV 0x01 3417 #define HERMON_WQE_SEND_NOPCODE_RDMAW 0x8 3418 #define HERMON_WQE_SEND_NOPCODE_RDMAWI 0x9 3419 #define HERMON_WQE_SEND_NOPCODE_SEND 0xA 3420 #define HERMON_WQE_SEND_NOPCODE_SENDI 0xB 3421 #define HERMON_WQE_SEND_NOPCODE_LSO 0xE 3422 #define HERMON_WQE_SEND_NOPCODE_RDMAR 0x10 3423 #define HERMON_WQE_SEND_NOPCODE_ATMCS 0x11 3424 #define HERMON_WQE_SEND_NOPCODE_ATMFA 0x12 3425 #define HERMON_WQE_SEND_NOPCODE_ATMCSE 0x14 3426 #define HERMON_WQE_SEND_NOPCODE_ATMFAE 0x15 3427 #define HERMON_WQE_SEND_NOPCODE_BIND 0x18 3428 #define HERMON_WQE_SEND_NOPCODE_FRWR 0x19 3429 #define HERMON_WQE_SEND_NOPCODE_LCL_INV 0x1B 3430 #define HERMON_WQE_SEND_NOPCODE_CONFIG 0x1F /* for ccq only */ 3431 3432 #define HERMON_WQE_SEND_SIGNALED_MASK 0x0000000C00000000ull 3433 #define HERMON_WQE_SEND_SOLICIT_MASK 0x0000000200000000ull 3434 #define HERMON_WQE_SEND_IMMEDIATE_MASK 0x0000000100000000ull 3435 3436 struct hermon_hw_snd_wqe_ud_s { 3437 struct hermon_hw_udav_s ud_addr_v; 3438 3439 uint32_t :8; 3440 uint32_t dest_qp :24; 3441 uint32_t qkey :32; 3442 uint32_t :32; 3443 uint32_t :32; 3444 }; 3445 #define HERMON_WQE_SENDHDR_UD_AV_MASK 0xFFFFFFFFFFFFFFE0ull 3446 #define HERMON_WQE_SENDHDR_UD_DQPN_MASK 0xFFFFFF 3447 3448 struct hermon_hw_snd_wqe_bind_s { 3449 uint32_t ae :1; 3450 uint32_t rw :1; 3451 uint32_t rr :1; 3452 uint32_t :3; 3453 uint32_t l_64 :1; 3454 uint32_t :25; 3455 3456 uint32_t win_t :1; 3457 uint32_t z_base :1; 3458 uint32_t :30; 3459 3460 uint32_t new_rkey; 3461 uint32_t reg_lkey; 3462 uint64_t addr; 3463 uint64_t len; 3464 }; 3465 #define HERMON_WQE_SENDHDR_BIND_ATOM 0x8000000000000000ull 3466 #define HERMON_WQE_SENDHDR_BIND_WR 0x4000000000000000ull 3467 #define HERMON_WQE_SENDHDR_BIND_RD 0x2000000000000000ull 3468 3469 struct hermon_hw_snd_wqe_remaddr_s { 3470 uint64_t vaddr; 3471 uint32_t rkey; 3472 uint32_t :32; 3473 }; 3474 3475 struct hermon_hw_snd_wqe_atomic_s { 3476 uint64_t swap_add; 3477 uint64_t compare; 3478 }; 3479 3480 struct hermon_hw_snd_wqe_atomic_ext_s { 3481 uint64_t swap_add; 3482 uint64_t compare; 3483 uint64_t swapmask; 3484 uint64_t cmpmask; 3485 }; 3486 3487 3488 3489 struct hermon_hw_snd_wqe_local_inv_s { 3490 uint32_t :6; 3491 uint32_t atc_shoot :1; 3492 uint32_t :25; 3493 3494 uint32_t :32; 3495 3496 uint32_t mkey; 3497 3498 uint32_t :25; 3499 uint32_t guest_id :7; /* for atc shootdown */ 3500 3501 uint32_t rsrv0[6]; 3502 3503 uint32_t p_addrh; 3504 uint32_t p_addrl :23; 3505 uint32_t :9; 3506 }; 3507 3508 struct hermon_hw_snd_wqe_frwr_s { 3509 uint32_t rem_atomic :1; 3510 uint32_t rem_write :1; 3511 uint32_t rem_read :1; 3512 uint32_t loc_write :1; 3513 uint32_t loc_read :1; 3514 uint32_t fbo_en :1; 3515 uint32_t len_64 :1; 3516 uint32_t :3; /* but some for FCoIB */ 3517 uint32_t bind_en :1; 3518 uint32_t blk_pg_mode :1; 3519 uint32_t mtt_rep :4; 3520 uint32_t :16; 3521 3522 uint32_t mkey; /* swapped w/ addrh relative to arbel */ 3523 3524 uint32_t pbl_addrh; 3525 3526 uint32_t pbl_addrl :26; 3527 uint32_t :6; 3528 3529 uint64_t start_addr; 3530 3531 uint64_t reg_len; /* w/ len_64 allows 65 bits of length */ 3532 3533 uint32_t :11; 3534 uint32_t fbo :21; 3535 3536 uint32_t :11; 3537 uint32_t pge_blk_sz :21; 3538 3539 uint32_t rsrv0[2]; 3540 }; 3541 3542 /* 3543 * NOTE: Some hermon-PRM defined Send WQE segments are not defined here 3544 * because they will not be used initially: they should be added and 3545 * used later on: 3546 * FCP-3 init 3547 * FCP-3 Control 3548 * Large Send Offload 3549 * 3550 */ 3551 3552 /* 3553 * Hermon "MLX transport" Work Queue Element (WQE) 3554 * The format of the MLX WQE is similar to that of the Send WQE (above) 3555 * with the following exceptions. MLX WQEs are used for sending MADs on 3556 * special QPs 0 and 1. Everything following the "Next/Ctrl" header 3557 * (defined below) consists of scatter-gather list entries. The contents 3558 * of these SGLs (also defined below) will be put on the wire exactly as 3559 * they appear in the buffers. In addition, the VCRC and the ICRC of each 3560 * sent packet can be modified by changing values in the following header 3561 * or in the payload of the packet itself. 3562 */ 3563 3564 3565 struct hermon_hw_mlx_wqe_nextctrl_s { 3566 uint32_t owner :1; 3567 uint32_t :23; 3568 uint32_t :3; 3569 uint32_t opcode :5; /* is 0x0A (send) for MLX */ 3570 3571 uint32_t :26; 3572 uint32_t ds :6; /* WQE size in octowords */ 3573 3574 uint32_t :14; 3575 uint32_t vl15 :1; 3576 uint32_t slr :1; 3577 uint32_t max_srate :4; 3578 uint32_t sl :4; 3579 uint32_t :3; /* FCoIB usage */ 3580 uint32_t icrc :1; /* 1==don't replace icrc fld */ 3581 uint32_t cq_gen :2; /* 00= no cqe, 11==cqe */ 3582 uint32_t :1; 3583 uint32_t force_lb :1; 3584 3585 uint32_t rlid :16; 3586 uint32_t :16; 3587 }; 3588 3589 3590 #define HERMON_WQE_MLXHDR_VL15_MASK 0x0002000000000000ull 3591 #define HERMON_WQE_MLXHDR_SLR_MASK 0x0001000000000000ull 3592 #define HERMON_WQE_MLXHDR_SRATE_SHIFT 44 3593 #define HERMON_WQE_MLXHDR_SL_SHIFT 40 3594 #define HERMON_WQE_MLXHDR_SIGNALED_MASK 0x0000000800000000ull 3595 #define HERMON_WQE_MLXHDR_RLID_SHIFT 16 3596 3597 3598 /* 3599 * Hermon Receive Work Queue Element (WQE) 3600 * Unlike the Send WQE, the Receive WQE is built ONLY of 16-byte segments. A 3601 * "Next/Ctrl" segment is no longer needed, because of the fixed 3602 * receive queue stride (RQ.STRIDE). It contains just 3603 * some number of scatter list entries for the incoming message. 3604 * 3605 * The format of the scatter-gather list entries is shown below. For 3606 * Receive WQEs the "inline_data" field must be cleared (i.e. data segments 3607 * cannot contain inline data). 3608 */ 3609 3610 3611 struct hermon_hw_wqe_sgl_s { 3612 uint32_t inline_data :1; 3613 uint32_t byte_cnt :31; 3614 3615 uint32_t lkey; 3616 3617 uint64_t addr; 3618 }; 3619 #define HERMON_WQE_SGL_BYTE_CNT_MASK 0x7FFFFFFF 3620 #define HERMON_WQE_SGL_INLINE_MASK 0x80000000 3621 3622 /* 3623 * The following defines are used when building descriptors for special QP 3624 * work requests (i.e. MLX transport WQEs). Note: Because Hermon MLX transport 3625 * requires the driver to build actual IB packet headers, we use these defines 3626 * for the most common fields in those headers. 3627 */ 3628 3629 3630 #define HERMON_MLX_VL15_LVER 0xF0000000 3631 #define HERMON_MLX_VL0_LVER 0x00000000 3632 #define HERMON_MLX_IPVER_TC_FLOW 0x60000000 3633 #define HERMON_MLX_TC_SHIFT 20 3634 #define HERMON_MLX_DEF_PKEY 0xFFFF 3635 #define HERMON_MLX_GSI_QKEY 0x80010000 3636 #define HERMON_MLX_UDSEND_OPCODE 0x64000000 3637 #define HERMON_MLX_DQPN_MASK 0xFFFFFF 3638 3639 /* 3640 * The following macros are used for building each of the individual 3641 * segments that can make up a Hermon WQE. Note: We try not to use the 3642 * structures (with their associated bitfields) here, instead opting to 3643 * build and put 64-bit or 32-bit chunks to the WQEs as appropriate, 3644 * primarily because using the bitfields appears to force more read-modify- 3645 * write operations. 3646 * 3647 * HERMON_WQE_BUILD_UD - Builds Unreliable Datagram Segment 3648 * 3649 * HERMON_WQE_BUILD_REMADDR - Builds Remote Address Segment using 3650 * RDMA info from the work request 3651 * HERMON_WQE_BUILD_RC_ATOMIC_REMADDR - Builds Remote Address Segment 3652 * for RC Atomic work requests 3653 * HERMON_WQE_BUILD_ATOMIC - Builds Atomic Segment using atomic 3654 * info from the work request 3655 * HERMON_WQE_BUILD_BIND - Builds the Bind Memory Window 3656 * Segment using bind info from the 3657 * work request 3658 * HERMON_WQE_BUILD_DATA_SEG - Builds the individual Data Segments 3659 * for Send, Receive, and MLX WQEs 3660 * HERMON_WQE_BUILD_INLINE - Builds an "inline" Data Segment 3661 * (primarily for MLX transport) 3662 * HERMON_WQE_BUILD_INLINE_ICRC - Also builds an "inline" Data Segment 3663 * (but used primarily in the ICRC 3664 * portion of MLX transport WQEs) 3665 * HERMON_WQE_LINKNEXT - Links the current WQE to the 3666 * previous one 3667 * HERMON_WQE_LINKFIRST - Links the first WQE on the current 3668 * chain to the previous WQE 3669 * HERMON_WQE_BUILD_MLX_LRH - Builds the inline LRH header for 3670 * MLX transport MADs 3671 * HERMON_WQE_BUILD_MLX_GRH - Builds the inline GRH header for 3672 * MLX transport MADs 3673 * HERMON_WQE_BUILD_MLX_BTH - Builds the inline BTH header for 3674 * MLX transport MADs 3675 * HERMON_WQE_BUILD_MLX_DETH - Builds the inline DETH header for 3676 * MLX transport MADs 3677 */ 3678 #define HERMON_WQE_BUILD_UD(qp, ud, ah, dest) \ 3679 { \ 3680 uint64_t *tmp; \ 3681 uint64_t *udav; \ 3682 \ 3683 tmp = (uint64_t *)(ud); \ 3684 udav = (uint64_t *)(ah)->ah_udav; \ 3685 tmp[0] = ntohll(udav[0]); \ 3686 tmp[1] = ntohll(udav[1]); \ 3687 tmp[2] = ntohll(udav[2]); \ 3688 tmp[3] = ntohll(udav[3]); \ 3689 tmp[4] = ntohll((((uint64_t)((dest)->ud_dst_qpn & \ 3690 HERMON_WQE_SENDHDR_UD_DQPN_MASK) << 32) | \ 3691 (dest)->ud_qkey)); \ 3692 tmp[5] = 0; \ 3693 } 3694 3695 #define HERMON_WQE_BUILD_LSO(qp, ds, mss, hdr_sz) \ 3696 *(uint32_t *)(ds) = htonl(((mss) << 16) | hdr_sz); 3697 3698 #define HERMON_WQE_BUILD_REMADDR(qp, ra, wr_rdma) \ 3699 { \ 3700 uint64_t *tmp; \ 3701 \ 3702 tmp = (uint64_t *)(ra); \ 3703 tmp[0] = htonll((wr_rdma)->rdma_raddr); \ 3704 tmp[1] = htonll((uint64_t)(wr_rdma)->rdma_rkey << 32); \ 3705 } 3706 3707 #define HERMON_WQE_BUILD_RC_ATOMIC_REMADDR(qp, rc, wr) \ 3708 { \ 3709 uint64_t *tmp; \ 3710 \ 3711 tmp = (uint64_t *)(rc); \ 3712 tmp[0] = htonll((wr)->wr.rc.rcwr.atomic->atom_raddr); \ 3713 tmp[1] = htonll((uint64_t)(wr)->wr.rc.rcwr.atomic->atom_rkey << 32); \ 3714 } 3715 3716 #define HERMON_WQE_BUILD_ATOMIC(qp, at, wr_atom) \ 3717 { \ 3718 uint64_t *tmp; \ 3719 \ 3720 tmp = (uint64_t *)(at); \ 3721 tmp[0] = htonll((wr_atom)->atom_arg2); \ 3722 tmp[1] = htonll((wr_atom)->atom_arg1); \ 3723 } 3724 3725 #define HERMON_WQE_BUILD_BIND(qp, bn, wr_bind) \ 3726 { \ 3727 uint64_t *tmp; \ 3728 uint64_t bn0_tmp; \ 3729 ibt_bind_flags_t bind_flags; \ 3730 \ 3731 tmp = (uint64_t *)(bn); \ 3732 bind_flags = (wr_bind)->bind_flags; \ 3733 bn0_tmp = (bind_flags & IBT_WR_BIND_ATOMIC) ? \ 3734 HERMON_WQE_SENDHDR_BIND_ATOM : 0; \ 3735 bn0_tmp |= (bind_flags & IBT_WR_BIND_WRITE) ? \ 3736 HERMON_WQE_SENDHDR_BIND_WR : 0; \ 3737 bn0_tmp |= (bind_flags & IBT_WR_BIND_READ) ? \ 3738 HERMON_WQE_SENDHDR_BIND_RD : 0; \ 3739 tmp[0] = htonll(bn0_tmp); \ 3740 tmp[1] = htonll(((uint64_t)(wr_bind)->bind_rkey_out << 32) | \ 3741 (wr_bind)->bind_lkey); \ 3742 tmp[2] = htonll((wr_bind)->bind_va); \ 3743 tmp[3] = htonll((wr_bind)->bind_len); \ 3744 } 3745 3746 #define HERMON_WQE_BUILD_DATA_SEG_RECV(ds, sgl) \ 3747 { \ 3748 uint64_t *tmp; \ 3749 \ 3750 tmp = (uint64_t *)(ds); \ 3751 tmp[0] = htonll((((uint64_t)((sgl)->ds_len & \ 3752 HERMON_WQE_SGL_BYTE_CNT_MASK) << 32) | (sgl)->ds_key)); \ 3753 tmp[1] = htonll((sgl)->ds_va); \ 3754 } 3755 #define HERMON_WQE_BUILD_DATA_SEG_SEND(ds, sgl) \ 3756 { \ 3757 ((uint64_t *)(ds))[1] = htonll((sgl)->ds_va); \ 3758 ((uint32_t *)(ds))[1] = htonl((sgl)->ds_key); \ 3759 membar_producer(); \ 3760 ((uint32_t *)(ds))[0] = \ 3761 htonl((sgl)->ds_len & HERMON_WQE_SGL_BYTE_CNT_MASK); \ 3762 } 3763 3764 #define HERMON_WQE_BUILD_INLINE(qp, ds, sz) \ 3765 *(uint32_t *)(ds) = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz)) 3766 3767 #define HERMON_WQE_BUILD_INLINE_ICRC(qp, ds, sz, icrc) \ 3768 { \ 3769 uint32_t *tmp; \ 3770 \ 3771 tmp = (uint32_t *)(ds); \ 3772 tmp[0] = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz)); \ 3773 tmp[1] = htonl(icrc); \ 3774 } 3775 3776 #define HERMON_WQE_SET_CTRL_SEGMENT(desc, desc_sz, fence, \ 3777 imm, sol, sig, ip_cksum, qp) \ 3778 { \ 3779 uint32_t *tmp; \ 3780 uint32_t cntr_tmp; \ 3781 \ 3782 /* do not set the first dword (owner/opcode) here */ \ 3783 tmp = (uint32_t *)desc; \ 3784 cntr_tmp = (fence << 6) | desc_sz; \ 3785 tmp[1] = ntohl(cntr_tmp); \ 3786 cntr_tmp = 0; \ 3787 if ((sol) != 0) cntr_tmp |= 0x02; \ 3788 if ((sig) != 0) cntr_tmp |= 0x0C; \ 3789 /*LINTED*/ \ 3790 if (ip_cksum) cntr_tmp |= 0x30; \ 3791 tmp[2] = ntohl(cntr_tmp); \ 3792 tmp[3] = ntohl(imm); \ 3793 } 3794 3795 #define HERMON_WQE_SET_MLX_CTRL_SEGMENT(desc, desc_sz, sig, maxstat, \ 3796 lid, qp, sl) \ 3797 { \ 3798 uint32_t *tmp; \ 3799 uint32_t cntr_tmp; \ 3800 \ 3801 tmp = (uint32_t *)desc; \ 3802 cntr_tmp = htonl(tmp[0]); \ 3803 cntr_tmp &= 0x80000000; \ 3804 cntr_tmp |= HERMON_WQE_SEND_NOPCODE_SEND; \ 3805 tmp[0] = ntohl(cntr_tmp); \ 3806 tmp[1] = ntohl(desc_sz); \ 3807 cntr_tmp = ((maxstat << 4) | (sl & 0xff)) << 8; \ 3808 if (qp->qp_is_special == HERMON_QP_SMI) \ 3809 cntr_tmp |= (0x02 << 16); \ 3810 if (lid == IB_LID_PERMISSIVE) \ 3811 cntr_tmp |= (0x01 << 16); \ 3812 if ((sig) != 0) \ 3813 cntr_tmp |= 0xC; \ 3814 tmp[2] = ntohl(cntr_tmp); \ 3815 tmp[3] = ntohl((lid) << 16); \ 3816 } 3817 3818 #define HERMON_WQE_BUILD_MLX_LRH(lrh, qp, udav, pktlen) \ 3819 { \ 3820 uint32_t *tmp; \ 3821 uint32_t lrh_tmp; \ 3822 \ 3823 tmp = (uint32_t *)(void *)(lrh); \ 3824 \ 3825 if ((qp)->qp_is_special == HERMON_QP_SMI) { \ 3826 lrh_tmp = HERMON_MLX_VL15_LVER; \ 3827 } else { \ 3828 lrh_tmp = HERMON_MLX_VL0_LVER | ((udav)->sl << 20); \ 3829 } \ 3830 if ((udav)->grh) { \ 3831 lrh_tmp |= (IB_LRH_NEXT_HDR_GRH << 16); \ 3832 } else { \ 3833 lrh_tmp |= (IB_LRH_NEXT_HDR_BTH << 16); \ 3834 } \ 3835 lrh_tmp |= (udav)->rlid; \ 3836 tmp[0] = htonl(lrh_tmp); \ 3837 \ 3838 lrh_tmp = (pktlen) << 16; \ 3839 if ((udav)->rlid == IB_LID_PERMISSIVE) { \ 3840 lrh_tmp |= IB_LID_PERMISSIVE; \ 3841 } else { \ 3842 lrh_tmp |= (udav)->ml_path; \ 3843 } \ 3844 tmp[1] = htonl(lrh_tmp); \ 3845 } 3846 3847 /* 3848 * Note: The GRH payload length, calculated below, is the overall packet 3849 * length (in bytes) minus LRH header and GRH headers. 3850 * 3851 * Also note: Filling in the GIDs in the way we do below is helpful because 3852 * it avoids potential alignment restrictions and/or conflicts. 3853 */ 3854 #define HERMON_WQE_BUILD_MLX_GRH(state, grh, qp, udav, pktlen) \ 3855 { \ 3856 uint32_t *tmp; \ 3857 uint32_t grh_tmp; \ 3858 ib_gid_t sgid; \ 3859 \ 3860 tmp = (uint32_t *)(grh); \ 3861 \ 3862 grh_tmp = HERMON_MLX_IPVER_TC_FLOW; \ 3863 grh_tmp |= (udav)->tclass << HERMON_MLX_TC_SHIFT; \ 3864 grh_tmp |= (udav)->flow_label; \ 3865 tmp[0] = htonl(grh_tmp); \ 3866 \ 3867 grh_tmp = (((pktlen) << 2) - (sizeof (ib_lrh_hdr_t) + \ 3868 sizeof (ib_grh_t))) << 16; \ 3869 grh_tmp |= (IB_GRH_NEXT_HDR_BTH << 8); \ 3870 grh_tmp |= (udav)->hop_limit; \ 3871 tmp[1] = htonl(grh_tmp); \ 3872 \ 3873 sgid.gid_prefix = (state)->hs_sn_prefix[(qp)->qp_portnum]; \ 3874 sgid.gid_guid = (state)->hs_guid[(qp)->qp_portnum] \ 3875 [(udav)->mgid_index]; \ 3876 bcopy(&sgid, &tmp[2], sizeof (ib_gid_t)); \ 3877 bcopy(&(udav)->rgid_h, &tmp[6], sizeof (ib_gid_t)); \ 3878 } 3879 3880 #define HERMON_WQE_BUILD_MLX_BTH(state, bth, qp, wr) \ 3881 { \ 3882 uint32_t *tmp; \ 3883 uint32_t bth_tmp; \ 3884 \ 3885 tmp = (uint32_t *)(bth); \ 3886 \ 3887 bth_tmp = HERMON_MLX_UDSEND_OPCODE; \ 3888 if ((wr)->wr_flags & IBT_WR_SEND_SOLICIT) { \ 3889 bth_tmp |= (IB_BTH_SOLICITED_EVENT_MASK << 16); \ 3890 } \ 3891 if (qp->qp_is_special == HERMON_QP_SMI) { \ 3892 bth_tmp |= HERMON_MLX_DEF_PKEY; \ 3893 } else { \ 3894 bth_tmp |= (state)->hs_pkey[(qp)->qp_portnum] \ 3895 [(qp)->qp_pkeyindx]; \ 3896 } \ 3897 tmp[0] = htonl(bth_tmp); \ 3898 tmp[1] = htonl((wr)->wr.ud.udwr_dest->ud_dst_qpn & \ 3899 HERMON_MLX_DQPN_MASK); \ 3900 tmp[2] = 0x0; \ 3901 } 3902 3903 #define HERMON_WQE_BUILD_MLX_DETH(deth, qp) \ 3904 { \ 3905 uint32_t *tmp; \ 3906 \ 3907 tmp = (uint32_t *)(deth); \ 3908 \ 3909 if ((qp)->qp_is_special == HERMON_QP_SMI) { \ 3910 tmp[0] = 0x0; \ 3911 tmp[1] = 0x0; \ 3912 } else { \ 3913 tmp[0] = htonl(HERMON_MLX_GSI_QKEY); \ 3914 tmp[1] = htonl(0x1); \ 3915 } \ 3916 } 3917 3918 3919 3920 3921 3922 3923 /* 3924 * Flash interface: 3925 * Below we have PCI config space space offsets for flash interface 3926 * access, offsets within Hermon CR space for accessing flash-specific 3927 * information or settings, masks used for flash settings, and 3928 * timeout values for flash operations. 3929 */ 3930 #define HERMON_HW_FLASH_CFG_HWREV 8 3931 #define HERMON_HW_FLASH_CFG_ADDR 88 3932 #define HERMON_HW_FLASH_CFG_DATA 92 3933 3934 #define HERMON_HW_FLASH_RESET_AMD 0xF0 3935 #define HERMON_HW_FLASH_RESET_INTEL 0xFF 3936 #define HERMON_HW_FLASH_CPUMODE 0xF0150 3937 #define HERMON_HW_FLASH_ADDR 0xF01A4 3938 #define HERMON_HW_FLASH_DATA 0xF01A8 3939 #define HERMON_HW_FLASH_GPIO_SEMA 0xF03FC 3940 #define HERMON_HW_FLASH_WRCONF_SEMA 0xF0380 3941 #define HERMON_HW_FLASH_GPIO_DATA 0xF0040 3942 #define HERMON_HW_FLASH_GPIO_MOD1 0xF004C 3943 #define HERMON_HW_FLASH_GPIO_MOD0 0xF0050 3944 #define HERMON_HW_FLASH_GPIO_DATACLEAR 0xF00D4 3945 #define HERMON_HW_FLASH_GPIO_DATASET 0xF00DC 3946 #define HERMON_HW_FLASH_GPIO_LOCK 0xF0048 3947 #define HERMON_HW_FLASH_GPIO_UNLOCK_VAL 0xD42F 3948 #define HERMON_HW_FLASH_GPIO_PIN_ENABLE 0x1E000000 3949 3950 #define HERMON_HW_FLASH_CPU_MASK 0xC0000000 3951 #define HERMON_HW_FLASH_CPU_SHIFT 30 3952 #define HERMON_HW_FLASH_ADDR_MASK 0x0007FFFC 3953 #define HERMON_HW_FLASH_CMD_MASK 0xE0000000 3954 #define HERMON_HW_FLASH_BANK_MASK 0xFFF80000 3955 3956 #define HERMON_HW_FLASH_SPI_BUSY 0x40000000 3957 #define HERMON_HW_FLASH_SPI_WIP 0x01000000 3958 #define HERMON_HW_FLASH_SPI_READ_OP 0x00000001 3959 #define HERMON_HW_FLASH_SPI_USE_INSTR 0x00000040 3960 #define HERMON_HW_FLASH_SPI_NO_ADDR 0x00000020 3961 #define HERMON_HW_FLASH_SPI_NO_DATA 0x00000010 3962 #define HERMON_HW_FLASH_SPI_TRANS_SZ_4B 0x00000200 3963 3964 #define HERMON_HW_FLASH_SPI_SECTOR_ERASE 0xD8 3965 #define HERMON_HW_FLASH_SPI_READ 0x03 3966 #define HERMON_HW_FLASH_SPI_PAGE_PROGRAM 0x02 3967 #define HERMON_HW_FLASH_SPI_READ_STATUS_REG 0x05 3968 #define HERMON_HW_FLASH_SPI_WRITE_ENABLE 0x06 3969 #define HERMON_HW_FLASH_SPI_READ_ESIGNATURE 0xAB 3970 3971 #define HERMON_HW_FLASH_SPI_GW 0xF0400 3972 #define HERMON_HW_FLASH_SPI_ADDR 0xF0404 3973 #define HERMON_HW_FLASH_SPI_DATA 0xF0410 3974 #define HERMON_HW_FLASH_SPI_DATA4 0xF0414 3975 #define HERMON_HW_FLASH_SPI_DATA8 0xF0418 3976 #define HERMON_HW_FLASH_SPI_DATA12 0xF041C 3977 #define HERMON_HW_FLASH_SPI_ADDR_MASK 0x00FFFFFF 3978 #define HERMON_HW_FLASH_SPI_INSTR_PHASE_OFF 0x04 3979 #define HERMON_HW_FLASH_SPI_ADDR_PHASE_OFF 0x08 3980 #define HERMON_HW_FLASH_SPI_DATA_PHASE_OFF 0x10 3981 #define HERMON_HW_FLASH_SPI_ENABLE_OFF 0x2000 3982 #define HERMON_HW_FLASH_SPI_CS_OFF 0x800 3983 #define HERMON_HW_FLASH_SPI_INSTR_OFF 0x10000 3984 #define HERMON_HW_FLASH_SPI_INSTR_SHIFT 0x10 3985 #define HERMON_HW_FLASH_SPI_BOOT_ADDR_REG 0xF0000 3986 3987 #define HERMON_HW_FLASH_TIMEOUT_WRITE 300 3988 #define HERMON_HW_FLASH_TIMEOUT_ERASE 1000000 3989 #define HERMON_HW_FLASH_TIMEOUT_GPIO_SEMA 1000 3990 #define HERMON_HW_FLASH_TIMEOUT_CONFIG 50 3991 3992 #define HERMON_HW_FLASH_ICS_ERASE 0x20 3993 #define HERMON_HW_FLASH_ICS_ERROR 0x3E 3994 #define HERMON_HW_FLASH_ICS_WRITE 0x40 3995 #define HERMON_HW_FLASH_ICS_STATUS 0x70 3996 #define HERMON_HW_FLASH_ICS_READY 0x80 3997 #define HERMON_HW_FLASH_ICS_CONFIRM 0xD0 3998 #define HERMON_HW_FLASH_ICS_READ 0xFF 3999 4000 #ifdef __cplusplus 4001 } 4002 #endif 4003 4004 #endif /* _SYS_IB_ADAPTERS_HERMON_HW_H */ 4005