1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_IB_ADAPTERS_HERMON_HW_H 28 #define _SYS_IB_ADAPTERS_HERMON_HW_H 29 30 /* 31 * hermon_hw.h 32 * Contains all the structure definitions and #defines for all Hermon 33 * hardware resources and registers (as defined by the Hermon register 34 * specification). Wherever possible, the names in the Hermon spec 35 * have been preserved in the structure and field names below. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/conf.h> 40 #include <sys/ddi.h> 41 #include <sys/sunddi.h> 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 48 /* 49 * PCI IDs for supported chipsets 50 */ 51 #define PCI_VENID_MLX 0x15b3 52 #define PCI_DEVID_HERMON_SDR 0x6340 /* Mellanox MT25208-SDR PCIe Gen1 */ 53 #define PCI_DEVID_HERMON_DDR 0x634A /* Mellanox MT25208-DDR PCIe Gen1 */ 54 #define PCI_DEVID_HERMON_DDRG2 0x6732 /* Mellanox MT25208-DDR PCIe Gen2 */ 55 #define PCI_DEVID_HERMON_QDRG2 0x673C /* Mellanox MT25208-QDR PCIe Gen2 */ 56 #define PCI_DEVID_HERMON_MAINT 0x0191 /* Maintenance/Mem Controller Mode */ 57 58 /* 59 * Native page size of the adapter 60 */ 61 #define HERMON_PAGESIZE 0x1000 /* 4Kb */ 62 #define HERMON_PAGEOFFSET (HERMON_PAGESIZE - 1) 63 #define HERMON_PAGEMASK (~HERMON_PAGEOFFSET) 64 #define HERMON_PAGESHIFT 0xC /* 12 */ 65 66 /* 67 * Offsets into the CMD BAR (BAR 0) for many of the more interesting hardware 68 * registers. These registers include the HCR (more below), and the software 69 * reset register (SW_RESET). 70 */ 71 #define HERMON_CMD_HCR_OFFSET 0x80680 /* PRM */ 72 #define HERMON_CMD_SW_RESET_OFFSET 0xF0010 /* PRM */ 73 #define HERMON_CMD_SW_SEMAPHORE_OFFSET 0xF03FC /* PRM */ 74 #define HERMON_CMD_OFFSET_MASK 0xFFFFF /* per MLX instruction */ 75 76 77 /* 78 * Ownership flags used to define hardware or software ownership for 79 * various Hermon resources 80 */ 81 #define HERMON_HW_OWNER 0x1 82 #define HERMON_SW_OWNER 0x0 83 84 /* 85 * Determines whether or not virtual-to-physical address translation is 86 * required. Several of the Hermon hardware structures can be optionally 87 * accessed by Hermon without going through the TPT address translation 88 * tables. 89 */ 90 #define HERMON_VA2PA_XLAT_ENABLED 0x1 91 #define HERMON_VA2PA_XLAT_DISABLED 0x0 92 93 /* 94 * HCA Command Register (HCR) 95 * The HCR command interface provides privileged access to the HCA in 96 * order to query, configure and modify HCA execution. It is the 97 * primary mechanism through which mailboxes may be posted to Hermon 98 * firmware. To use this interface software fills the HCR with pointers 99 * to input and output mailboxes. Some commands support immediate 100 * parameters, however, and for these commands the HCR will contain the 101 * input or output parameters. Command execution completion can be 102 * detected either by the software polling the HCR or by waiting for a 103 * command completion event. 104 */ 105 struct hermon_hw_hcr_s { 106 uint32_t in_param0; 107 uint32_t in_param1; 108 uint32_t input_modifier; 109 uint32_t out_param0; 110 uint32_t out_param1; 111 uint32_t token; 112 uint32_t cmd; 113 }; 114 #define HERMON_HCR_TOKEN_MASK 0xFFFF0000 115 #define HERMON_HCR_TOKEN_SHIFT 16 116 117 #define HERMON_HCR_CMD_STATUS_MASK 0xFF000000 118 #define HERMON_HCR_CMD_GO_MASK 0x00800000 119 #define HERMON_HCR_CMD_E_MASK 0x00400000 120 #define HERMON_HCR_CMD_T_MASK 0x00200000 121 #define HERMON_HCR_CMD_OPMOD_MASK 0x0000F000 122 #define HERMON_HCR_CMD_OPCODE_MASK 0x00000FFF 123 #define HERMON_HCR_CMD_STATUS_SHFT 24 124 #define HERMON_HCR_CMD_GO_SHFT 23 125 #define HERMON_HCR_CMD_E_SHFT 22 126 #define HERMON_HCR_CMD_T_SHFT 21 127 #define HERMON_HCR_CMD_OPMOD_SHFT 12 128 129 /* 130 * Arbel "QUERY_DEV_LIM" command - Hermon, "QUERY_DEV_CAP" - Same hex code 131 * same function as tavor/arbel QUERY_DEV_LIM, just renamed (whatever). 132 * The QUERY_DEV_LIM command returns the device limits and capabilities 133 * supported by the Hermon device. This command must be run before 134 * running the INIT_HCA command (below) in order to determine the maximum 135 * capabilities of the device and which optional features are supported. 136 */ 137 #ifdef _LITTLE_ENDIAN 138 struct hermon_hw_querydevlim_s { 139 uint32_t rsrv0[4]; 140 141 uint32_t log_max_scqs :4; 142 uint32_t :4; 143 uint32_t num_rsvd_scqs :6; 144 uint32_t :2; 145 uint32_t log_max_srq :5; 146 uint32_t :7; 147 uint32_t log_rsvd_srq :4; 148 149 uint32_t log_max_qp :5; 150 uint32_t :3; 151 uint32_t log_rsvd_qp :4; 152 uint32_t :4; 153 uint32_t log_max_qp_sz :8; 154 uint32_t log_max_srq_sz :8; 155 156 uint32_t log_max_eq :4; 157 uint32_t :4; 158 uint32_t num_rsvd_eq :4; 159 uint32_t :4; 160 uint32_t log_max_dmpt :6; 161 uint32_t :2; 162 uint32_t log_max_eq_sz :8; 163 164 uint32_t log_max_cq :5; 165 uint32_t :3; 166 uint32_t log_rsvd_cq :4; 167 uint32_t :4; 168 uint32_t log_max_cq_sz :8; 169 uint32_t :8; 170 171 172 uint32_t :32; 173 174 uint32_t log_max_mtt :6; 175 uint32_t :2; 176 uint32_t log_rsvd_dmpt :4; 177 uint32_t :4; 178 uint32_t log_max_mrw_sz :8; 179 uint32_t :4; 180 uint32_t log_rsvd_mtt :4; 181 182 uint32_t log_max_ra_glob :6; 183 uint32_t :2; 184 uint32_t log_max_rss_tbl_sz :4; 185 uint32_t rss_toep :1; /* rss toeplitz hashing */ 186 uint32_t rss_xor :1; /* rss xor hashing */ 187 uint32_t :2; 188 uint32_t log_max_gso_sz :5; /* Lge Send Offload */ 189 uint32_t :11; /* new w/ 0.35, RSS info */ 190 191 uint32_t log_max_ra_res_qp :6; 192 uint32_t :10; 193 uint32_t log_max_ra_req_qp :6; 194 uint32_t :10; 195 196 uint32_t num_ports :4; 197 uint32_t :12; 198 uint32_t ca_ack_delay :5; 199 uint32_t :11; 200 201 uint32_t mod_wr_srq :1; 202 uint32_t :31; 203 204 uint32_t :4; 205 uint32_t :12; 206 uint32_t stat_rate_sup :16; 207 208 uint32_t :4; 209 uint32_t :12; 210 uint32_t :8; 211 uint32_t log_max_msg :5; 212 uint32_t :3; 213 214 uint32_t rc :1; 215 uint32_t uc :1; 216 uint32_t ud :1; 217 uint32_t xrc :1; 218 uint32_t rcm :1; 219 uint32_t fcoib :1; 220 uint32_t srq :1; 221 uint32_t ipoib_cksm :1; 222 uint32_t pkey_v :1; 223 uint32_t qkey_v :1; 224 uint32_t vmm :1; 225 uint32_t :5; 226 uint32_t mem_win :1; 227 uint32_t apm :1; 228 uint32_t atomic :1; 229 uint32_t raw_multi :1; 230 uint32_t avp :1; 231 uint32_t ud_multi :1; 232 uint32_t :2; 233 uint32_t pg_on_demand :1; 234 uint32_t router :1; 235 uint32_t :6; 236 237 uint32_t :32; 238 239 uint32_t log_max_bf_page :6; 240 uint32_t :2; 241 uint32_t log_max_bf_req_ppg :6; 242 uint32_t :2; 243 uint32_t log_bf_reg_sz :5; 244 uint32_t :10; 245 uint32_t blu_flm :1; 246 247 uint32_t log_pg_sz :8; 248 uint32_t :8; 249 uint32_t log_max_uar_sz :6; 250 uint32_t :6; 251 uint32_t num_rsvd_uar :4; 252 253 uint32_t max_desc_sz_rq :16; 254 uint32_t max_sg_rq :8; 255 uint32_t :8; 256 257 uint32_t max_desc_sz_sq :16; 258 uint32_t max_sg_sq :8; 259 uint32_t :8; 260 261 uint32_t rsvd_fcoib[2]; 262 263 uint32_t log_max_srcd :4; 264 uint32_t :8; 265 uint32_t num_rsvd_srcds :4; 266 uint32_t log_max_pd :5; 267 uint32_t :7; 268 uint32_t num_rsvd_pd :4; 269 270 uint32_t log_max_mcg :8; 271 uint32_t num_rsvd_mcg :4; 272 uint32_t :4; 273 uint32_t log_max_qp_mcg :8; 274 uint32_t :8; 275 276 uint32_t rsrv2[6]; 277 278 uint32_t altc_entry_sz :16; 279 uint32_t aux_entry_sz :16; 280 281 uint32_t qpc_entry_sz :16; 282 uint32_t rdmardc_entry_sz :16; 283 284 uint32_t cmpt_entry_sz :16; 285 uint32_t srq_entry_sz :16; 286 287 uint32_t cqc_entry_sz :16; 288 uint32_t eqc_entry_sz :16; 289 290 uint32_t bmme :1; 291 uint32_t win_type :1; 292 uint32_t mps :1; 293 uint32_t bl :1; 294 uint32_t zb :1; 295 uint32_t lif :1; 296 uint32_t local_inv :1; 297 uint32_t remote_inv :1; 298 uint32_t :1; 299 uint32_t win_type2 :1; 300 uint32_t reserved_lkey :1; 301 uint32_t fast_reg_wr :1; 302 uint32_t :20; 303 304 uint32_t dmpt_entry_sz :16; 305 uint32_t mtt_entry_sz :16; 306 307 uint32_t :32; 308 309 uint32_t rsv_lkey; 310 311 uint64_t max_icm_size; 312 313 uint32_t rsrv3[22]; 314 }; 315 316 #else /* BIG ENDIAN */ 317 318 struct hermon_hw_querydevlim_s { 319 uint32_t rsrv0[4]; 320 321 uint32_t log_max_srq_sz :8; 322 uint32_t log_max_qp_sz :8; 323 uint32_t :4; 324 uint32_t log_rsvd_qp :4; 325 uint32_t :3; 326 uint32_t log_max_qp :5; 327 328 uint32_t log_rsvd_srq :4; 329 uint32_t :7; 330 uint32_t log_max_srq :5; 331 uint32_t :2; 332 uint32_t num_rsvd_scqs :6; 333 uint32_t :4; 334 uint32_t log_max_scqs :4; 335 336 uint32_t :8; 337 uint32_t log_max_cq_sz :8; 338 uint32_t :4; 339 uint32_t log_rsvd_cq :4; 340 uint32_t :3; 341 uint32_t log_max_cq :5; 342 343 uint32_t log_max_eq_sz :8; 344 uint32_t :2; 345 uint32_t log_max_dmpt :6; 346 uint32_t :4; 347 uint32_t num_rsvd_eq :4; 348 uint32_t :4; 349 uint32_t log_max_eq :4; 350 351 uint32_t log_rsvd_mtt :4; 352 uint32_t :4; 353 uint32_t log_max_mrw_sz :8; 354 uint32_t :4; 355 uint32_t log_rsvd_dmpt :4; 356 uint32_t :2; 357 uint32_t log_max_mtt :6; 358 359 uint32_t :32; 360 361 uint32_t :10; 362 uint32_t log_max_ra_req_qp :6; 363 uint32_t :10; 364 uint32_t log_max_ra_res_qp :6; 365 366 uint32_t :11; /* new w/ 0.35, RSS info */ 367 uint32_t log_max_gso_sz :5; /* Lge Send Offload */ 368 uint32_t :2; 369 uint32_t rss_xor :1; /* rss xor hashing */ 370 uint32_t rss_toep :1; /* rss toeplitz hashing */ 371 uint32_t log_max_rss_tbl_sz :4; 372 uint32_t :2; 373 uint32_t log_max_ra_glob :6; 374 375 uint32_t :31; 376 uint32_t mod_wr_srq :1; 377 378 uint32_t :11; 379 uint32_t ca_ack_delay :5; 380 /* PRM 0.35, stuff moved to per port info */ 381 uint32_t :12; 382 uint32_t num_ports :4; 383 384 uint32_t :3; 385 uint32_t log_max_msg :5; 386 uint32_t :8; 387 uint32_t :12; 388 uint32_t :4; 389 390 uint32_t stat_rate_sup :16; 391 uint32_t :12; 392 uint32_t :4; 393 394 uint32_t :32; 395 396 uint32_t :6; 397 uint32_t router :1; 398 uint32_t pg_on_demand :1; 399 uint32_t :2; 400 uint32_t ud_multi :1; 401 uint32_t avp :1; 402 uint32_t raw_multi :1; 403 uint32_t atomic :1; 404 uint32_t apm :1; 405 uint32_t mem_win :1; 406 uint32_t :5; 407 uint32_t vmm :1; 408 uint32_t qkey_v :1; 409 uint32_t pkey_v :1; 410 uint32_t ipoib_cksm :1; 411 uint32_t srq :1; 412 uint32_t fcoib :1; 413 uint32_t rcm :1; 414 uint32_t xrc :1; 415 uint32_t ud :1; 416 uint32_t uc :1; 417 uint32_t rc :1; 418 419 uint32_t num_rsvd_uar :4; 420 uint32_t :6; 421 uint32_t log_max_uar_sz :6; 422 uint32_t :8; 423 uint32_t log_pg_sz :8; 424 425 uint32_t blu_flm :1; 426 uint32_t :10; 427 uint32_t log_bf_reg_sz :5; 428 uint32_t :2; 429 uint32_t log_max_bf_req_ppg :6; 430 uint32_t :2; 431 uint32_t log_max_bf_page :6; 432 433 uint32_t :8; 434 uint32_t max_sg_sq :8; 435 uint32_t max_desc_sz_sq :16; 436 437 uint32_t :8; 438 uint32_t max_sg_rq :8; 439 uint32_t max_desc_sz_rq :16; 440 441 uint32_t rsvd_fcoib[2]; 442 443 uint32_t :8; 444 uint32_t log_max_qp_mcg :8; 445 uint32_t :4; 446 uint32_t num_rsvd_mcg :4; 447 uint32_t log_max_mcg :8; 448 449 uint32_t num_rsvd_pd :4; 450 uint32_t :7; 451 uint32_t log_max_pd :5; 452 uint32_t num_rsvd_srcds :4; 453 uint32_t :8; 454 uint32_t log_max_srcd :4; 455 456 uint32_t rsrv2[6]; 457 458 uint32_t rdmardc_entry_sz :16; 459 uint32_t qpc_entry_sz :16; 460 461 uint32_t aux_entry_sz :16; 462 uint32_t altc_entry_sz :16; 463 464 uint32_t eqc_entry_sz :16; 465 uint32_t cqc_entry_sz :16; 466 467 uint32_t srq_entry_sz :16; 468 uint32_t cmpt_entry_sz :16; 469 470 uint32_t mtt_entry_sz :16; 471 uint32_t dmpt_entry_sz :16; 472 473 uint32_t :20; 474 uint32_t fast_reg_wr :1; 475 uint32_t reserved_lkey :1; 476 uint32_t win_type2 :1; 477 uint32_t :1; 478 uint32_t remote_inv :1; 479 uint32_t local_inv :1; 480 uint32_t lif :1; 481 uint32_t zb :1; 482 uint32_t bl :1; 483 uint32_t mps :1; 484 uint32_t win_type :1; 485 uint32_t bmme :1; 486 487 uint32_t rsv_lkey; 488 489 uint32_t :32; 490 491 uint64_t max_icm_size; 492 493 uint32_t rsrv3[22]; 494 }; 495 #endif 496 497 498 499 /* 500 * Hermon "QUERY_FW" command 501 * The QUERY_FW command retrieves the firmware revision and the Command 502 * Interface revision. The command also returns the HCA attached local 503 * memory area (DDR) which is used by the firmware. Below we also 504 * include some defines which are used to enforce a minimum firmware 505 * version check (see hermon_fw_version_check() for more details). 506 */ 507 508 #ifdef _LITTLE_ENDIAN 509 struct hermon_hw_queryfw_s { 510 uint32_t fw_rev_minor :16; 511 uint32_t fw_rev_subminor :16; 512 513 uint32_t fw_rev_major :16; 514 uint32_t fw_pages :16; 515 516 uint32_t log_max_cmd :8; 517 uint32_t :23; 518 uint32_t dbg_trace :1; 519 520 uint32_t cmd_intf_rev :16; 521 uint32_t :16; 522 523 uint32_t fw_day :8; 524 uint32_t fw_month :8; 525 uint32_t fw_year :16; 526 527 uint32_t :1; 528 uint32_t ccq :1; 529 uint32_t :6; 530 uint32_t fw_sec :8; 531 uint32_t fw_min :8; 532 uint32_t fw_hour :8; 533 534 uint32_t rsrv0[2]; 535 536 uint64_t clr_intr_offs; 537 538 uint32_t :32; 539 540 uint32_t :30; 541 uint32_t clr_int_bar :2; 542 543 uint64_t error_buf_addr; 544 545 uint32_t :30; 546 uint32_t err_buf_bar :2; 547 548 uint32_t error_buf_sz; 549 550 uint32_t rsrv2[48]; 551 }; 552 #else 553 struct hermon_hw_queryfw_s { 554 uint32_t fw_pages :16; 555 uint32_t fw_rev_major :16; 556 557 uint32_t fw_rev_subminor :16; 558 uint32_t fw_rev_minor :16; 559 560 uint32_t :16; 561 uint32_t cmd_intf_rev :16; 562 563 uint32_t dbg_trace :1; 564 uint32_t :23; 565 uint32_t log_max_cmd :8; 566 567 uint32_t fw_hour :8; 568 uint32_t fw_min :8; 569 uint32_t fw_sec :8; 570 uint32_t :6; 571 uint32_t ccq :1; 572 uint32_t :1; 573 574 uint32_t fw_year :16; 575 uint32_t fw_month :8; 576 uint32_t fw_day :8; 577 578 uint32_t rsrv1[2]; 579 580 uint64_t clr_intr_offs; 581 582 uint32_t clr_int_bar :2; 583 uint32_t :30; 584 585 uint32_t :32; 586 587 uint64_t error_buf_addr; 588 589 uint32_t error_buf_sz; 590 591 uint32_t err_buf_bar :2; 592 uint32_t :30; 593 594 uint32_t rsrv2[48]; 595 }; 596 #endif 597 598 /* 599 * need to have min 2.3.0 to include config_spec_qp and SMA in FW 600 */ 601 602 #define HERMON_FW_VER_MAJOR 0x0002 /* TBD for Hermon */ 603 #define HERMON_FW_VER_MINOR 0x0005 604 #define HERMON_FW_VER_SUBMINOR 0x0000 605 606 /* 607 * Hermon "QUERY_ADAPTER" command 608 * The QUERY_ADAPTER command retrieves adapter specific parameters. The 609 * command also retrieves the PCI(X) interrupt pin routing for each of 610 * the INTx# pins supported by the device. This information is used by 611 * the driver during interrupt processing in order to clear the appropriate 612 * interrupt bit. 613 */ 614 #ifdef _LITTLE_ENDIAN 615 struct hermon_hw_queryadapter_s { 616 uint32_t rsrv0[4]; 617 618 uint32_t :32; 619 620 uint32_t :24; 621 uint32_t inta_pin :8; 622 623 uint32_t vsd_vend_id :16; /* added v35 hermon */ 624 uint32_t :16; 625 626 uint32_t :32; 627 628 uint32_t vsd[52]; 629 uint32_t psid[4]; 630 }; 631 #else 632 struct hermon_hw_queryadapter_s { 633 uint32_t rsrv0[4]; 634 635 uint32_t inta_pin :8; 636 uint32_t :24; 637 638 uint32_t :32; 639 640 uint32_t :32; 641 642 uint32_t :16; 643 uint32_t vsd_vend_id :16; /* added v35 hermon */ 644 645 uint32_t vsd[52]; 646 uint32_t psid[4]; 647 }; 648 #endif 649 #define HERMON_REV_A0 0xA0 650 #define HERMON_REV_A1 0xA1 651 652 /* 653 * Virtual physical mapping structure for: MAP_FA, MAP_ICM_AUX, and 654 * MAP_ICM commands. 655 */ 656 657 #ifdef _LITTLE_ENDIAN 658 struct hermon_hw_vpm_s { 659 uint32_t :12; 660 uint32_t vaddr_l :20; 661 uint32_t vaddr_h; 662 663 uint32_t log2sz :5; 664 uint32_t :7; 665 uint32_t paddr_l :20; 666 uint32_t paddr_h; 667 }; 668 #else 669 struct hermon_hw_vpm_s { 670 uint32_t vaddr_h; 671 uint32_t vaddr_l :20; 672 uint32_t :12; 673 674 uint32_t paddr_h; 675 uint32_t paddr_l :20; 676 uint32_t :7; 677 uint32_t log2sz :5; 678 }; 679 #endif 680 681 682 683 684 /* 685 * Hermon "INIT_HCA" and "QUERY_HCA" commands 686 * The INIT_HCA command configures all HCA resources in HCA attached local 687 * memory and some system relevant information. The same mailbox output 688 * format is used by the QUERY_HCA command. All parameters, which are 689 * specifically the output of the QUERY_HCA command are marked as 690 * "QUERY_HCA only". These parameters are not configurable through the 691 * INIT_HCA command, but can be retrieved as read-only through the 692 * QUERY_HCA command. 693 * 694 * Below we first define several structures which help make up the whole 695 * of the INIT_HCA/QUERY_HCA command. These are: 696 * hermon_hw_qp_ee_cq_eq_rdb_t for "QPC/EEC/CQC/EQC/RDB Parameters", 697 * hermon_udav_mem_param_t for "Memory Access Parameters for UDAV Table", 698 * hermon_multicast_param_t for "Multicast Support Parameters", 699 * hermon_tpt_param_t for "Translation and Protection Table Parameters", 700 * and hermon_uar_param_t for Hermon "UAR Parameters". 701 */ 702 703 /* 704 * need to consider removing any ref to "ee", hermon doesn't support 705 * ee/rd stuff, and they've taken away the pretense 706 */ 707 708 709 #ifdef _LITTLE_ENDIAN 710 typedef struct hermon_hw_qp_ee_cq_eq_rdb_s { 711 uint32_t rsrv0[4]; 712 713 uint32_t log_num_qp :5; 714 uint32_t qpc_baseaddr_l :27; 715 uint32_t qpc_baseaddr_h; 716 717 uint32_t rsrv1[4]; 718 719 uint32_t log_num_srq :5; 720 uint32_t srqc_baseaddr_l :27; 721 uint32_t srqc_baseaddr_h; 722 723 uint32_t log_num_cq :5; 724 uint32_t cqc_baseaddr_l :27; 725 uint32_t cqc_baseaddr_h; 726 727 uint32_t rsrv2[2]; 728 729 uint64_t altc_baseaddr; 730 731 uint32_t rsrv3[2]; 732 733 uint64_t auxc_baseaddr; 734 735 uint32_t rsrv4[2]; 736 737 uint32_t log_num_eq :5; 738 uint32_t eqc_baseaddr_l :27; 739 uint32_t eqc_baseaddr_h; 740 741 uint32_t rsv5[2]; 742 743 uint32_t log_num_rdmardc :3; 744 uint32_t :2; 745 uint32_t rdmardc_baseaddr_l :27; 746 uint32_t rdmardc_baseaddr_h; 747 748 uint32_t rsrv6[2]; 749 } hermon_hw_qp_ee_cq_eq_rdb_t; 750 #else 751 typedef struct hermon_hw_qp_ee_cq_eq_rdb_s { 752 uint32_t rsrv0[4]; 753 754 uint32_t qpc_baseaddr_h; 755 uint32_t qpc_baseaddr_l :27; 756 uint32_t log_num_qp :5; 757 758 uint32_t rsrv1[4]; 759 760 uint32_t srqc_baseaddr_h; 761 uint32_t srqc_baseaddr_l :27; 762 uint32_t log_num_srq :5; 763 764 uint32_t cqc_baseaddr_h; 765 uint32_t cqc_baseaddr_l :27; 766 uint32_t log_num_cq :5; 767 768 uint32_t rsrv2[2]; 769 770 uint64_t altc_baseaddr; 771 772 uint32_t rsrv3[2]; 773 774 uint64_t auxc_baseaddr; 775 776 uint32_t rsrv4[2]; 777 778 uint32_t eqc_baseaddr_h; 779 uint32_t eqc_baseaddr_l :27; 780 uint32_t log_num_eq :5; 781 782 uint32_t rsv5[2]; 783 784 uint32_t rdmardc_baseaddr_h; 785 uint32_t rdmardc_baseaddr_l :27; 786 uint32_t :2; 787 uint32_t log_num_rdmardc :3; 788 789 uint32_t rsrv6[2]; 790 } hermon_hw_qp_ee_cq_eq_rdb_t; 791 #endif 792 793 794 795 796 #ifdef _LITTLE_ENDIAN 797 typedef struct hermon_multicast_param_s { 798 uint64_t mc_baseaddr; 799 800 uint32_t rsrv0[2]; 801 802 uint32_t log_mc_tbl_hash_sz :5; 803 uint32_t :27; 804 805 uint32_t log_mc_tbl_ent :5; 806 uint32_t :27; 807 808 uint32_t :32; 809 810 uint32_t log_mc_tbl_sz :5; 811 uint32_t :19; 812 uint32_t mc_hash_fn :3; 813 uint32_t :5; 814 } hermon_multicast_param_t; 815 #else 816 typedef struct hermon_multicast_param_s { 817 uint64_t mc_baseaddr; 818 819 uint32_t rsrv0[2]; 820 821 uint32_t :27; 822 uint32_t log_mc_tbl_ent :5; 823 824 uint32_t :27; 825 uint32_t log_mc_tbl_hash_sz :5; 826 827 uint32_t :5; 828 uint32_t mc_hash_fn :3; 829 uint32_t :19; 830 uint32_t log_mc_tbl_sz :5; 831 832 uint32_t :32; 833 } hermon_multicast_param_t; 834 #endif 835 836 #define HERMON_MCG_DEFAULT_HASH_FN 0x0 837 838 #ifdef _LITTLE_ENDIAN 839 typedef struct hermon_tpt_param_s { 840 uint64_t dmpt_baseaddr; 841 842 uint32_t :32; 843 uint32_t log_dmpt_sz :6; 844 uint32_t :2; 845 uint32_t pgfault_rnr_to :5; 846 uint32_t :19; 847 848 uint64_t mtt_baseaddr; 849 850 uint64_t cmpt_baseaddr; 851 } hermon_tpt_param_t; 852 #else 853 typedef struct hermon_tpt_param_s { 854 uint64_t dmpt_baseaddr; 855 856 uint32_t :19; 857 uint32_t pgfault_rnr_to :5; 858 uint32_t :2; 859 uint32_t log_dmpt_sz :6; 860 uint32_t :32; 861 862 uint64_t mtt_baseaddr; 863 864 uint64_t cmpt_baseaddr; 865 } hermon_tpt_param_t; 866 #endif 867 868 869 #ifdef _LITTLE_ENDIAN 870 typedef struct hermon_uar_param_s { 871 uint32_t rsvd0[2]; 872 873 uint32_t :32; 874 875 uint32_t uar_pg_sz :8; 876 uint32_t log_max_uars :4; 877 uint32_t :20; 878 879 uint32_t resvd1[4]; 880 } hermon_uar_param_t; 881 #else 882 typedef struct hermon_uar_param_s { 883 uint32_t rsvd0[2]; 884 885 uint32_t :20; 886 uint32_t log_max_uars :4; 887 uint32_t uar_pg_sz :8; 888 889 uint32_t :32; 890 891 uint32_t resvd1[4]; 892 } hermon_uar_param_t; 893 #endif 894 895 /* 896 * NEW for Hermon 897 * QP Allocation Params 898 * 899 */ 900 901 #ifdef _LITTLE_ENDIAN 902 typedef struct hermon_qp_alloc_param_s { 903 uint32_t :32; 904 905 uint32_t ccq_base :24; 906 uint32_t log2ccqs :5; 907 uint32_t :2; 908 uint32_t ccq_en :1; 909 910 uint32_t rsvd[6]; /* but 0x14 def'd for fibre channel */ 911 } hermon_qp_alloc_param_t; 912 #else /* BIG ENDIAN */ 913 typedef struct hermon_qp_alloc_param_s { 914 uint32_t ccq_en :1; 915 uint32_t :2; 916 uint32_t log2ccqs :5; 917 uint32_t ccq_base :24; 918 919 uint32_t :32; 920 921 uint32_t rsvd[6]; /* but 0x14 def'd for fibre channel */ 922 } hermon_qp_alloc_param_t; 923 #endif 924 925 #ifdef _LITTLE_ENDIAN 926 struct hermon_hw_initqueryhca_s { 927 uint32_t :32; 928 929 uint32_t :24; 930 uint32_t version :8; 931 932 uint32_t :13; 933 uint32_t log2_cacheline :3; 934 uint32_t hca_core_clock :16; /* QUERY_HCA only */ 935 936 uint32_t :32; 937 938 uint32_t udav_port_chk :1; 939 uint32_t big_endian :1; 940 uint32_t :1; 941 uint32_t chsum_en :1; 942 uint32_t :28; 943 944 uint32_t router_qp :24; 945 uint32_t :5; 946 uint32_t ipr2 :1; 947 uint32_t ipr1 :1; 948 uint32_t router_en :1; 949 950 uint32_t rsrv1[2]; 951 952 hermon_hw_qp_ee_cq_eq_rdb_t context; 953 954 uint32_t rsrv2[8]; 955 956 hermon_multicast_param_t multi; 957 958 uint32_t rsrv3[4]; 959 960 hermon_tpt_param_t tpt; 961 962 uint32_t rsrv4[4]; 963 964 hermon_uar_param_t uar; 965 966 uint32_t rsrv5[4]; 967 968 hermon_qp_alloc_param_t qp_alloc; 969 970 uint32_t rsrv6[100]; /* from 0x16c to 0x2fc offsets */ 971 }; 972 #else /* BIG ENDIAN */ 973 struct hermon_hw_initqueryhca_s { 974 uint32_t version :8; 975 uint32_t :24; 976 977 uint32_t :32; 978 979 uint32_t :32; 980 981 uint32_t hca_core_clock :16; /* QUERY_HCA only */ 982 uint32_t log2_cacheline :3; 983 uint32_t :13; 984 985 uint32_t router_en :1; 986 uint32_t ipr1 :1; 987 uint32_t ipr2 :1; 988 uint32_t :5; 989 uint32_t router_qp :24; 990 991 uint32_t :28; 992 uint32_t chsum_en :1; 993 uint32_t :1; 994 uint32_t big_endian :1; 995 uint32_t udav_port_chk :1; 996 997 uint32_t rsrv1[2]; 998 999 hermon_hw_qp_ee_cq_eq_rdb_t context; 1000 1001 uint32_t rsrv2[8]; 1002 1003 hermon_multicast_param_t multi; 1004 1005 uint32_t rsrv3[4]; 1006 1007 hermon_tpt_param_t tpt; 1008 1009 uint32_t rsrv4[4]; 1010 1011 hermon_uar_param_t uar; 1012 1013 uint32_t rsrv5[4]; 1014 1015 hermon_qp_alloc_param_t qp_alloc; 1016 1017 uint32_t rsrv6[100]; /* from 0x16c to 0x2fc offsets */ 1018 }; 1019 #endif 1020 #define HERMON_UDAV_PROTECT_DISABLED 0x0 1021 #define HERMON_UDAV_PROTECT_ENABLED 0x1 1022 #define HERMON_UDAV_PORTCHK_DISABLED 0x0 1023 #define HERMON_UDAV_PORTCHK_ENABLED 0x1 1024 1025 1026 /* 1027 * Hermon "INIT_IB"/"INIT_PORT" command 1028 * The INIT_IB/INIT_PORT command enables the physical layer of an IB port. 1029 * It provides control over the IB port attributes. The capabilities 1030 * requested here should not exceed the device limits, as retrieved by 1031 * the QUERY_DEV_LIM/CAP command (above). To query information about the IB 1032 * port or node, the driver may submit GetPortInfo or GetNodeInfo MADs 1033 * through the Hermon MAD_IFC command. 1034 * 1035 * Changed name to initport, but operates similar to initib - but as of 1036 * PRM v0.35c the initport just does that, and the params set previously 1037 * by initib are now set in SET_PORT 1038 */ 1039 1040 1041 1042 1043 /* 1044 * HERMON query_port and set_port commands. QUERY_PORT is new for hermon, 1045 * doing some of what used to be done in the QUERY_DEV_CAP command. It is 1046 * introduced in PRM v0.35 and will need to be added to the list of 1047 * supported HCA commands 1048 * 1049 * SET_PORT is similar to the SET_IB command from tavor and arbel. Here, 1050 * tho, it's more extensive and will be easier to deal with I suspect by 1051 * making it a structure and filling it in and then doing the copy to the 1052 * mailbox (instead of just writing the minimal information to the mailbox 1053 * directly as was done for the previous HCAs). 1054 */ 1055 1056 #ifdef _LITTLE_ENDIAN 1057 struct hermon_hw_query_port_s { 1058 uint32_t log_max_pkey :4; /* pkey table size */ 1059 uint32_t log_max_gid :4; /* max gids / port */ 1060 /* was max_port_width arbel: long list of values */ 1061 uint32_t ib_port_wid :4; 1062 uint32_t :4; 1063 uint32_t :4; /* other types possibly */ 1064 uint32_t :4; 1065 /* 1066 * 0x1=2.5G, 0x3=2.5 or 5.0G, 0x5=2.5 or 10G 1067 * 0x7=2.5, 5.0, or 10G, others rsvd 1068 */ 1069 uint32_t ib_link_spd :4; 1070 1071 uint32_t :4; 1072 1073 uint32_t :16; /* used for other types (?) */ 1074 uint32_t ib_mtu :4; 1075 /* 1076 * 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 1077 * 0x5=4096, others rsvd 1078 */ 1079 uint32_t :4; 1080 uint32_t port_type :8; /* 0x00, 0x01 IB, others TBD */ 1081 1082 uint32_t :32; 1083 /* max vl's supported (not incl vl_15) */ 1084 uint32_t max_vl :4; 1085 uint32_t :4; 1086 uint32_t :8; /* but others possibly */ 1087 uint32_t :16; 1088 1089 uint32_t rsvd0[2]; /* but for other types */ 1090 uint32_t rsvd1[504]; 1091 }; 1092 #else /* BIG ENDIAN */ 1093 struct hermon_hw_query_port_s { 1094 uint32_t port_type :8; /* 0x00, 0x01 IB, others TBD */ 1095 uint32_t :4; 1096 /* 1097 * 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 1098 * 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 1099 */ 1100 uint32_t ib_mtu :4; 1101 /* 0x5=4096, others rsvd */ 1102 uint32_t :16; /* used for other types (?) */ 1103 1104 uint32_t :4; 1105 uint32_t ib_link_spd :4; 1106 /* 1107 * 0x1=2.5G, 0x3=2.5 or 5.0G, 0x5=2.5 or 10G 1108 * 0x7=2.5, 5.0, or 10G, others rsvd 1109 */ 1110 uint32_t :4; 1111 uint32_t :4; /* other types possibly */ 1112 uint32_t :4; 1113 /* was max_port_width arbel: long list of values */ 1114 uint32_t ib_port_wid :4; 1115 uint32_t log_max_gid :4; /* max gids / port */ 1116 uint32_t log_max_pkey :4; /* pkey table size */ 1117 1118 uint32_t :16; 1119 uint32_t :8; /* but others possibly */ 1120 uint32_t :4; 1121 /* max vl's supported (not incl vl_15) */ 1122 uint32_t max_vl :4; 1123 1124 uint32_t :32; 1125 1126 uint32_t rsvd0[2]; /* but for other types */ 1127 uint32_t rsvd1[504]; 1128 1129 }; 1130 #endif 1131 1132 #ifdef _LITTLE_ENDIAN 1133 struct hermon_hw_set_port_s { 1134 uint32_t cap_mask; 1135 1136 uint32_t rqk :1; /* reset qkey violation cntr */ 1137 uint32_t rcm :1; /* reset capability mask */ 1138 uint32_t :2; 1139 uint32_t vl_cap :4; 1140 uint32_t :4; 1141 uint32_t mtu_cap :4; 1142 uint32_t g0 :1; /* set port GUID0 */ 1143 uint32_t ng :1; /* set node GUID (all ports) */ 1144 uint32_t sig :1; /* set sys image */ 1145 uint32_t mg :1; /* change GID table */ 1146 uint32_t mp :1; /* change pkey table size */ 1147 uint32_t mvc :1; /* change vl_cap */ 1148 uint32_t mmc :1; /* change mtu_cap */ 1149 uint32_t :9; 1150 1151 uint64_t sys_img_guid; 1152 1153 uint64_t guid0; 1154 1155 uint64_t node_guid; 1156 1157 uint32_t sniff_qpn_base :24; 1158 uint32_t ge :1; /* glob egress sniff enabled */ 1159 uint32_t gi :1; /* glob ingress sniff enabled */ 1160 uint32_t qe :1; /* qp-egress sniff enable */ 1161 uint32_t qi :1; /* qp-ingress sniff enabled */ 1162 uint32_t :4; 1163 1164 uint32_t router_qpn_base :24; 1165 uint32_t routermode :1; 1166 uint32_t :7; 1167 1168 uint32_t :32; 1169 1170 uint32_t max_guid :16; /* valid if noted above */ 1171 uint32_t max_pkey :16; /* valid if noted above */ 1172 1173 uint32_t rsrd0[500]; 1174 }; 1175 #else /* BIG ENDIAN */ 1176 struct hermon_hw_set_port_s { 1177 uint32_t :9; 1178 uint32_t mmc :1; /* change mtu_cap */ 1179 uint32_t mvc :1; /* change vl_cap */ 1180 uint32_t mp :1; /* change pkey table size */ 1181 uint32_t mg :1; /* change GID table size */ 1182 uint32_t sig :1; /* set sys image GUID */ 1183 uint32_t ng :1; /* set node GUID (all ports) */ 1184 uint32_t g0 :1; /* set port GUID0 */ 1185 uint32_t mtu_cap :4; 1186 uint32_t :4; 1187 uint32_t vl_cap :4; 1188 uint32_t :2; 1189 uint32_t rcm :1; /* reset capability mask */ 1190 uint32_t rqk :1; /* reset qkey violation cntr */ 1191 1192 uint32_t cap_mask; 1193 1194 uint64_t sys_img_guid; 1195 1196 uint64_t guid0; 1197 1198 uint64_t node_guid; 1199 1200 uint32_t :7; 1201 uint32_t routermode :1; 1202 uint32_t router_qpn_base :24; 1203 1204 uint32_t :4; 1205 uint32_t qi :1; /* qp-ingress sniff enabled */ 1206 uint32_t qe :1; /* qp-egress sniff enable */ 1207 uint32_t gi :1; /* glob ingress sniff enabled */ 1208 uint32_t ge :1; /* glob egress sniff enabled */ 1209 uint32_t sniff_qpn_base :24; 1210 1211 uint32_t max_pkey :16; /* valid if noted above */ 1212 uint32_t max_guid :16; /* valid if noted above */ 1213 1214 uint32_t :32; 1215 1216 uint32_t rsrd0[500]; 1217 }; 1218 #endif 1219 1220 1221 1222 1223 /* 1224 * Hermon Memory Protection Table (MPT) entries 1225 * 1226 * The Memory Protection Table (MPT) contains the information associated 1227 * with all the regions and windows. The MPT table resides in a virtually- 1228 * contiguous area in ICM, and the memory key (R_Key or L_Key) is used to 1229 * calculate the physical address for accessing the entries in the table. 1230 * 1231 * 1232 * The SW2HW_MPT command transfers ownership of an MPT entry from software 1233 * to hardware. The command takes the MPT entry from the input mailbox and 1234 * stores it in the MPT in the hardware. The command will fail if the 1235 * requested MPT entry is already owned by the hardware or if the MPT index 1236 * given in the command is inconsistent with the MPT entry memory key. 1237 * The QUERY_MPT command retrieves a snapshot of an MPT entry. The command 1238 * takes the current state of an MPT entry from the hardware and stores it 1239 * in the output mailbox. The command will fail if the requested MPT entry 1240 * is already owned by software. 1241 * Finally, the HW2SW_MPT command transfers ownership of an MPT entry from 1242 * the hardware to the software. The command takes the MPT entry from the 1243 * hardware, invalidates it, and stores it in the output mailbox. The 1244 * command will fail if the requested entry is already owned by software. 1245 * The command will also fail if the MPT entry in question is a Memory 1246 * Region which has Memory Windows currently bound to it. 1247 * 1248 * The following structure is used in the SW2HW_MPT, QUERY_MPT, and 1249 * HW2SW_MPT commands, and ONLY for the dMPT - for data. 1250 */ 1251 1252 #ifdef _LITTLE_ENDIAN 1253 struct hermon_hw_dmpt_s { 1254 uint32_t :7; 1255 uint32_t bnd_qp :1; 1256 uint32_t qpn :24; /* dw 1, byte 4-7 */ 1257 1258 uint32_t :8; 1259 uint32_t reg_win :1; 1260 uint32_t phys_addr :1; 1261 uint32_t lr :1; 1262 uint32_t lw :1; 1263 uint32_t rr :1; 1264 uint32_t rw :1; 1265 uint32_t atomic :1; 1266 uint32_t en_bind :1; 1267 uint32_t atc_req :1; 1268 uint32_t atc_xlat :1; 1269 uint32_t :1; 1270 uint32_t no_snoop :1; 1271 uint32_t :8; 1272 uint32_t status :4; /* dw 0, byte 0-3 */ 1273 1274 uint32_t pd :24; 1275 uint32_t ren_inval :1; 1276 uint32_t en_inval :1; 1277 uint32_t net_cache :1; 1278 uint32_t fast_reg_en :1; 1279 uint32_t rem_acc_en :1; 1280 uint32_t w_dif :1; 1281 uint32_t m_dif :1; 1282 uint32_t :1; /* dw 2, byte 0xc-f */ 1283 1284 uint32_t mem_key; 1285 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1286 1287 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1288 1289 uint32_t win_cnt :24; 1290 uint32_t :8; /* dw 9, byte 0x24-27 */ 1291 1292 uint32_t lkey; /* dw 8, byte 0x20-23 */ 1293 1294 uint32_t mtt_addr_h :8; 1295 uint32_t :24; /* dw 11, byte 0x2c-2f */ 1296 1297 uint32_t mtt_rep :4; 1298 uint32_t :17; 1299 uint32_t blk_mode :1; 1300 uint32_t len_b64 :1; /* bit 64 of length */ 1301 uint32_t fbo_en :1; 1302 uint32_t :8; /* dw 10, byte 0x28-2b */ 1303 1304 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1305 1306 uint32_t :3; 1307 uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */ 1308 1309 uint32_t mtt_fbo :21; 1310 uint32_t :11; /* dw 15, byte 0x3c-3f */ 1311 1312 uint32_t entity_sz :21; 1313 uint32_t :11; /* dw 14, byte 0x38-3b */ 1314 #ifdef HERMON_NOTIMPL 1315 uint32_t dif_m_atag :16; 1316 uint32_t :16; /* dw 17, 0x44-47 */ 1317 1318 uint32_t dif_a_msk :16; 1319 uint32_t dif_v_msk :2; 1320 uint32_t dif_rep :2; 1321 uint32_t :9; 1322 uint32_t dif_err :3; /* dw 16, 0x40-43 */ 1323 1324 uint32_t dif_w_atag :16; 1325 uint32_t :16; /* dw 19, 0x4c-4f */ 1326 1327 uint32_t dif_m_rtagb; /* dw 18, 0x48-4b */ 1328 1329 uint32_t :32; 1330 1331 uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */ 1332 #endif /* HERMON_NOTIMPL */ 1333 }; 1334 1335 #else /* BIG ENDIAN */ 1336 struct hermon_hw_dmpt_s { 1337 uint32_t status :4; 1338 uint32_t :8; 1339 uint32_t no_snoop :1; 1340 uint32_t :1; 1341 uint32_t atc_xlat :1; 1342 uint32_t atc_req :1; 1343 uint32_t en_bind :1; 1344 uint32_t atomic :1; 1345 uint32_t rw :1; 1346 uint32_t rr :1; 1347 uint32_t lw :1; 1348 uint32_t lr :1; 1349 uint32_t phys_addr :1; 1350 uint32_t reg_win :1; 1351 uint32_t :8; /* dw 0, byte 0x0-3 */ 1352 1353 uint32_t qpn :24; 1354 uint32_t bnd_qp :1; 1355 uint32_t :7; /* dw 1, byte 0x4-7 */ 1356 1357 uint32_t mem_key; /* dw 2, byte 0x8-b */ 1358 1359 uint32_t :1; 1360 uint32_t m_dif :1; 1361 uint32_t w_dif :1; 1362 uint32_t rem_acc_en :1; 1363 uint32_t fast_reg_en :1; 1364 uint32_t net_cache :1; 1365 uint32_t en_inval :1; 1366 uint32_t ren_inval :1; 1367 uint32_t pd :24; /* dw 3, byte 0xc-f */ 1368 1369 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1370 1371 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1372 1373 uint32_t lkey; /* dw 8, bytd 0x20-23 */ 1374 1375 uint32_t :8; 1376 uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */ 1377 1378 uint32_t :8; 1379 uint32_t fbo_en :1; 1380 uint32_t len_b64 :1; /* bit 64 of length */ 1381 uint32_t blk_mode :1; 1382 uint32_t :17; 1383 uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */ 1384 1385 uint32_t :24; 1386 uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */ 1387 1388 uint32_t mtt_addr_l :29; 1389 uint32_t :3; /* dw 12, byte 0x30-33 */ 1390 1391 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1392 1393 uint32_t :11; 1394 uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */ 1395 1396 uint32_t :11; 1397 uint32_t mtt_fbo :21; /* dw 15, byte 0x3c-3f */ 1398 #ifdef HERMON_NOTIMPL 1399 1400 uint32_t dif_err :3; 1401 uint32_t :9; 1402 uint32_t dif_rep :2; 1403 uint32_t dif_v_msk :2; 1404 uint32_t dif_a_msk :16; /* dw 16, 0x40-43 */ 1405 1406 uint32_t :16; 1407 uint32_t dif_m_atag :16; /* dw 17, 0x44-47 */ 1408 1409 uint32_t dif_m_rtagb; /* dw 18, 0x48-4b */ 1410 1411 uint32_t :16; 1412 uint32_t dif_w_atag :16; /* dw 19, 0x4c-4f */ 1413 1414 uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */ 1415 1416 uint32_t :32; 1417 #endif /* HERMON_NOTIMPL */ 1418 }; 1419 #endif 1420 1421 /* 1422 * The following structure is for the CMPTs. This is NEVER actually built and 1423 * passed to the hardware - we use it to track information needed for the 1424 * context entries, and to facilitate the alloc tracking. It differs from 1425 * the dMPT sturcture above in that it does not have/need the "dif" stuff. 1426 * 1427 */ 1428 1429 1430 1431 #ifdef _LITTLE_ENDIAN 1432 struct hermon_hw_cmpt_s { 1433 uint32_t :7; 1434 uint32_t bnd_qp :1; 1435 uint32_t qpn :24; /* dw 1, byte 4-7 */ 1436 1437 uint32_t :8; 1438 uint32_t reg_win :1; 1439 uint32_t phys_addr :1; 1440 uint32_t lr :1; 1441 uint32_t lw :1; 1442 uint32_t rr :1; 1443 uint32_t rw :1; 1444 uint32_t atomic :1; 1445 uint32_t en_bind :1; 1446 uint32_t atc_req :1; 1447 uint32_t atc_xlat :1; 1448 uint32_t :1; 1449 uint32_t no_snoop :1; 1450 uint32_t :8; 1451 uint32_t status :4; /* dw 0, byte 0-3 */ 1452 1453 uint32_t pd :24; 1454 uint32_t ren_inval :1; 1455 uint32_t en_inval :1; 1456 uint32_t net_cache :1; 1457 uint32_t fast_reg_en :1; 1458 uint32_t rem_acc_en :1; 1459 uint32_t w_dif :1; 1460 uint32_t m_dif :1; 1461 uint32_t :1; /* dw 2, byte 0xc-f */ 1462 1463 uint32_t mem_key; 1464 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1465 1466 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1467 1468 uint32_t win_cnt :24; 1469 uint32_t :8; /* dw 9, byte 0x24-27 */ 1470 1471 uint32_t lkey; /* dw 8, byte 0x20-23 */ 1472 1473 uint32_t mtt_addr_h :8; 1474 uint32_t :24; /* dw 11, byte 0x2c-2f */ 1475 1476 uint32_t mtt_rep :4; 1477 uint32_t :17; 1478 uint32_t blk_mode :1; 1479 uint32_t len_b64 :1; /* bit 64 of length */ 1480 uint32_t fbo_en :1; 1481 uint32_t :8; /* dw 10, byte 0x28-2b */ 1482 1483 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1484 1485 uint32_t :3; 1486 uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */ 1487 1488 uint32_t mtt_fbo :21; 1489 uint32_t :11; /* dw 15, byte 0x3c-3f */ 1490 1491 uint32_t entity_sz :21; 1492 uint32_t :11; /* dw 14, byte 0x38-3b */ 1493 1494 }; 1495 1496 1497 #else /* BIG ENDIAN */ 1498 struct hermon_hw_cmpt_s { 1499 uint32_t status :4; 1500 uint32_t :8; 1501 uint32_t no_snoop :1; 1502 uint32_t :1; 1503 uint32_t atc_xlat :1; 1504 uint32_t atc_req :1; 1505 uint32_t en_bind :1; 1506 uint32_t atomic :1; 1507 uint32_t rw :1; 1508 uint32_t rr :1; 1509 uint32_t lw :1; 1510 uint32_t lr :1; 1511 uint32_t phys_addr :1; 1512 uint32_t reg_win :1; 1513 uint32_t :8; /* dw 0, byte 0x0-3 */ 1514 1515 uint32_t qpn :24; 1516 uint32_t bnd_qp :1; 1517 uint32_t :7; /* dw 1, byte 0x4-7 */ 1518 1519 uint32_t mem_key; /* dw 2, byte 0x8-b */ 1520 1521 uint32_t :1; 1522 uint32_t m_dif :1; 1523 uint32_t w_dif :1; 1524 uint32_t rem_acc_en :1; 1525 uint32_t fast_reg_en :1; 1526 uint32_t net_cache :1; 1527 uint32_t en_inval :1; 1528 uint32_t ren_inval :1; 1529 uint32_t pd :24; /* dw 3, byte 0xc-f */ 1530 1531 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ 1532 1533 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ 1534 1535 uint32_t lkey; /* dw 8, bytd 0x20-23 */ 1536 1537 uint32_t :8; 1538 uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */ 1539 1540 uint32_t :8; 1541 uint32_t fbo_en :1; 1542 uint32_t len_b64 :1; /* bit 64 of length */ 1543 uint32_t blk_mode :1; 1544 uint32_t :17; 1545 uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */ 1546 1547 uint32_t :24; 1548 uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */ 1549 1550 uint32_t mtt_addr_l :29; 1551 uint32_t :3; /* dw 12, byte 0x30-33 */ 1552 1553 uint32_t mtt_size; /* dw 13, byte 0x34-37 */ 1554 1555 uint32_t :11; 1556 uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */ 1557 }; 1558 #endif 1559 1560 1561 #define HERMON_MEM_CYCLE_GENERATE 0x1 1562 #define HERMON_IO_CYCLE_GENERATE 0x0 1563 1564 #define HERMON_MPT_IS_WINDOW 0x0 1565 #define HERMON_MPT_IS_REGION 0x1 1566 1567 #define HERMON_MPT_DEFAULT_VERSION 0x0 1568 1569 #define HERMON_UNLIMITED_WIN_BIND 0x0 1570 1571 #define HERMON_PHYSADDR_ENABLED 0x1 1572 #define HERMON_PHYSADDR_DISABLED 0x0 1573 1574 1575 /* 1576 * Hermon Memory Translation Table (MTT) entries 1577 * After accessing the MPT table (above) and validating the access rights 1578 * to the region/window, Hermon address translation moves to the next step 1579 * where it translates the virtual address to a physical address. This 1580 * translation is performed using the Memory Translation Table entries 1581 * (MTT). Note: The MTT in hardware is organized into segments and each 1582 * segment contains multiple address translation pages (MTT entries). 1583 * Each memory region (MPT above) points to the first segment in the MTT 1584 * that corresponds to that region. 1585 */ 1586 1587 #ifdef _LITTLE_ENDIAN 1588 struct hermon_hw_mtt_s { 1589 uint32_t present :1; 1590 uint32_t :2; 1591 uint32_t ptag_l :29; 1592 1593 uint32_t ptag_h; 1594 }; 1595 #else /* BIG_ENDIAN */ 1596 struct hermon_hw_mtt_s { 1597 uint32_t ptag_h; 1598 1599 uint32_t ptag_l :29; 1600 uint32_t :2; 1601 uint32_t present :1; 1602 }; 1603 1604 #endif 1605 #define HERMON_MTT_ENTRY_NOTPRESENT 0x0 1606 #define HERMON_MTT_ENTRY_PRESENT 0x1 1607 1608 1609 /* 1610 * Hermon Event Queue Context Table (EQC) entries 1611 * Hermon supports 512 Event Queues, and the status of Event Queues is stored 1612 * in the Event Queue Context (EQC) table. The EQC table is a virtually- 1613 * contiguous memory structure in the ICM. Each EQC 1614 * table entry contains Event Queue status and information required by 1615 * the hardware in order to access the event queue. 1616 * NOTE that in Hermon (as opposed to earlier HCAs), 1617 * you have to allocate ICM for 2**32 (or about 16 M), even though 1618 * it doesn't support that many. See PRM v35. Also, some set of them 1619 * will be available for each domain in a virtual environment, needing to 1620 * rething the allocation and usage model for EQs - in the future. 1621 * 1622 * The following structure is used in the SW2HW_EQ, QUERY_EQ, and HW2SW_EQ 1623 * commands. 1624 * The SW2HW_EQ command transfers ownership of an EQ context from software 1625 * to hardware. The command takes the EQC entry from the input mailbox and 1626 * stores it in the EQC in the hardware. The command will fail if the 1627 * requested EQC entry is already owned by the hardware. NOTE: the 1628 * initialization of the cMPT for the EQC occurs implicitly as a result 1629 * of executing this command, and MR has/had to be adjusted for it. 1630 * The QUERY_EQ command retrieves a snapshot of an EQC entry. The command 1631 * stores the snapshot in the output mailbox. The EQC state and its values 1632 * are not affected by the QUERY_EQ command. 1633 * Finally, the HW2SW_EQ command transfers ownership of an EQC entry from 1634 * the hardware to the software. The command takes the EQC entry from the 1635 * hardware and stores it in the output mailbox. The EQC entry will be 1636 * invalidated as a result of the command. It is the responsibility of the 1637 * software to unmap all the events, which might have been previously 1638 * mapped to the EQ, prior to issuing the HW2SW_EQ command. 1639 */ 1640 1641 1642 #ifdef _LITTLE_ENDIAN 1643 struct hermon_hw_eqc_s { 1644 uint32_t :32; 1645 1646 uint32_t :8; 1647 uint32_t state :4; 1648 uint32_t :5; 1649 uint32_t overrun_ignore :1; 1650 uint32_t ev_coalesc :1; 1651 uint32_t :9; 1652 uint32_t status :4; 1653 1654 uint32_t :24; 1655 uint32_t log_eq_sz :5; 1656 uint32_t :3; 1657 1658 uint32_t :5; 1659 uint32_t pg_offs :7; 1660 uint32_t :20; 1661 1662 uint32_t intr :10; 1663 uint32_t :22; 1664 1665 uint32_t eq_max_cnt :16; 1666 uint32_t eq_period :16; 1667 1668 uint32_t :3; 1669 uint32_t mtt_base_addrl :29; 1670 1671 uint32_t mtt_base_addrh :8; 1672 uint32_t :16; 1673 uint32_t log2_pgsz :6; /* in 4K pages */ 1674 uint32_t :2; 1675 1676 uint32_t rsrv0[2]; 1677 1678 uint32_t prod_indx :24; 1679 uint32_t :8; 1680 1681 uint32_t cons_indx :24; 1682 uint32_t :8; 1683 1684 uint64_t rsrv1[2]; /* force it to 8b alignment */ 1685 }; 1686 #else /* BIG ENDIAN */ 1687 struct hermon_hw_eqc_s { 1688 uint32_t status :4; 1689 uint32_t :9; 1690 uint32_t ev_coalesc :1; 1691 uint32_t overrun_ignore :1; 1692 uint32_t :5; 1693 uint32_t state :4; 1694 uint32_t :8; 1695 1696 uint32_t :32; 1697 1698 uint32_t :20; 1699 uint32_t pg_offs :7; 1700 uint32_t :5; 1701 1702 uint32_t :3; 1703 uint32_t log_eq_sz :5; 1704 uint32_t :24; 1705 1706 uint32_t eq_period :16; 1707 uint32_t eq_max_cnt :16; 1708 1709 uint32_t :22; 1710 uint32_t intr :10; 1711 1712 uint32_t :2; 1713 uint32_t log2_pgsz :6; /* in 4K pages */ 1714 uint32_t :16; 1715 uint32_t mtt_base_addrh :8; 1716 1717 uint32_t mtt_base_addrl :29; 1718 uint32_t :3; 1719 1720 uint32_t rsrv0[2]; 1721 1722 uint32_t :8; 1723 uint32_t cons_indx :24; 1724 1725 uint32_t :8; 1726 uint32_t prod_indx :24; 1727 1728 uint64_t rsrv1[2]; /* force it to 8b alignment */ 1729 }; 1730 #endif 1731 #define HERMON_EQ_STATUS_OK 0x0 1732 #define HERMON_EQ_STATUS_OVERFLOW 0x9 1733 #define HERMON_EQ_STATUS_WRITE_FAILURE 0xA 1734 1735 #define HERMON_EQ_ARMED 0x9 1736 #define HERMON_EQ_FIRED 0xA 1737 #define HERMON_EQ_ALWAYS_ARMED 0xB 1738 1739 1740 /* 1741 * Hermon Event Queue Entries (EQE) 1742 * Each EQE contains enough information for the software to identify the 1743 * source of the event. The following structures are used to define each 1744 * of the various kinds of events that the Hermon hardware will generate. 1745 * Note: The hermon_hw_eqe_t below is the generic "Event Queue Entry". All 1746 * other EQEs differ only in the contents of their "event_data" field. 1747 * 1748 * Below we first define several structures which define the contents of 1749 * the "event_data" fields: 1750 * hermon_hw_eqe_cq_t for "Completion Queue Events" 1751 * hermon_hw_eqe_qp_evt_t for "Queue Pair Events" such as Path Migration 1752 * Succeeded, Path Migration Failed, Communication Established, Send 1753 * Queue Drained, Local WQ Catastrophic Error, Invalid Request Local 1754 * WQ Error, and Local Access Violation WQ Error. 1755 * hermon_hw_eqe_cqerr_t for "Completion Queue Error Events" 1756 * hermon_hw_eqe_portstate_t for "Port State Change Events" 1757 * hermon_hw_eqe_gpio_t for "GPIO State Change Events" 1758 * hermon_hw_eqe_cmdcmpl_t for "Command Interface Completion Events" 1759 * hermon_hw_eqe_operr_t for "Operational and Catastrophic Error Events" 1760 * such as EQ Overflow, Misbehaved UAR page, Internal Parity Error, 1761 * Uplink bus error, and DDR data error. 1762 * hermon_hw_eqe_pgflt_t for "Not-present Page Fault on WQE or Data 1763 * Buffer Access". (Note: Currently, this event is unsupported). 1764 * 1765 * Note also: The following structures are not #define'd with both 1766 * little-endian and big-endian definitions. This is because their 1767 * individual fields are not directly accessed except through the macros 1768 * defined below. 1769 */ 1770 1771 1772 typedef struct hermon_hw_eqe_cq_s { 1773 uint32_t :8; 1774 uint32_t cqn :24; 1775 uint32_t rsrv0[5]; 1776 } hermon_hw_eqe_cq_t; 1777 1778 1779 1780 typedef struct hermon_hw_eqe_qp_evt_s { 1781 uint32_t :8; 1782 uint32_t qpn :24; 1783 1784 uint32_t rsrv0[5]; 1785 } hermon_hw_eqe_qpevt_t; 1786 1787 1788 typedef struct hermon_hw_eqe_cqerr_s { 1789 uint32_t :8; 1790 uint32_t cqn :24; 1791 1792 uint32_t :32; 1793 1794 uint32_t :24; 1795 uint32_t syndrome :8; 1796 1797 uint32_t rsrv0[3]; 1798 } hermon_hw_eqe_cqerr_t; 1799 #define HERMON_CQERR_OVERFLOW 0x1 1800 #define HERMON_CQERR_ACCESS_VIOLATION 0x2 1801 1802 1803 typedef struct hermon_hw_eqe_portstate_s { 1804 uint32_t rsrv0[2]; 1805 1806 uint32_t :2; 1807 uint32_t port :2; 1808 uint32_t :28; 1809 1810 uint32_t rsrv1[3]; 1811 } hermon_hw_eqe_portstate_t; 1812 #define HERMON_PORT_LINK_ACTIVE 0x4 1813 #define HERMON_PORT_LINK_DOWN 0x1 1814 1815 1816 typedef struct hermon_hw_eqe_gpio_s { 1817 uint32_t rsrv0[3]; 1818 1819 uint32_t gpio_ev0; 1820 1821 uint32_t gpio_ev1; 1822 1823 uint32_t :32; 1824 } hermon_hw_eqe_gpio_t; 1825 1826 1827 typedef struct hermon_hw_eqe_cmdcmpl_s { 1828 uint32_t :16; 1829 uint32_t token :16; 1830 1831 uint32_t :32; 1832 1833 uint32_t :24; 1834 uint32_t status :8; 1835 1836 uint32_t out_param0; 1837 1838 uint32_t out_param1; 1839 1840 uint32_t :32; 1841 } hermon_hw_eqe_cmdcmpl_t; 1842 1843 1844 typedef struct hermon_hw_eqe_operr_s { 1845 uint32_t rsrv0[2]; 1846 1847 uint32_t :24; 1848 uint32_t error_type :8; 1849 1850 uint32_t data; 1851 1852 uint32_t rsrv1[2]; 1853 } hermon_hw_eqe_operr_t; 1854 #define HERMON_ERREVT_EQ_OVERFLOW 0x1 1855 #define HERMON_ERREVT_BAD_UARPG 0x2 1856 #define HERMON_ERREVT_UPLINK_BUSERR 0x3 1857 #define HERMON_ERREVT_DDR_DATAERR 0x4 1858 #define HERMON_ERREVT_INTERNAL_PARITY 0x5 1859 1860 1861 typedef struct hermon_hw_eqe_pgflt_s { 1862 uint32_t rsrv0[2]; 1863 uint32_t :24; 1864 uint32_t fault_type :4; 1865 uint32_t wqv :1; 1866 uint32_t wqe_data :1; 1867 uint32_t rem_loc :1; 1868 uint32_t snd_rcv :1; 1869 uint32_t vaddr_h; 1870 uint32_t vaddr_l; 1871 uint32_t mem_key; 1872 } hermon_hw_eqe_pgflt_t; 1873 #define HERMON_PGFLT_PG_NOTPRESENT 0x8 1874 #define HERMON_PGFLT_PG_WRACC_VIOL 0xA 1875 #define HERMON_PGFLT_UNSUP_NOTPRESENT 0xE 1876 #define HERMON_PGFLT_UNSUP_WRACC_VIOL 0xF 1877 #define HERMON_PGFLT_WQE_CAUSED 0x1 1878 #define HERMON_PGFLT_DATA_CAUSED 0x0 1879 #define HERMON_PGFLT_REMOTE_CAUSED 0x1 1880 #define HERMON_PGFLT_LOCAL_CAUSED 0x0 1881 #define HERMON_PGFLT_SEND_CAUSED 0x1 1882 #define HERMON_PGFLT_RECV_CAUSED 0x0 1883 #define HERMON_PGFLT_DESC_CONSUMED 0x1 1884 #define HERMON_PGFLT_DESC_NOTCONSUMED 0x0 1885 1886 struct hermon_hw_eqe_s { 1887 uint32_t :8; 1888 uint32_t event_type :8; 1889 uint32_t :8; 1890 uint32_t event_subtype :8; 1891 union { 1892 hermon_hw_eqe_cq_t eqe_cq; 1893 hermon_hw_eqe_qpevt_t eqe_qpevt; 1894 hermon_hw_eqe_cqerr_t eqe_cqerr; 1895 hermon_hw_eqe_portstate_t eqe_portstate; 1896 hermon_hw_eqe_gpio_t eqe_gpio; 1897 hermon_hw_eqe_cmdcmpl_t eqe_cmdcmpl; 1898 hermon_hw_eqe_operr_t eqe_operr; 1899 hermon_hw_eqe_pgflt_t eqe_pgflt; 1900 } event_data; 1901 uint32_t :24; 1902 uint32_t owner :1; 1903 uint32_t :7; 1904 }; 1905 #define eqe_cq event_data.eqe_cq 1906 #define eqe_qpevt event_data.eqe_qpevt 1907 #define eqe_cqerr event_data.eqe_cqerr 1908 #define eqe_portstate event_data.eqe_portstate 1909 #define eqe_gpio event_data.eqe_gpio 1910 #define eqe_cmdcmpl event_data.eqe_cmdcmpl 1911 #define eqe_operr event_data.eqe_operr 1912 #define eqe_pgflt event_data.eqe_pgflt 1913 1914 /* 1915 * The following macros are used for extracting (and in some cases filling in) 1916 * information from EQEs 1917 */ 1918 #define HERMON_EQE_CQNUM_MASK 0x00FFFFFF 1919 #define HERMON_EQE_CQNUM_SHIFT 0 1920 #define HERMON_EQE_QPNUM_MASK 0x00FFFFFF 1921 #define HERMON_EQE_QPNUM_SHIFT 0 1922 #define HERMON_EQE_PORTNUM_MASK 0x30 1923 #define HERMON_EQE_PORTNUM_SHIFT 4 1924 #define HERMON_EQE_OWNER_MASK 0x00000080 1925 #define HERMON_EQE_OWNER_SHIFT 7 1926 1927 #define HERMON_EQE_EVTTYPE_GET(eq, eqe) \ 1928 (((uint8_t *)(eqe))[1]) 1929 #define HERMON_EQE_EVTSUBTYPE_GET(eq, eqe) \ 1930 (((uint8_t *)(eqe))[3]) 1931 #define HERMON_EQE_CQNUM_GET(eq, eqe) \ 1932 ((htonl(((uint32_t *)(eqe))[1]) & HERMON_EQE_CQNUM_MASK) >> \ 1933 HERMON_EQE_CQNUM_SHIFT) 1934 #define HERMON_EQE_QPNUM_GET(eq, eqe) \ 1935 ((htonl(((uint32_t *)(eqe))[1]) & HERMON_EQE_QPNUM_MASK) >> \ 1936 HERMON_EQE_QPNUM_SHIFT) 1937 #define HERMON_EQE_PORTNUM_GET(eq, eqe) \ 1938 (((((uint8_t *)(eqe))[12]) & HERMON_EQE_PORTNUM_MASK) >> \ 1939 HERMON_EQE_PORTNUM_SHIFT) 1940 #define HERMON_EQE_CMDTOKEN_GET(eq, eqe) \ 1941 htons(((uint16_t *)(eqe))[3]) 1942 #define HERMON_EQE_CMDSTATUS_GET(eq, eqe) \ 1943 (((uint8_t *)(eqe))[0xf]) 1944 #define HERMON_EQE_CMDOUTP0_GET(eq, eqe) \ 1945 htonl(((uint32_t *)(eqe))[4]) 1946 #define HERMON_EQE_CMDOUTP1_GET(eq, eqe) \ 1947 htonl(((uint32_t *)(eqe))[5]) 1948 #define HERMON_EQE_OPERRTYPE_GET(eq, eqe) \ 1949 (((uint8_t *)(eqe))[0xf]) 1950 #define HERMON_EQE_OPERRDATA_GET(eq, eqe) \ 1951 htonl(((uint32_t *)(eqe))[4]) 1952 /* 1953 * Hermon does ownership of CQ and EQ differently from Arbel & Tavor. 1954 * Now, you keep track of the TOTAL number of CQE's or EQE's that have been 1955 * processed, and the sense of the ownership bit changes each time through. 1956 * That is, if the size of the queue is 16, so 4 bits [3:0] are the index 1957 * number, then bit [4] is the ownership bit in the count. So you mask that 1958 * bit and compare it to the owner bit in the entry - if the same, then the 1959 * entry is in SW onwership. Otherwise, it's in hardware and the driver 1960 * does not consume it. 1961 */ 1962 1963 #define HERMON_EQE_OWNER_IS_SW(eq, eqe) \ 1964 ((((uint8_t *)(eqe))[0x1f] & HERMON_EQE_OWNER_MASK) == \ 1965 (((eq->eq_nexteqe) & eq->eq_bufsz) >> \ 1966 (eq->eq_log_eqsz - HERMON_EQE_OWNER_SHIFT))) 1967 1968 /* 1969 * Hermon Completion Queue Context Table (CQC) entries 1970 * The CQC table is a virtually-contiguous memory area residing in HCA's 1971 * ICM. Each CQC table entry contains information 1972 * required by the hardware to access the completion queue to post 1973 * completions (CQE). 1974 * 1975 * The following structure is used in the SW2HW_CQ, QUERY_CQ, RESIZE_CQ, 1976 * and HW2SW_CQ commands. 1977 * The SW2HW_CQ command transfers ownership of an CQ context from software 1978 * to hardware. The command takes the CQC entry from the input mailbox and 1979 * stores it in the CQC in the hardware. The command will fail if the 1980 * requested CQC entry is already owned by the hardware. 1981 * The QUERY_CQ command retrieves a snapshot of a CQC entry. The command 1982 * stores the snapshot in the output mailbox. The CQC state and its values 1983 * are not affected by the QUERY_CQ command. 1984 * Finally, the HW2SW_CQ command transfers ownership of a CQC entry from 1985 * the hardware to the software. The command takes the CQC entry from the 1986 * hardware and stores it in the output mailbox. The CQC entry will be 1987 * invalidated as a result of the command. 1988 */ 1989 1990 1991 #ifdef _LITTLE_ENDIAN 1992 struct hermon_hw_cqc_s { 1993 uint32_t :32; 1994 1995 uint32_t :8; 1996 uint32_t state :4; 1997 uint32_t :5; 1998 uint32_t overrun_ignore :1; 1999 uint32_t cqe_coalesc :1; 2000 uint32_t :9; 2001 uint32_t status :4; 2002 2003 uint32_t usr_page :24; 2004 uint32_t log_cq_sz :5; 2005 uint32_t :3; 2006 2007 uint32_t :5; 2008 uint32_t pg_offs :7; 2009 uint32_t :20; 2010 2011 uint32_t c_eqn :9; 2012 uint32_t :23; 2013 2014 uint32_t cq_max_cnt :16; 2015 uint32_t cq_period :16; 2016 2017 uint32_t :3; 2018 uint32_t mtt_base_addl :29; 2019 2020 uint32_t mtt_base_addh :8; 2021 uint32_t :16; 2022 uint32_t log2_pgsz :6; 2023 uint32_t :2; 2024 2025 uint32_t solicit_prod_indx :24; 2026 uint32_t :8; 2027 2028 uint32_t last_notified_indx :24; 2029 uint32_t :8; 2030 2031 uint32_t prod_cntr :24; /* producer counter */ 2032 uint32_t :8; 2033 2034 uint32_t cons_cntr :24; /* consumer counter */ 2035 uint32_t :8; 2036 2037 uint32_t rsrv0[2]; 2038 2039 uint32_t :3; 2040 uint32_t dbr_addrl :29; 2041 2042 uint32_t dbr_addrh; 2043 2044 uint64_t rsrv1[8]; /* hermon, match DEV_CAP size */ 2045 }; 2046 #else 2047 struct hermon_hw_cqc_s { 2048 uint32_t status :4; 2049 uint32_t :9; 2050 uint32_t cqe_coalesc :1; 2051 uint32_t overrun_ignore :1; 2052 uint32_t :5; 2053 uint32_t state :4; 2054 uint32_t :8; 2055 2056 uint32_t :32; 2057 2058 uint32_t :20; 2059 uint32_t pg_offs :7; 2060 uint32_t :5; 2061 2062 uint32_t :3; 2063 uint32_t log_cq_sz :5; 2064 uint32_t usr_page :24; 2065 2066 uint32_t cq_period :16; 2067 uint32_t cq_max_cnt :16; 2068 2069 uint32_t :23; 2070 uint32_t c_eqn :9; 2071 2072 uint32_t :2; 2073 uint32_t log2_pgsz :6; 2074 uint32_t :16; 2075 uint32_t mtt_base_addh :8; 2076 2077 uint32_t mtt_base_addl :29; 2078 uint32_t :3; 2079 2080 uint32_t :8; 2081 uint32_t last_notified_indx :24; 2082 2083 uint32_t :8; 2084 uint32_t solicit_prod_indx :24; 2085 2086 uint32_t :8; 2087 uint32_t cons_cntr :24; /* consumer counter */ 2088 2089 uint32_t :8; 2090 uint32_t prod_cntr :24; /* priducer counter */ 2091 2092 uint32_t rsrv0[2]; 2093 2094 uint32_t dbr_addrh; 2095 2096 uint32_t dbr_addrl :29; 2097 uint32_t :3; 2098 2099 uint64_t rsrv1[8]; /* hermon, match DEV_CAP size */ 2100 }; 2101 #endif 2102 #define HERMON_CQ_STATUS_OK 0x0 2103 #define HERMON_CQ_STATUS_OVERFLOW 0x9 2104 #define HERMON_CQ_STATUS_WRITE_FAILURE 0xA 2105 2106 #define HERMON_CQ_DISARMED 0x0 2107 #define HERMON_CQ_ARMED 0x1 2108 #define HERMON_CQ_ARMED_SOLICITED 0x4 2109 #define HERMON_CQ_FIRED 0xA 2110 2111 /* 2112 * Hermon Completion Queue Entries (CQE) 2113 * Each CQE contains enough information for the software to associate the 2114 * completion with the Work Queue Element (WQE) to which it corresponds. 2115 * 2116 * Note: The following structure is not #define'd with both little-endian 2117 * and big-endian definitions. This is because each CQE's individual 2118 * fields are not directly accessed except through the macros defined below. 2119 */ 2120 2121 2122 struct hermon_hw_cqe_s { 2123 uint32_t dife :1; 2124 uint32_t :2; 2125 uint32_t fl :1; 2126 uint32_t fccrc_sd :1; 2127 uint32_t d2s :1; 2128 uint32_t :2; 2129 uint32_t my_qpn :24; 2130 2131 uint32_t immed_rss_val_key; 2132 2133 uint32_t grh :1; 2134 uint32_t ml_path :7; 2135 uint32_t srq_rqpn :24; 2136 2137 uint32_t sl :4; 2138 uint32_t :12; 2139 uint32_t slid :16; 2140 2141 uint32_t ipoib_status; 2142 2143 uint32_t byte_cnt; 2144 2145 uint32_t wqe_cntr :16; 2146 uint32_t checksum :16; 2147 2148 uint32_t :8; 2149 uint32_t :16; 2150 uint32_t owner :1; 2151 uint32_t send_or_recv :1; 2152 uint32_t inline_scatter :1; 2153 uint32_t opcode :5; 2154 }; 2155 #define HERMON_COMPLETION_RECV 0x0 2156 #define HERMON_COMPLETION_SEND 0x1 2157 2158 #define HERMON_CQE_DEFAULT_VERSION 0x0 2159 2160 /* 2161 * The following macros are used for extracting (and in some cases filling in) 2162 * information from CQEs 2163 */ 2164 #define HERMON_CQE_QPNUM_MASK 0x00FFFFFF 2165 #define HERMON_CQE_QPNUM_SHIFT 0 2166 2167 2168 #define HERMON_CQE_DQPN_MASK 0x00FFFFFF 2169 #define HERMON_CQE_DQPN_SHIFT 0 2170 2171 2172 #define HERMON_CQE_SL_SHIFT 4 2173 #define HERMON_CQE_GRH_MASK 0x80 2174 #define HERMON_CQE_PATHBITS_MASK 0x7F 2175 #define HERMON_CQE_SLID_15_8 0xe 2176 #define HERMON_CQE_SLID_7_0 0xf 2177 #define HERMON_CQE_OPCODE_MASK 0x1F 2178 #define HERMON_CQE_SENDRECV_MASK 0x40 2179 #define HERMON_CQE_SENDRECV_SHIFT 6 2180 #define HERMON_CQE_OWNER_MASK 0x80 2181 #define HERMON_CQE_OWNER_SHIFT 7 2182 #define HERMON_CQE_WQECNTR_15_8 0x18 2183 #define HERMON_CQE_WQECNTR_7_0 0x19 2184 /* Byte offsets for IPoIB Checksum Offload fields */ 2185 #define HERMON_CQE_CKSUM_15_8 0x1a 2186 #define HERMON_CQE_CKSUM_7_0 0x1b 2187 #define HERMON_CQE_IPOK 0x10 /* byte 0x10 in cqe */ 2188 #define HERMON_CQE_IPOK_BIT 0x10 /* bitmask for OK bit */ 2189 2190 #define HERMON_CQE_IS_IPOK(cq, cqe) \ 2191 (((uint8_t *)(cqe))[HERMON_CQE_IPOK] & HERMON_CQE_IPOK_BIT) 2192 2193 #define HERMON_CQE_CKSUM(cq, cqe) \ 2194 ((((uint8_t *)(cqe))[HERMON_CQE_CKSUM_15_8] << 8) | \ 2195 (((uint8_t *)(cqe))[HERMON_CQE_CKSUM_7_0])) 2196 2197 #define HERMON_CQE_IPOIB_STATUS(cq, cqe) \ 2198 htonl((((uint32_t *)(cqe)))[4]) 2199 2200 #define HERMON_CQE_QPNUM_GET(cq, cqe) \ 2201 ((htonl((((uint32_t *)(cqe)))[0]) & HERMON_CQE_QPNUM_MASK) >> \ 2202 HERMON_CQE_QPNUM_SHIFT) 2203 2204 #define HERMON_CQE_IMM_ETH_PKEY_CRED_GET(cq, cqe) \ 2205 htonl(((uint32_t *)(cqe))[1]) 2206 2207 #define HERMON_CQE_DQPN_GET(cq, cqe) \ 2208 ((htonl(((uint32_t *)(cqe))[2]) & HERMON_CQE_DQPN_MASK) >> \ 2209 HERMON_CQE_DQPN_SHIFT) 2210 2211 #define HERMON_CQE_GRH_GET(cq, cqe) \ 2212 (((uint8_t *)(cqe))[8] & HERMON_CQE_GRH_MASK) 2213 2214 #define HERMON_CQE_PATHBITS_GET(cq, cqe) \ 2215 (((uint8_t *)(cqe))[8] & HERMON_CQE_PATHBITS_MASK) 2216 2217 #define HERMON_CQE_DLID_GET(cq, cqe) \ 2218 ((((uint8_t *)(cqe))[HERMON_CQE_SLID_15_8] << 8) | \ 2219 (((uint8_t *)(cqe))[HERMON_CQE_SLID_7_0])) 2220 2221 #define HERMON_CQE_SL_GET(cq, cqe) \ 2222 ((((uint8_t *)(cqe))[12]) >> HERMON_CQE_SL_SHIFT) 2223 2224 #define HERMON_CQE_BYTECNT_GET(cq, cqe) \ 2225 htonl(((uint32_t *)(cqe))[5]) 2226 2227 #define HERMON_CQE_WQECNTR_GET(cq, cqe) \ 2228 ((((uint8_t *)(cqe))[HERMON_CQE_WQECNTR_15_8] << 8) | \ 2229 (((uint8_t *)(cqe))[HERMON_CQE_WQECNTR_7_0])) 2230 2231 #define HERMON_CQE_ERROR_SYNDROME_GET(cq, cqe) \ 2232 (((uint8_t *)(cqe))[27]) 2233 2234 #define HERMON_CQE_OPCODE_GET(cq, cqe) \ 2235 ((((uint8_t *)(cqe))[31]) & HERMON_CQE_OPCODE_MASK) 2236 2237 #define HERMON_CQE_SENDRECV_GET(cq, cqe) \ 2238 (((((uint8_t *)(cqe))[31]) & HERMON_CQE_SENDRECV_MASK) >> \ 2239 HERMON_CQE_SENDRECV_SHIFT) 2240 2241 /* See Comment above for EQE - ownership of CQE is handled the same */ 2242 2243 #define HERMON_CQE_OWNER_IS_SW(cq, cqe, considx) \ 2244 (((((uint8_t *)(cqe))[31] & HERMON_CQE_OWNER_MASK) >> \ 2245 HERMON_CQE_OWNER_SHIFT) == \ 2246 (((considx) & cq->cq_bufsz) >> cq->cq_log_cqsz)) 2247 2248 /* 2249 * Hermon Shared Receive Queue (SRQ) Context Entry Format 2250 */ 2251 2252 #ifdef _LITTLE_ENDIAN 2253 struct hermon_hw_srqc_s { 2254 uint32_t xrc_domain :16; 2255 uint32_t :8; 2256 uint32_t log_rq_stride :3; 2257 uint32_t :5; 2258 2259 uint32_t srqn :24; 2260 uint32_t log_srq_size :4; 2261 uint32_t state :4; 2262 2263 uint32_t :32; 2264 2265 uint32_t cqn_xrc :24; 2266 uint32_t :2; 2267 uint32_t page_offs :6; 2268 2269 uint32_t :3; 2270 uint32_t mtt_base_addrl :29; 2271 2272 uint32_t mtt_base_addrh :8; 2273 uint32_t :16; 2274 uint32_t log2_pgsz :6; 2275 uint32_t :2; 2276 2277 uint32_t wqe_cnt :16; 2278 uint32_t lwm :16; 2279 2280 uint32_t pd :24; 2281 uint32_t :8; 2282 2283 uint32_t :32; 2284 2285 uint32_t srq_wqe_cntr :16; 2286 uint32_t :16; 2287 2288 uint32_t :2; 2289 uint32_t dbr_addrl :30; 2290 2291 uint32_t dbr_addrh; 2292 2293 uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */ 2294 2295 }; 2296 #else 2297 struct hermon_hw_srqc_s { 2298 uint32_t state :4; 2299 uint32_t log_srq_size :4; 2300 uint32_t srqn :24; 2301 2302 uint32_t :5; 2303 uint32_t log_rq_stride :3; 2304 uint32_t :8; 2305 uint32_t xrc_domain :16; 2306 2307 uint32_t page_offs :6; 2308 uint32_t :2; 2309 uint32_t cqn_xrc :24; 2310 2311 uint32_t :32; 2312 2313 uint32_t :2; 2314 uint32_t log2_pgsz :6; 2315 uint32_t :16; 2316 uint32_t mtt_base_addrh :8; 2317 2318 uint32_t mtt_base_addrl :29; 2319 uint32_t :3; 2320 2321 uint32_t :8; 2322 uint32_t pd :24; 2323 2324 uint32_t lwm :16; 2325 uint32_t wqe_cnt :16; 2326 2327 uint32_t :16; 2328 uint32_t srq_wqe_cntr :16; 2329 2330 uint32_t :32; 2331 2332 uint32_t dbr_addrh; 2333 2334 uint32_t dbr_addrl :30; 2335 uint32_t :2; 2336 2337 uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */ 2338 }; 2339 #endif 2340 2341 /* 2342 * Hermon MOD_STAT_CFG input mailbox structure 2343 */ 2344 2345 2346 #ifdef _LITTLE_ENDIAN 2347 struct hermon_hw_mod_stat_cfg_s { 2348 uint32_t rsvd0; 2349 2350 uint32_t :14; 2351 uint32_t dife :1; 2352 uint32_t dife_m :1; 2353 uint32_t rx_options :4; 2354 uint32_t :3; 2355 uint32_t rx_options_m :1; 2356 uint32_t tx_options :4; 2357 uint32_t :3; 2358 uint32_t tx_options_m :1; 2359 2360 uint32_t lid :16; 2361 uint32_t lid_m :1; 2362 uint32_t :3; 2363 uint32_t port_en :1; 2364 uint32_t port_en_m :1; 2365 uint32_t :10; 2366 2367 uint32_t rsvd1; 2368 2369 uint32_t guid_hi; 2370 2371 uint32_t :31; 2372 uint32_t guid_hi_m :1; 2373 2374 uint32_t guid_lo; 2375 uint32_t :31; 2376 2377 uint32_t guid_lo_m :1; 2378 2379 uint32_t rsvd[4]; 2380 2381 uint32_t inbuf_ind_en :3; 2382 uint32_t :1; 2383 uint32_t sd_main :4; 2384 uint32_t :4; 2385 uint32_t sd_equal :4; 2386 uint32_t :4; 2387 uint32_t sd_mux_main :2; 2388 uint32_t :2; 2389 uint32_t mux_eq :2; 2390 uint32_t :2; 2391 uint32_t sigdet_th :3; 2392 uint32_t :1; 2393 2394 uint32_t ob_preemp_pre :5; 2395 uint32_t :3; 2396 uint32_t op_preemp_post :5; 2397 uint32_t :3; 2398 uint32_t ob_preemp_main :5; 2399 uint32_t :3; 2400 uint32_t ob_preemp :5; 2401 uint32_t :2; 2402 uint32_t serdes_m :1; 2403 2404 uint32_t reserved[50]; 2405 }; 2406 #else /* BIG ENDIAN */ 2407 struct hermon_hw_mod_stat_cfg_s { 2408 uint32_t tx_options_m :1; 2409 uint32_t :3; 2410 uint32_t tx_options :4; 2411 uint32_t rx_options_m :1; 2412 uint32_t :3; 2413 uint32_t rx_options :4; 2414 uint32_t dife_m :1; 2415 uint32_t dife :1; 2416 uint32_t :14; 2417 2418 uint32_t rsvd0; 2419 2420 uint32_t rsvd1; 2421 2422 uint32_t :10; 2423 uint32_t port_en_m :1; 2424 uint32_t port_en :1; 2425 uint32_t :3; 2426 uint32_t lid_m :1; 2427 uint32_t lid :16; 2428 2429 uint32_t guid_hi_m :1; 2430 uint32_t :31; 2431 2432 uint32_t guid_hi; 2433 2434 uint32_t guid_lo_m :1; 2435 uint32_t :31; 2436 2437 uint32_t guid_lo; 2438 2439 uint32_t rsvd[4]; 2440 2441 uint32_t serdes_m :1; 2442 uint32_t :2; 2443 uint32_t ob_preemp :5; 2444 uint32_t :3; 2445 uint32_t ob_preemp_main :5; 2446 uint32_t :3; 2447 uint32_t op_preemp_post :5; 2448 uint32_t :3; 2449 uint32_t ob_preemp_pre :5; 2450 2451 uint32_t :1; 2452 uint32_t sigdet_th :3; 2453 uint32_t :2; 2454 uint32_t mux_eq :2; 2455 uint32_t :2; 2456 uint32_t sd_mux_main :2; 2457 uint32_t :4; 2458 uint32_t sd_equal :4; 2459 uint32_t :4; 2460 uint32_t sd_main :4; 2461 uint32_t :1; 2462 uint32_t inbuf_ind_en :3; 2463 2464 uint32_t reserved[50]; 2465 }; 2466 #endif 2467 2468 2469 /* 2470 * Hermon MOD_STAT_CFG input modifier structure 2471 */ 2472 struct hermon_hw_msg_in_mod_s { 2473 #ifdef _LITTLE_ENDIAN 2474 uint32_t offset :8; 2475 uint32_t port_num :8; 2476 uint32_t lane_num :4; 2477 uint32_t link_speed :3; 2478 uint32_t auto_neg :1; 2479 uint32_t :8; 2480 #else 2481 uint32_t :8; 2482 uint32_t auto_neg :1; 2483 uint32_t link_speed :3; 2484 uint32_t lane_num :4; 2485 uint32_t port_num :8; 2486 uint32_t offset :8; 2487 #endif 2488 }; 2489 2490 2491 /* 2492 * Hermon UD Address Vector (UDAV) 2493 * Hermon UDAV are used in conjunction with Unreliable Datagram (UD) send 2494 * WQEs. Each UD send message contains an address vector in in the datagram 2495 * segment. The verbs consumer must use special verbs to create and modify 2496 * address handles, each of which contains a UDAV structure. When posting 2497 * send WQEs to UD QP, the verbs consumer must supply a valid address 2498 * handle/UDAV. 2499 */ 2500 2501 2502 #ifdef _LITTLE_ENDIAN 2503 struct hermon_hw_udav_s { 2504 uint32_t rlid :16; 2505 uint32_t ml_path :7; 2506 uint32_t grh :1; 2507 uint32_t :8; 2508 2509 uint32_t pd :24; 2510 uint32_t portnum :2; 2511 uint32_t :5; 2512 uint32_t force_lp :1; 2513 2514 uint32_t flow_label :20; 2515 uint32_t tclass :8; 2516 uint32_t sl :4; 2517 2518 uint32_t hop_limit :8; 2519 uint32_t max_stat_rate :4; 2520 uint32_t :4; 2521 uint32_t mgid_index :7; 2522 uint32_t :9; 2523 2524 uint64_t rgid_h; 2525 uint64_t rgid_l; 2526 }; 2527 #else 2528 struct hermon_hw_udav_s { 2529 uint32_t force_lb :1; 2530 uint32_t :5; 2531 uint32_t portnum :2; 2532 uint32_t pd :24; 2533 2534 uint32_t :8; 2535 uint32_t grh :1; 2536 uint32_t ml_path :7; 2537 uint32_t rlid :16; 2538 2539 uint32_t :9; 2540 uint32_t mgid_index :7; 2541 uint32_t :4; 2542 uint32_t max_stat_rate :4; 2543 uint32_t hop_limit :8; 2544 2545 uint32_t sl :4; 2546 uint32_t tclass :8; 2547 uint32_t flow_label :20; 2548 2549 uint64_t rgid_h; 2550 uint64_t rgid_l; 2551 }; 2552 #endif 2553 #define HERMON_UDAV_MODIFY_MASK0 0xFCFFFFFFFF000000ULL 2554 #define HERMON_UDAV_MODIFY_MASK1 0xFF80F00000000000ULL 2555 2556 2557 /* 2558 * Hermon Queue Pair Context Table (QPC) entries 2559 * The QPC table is a virtually-contiguous memory area residing in HCA 2560 * ICM. Each QPC entry is accessed for reads and writes 2561 * by the HCA while executing work requests on the associated QP. 2562 * 2563 * The following structure is used in the RST2INIT_QP, INIT2INIT_QP, 2564 * INIT2RTR_QP, RTR2RTS_QP, RTS2RTS_QP, SQERR2RTS_QP, TOERR_QP, RTS2SQD_QP, 2565 * SQD2RTS_QP, TORST_QP, and QUERY_QP commands. 2566 * With the exception of the QUERY_QP command, each of these commands reads 2567 * from some portion of the QPC in the input mailbox and modified the QPC 2568 * stored in the hardware. The QUERY_QP command retrieves a snapshot of a 2569 * QPC entry. The command stores the snapshot in the output mailbox. The 2570 * QPC state and its values are not affected by the QUERY_QP command. 2571 * 2572 * Below we first define the hermon_hw_addr_path_t or "Hermon Address Path" 2573 * structure. This structure is used to provide address path information 2574 * (both primary and secondary) for each QP context. Note: Since this 2575 * structure is _very_ similar to the hermon_hw_udav_t structure above, 2576 * we are able to leverage the similarity with filling in and reading from 2577 * the two types of structures. See hermon_get_addr_path() and 2578 * hermon_set_addr_path() in hermon_misc.c for more details. 2579 */ 2580 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2581 #pragma pack(4) 2582 #endif 2583 2584 #ifdef _LITTLE_ENDIAN 2585 struct hermon_hw_addr_path_s { 2586 uint32_t rlid :16; 2587 uint32_t mlid :7; 2588 uint32_t grh :1; 2589 uint32_t cntr_idx :8; 2590 2591 uint32_t pkey_indx :7; 2592 uint32_t :22; 2593 uint32_t :2; /* but may be used for enet */ 2594 uint32_t force_lb :1; 2595 2596 uint32_t flow_label :20; 2597 uint32_t tclass :8; 2598 uint32_t :4; 2599 2600 uint32_t hop_limit :8; 2601 uint32_t max_stat_rate :4; 2602 uint32_t :4; 2603 uint32_t mgid_index :7; 2604 uint32_t :4; 2605 uint32_t ack_timeout :5; 2606 2607 uint64_t rgid_h; 2608 uint64_t rgid_l; 2609 2610 uint32_t :32; /* but may be used for enet */ 2611 2612 uint32_t :12; /* but may be used for enet */ 2613 uint32_t fsip :1; 2614 uint32_t :3; 2615 uint32_t :7; 2616 uint32_t :1; 2617 uint32_t sched_q :8; 2618 2619 2620 uint32_t :32; 2621 }; 2622 #else 2623 struct hermon_hw_addr_path_s { 2624 uint32_t force_lb :1; 2625 uint32_t :2; /* but may be used for enet */ 2626 uint32_t :22; 2627 uint32_t pkey_indx :7; 2628 2629 uint32_t cntr_idx :8; 2630 uint32_t grh :1; 2631 uint32_t mlid :7; 2632 uint32_t rlid :16; 2633 2634 uint32_t ack_timeout :5; 2635 uint32_t :4; 2636 uint32_t mgid_index :7; 2637 uint32_t :4; 2638 uint32_t max_stat_rate :4; 2639 uint32_t hop_limit :8; 2640 2641 uint32_t :4; 2642 uint32_t tclass :8; 2643 uint32_t flow_label :20; 2644 2645 uint64_t rgid_h; 2646 uint64_t rgid_l; 2647 2648 uint32_t sched_q :8; 2649 uint32_t :1; 2650 uint32_t :7; 2651 uint32_t :3; 2652 uint32_t fsip :1; 2653 uint32_t :12; /* but may be used for enet */ 2654 2655 uint32_t :32; /* but may be used for enet */ 2656 2657 uint32_t :32; 2658 }; 2659 #endif /* LITTLE ENDIAN */ 2660 2661 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2662 #pragma pack() 2663 #endif 2664 2665 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2666 #pragma pack(4) 2667 #endif 2668 #ifdef _LITTLE_ENDIAN 2669 struct hermon_hw_qpc_s { 2670 uint32_t pd :24; 2671 uint32_t :8; 2672 2673 uint32_t :11; 2674 uint32_t pm_state :2; 2675 uint32_t rss :1; 2676 uint32_t :2; 2677 uint32_t serv_type :8; 2678 uint32_t :4; 2679 uint32_t state :4; 2680 2681 uint32_t usr_page :24; 2682 uint32_t :8; 2683 2684 uint32_t :4; 2685 uint32_t rlky :1; 2686 uint32_t :3; 2687 uint32_t log_sq_stride :3; 2688 uint32_t log_sq_size :4; 2689 uint32_t sq_no_prefetch :1; 2690 uint32_t log_rq_stride :3; 2691 uint32_t log_rq_size :4; 2692 uint32_t :1; 2693 uint32_t msg_max :5; 2694 uint32_t mtu :3; 2695 2696 uint32_t rem_qpn :24; 2697 uint32_t :8; 2698 2699 uint32_t loc_qpn :24; 2700 uint32_t :8; 2701 2702 hermon_hw_addr_path_t pri_addr_path; 2703 2704 hermon_hw_addr_path_t alt_addr_path; 2705 2706 uint32_t :32; 2707 2708 uint32_t :5; 2709 uint32_t cur_retry_cnt :3; 2710 uint32_t cur_rnr_retry :3; 2711 uint32_t fre :1; 2712 uint32_t :1; 2713 uint32_t rnr_retry :3; 2714 uint32_t retry_cnt :3; 2715 uint32_t :2; 2716 uint32_t sra_max :3; 2717 uint32_t :4; 2718 uint32_t ack_req_freq :4; 2719 2720 uint32_t cqn_snd :24; 2721 uint32_t :8; 2722 2723 uint32_t next_snd_psn :24; 2724 uint32_t :8; 2725 2726 uint32_t :32; 2727 2728 uint32_t :32; 2729 2730 uint32_t ssn :24; 2731 uint32_t :8; 2732 2733 uint32_t last_acked_psn :24; 2734 uint32_t :8; 2735 2736 uint32_t next_rcv_psn :24; 2737 uint32_t min_rnr_nak :5; 2738 uint32_t :3; 2739 2740 uint32_t :4; 2741 uint32_t ric :1; 2742 uint32_t :1; 2743 uint32_t page_offs :6; 2744 uint32_t :1; 2745 uint32_t rae :1; 2746 uint32_t rwe :1; 2747 uint32_t rre :1; 2748 uint32_t :5; 2749 uint32_t rra_max :3; 2750 uint32_t :8; 2751 2752 uint32_t cqn_rcv :24; 2753 uint32_t :8; 2754 2755 uint32_t srcd :16; 2756 uint32_t :16; 2757 2758 uint32_t :2; 2759 uint32_t dbr_addrl :30; 2760 2761 uint32_t dbr_addrh :32; 2762 2763 uint32_t srq_number :24; 2764 uint32_t srq_en :1; 2765 uint32_t :7; 2766 2767 uint32_t qkey; 2768 2769 uint32_t sq_wqe_counter :16; 2770 uint32_t rq_wqe_counter :16; 2771 2772 uint32_t rmsn :24; 2773 uint32_t :8; 2774 2775 uint32_t rsrv0[2]; 2776 2777 /* new w/ hermon */ 2778 2779 uint32_t base_mkey :24; /* bits 32-8, low 7 m/b 0 */ 2780 uint32_t num_rmc_peers :8; 2781 2782 uint32_t rmc_parent_qpn :24; 2783 uint32_t header_sep :1; 2784 uint32_t inline_scatter :1; /* m/b 0 for srq */ 2785 uint32_t :1; 2786 uint32_t rmc_enable :2; 2787 uint32_t :2; /* may use one bit for enet */ 2788 uint32_t mkey_remap :1; 2789 2790 uint32_t :3; 2791 uint32_t mtt_base_addrl :29; 2792 2793 uint32_t mtt_base_addrh :8; 2794 uint32_t :16; 2795 uint32_t log2_pgsz :6; 2796 uint32_t :2; 2797 2798 uint32_t rsvd[12]; /* may/will be used for FCoIB */ 2799 }; 2800 #else /* BIG ENDIAN */ 2801 struct hermon_hw_qpc_s { 2802 uint32_t state :4; 2803 uint32_t :4; 2804 uint32_t serv_type :8; 2805 uint32_t :2; 2806 uint32_t rss :1; 2807 uint32_t pm_state :2; 2808 uint32_t :11; 2809 2810 uint32_t :8; 2811 uint32_t pd :24; 2812 2813 uint32_t mtu :3; 2814 uint32_t msg_max :5; 2815 uint32_t :1; 2816 uint32_t log_rq_size :4; 2817 uint32_t log_rq_stride :3; 2818 uint32_t sq_no_prefetch :1; 2819 uint32_t log_sq_size :4; 2820 uint32_t log_sq_stride :3; 2821 uint32_t :3; 2822 uint32_t rlky :1; 2823 uint32_t :4; 2824 2825 uint32_t :8; 2826 uint32_t usr_page :24; 2827 2828 uint32_t :8; 2829 uint32_t loc_qpn :24; 2830 2831 uint32_t :8; 2832 uint32_t rem_qpn :24; 2833 2834 hermon_hw_addr_path_t pri_addr_path; 2835 2836 hermon_hw_addr_path_t alt_addr_path; 2837 2838 uint32_t ack_req_freq :4; 2839 uint32_t :4; 2840 uint32_t sra_max :3; 2841 uint32_t :2; 2842 uint32_t retry_cnt :3; 2843 uint32_t rnr_retry :3; 2844 uint32_t :1; 2845 uint32_t fre :1; 2846 uint32_t cur_rnr_retry :3; 2847 uint32_t cur_retry_cnt :3; 2848 uint32_t :5; 2849 2850 uint32_t :32; 2851 2852 uint32_t :8; 2853 uint32_t next_snd_psn :24; 2854 2855 uint32_t :8; 2856 uint32_t cqn_snd :24; 2857 2858 uint32_t :32; 2859 2860 uint32_t :32; 2861 2862 uint32_t :8; 2863 uint32_t last_acked_psn :24; 2864 2865 uint32_t :8; 2866 uint32_t ssn :24; 2867 2868 uint32_t :8; 2869 uint32_t rra_max :3; 2870 uint32_t :5; 2871 uint32_t rre :1; 2872 uint32_t rwe :1; 2873 uint32_t rae :1; 2874 uint32_t :1; 2875 uint32_t page_offs :6; 2876 uint32_t :1; 2877 uint32_t ric :1; 2878 uint32_t :4; 2879 2880 uint32_t :3; 2881 uint32_t min_rnr_nak :5; 2882 uint32_t next_rcv_psn :24; 2883 2884 uint32_t :16; 2885 uint32_t srcd :16; 2886 2887 uint32_t :8; 2888 uint32_t cqn_rcv :24; 2889 2890 uint32_t dbr_addrh :32; 2891 2892 uint32_t dbr_addrl :30; 2893 uint32_t :2; 2894 2895 uint32_t qkey; 2896 2897 uint32_t :7; 2898 uint32_t srq_en :1; 2899 uint32_t srq_number :24; 2900 2901 uint32_t :8; 2902 uint32_t rmsn :24; 2903 2904 uint32_t rq_wqe_counter :16; 2905 uint32_t sq_wqe_counter :16; 2906 2907 uint32_t rsrv0[2]; 2908 2909 /* new w/ hermon */ 2910 2911 uint32_t mkey_remap :1; 2912 uint32_t :2; /* may use one bit for enet */ 2913 uint32_t rmc_enable :2; 2914 uint32_t :1; 2915 uint32_t inline_scatter :1; /* m/b 0 for srq */ 2916 uint32_t header_sep :1; 2917 uint32_t rmc_parent_qpn :24; 2918 2919 uint32_t num_rmc_peers :8; 2920 uint32_t base_mkey :24; /* bits 32-8, low 7 m/b 0 */ 2921 2922 uint32_t :2; 2923 uint32_t log2_pgsz :6; 2924 uint32_t :16; 2925 uint32_t mtt_base_addrh :8; 2926 2927 uint32_t mtt_base_addrl :29; 2928 uint32_t :3; 2929 2930 uint32_t rsvd[12]; /* may/will be used for FCoIB */ 2931 }; 2932 #endif /* LITTLE ENDIAN */ 2933 2934 #if (DATAMODEL_NATIVE == DATAMODEL_LP64) 2935 #pragma pack() 2936 #endif 2937 2938 #define HERMON_QP_RESET 0x0 2939 #define HERMON_QP_INIT 0x1 2940 #define HERMON_QP_RTR 0x2 2941 #define HERMON_QP_RTS 0x3 2942 #define HERMON_QP_SQERR 0x4 2943 #define HERMON_QP_SQD 0x5 2944 #define HERMON_QP_ERR 0x6 2945 #define HERMON_QP_SQDRAINING 0x7 2946 2947 #define HERMON_QP_RC 0x0 2948 #define HERMON_QP_UC 0x1 2949 #define HERMON_QP_UD 0x3 2950 #define HERMON_QP_MLX 0x7 2951 2952 #define HERMON_QP_PMSTATE_MIGRATED 0x3 2953 #define HERMON_QP_PMSTATE_ARMED 0x0 2954 #define HERMON_QP_PMSTATE_REARM 0x1 2955 2956 #define HERMON_QP_DESC_EVT_DISABLED 0x0 2957 #define HERMON_QP_DESC_EVT_ENABLED 0x1 2958 2959 #define HERMON_QP_FLIGHT_LIM_UNLIMITED 0xF 2960 2961 #define HERMON_QP_SQ_ALL_SIGNALED 0x1 2962 #define HERMON_QP_SQ_WR_SIGNALED 0x0 2963 #define HERMON_QP_RQ_ALL_SIGNALED 0x1 2964 #define HERMON_QP_RQ_WR_SIGNALED 0x0 2965 2966 #define HERMON_QP_SRQ_ENABLED 0x1 2967 #define HERMON_QP_SRQ_DISABLED 0x0 2968 2969 #define HERMON_QP_WQE_BASE_SHIFT 0x6 2970 2971 /* 2972 * Hermon Multicast Group Member (MCG) 2973 * Hermon MCG are organized in a virtually-contiguous memory table (the 2974 * Multicast Group Table) in the ICM. This table is 2975 * actually comprised of two consecutive tables: the Multicast Group Hash 2976 * Table (MGHT) and the Additional Multicast Group Members Table (AMGM). 2977 * Each such entry contains an MGID and a list of QPs that are attached to 2978 * the multicast group. Each such entry may also include an index to an 2979 * Additional Multicast Group Member Table (AMGM) entry. The AMGMs are 2980 * used to form a linked list of MCG entries that all map to the same hash 2981 * value. The MCG entry size is configured through the INIT_HCA command. 2982 * Note: An MCG actually consists of a single hermon_hw_mcg_t and some 2983 * number of hermon_hw_mcg_qp_list_t (such that the combined structure is a 2984 * power-of-2). 2985 * 2986 * The following structures are used in the READ_MGM and WRITE_MGM commands. 2987 * The READ_MGM command reads an MCG entry from the multicast table and 2988 * returns it in the output mailbox. Note: This operation does not affect 2989 * the MCG entry state or values. 2990 * The WRITE_MGM command retrieves an MCG entry from the input mailbox and 2991 * stores it in the multicast group table at the index specified in the 2992 * command. Once the command has finished execution, the multicast group 2993 * table is updated. The old entry contents are lost. 2994 */ 2995 #ifdef _LITTLE_ENDIAN 2996 struct hermon_hw_mcg_s { 2997 uint32_t member_cnt :24; 2998 uint32_t :8; 2999 3000 uint32_t :6; 3001 uint32_t next_gid_indx :26; 3002 3003 uint32_t :32; 3004 uint32_t :32; 3005 3006 uint64_t mgid_h; 3007 uint64_t mgid_l; 3008 }; 3009 #else 3010 struct hermon_hw_mcg_s { 3011 uint32_t next_gid_indx :26; 3012 uint32_t :6; 3013 3014 uint32_t :8; 3015 uint32_t member_cnt :24; 3016 3017 uint32_t :32; 3018 uint32_t :32; 3019 3020 uint64_t mgid_h; 3021 uint64_t mgid_l; 3022 }; 3023 #endif 3024 3025 3026 /* Multicast Group Member - QP List entries */ 3027 #ifdef _LITTLE_ENDIAN 3028 struct hermon_hw_mcg_qp_list_s { 3029 uint32_t qpn :24; 3030 uint32_t :6; 3031 uint32_t blk_lb :1; 3032 uint32_t :1; 3033 }; 3034 #else 3035 struct hermon_hw_mcg_qp_list_s { 3036 uint32_t :1; 3037 uint32_t blk_lb :1; 3038 uint32_t :6; 3039 uint32_t qpn :24; 3040 }; 3041 #endif 3042 3043 #define HERMON_MCG_QPN_BLOCK_LB 0x40000000 3044 3045 /* 3046 * Structure for getting the peformance counters from the HCA 3047 */ 3048 3049 #ifdef _LITTLE_ENDIAN 3050 struct hermon_hw_sm_perfcntr_s { 3051 uint32_t linkdown :8; 3052 uint32_t linkerrrec :8; 3053 uint32_t symerr :16; 3054 3055 uint32_t cntrsel :16; 3056 uint32_t portsel :8; 3057 uint32_t :8; 3058 3059 uint32_t portxmdiscard :16; 3060 uint32_t portrcvswrelay :16; 3061 3062 uint32_t portrcvrem :16; 3063 uint32_t portrcv :16; 3064 3065 uint32_t vl15drop :16; 3066 uint32_t :16; 3067 3068 uint32_t xsbuffovrun :4; 3069 uint32_t locallinkint :4; 3070 uint32_t :8; 3071 uint32_t portrcconstr :8; 3072 uint32_t portxmconstr :8; 3073 3074 uint32_t portrcdata; 3075 3076 uint32_t portxmdata; 3077 3078 uint32_t portrcpkts; 3079 3080 uint32_t portxmpkts; 3081 3082 uint32_t reserved; 3083 3084 uint32_t portxmwait; 3085 }; 3086 #else /* BIG ENDIAN */ 3087 struct hermon_hw_sm_perfcntr_s { 3088 uint32_t :8; 3089 uint32_t portsel :8; 3090 uint32_t cntrsel :16; 3091 3092 uint32_t symerr :16; 3093 uint32_t linkerrrec :8; 3094 uint32_t linkdown :8; 3095 3096 uint32_t portrcv :16; 3097 uint32_t portrcvrem :16; 3098 3099 uint32_t portrcvswrelay :16; 3100 uint32_t portxmdiscard :16; 3101 3102 uint32_t portxmconstr :8; 3103 uint32_t portrcconstr :8; 3104 uint32_t :8; 3105 uint32_t locallinkint :4; 3106 uint32_t xsbuffovrun :4; 3107 3108 uint32_t :16; 3109 uint32_t vl15drop :16; 3110 3111 uint32_t portxmdata; 3112 3113 uint32_t portrcdata; 3114 3115 uint32_t portxmpkts; 3116 3117 uint32_t portrcpkts; 3118 3119 uint32_t portxmwait; 3120 3121 uint32_t reserved; 3122 }; 3123 #endif 3124 3125 /* 3126 * Structure for getting the extended peformance counters from the HCA 3127 */ 3128 3129 #ifdef _LITTLE_ENDIAN 3130 struct hermon_hw_sm_extperfcntr_s { 3131 uint32_t rsvd; 3132 uint32_t cntrsel :16; 3133 uint32_t portsel :8; 3134 uint32_t :8; 3135 3136 uint64_t portxmdata; 3137 3138 uint64_t portrcdata; 3139 3140 uint64_t portxmpkts; 3141 3142 uint64_t portrcpkts; 3143 3144 uint64_t portunicastxmpkts; 3145 3146 uint64_t portunicastrcpkts; 3147 3148 uint64_t portmulticastxmpkts; 3149 3150 uint64_t portmulticastrcpkts; 3151 }; 3152 #else /* BIG ENDIAN */ 3153 struct hermon_hw_sm_extperfcntr_s { 3154 uint32_t :8; 3155 uint32_t portsel :8; 3156 uint32_t cntrsel :16; 3157 uint32_t rsvd; 3158 3159 uint64_t portxmdata; 3160 3161 uint64_t portrcdata; 3162 3163 uint64_t portxmpkts; 3164 3165 uint64_t portrcpkts; 3166 3167 uint64_t portunicastxmpkts; 3168 3169 uint64_t portunicastrcpkts; 3170 3171 uint64_t portmulticastxmpkts; 3172 3173 uint64_t portmulticastrcpkts; 3174 }; 3175 #endif 3176 3177 3178 /* 3179 * Hermon User Access Region (UAR) 3180 * 3181 * JBDB : writeup on the UAR for memfree 3182 * 3183 * JBDB : writeup on the structures 3184 * UAR page 3185 * DB register 3186 * DB record 3187 * UCE 3188 * 3189 * [es] and change it even further for hermon 3190 * the whole UAR and doorbell record (dbr) approach is changed again 3191 * from arbel, and needs commenting 3192 * 3193 * -- Tavor comment 3194 * 3195 * 3196 * Tavor doorbells are each rung by writing to the doorbell registers that 3197 * form a User Access Region (UAR). A doorbell is a write-only hardware 3198 * register which enables passing information from software to hardware 3199 * with minimum software latency. A write operation from the host software 3200 * to these doorbell registers passes information about the HCA resources 3201 * and initiates processing of the doorbell data. There are 6 types of 3202 * doorbells in Tavor. 3203 * 3204 * "Send Doorbell" for synchronizing the attachment of a WQE (or a chain 3205 * of WQEs) to the send queue. 3206 * "RD Send Doorbell" (Same as above, except for RD QPs) is not supported. 3207 * "Receive Doorbell" for synchronizing the attachment of a WQE (or a chain 3208 * of WQEs) to the receive queue. 3209 * "CQ Doorbell" for updating the CQ consumer index and requesting 3210 * completion notifications. 3211 * "EQ Doorbell" for updating the EQ consumer index, arming interrupt 3212 * triggering, and disarming CQ notification requests. 3213 * "InfiniBlast" (which would have enabled access to the "InfiniBlast 3214 * buffer") is not supported. 3215 * 3216 * Note: The tavor_hw_uar_t below is the container for all of the various 3217 * doorbell types. Below we first define several structures which make up 3218 * the contents of those doorbell types. 3219 * 3220 * Note also: The following structures are not #define'd with both little- 3221 * endian and big-endian definitions. This is because each doorbell type 3222 * is not directly accessed except through a single ddi_put64() operation 3223 * (see tavor_qp_send_doorbell, tavor_qp_recv_doorbell, tavor_cq_doorbell, 3224 * or tavor_eq_doorbell) 3225 */ 3226 3227 /* 3228 * Send doorbell register structure 3229 */ 3230 typedef struct hermon_hw_send_db_reg_s { 3231 uint32_t :32; 3232 3233 uint32_t snd_q_num :24; 3234 uint32_t :8; 3235 } hermon_hw_send_db_reg_t; 3236 3237 #define HERMON_QPSNDDB_QPN_SHIFT 0x8 3238 3239 /* Max descriptors per Hermon doorbell */ 3240 #define HERMON_QP_MAXDESC_PER_DB 256 3241 3242 /* 3243 * CQ doorbell register structure 3244 */ 3245 typedef struct hermon_hw_cq_db_reg_s { 3246 uint32_t :2; 3247 uint32_t cmd_sn :2; 3248 uint32_t :2; 3249 uint32_t cmd :2; 3250 uint32_t cqn :24; 3251 3252 uint32_t :8; 3253 /* consumer cntr of last polled completion */ 3254 uint32_t cq_ci :24; 3255 } hermon_hw_cq_db_reg_t; 3256 3257 #define HERMON_CQDB_CMD_SHIFT 0x18 /* dec 24 */ 3258 #define HERMON_CQDB_CMDSN_SHIFT 0x1C /* dec 28 */ 3259 3260 3261 #define HERMON_CQDB_NOTIFY_CQ 0x02 3262 #define HERMON_CQDB_NOTIFY_CQ_SOLICIT 0x01 3263 3264 /* Default value for use in NOTIFY_CQ doorbell */ 3265 #define HERMON_CQDB_DEFAULT_PARAM 0xFFFFFFFF 3266 3267 typedef struct hermon_hw_guest_eq_ci_s { /* guest op eq consumer index */ 3268 uint32_t armed :1; 3269 uint32_t :7; 3270 uint32_t guestos_ci :24; 3271 3272 uint32_t :32; 3273 } hermon_hw_guest_eq_ci_t; 3274 3275 3276 3277 /* 3278 * UAR page structure, containing all doorbell registers 3279 */ 3280 struct hermon_hw_uar_s { 3281 uint32_t rsrv0[4]; 3282 3283 hermon_hw_send_db_reg_t send; 3284 3285 uint32_t rsrv1[2]; 3286 3287 hermon_hw_cq_db_reg_t cq; 3288 3289 uint32_t rsrv2[502]; /* next is at offset 0x800 */ 3290 3291 hermon_hw_guest_eq_ci_t g_eq0; 3292 hermon_hw_guest_eq_ci_t g_eq1; 3293 hermon_hw_guest_eq_ci_t g_eq2; 3294 hermon_hw_guest_eq_ci_t g_eq3; 3295 3296 uint32_t rsrv3[504]; /* end of page */ 3297 }; 3298 3299 /* 3300 * QP (RQ, SRQ) doorbell record-specific data 3301 * Note that this structure is NOT in ICM, but just kept in host memory 3302 * and managed independently of PRM or other constraints. Also, though 3303 * the qp/srq doorbell need to be only 4 bytes, it is 8 bytes in memory for 3304 * ease of management. Hermon defines its usage in the QP chapter. 3305 */ 3306 typedef struct hermon_hw_qp_db_s { 3307 uint32_t :16; 3308 uint32_t rcv_wqe_cntr :16; /* wqe_counter */ 3309 3310 uint32_t :32; 3311 } hermon_hw_qp_db_t; 3312 3313 /* 3314 * CQ (ARM and SET_CI) doorbell record-specific data 3315 * See comment above re: QP doorbell. This dbr is 8 bytes long, and its 3316 * usage is defined in PRM chapter on Completion Queues 3317 */ 3318 typedef struct hermon_hw_cq_arm_db_s { 3319 uint32_t :8; 3320 uint32_t update_ci :24; 3321 3322 uint32_t :2; 3323 /* sequence number of the doorbell ring % 4 */ 3324 uint32_t cmd_sn :2; 3325 uint32_t :1; 3326 uint32_t cmd :3; /* command */ 3327 uint32_t cq_ci :24; 3328 } hermon_hw_cq_db_t; 3329 3330 #define HERMON_CQ_DB_CMD_SOLICTED 0x01 3331 #define HERMON_CQ_DB_CMD_NEXT 0x02 3332 3333 3334 /* 3335 * Hermon Blue Flame (BF) 3336 * Hermon has the ability to do a low-latency write of successive WQEs 3337 * for the HCA. This utilizes part of the memory area behind the 3338 * same BAR as the UAR page (see above) - half the area is devoted to 3339 * UAR pages, the other half to BlueFlame (though in fairness, the return 3340 * information from QUERY_DEV_CAP should be consulted _in case_ they ever 3341 * decide to change it. 3342 * 3343 * We define the structures to access them below. 3344 */ 3345 3346 3347 /* 3348 * Hermon Send Work Queue Element (WQE) 3349 * A Hermon Send WQE is built of the following segments, each of which is a 3350 * multiple of 16 bytes. Note: Each individual WQE may contain only a 3351 * subset of these segments described below (according to the operation type 3352 * and transport type of the QP). 3353 * 3354 * The first 16 bytes of ever WQE are formed from the "Ctrl" segment. 3355 * This segment contains the address of the next WQE to be executed and the 3356 * information required in order to allocate the resources to execute the 3357 * next WQE. The "Ctrl" part of this segment contains the control 3358 * information required to execute the WQE, including the opcode and other 3359 * control information. 3360 * The "Datagram" segment contains address information required in order to 3361 * form a UD message. 3362 * The "Bind" segment contains the parameters required for a Bind Memory 3363 * Window operation. 3364 * The "Remote Address" segment is present only in RDMA or Atomic WQEs and 3365 * specifies remote virtual addresses and RKey, respectively. Length of 3366 * the remote access is calculated from the scatter/gather list (for 3367 * RDMA-write/RDMA-read) or set to eight (for Atomic). 3368 * The "Atomic" segment is present only in Atomic WQEs and specifies 3369 * Swap/Add and Compare data. 3370 * 3371 * Note: The following structures are not #define'd with both little-endian 3372 * and big-endian definitions. This is because their individual fields are 3373 * not directly accessed except through macros defined below. 3374 */ 3375 3376 3377 struct hermon_hw_snd_wqe_ctrl_s { 3378 uint32_t owner :1; 3379 /* NOTE: some/many may be used by enet */ 3380 uint32_t :26; 3381 uint32_t opcode :5; 3382 /* NOTE: some will be used by enet */ 3383 uint32_t :25; 3384 uint32_t fence :1; 3385 /* WQE size in octowords */ 3386 uint32_t ds :6; 3387 /* SRC remote buffer if impl */ 3388 uint32_t src_rem_buf :24; 3389 uint32_t so :1; 3390 uint32_t :1; /* FCoIB only */ 3391 uint32_t tcp_udp :1; /* Checksumming */ 3392 uint32_t ip :1; /* Checksumming */ 3393 uint32_t cq_gen :2; /* 00=no cqe, 11= gen cqe */ 3394 /* set means solicit bit in last packet */ 3395 uint32_t s :1; 3396 uint32_t force_lb :1; 3397 3398 uint32_t immediate :32; 3399 }; 3400 3401 struct hermon_hw_srq_wqe_next_s { 3402 uint32_t :16; 3403 uint32_t next_wqe_idx :16; 3404 3405 uint32_t rsvd[3]; 3406 }; 3407 3408 3409 #define HERMON_WQE_SEND_FENCE_MASK 0x40 3410 3411 #define HERMON_WQE_SEND_NOPCODE_NOP 0x00 3412 #define HERMON_WQE_SEND_NOPCODE_SND_INV 0x01 3413 #define HERMON_WQE_SEND_NOPCODE_RDMAW 0x8 3414 #define HERMON_WQE_SEND_NOPCODE_RDMAWI 0x9 3415 #define HERMON_WQE_SEND_NOPCODE_SEND 0xA 3416 #define HERMON_WQE_SEND_NOPCODE_SENDI 0xB 3417 #define HERMON_WQE_SEND_NOPCODE_LSO 0xE 3418 #define HERMON_WQE_SEND_NOPCODE_RDMAR 0x10 3419 #define HERMON_WQE_SEND_NOPCODE_ATMCS 0x11 3420 #define HERMON_WQE_SEND_NOPCODE_ATMFA 0x12 3421 #define HERMON_WQE_SEND_NOPCODE_ATMCSE 0x14 3422 #define HERMON_WQE_SEND_NOPCODE_ATMFAE 0x15 3423 #define HERMON_WQE_SEND_NOPCODE_BIND 0x18 3424 #define HERMON_WQE_SEND_NOPCODE_FRWR 0x19 3425 #define HERMON_WQE_SEND_NOPCODE_LCL_INV 0x1B 3426 #define HERMON_WQE_SEND_NOPCODE_CONFIG 0x1F /* for ccq only */ 3427 3428 #define HERMON_WQE_SEND_SIGNALED_MASK 0x0000000C00000000ull 3429 #define HERMON_WQE_SEND_SOLICIT_MASK 0x0000000200000000ull 3430 #define HERMON_WQE_SEND_IMMEDIATE_MASK 0x0000000100000000ull 3431 3432 struct hermon_hw_snd_wqe_ud_s { 3433 struct hermon_hw_udav_s ud_addr_v; 3434 3435 uint32_t :8; 3436 uint32_t dest_qp :24; 3437 uint32_t qkey :32; 3438 uint32_t :32; 3439 uint32_t :32; 3440 }; 3441 #define HERMON_WQE_SENDHDR_UD_AV_MASK 0xFFFFFFFFFFFFFFE0ull 3442 #define HERMON_WQE_SENDHDR_UD_DQPN_MASK 0xFFFFFF 3443 3444 struct hermon_hw_snd_wqe_bind_s { 3445 uint32_t ae :1; 3446 uint32_t rw :1; 3447 uint32_t rr :1; 3448 uint32_t :3; 3449 uint32_t l_64 :1; 3450 uint32_t :25; 3451 3452 uint32_t win_t :1; 3453 uint32_t z_base :1; 3454 uint32_t :30; 3455 3456 uint32_t new_rkey; 3457 uint32_t reg_lkey; 3458 uint64_t addr; 3459 uint64_t len; 3460 }; 3461 #define HERMON_WQE_SENDHDR_BIND_ATOM 0x8000000000000000ull 3462 #define HERMON_WQE_SENDHDR_BIND_WR 0x4000000000000000ull 3463 #define HERMON_WQE_SENDHDR_BIND_RD 0x2000000000000000ull 3464 3465 struct hermon_hw_snd_wqe_remaddr_s { 3466 uint64_t vaddr; 3467 uint32_t rkey; 3468 uint32_t :32; 3469 }; 3470 3471 struct hermon_hw_snd_wqe_atomic_s { 3472 uint64_t swap_add; 3473 uint64_t compare; 3474 }; 3475 3476 struct hermon_hw_snd_wqe_atomic_ext_s { 3477 uint64_t swap_add; 3478 uint64_t compare; 3479 uint64_t swapmask; 3480 uint64_t cmpmask; 3481 }; 3482 3483 3484 3485 struct hermon_hw_snd_wqe_local_inv_s { 3486 uint32_t :6; 3487 uint32_t atc_shoot :1; 3488 uint32_t :25; 3489 3490 uint32_t :32; 3491 3492 uint32_t mkey; 3493 3494 uint32_t :25; 3495 uint32_t guest_id :7; /* for atc shootdown */ 3496 3497 uint32_t rsrv0[6]; 3498 3499 uint32_t p_addrh; 3500 uint32_t p_addrl :23; 3501 uint32_t :9; 3502 }; 3503 3504 struct hermon_hw_snd_wqe_frwr_s { 3505 uint32_t rem_atomic :1; 3506 uint32_t rem_write :1; 3507 uint32_t rem_read :1; 3508 uint32_t loc_write :1; 3509 uint32_t loc_read :1; 3510 uint32_t fbo_en :1; 3511 uint32_t len_64 :1; 3512 uint32_t :3; /* but some for FCoIB */ 3513 uint32_t bind_en :1; 3514 uint32_t blk_pg_mode :1; 3515 uint32_t mtt_rep :4; 3516 uint32_t :16; 3517 3518 uint32_t mkey; /* swapped w/ addrh relative to arbel */ 3519 3520 uint32_t pbl_addrh; 3521 3522 uint32_t pbl_addrl :26; 3523 uint32_t :6; 3524 3525 uint64_t start_addr; 3526 3527 uint64_t reg_len; /* w/ len_64 allows 65 bits of length */ 3528 3529 uint32_t :11; 3530 uint32_t fbo :21; 3531 3532 uint32_t :11; 3533 uint32_t pge_blk_sz :21; 3534 3535 uint32_t rsrv0[2]; 3536 }; 3537 3538 /* 3539 * NOTE: Some hermon-PRM defined Send WQE segments are not defined here 3540 * because they will not be used initially: they should be added and 3541 * used later on: 3542 * FCP-3 init 3543 * FCP-3 Control 3544 * Large Send Offload 3545 * 3546 */ 3547 3548 /* 3549 * Hermon "MLX transport" Work Queue Element (WQE) 3550 * The format of the MLX WQE is similar to that of the Send WQE (above) 3551 * with the following exceptions. MLX WQEs are used for sending MADs on 3552 * special QPs 0 and 1. Everything following the "Next/Ctrl" header 3553 * (defined below) consists of scatter-gather list entries. The contents 3554 * of these SGLs (also defined below) will be put on the wire exactly as 3555 * they appear in the buffers. In addition, the VCRC and the ICRC of each 3556 * sent packet can be modified by changing values in the following header 3557 * or in the payload of the packet itself. 3558 */ 3559 3560 3561 struct hermon_hw_mlx_wqe_nextctrl_s { 3562 uint32_t owner :1; 3563 uint32_t :23; 3564 uint32_t :3; 3565 uint32_t opcode :5; /* is 0x0A (send) for MLX */ 3566 3567 uint32_t :26; 3568 uint32_t ds :6; /* WQE size in octowords */ 3569 3570 uint32_t :14; 3571 uint32_t vl15 :1; 3572 uint32_t slr :1; 3573 uint32_t max_srate :4; 3574 uint32_t sl :4; 3575 uint32_t :3; /* FCoIB usage */ 3576 uint32_t icrc :1; /* 1==don't replace icrc fld */ 3577 uint32_t cq_gen :2; /* 00= no cqe, 11==cqe */ 3578 uint32_t :1; 3579 uint32_t force_lb :1; 3580 3581 uint32_t rlid :16; 3582 uint32_t :16; 3583 }; 3584 3585 3586 #define HERMON_WQE_MLXHDR_VL15_MASK 0x0002000000000000ull 3587 #define HERMON_WQE_MLXHDR_SLR_MASK 0x0001000000000000ull 3588 #define HERMON_WQE_MLXHDR_SRATE_SHIFT 44 3589 #define HERMON_WQE_MLXHDR_SL_SHIFT 40 3590 #define HERMON_WQE_MLXHDR_SIGNALED_MASK 0x0000000800000000ull 3591 #define HERMON_WQE_MLXHDR_RLID_SHIFT 16 3592 3593 3594 /* 3595 * Hermon Receive Work Queue Element (WQE) 3596 * Unlike the Send WQE, the Receive WQE is built ONLY of 16-byte segments. A 3597 * "Next/Ctrl" segment is no longer needed, because of the fixed 3598 * receive queue stride (RQ.STRIDE). It contains just 3599 * some number of scatter list entries for the incoming message. 3600 * 3601 * The format of the scatter-gather list entries is shown below. For 3602 * Receive WQEs the "inline_data" field must be cleared (i.e. data segments 3603 * cannot contain inline data). 3604 */ 3605 3606 3607 struct hermon_hw_wqe_sgl_s { 3608 uint32_t inline_data :1; 3609 uint32_t byte_cnt :31; 3610 3611 uint32_t lkey; 3612 3613 uint64_t addr; 3614 }; 3615 #define HERMON_WQE_SGL_BYTE_CNT_MASK 0x7FFFFFFF 3616 #define HERMON_WQE_SGL_INLINE_MASK 0x80000000 3617 3618 /* 3619 * The following defines are used when building descriptors for special QP 3620 * work requests (i.e. MLX transport WQEs). Note: Because Hermon MLX transport 3621 * requires the driver to build actual IB packet headers, we use these defines 3622 * for the most common fields in those headers. 3623 */ 3624 3625 3626 #define HERMON_MLX_VL15_LVER 0xF0000000 3627 #define HERMON_MLX_VL0_LVER 0x00000000 3628 #define HERMON_MLX_IPVER_TC_FLOW 0x60000000 3629 #define HERMON_MLX_TC_SHIFT 20 3630 #define HERMON_MLX_DEF_PKEY 0xFFFF 3631 #define HERMON_MLX_GSI_QKEY 0x80010000 3632 #define HERMON_MLX_UDSEND_OPCODE 0x64000000 3633 #define HERMON_MLX_DQPN_MASK 0xFFFFFF 3634 3635 /* 3636 * The following macros are used for building each of the individual 3637 * segments that can make up a Hermon WQE. Note: We try not to use the 3638 * structures (with their associated bitfields) here, instead opting to 3639 * build and put 64-bit or 32-bit chunks to the WQEs as appropriate, 3640 * primarily because using the bitfields appears to force more read-modify- 3641 * write operations. 3642 * 3643 * HERMON_WQE_BUILD_UD - Builds Unreliable Datagram Segment 3644 * 3645 * HERMON_WQE_BUILD_REMADDR - Builds Remote Address Segment using 3646 * RDMA info from the work request 3647 * HERMON_WQE_BUILD_RC_ATOMIC_REMADDR - Builds Remote Address Segment 3648 * for RC Atomic work requests 3649 * HERMON_WQE_BUILD_ATOMIC - Builds Atomic Segment using atomic 3650 * info from the work request 3651 * HERMON_WQE_BUILD_BIND - Builds the Bind Memory Window 3652 * Segment using bind info from the 3653 * work request 3654 * HERMON_WQE_BUILD_DATA_SEG - Builds the individual Data Segments 3655 * for Send, Receive, and MLX WQEs 3656 * HERMON_WQE_BUILD_INLINE - Builds an "inline" Data Segment 3657 * (primarily for MLX transport) 3658 * HERMON_WQE_BUILD_INLINE_ICRC - Also builds an "inline" Data Segment 3659 * (but used primarily in the ICRC 3660 * portion of MLX transport WQEs) 3661 * HERMON_WQE_LINKNEXT - Links the current WQE to the 3662 * previous one 3663 * HERMON_WQE_LINKFIRST - Links the first WQE on the current 3664 * chain to the previous WQE 3665 * HERMON_WQE_BUILD_MLX_LRH - Builds the inline LRH header for 3666 * MLX transport MADs 3667 * HERMON_WQE_BUILD_MLX_GRH - Builds the inline GRH header for 3668 * MLX transport MADs 3669 * HERMON_WQE_BUILD_MLX_BTH - Builds the inline BTH header for 3670 * MLX transport MADs 3671 * HERMON_WQE_BUILD_MLX_DETH - Builds the inline DETH header for 3672 * MLX transport MADs 3673 */ 3674 #define HERMON_WQE_BUILD_UD(qp, ud, ah, dest) \ 3675 { \ 3676 uint64_t *tmp; \ 3677 uint64_t *udav; \ 3678 \ 3679 tmp = (uint64_t *)(ud); \ 3680 udav = (uint64_t *)(ah)->ah_udav; \ 3681 tmp[0] = ntohll(udav[0]); \ 3682 tmp[1] = ntohll(udav[1]); \ 3683 tmp[2] = ntohll(udav[2]); \ 3684 tmp[3] = ntohll(udav[3]); \ 3685 tmp[4] = ntohll((((uint64_t)((dest)->ud_dst_qpn & \ 3686 HERMON_WQE_SENDHDR_UD_DQPN_MASK) << 32) | \ 3687 (dest)->ud_qkey)); \ 3688 tmp[5] = 0; \ 3689 } 3690 3691 #define HERMON_WQE_BUILD_LSO(qp, ds, mss, hdr_sz) \ 3692 *(uint32_t *)(ds) = htonl(((mss) << 16) | hdr_sz); 3693 3694 #define HERMON_WQE_BUILD_REMADDR(qp, ra, wr_rdma) \ 3695 { \ 3696 uint64_t *tmp; \ 3697 \ 3698 tmp = (uint64_t *)(ra); \ 3699 tmp[0] = htonll((wr_rdma)->rdma_raddr); \ 3700 tmp[1] = htonll((uint64_t)(wr_rdma)->rdma_rkey << 32); \ 3701 } 3702 3703 #define HERMON_WQE_BUILD_RC_ATOMIC_REMADDR(qp, rc, wr) \ 3704 { \ 3705 uint64_t *tmp; \ 3706 \ 3707 tmp = (uint64_t *)(rc); \ 3708 tmp[0] = htonll((wr)->wr.rc.rcwr.atomic->atom_raddr); \ 3709 tmp[1] = htonll((uint64_t)(wr)->wr.rc.rcwr.atomic->atom_rkey << 32); \ 3710 } 3711 3712 #define HERMON_WQE_BUILD_ATOMIC(qp, at, wr_atom) \ 3713 { \ 3714 uint64_t *tmp; \ 3715 \ 3716 tmp = (uint64_t *)(at); \ 3717 tmp[0] = htonll((wr_atom)->atom_arg2); \ 3718 tmp[1] = htonll((wr_atom)->atom_arg1); \ 3719 } 3720 3721 #define HERMON_WQE_BUILD_BIND(qp, bn, wr_bind) \ 3722 { \ 3723 uint64_t *tmp; \ 3724 uint64_t bn0_tmp; \ 3725 ibt_bind_flags_t bind_flags; \ 3726 \ 3727 tmp = (uint64_t *)(bn); \ 3728 bind_flags = (wr_bind)->bind_flags; \ 3729 bn0_tmp = (bind_flags & IBT_WR_BIND_ATOMIC) ? \ 3730 HERMON_WQE_SENDHDR_BIND_ATOM : 0; \ 3731 bn0_tmp |= (bind_flags & IBT_WR_BIND_WRITE) ? \ 3732 HERMON_WQE_SENDHDR_BIND_WR : 0; \ 3733 bn0_tmp |= (bind_flags & IBT_WR_BIND_READ) ? \ 3734 HERMON_WQE_SENDHDR_BIND_RD : 0; \ 3735 tmp[0] = htonll(bn0_tmp); \ 3736 tmp[1] = htonll(((uint64_t)(wr_bind)->bind_rkey_out << 32) | \ 3737 (wr_bind)->bind_lkey); \ 3738 tmp[2] = htonll((wr_bind)->bind_va); \ 3739 tmp[3] = htonll((wr_bind)->bind_len); \ 3740 } 3741 3742 #define HERMON_WQE_BUILD_DATA_SEG_RECV(ds, sgl) \ 3743 { \ 3744 uint64_t *tmp; \ 3745 \ 3746 tmp = (uint64_t *)(ds); \ 3747 tmp[0] = htonll((((uint64_t)((sgl)->ds_len & \ 3748 HERMON_WQE_SGL_BYTE_CNT_MASK) << 32) | (sgl)->ds_key)); \ 3749 tmp[1] = htonll((sgl)->ds_va); \ 3750 } 3751 #define HERMON_WQE_BUILD_DATA_SEG_SEND(ds, sgl) \ 3752 { \ 3753 ((uint64_t *)(ds))[1] = htonll((sgl)->ds_va); \ 3754 ((uint32_t *)(ds))[1] = htonl((sgl)->ds_key); \ 3755 membar_producer(); \ 3756 ((uint32_t *)(ds))[0] = \ 3757 htonl((sgl)->ds_len & HERMON_WQE_SGL_BYTE_CNT_MASK); \ 3758 } 3759 3760 #define HERMON_WQE_BUILD_INLINE(qp, ds, sz) \ 3761 *(uint32_t *)(ds) = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz)) 3762 3763 #define HERMON_WQE_BUILD_INLINE_ICRC(qp, ds, sz, icrc) \ 3764 { \ 3765 uint32_t *tmp; \ 3766 \ 3767 tmp = (uint32_t *)(ds); \ 3768 tmp[0] = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz)); \ 3769 tmp[1] = htonl(icrc); \ 3770 } 3771 3772 #define HERMON_WQE_SET_CTRL_SEGMENT(desc, desc_sz, fence, \ 3773 imm, sol, sig, ip_cksum, qp) \ 3774 { \ 3775 uint32_t *tmp; \ 3776 uint32_t cntr_tmp; \ 3777 \ 3778 /* do not set the first dword (owner/opcode) here */ \ 3779 tmp = (uint32_t *)desc; \ 3780 cntr_tmp = (fence << 6) | desc_sz; \ 3781 tmp[1] = ntohl(cntr_tmp); \ 3782 cntr_tmp = 0; \ 3783 if ((sol) != 0) cntr_tmp |= 0x02; \ 3784 if ((sig) != 0) cntr_tmp |= 0x0C; \ 3785 /*LINTED*/ \ 3786 if (ip_cksum) cntr_tmp |= 0x30; \ 3787 tmp[2] = ntohl(cntr_tmp); \ 3788 tmp[3] = ntohl(imm); \ 3789 } 3790 3791 #define HERMON_WQE_SET_MLX_CTRL_SEGMENT(desc, desc_sz, sig, maxstat, \ 3792 lid, qp, sl) \ 3793 { \ 3794 uint32_t *tmp; \ 3795 uint32_t cntr_tmp; \ 3796 \ 3797 tmp = (uint32_t *)desc; \ 3798 cntr_tmp = htonl(tmp[0]); \ 3799 cntr_tmp &= 0x80000000; \ 3800 cntr_tmp |= HERMON_WQE_SEND_NOPCODE_SEND; \ 3801 tmp[0] = ntohl(cntr_tmp); \ 3802 tmp[1] = ntohl(desc_sz); \ 3803 cntr_tmp = ((maxstat << 4) | (sl & 0xff)) << 8; \ 3804 if (qp->qp_is_special == HERMON_QP_SMI) \ 3805 cntr_tmp |= (0x02 << 16); \ 3806 if (lid == IB_LID_PERMISSIVE) \ 3807 cntr_tmp |= (0x01 << 16); \ 3808 if ((sig) != 0) \ 3809 cntr_tmp |= 0xC; \ 3810 tmp[2] = ntohl(cntr_tmp); \ 3811 tmp[3] = ntohl((lid) << 16); \ 3812 } 3813 3814 #define HERMON_WQE_BUILD_MLX_LRH(lrh, qp, udav, pktlen) \ 3815 { \ 3816 uint32_t *tmp; \ 3817 uint32_t lrh_tmp; \ 3818 \ 3819 tmp = (uint32_t *)(void *)(lrh); \ 3820 \ 3821 if ((qp)->qp_is_special == HERMON_QP_SMI) { \ 3822 lrh_tmp = HERMON_MLX_VL15_LVER; \ 3823 } else { \ 3824 lrh_tmp = HERMON_MLX_VL0_LVER | ((udav)->sl << 20); \ 3825 } \ 3826 if ((udav)->grh) { \ 3827 lrh_tmp |= (IB_LRH_NEXT_HDR_GRH << 16); \ 3828 } else { \ 3829 lrh_tmp |= (IB_LRH_NEXT_HDR_BTH << 16); \ 3830 } \ 3831 lrh_tmp |= (udav)->rlid; \ 3832 tmp[0] = htonl(lrh_tmp); \ 3833 \ 3834 lrh_tmp = (pktlen) << 16; \ 3835 if ((udav)->rlid == IB_LID_PERMISSIVE) { \ 3836 lrh_tmp |= IB_LID_PERMISSIVE; \ 3837 } else { \ 3838 lrh_tmp |= (udav)->ml_path; \ 3839 } \ 3840 tmp[1] = htonl(lrh_tmp); \ 3841 } 3842 3843 /* 3844 * Note: The GRH payload length, calculated below, is the overall packet 3845 * length (in bytes) minus LRH header and GRH headers. 3846 * 3847 * Also note: Filling in the GIDs in the way we do below is helpful because 3848 * it avoids potential alignment restrictions and/or conflicts. 3849 */ 3850 #define HERMON_WQE_BUILD_MLX_GRH(state, grh, qp, udav, pktlen) \ 3851 { \ 3852 uint32_t *tmp; \ 3853 uint32_t grh_tmp; \ 3854 ib_gid_t sgid; \ 3855 \ 3856 tmp = (uint32_t *)(grh); \ 3857 \ 3858 grh_tmp = HERMON_MLX_IPVER_TC_FLOW; \ 3859 grh_tmp |= (udav)->tclass << HERMON_MLX_TC_SHIFT; \ 3860 grh_tmp |= (udav)->flow_label; \ 3861 tmp[0] = htonl(grh_tmp); \ 3862 \ 3863 grh_tmp = (((pktlen) << 2) - (sizeof (ib_lrh_hdr_t) + \ 3864 sizeof (ib_grh_t))) << 16; \ 3865 grh_tmp |= (IB_GRH_NEXT_HDR_BTH << 8); \ 3866 grh_tmp |= (udav)->hop_limit; \ 3867 tmp[1] = htonl(grh_tmp); \ 3868 \ 3869 sgid.gid_prefix = (state)->hs_sn_prefix[(qp)->qp_portnum]; \ 3870 sgid.gid_guid = (state)->hs_guid[(qp)->qp_portnum] \ 3871 [(udav)->mgid_index]; \ 3872 bcopy(&sgid, &tmp[2], sizeof (ib_gid_t)); \ 3873 bcopy(&(udav)->rgid_h, &tmp[6], sizeof (ib_gid_t)); \ 3874 } 3875 3876 #define HERMON_WQE_BUILD_MLX_BTH(state, bth, qp, wr) \ 3877 { \ 3878 uint32_t *tmp; \ 3879 uint32_t bth_tmp; \ 3880 \ 3881 tmp = (uint32_t *)(bth); \ 3882 \ 3883 bth_tmp = HERMON_MLX_UDSEND_OPCODE; \ 3884 if ((wr)->wr_flags & IBT_WR_SEND_SOLICIT) { \ 3885 bth_tmp |= (IB_BTH_SOLICITED_EVENT_MASK << 16); \ 3886 } \ 3887 if (qp->qp_is_special == HERMON_QP_SMI) { \ 3888 bth_tmp |= HERMON_MLX_DEF_PKEY; \ 3889 } else { \ 3890 bth_tmp |= (state)->hs_pkey[(qp)->qp_portnum] \ 3891 [(qp)->qp_pkeyindx]; \ 3892 } \ 3893 tmp[0] = htonl(bth_tmp); \ 3894 tmp[1] = htonl((wr)->wr.ud.udwr_dest->ud_dst_qpn & \ 3895 HERMON_MLX_DQPN_MASK); \ 3896 tmp[2] = 0x0; \ 3897 } 3898 3899 #define HERMON_WQE_BUILD_MLX_DETH(deth, qp) \ 3900 { \ 3901 uint32_t *tmp; \ 3902 \ 3903 tmp = (uint32_t *)(deth); \ 3904 \ 3905 if ((qp)->qp_is_special == HERMON_QP_SMI) { \ 3906 tmp[0] = 0x0; \ 3907 tmp[1] = 0x0; \ 3908 } else { \ 3909 tmp[0] = htonl(HERMON_MLX_GSI_QKEY); \ 3910 tmp[1] = htonl(0x1); \ 3911 } \ 3912 } 3913 3914 3915 3916 3917 3918 3919 /* 3920 * Flash interface: 3921 * Below we have PCI config space space offsets for flash interface 3922 * access, offsets within Hermon CR space for accessing flash-specific 3923 * information or settings, masks used for flash settings, and 3924 * timeout values for flash operations. 3925 */ 3926 #define HERMON_HW_FLASH_CFG_HWREV 8 3927 #define HERMON_HW_FLASH_CFG_ADDR 88 3928 #define HERMON_HW_FLASH_CFG_DATA 92 3929 3930 #define HERMON_HW_FLASH_RESET_AMD 0xF0 3931 #define HERMON_HW_FLASH_RESET_INTEL 0xFF 3932 #define HERMON_HW_FLASH_CPUMODE 0xF0150 3933 #define HERMON_HW_FLASH_ADDR 0xF01A4 3934 #define HERMON_HW_FLASH_DATA 0xF01A8 3935 #define HERMON_HW_FLASH_GPIO_SEMA 0xF03FC 3936 #define HERMON_HW_FLASH_WRCONF_SEMA 0xF0380 3937 #define HERMON_HW_FLASH_GPIO_DATA 0xF0040 3938 #define HERMON_HW_FLASH_GPIO_MOD1 0xF004C 3939 #define HERMON_HW_FLASH_GPIO_MOD0 0xF0050 3940 #define HERMON_HW_FLASH_GPIO_DATACLEAR 0xF00D4 3941 #define HERMON_HW_FLASH_GPIO_DATASET 0xF00DC 3942 #define HERMON_HW_FLASH_GPIO_LOCK 0xF0048 3943 #define HERMON_HW_FLASH_GPIO_UNLOCK_VAL 0xD42F 3944 #define HERMON_HW_FLASH_GPIO_PIN_ENABLE 0x1E000000 3945 3946 #define HERMON_HW_FLASH_CPU_MASK 0xC0000000 3947 #define HERMON_HW_FLASH_CPU_SHIFT 30 3948 #define HERMON_HW_FLASH_ADDR_MASK 0x0007FFFC 3949 #define HERMON_HW_FLASH_CMD_MASK 0xE0000000 3950 #define HERMON_HW_FLASH_BANK_MASK 0xFFF80000 3951 3952 #define HERMON_HW_FLASH_SPI_BUSY 0x40000000 3953 #define HERMON_HW_FLASH_SPI_WIP 0x01000000 3954 #define HERMON_HW_FLASH_SPI_READ_OP 0x00000001 3955 #define HERMON_HW_FLASH_SPI_USE_INSTR 0x00000040 3956 #define HERMON_HW_FLASH_SPI_NO_ADDR 0x00000020 3957 #define HERMON_HW_FLASH_SPI_NO_DATA 0x00000010 3958 #define HERMON_HW_FLASH_SPI_TRANS_SZ_4B 0x00000200 3959 3960 #define HERMON_HW_FLASH_SPI_SECTOR_ERASE 0xD8 3961 #define HERMON_HW_FLASH_SPI_READ 0x03 3962 #define HERMON_HW_FLASH_SPI_PAGE_PROGRAM 0x02 3963 #define HERMON_HW_FLASH_SPI_READ_STATUS_REG 0x05 3964 #define HERMON_HW_FLASH_SPI_WRITE_ENABLE 0x06 3965 #define HERMON_HW_FLASH_SPI_READ_ESIGNATURE 0xAB 3966 3967 #define HERMON_HW_FLASH_SPI_GW 0xF0400 3968 #define HERMON_HW_FLASH_SPI_ADDR 0xF0404 3969 #define HERMON_HW_FLASH_SPI_DATA 0xF0410 3970 #define HERMON_HW_FLASH_SPI_DATA4 0xF0414 3971 #define HERMON_HW_FLASH_SPI_DATA8 0xF0418 3972 #define HERMON_HW_FLASH_SPI_DATA12 0xF041C 3973 #define HERMON_HW_FLASH_SPI_ADDR_MASK 0x00FFFFFF 3974 #define HERMON_HW_FLASH_SPI_INSTR_PHASE_OFF 0x04 3975 #define HERMON_HW_FLASH_SPI_ADDR_PHASE_OFF 0x08 3976 #define HERMON_HW_FLASH_SPI_DATA_PHASE_OFF 0x10 3977 #define HERMON_HW_FLASH_SPI_ENABLE_OFF 0x2000 3978 #define HERMON_HW_FLASH_SPI_CS_OFF 0x800 3979 #define HERMON_HW_FLASH_SPI_INSTR_OFF 0x10000 3980 #define HERMON_HW_FLASH_SPI_INSTR_SHIFT 0x10 3981 #define HERMON_HW_FLASH_SPI_BOOT_ADDR_REG 0xF0000 3982 3983 #define HERMON_HW_FLASH_TIMEOUT_WRITE 300 3984 #define HERMON_HW_FLASH_TIMEOUT_ERASE 1000000 3985 #define HERMON_HW_FLASH_TIMEOUT_GPIO_SEMA 1000 3986 #define HERMON_HW_FLASH_TIMEOUT_CONFIG 50 3987 3988 #define HERMON_HW_FLASH_ICS_ERASE 0x20 3989 #define HERMON_HW_FLASH_ICS_ERROR 0x3E 3990 #define HERMON_HW_FLASH_ICS_WRITE 0x40 3991 #define HERMON_HW_FLASH_ICS_STATUS 0x70 3992 #define HERMON_HW_FLASH_ICS_READY 0x80 3993 #define HERMON_HW_FLASH_ICS_CONFIRM 0xD0 3994 #define HERMON_HW_FLASH_ICS_READ 0xFF 3995 3996 #ifdef __cplusplus 3997 } 3998 #endif 3999 4000 #endif /* _SYS_IB_ADAPTERS_HERMON_HW_H */ 4001