1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2008 QLogic Corporation */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _QL_XIOCTL_H 30 #define _QL_XIOCTL_H 31 32 33 /* 34 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 35 * 36 * *********************************************************************** 37 * * ** 38 * * NOTICE ** 39 * * COPYRIGHT (C) 1996-2008 QLOGIC CORPORATION ** 40 * * ALL RIGHTS RESERVED ** 41 * * ** 42 * *********************************************************************** 43 * 44 */ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 #include <exioct.h> 51 52 /* 0xFFFFFA Mgmt Server */ 53 #define MANAGEMENT_SERVER_LOOP_ID 0xfe 54 #define MANAGEMENT_SERVER_24XX_LOOP_ID 0x7ef 55 56 /* Returned Mailbox registers. */ 57 typedef struct ql_mbx_ret { 58 uint16_t mb[MAX_MBOX_COUNT]; 59 } ql_mbx_ret_t; 60 61 /* 62 * Name type defines for use with qla2x00_scsi_passthru() and 63 * elsewhere when searching for name matches. 64 * NOTE that these defines are used both as flags and values. 65 */ 66 #define QLNT_NODE 0x01 67 #define QLNT_PORT 0x02 68 #define QLNT_BOTH (QLNT_NODE | QLNT_PORT) 69 #define QLNT_PID 0x04 70 #define QLNT_LOOP_ID 0x08 71 #define QLNT_MASK 0x0F 72 73 /* 74 * CT information unit basic preamble. 75 */ 76 typedef struct ql_ct_iu_preamble { 77 uint8_t revision; 78 uint8_t in_id[3]; 79 uint8_t gs_type; 80 uint8_t gs_subtype; 81 uint8_t options; 82 uint8_t reserved; 83 uint16_t command_response_code; 84 uint16_t max_residual_size; 85 uint8_t fragment_id; 86 uint8_t reason_code; 87 uint8_t reason_code_explanation; 88 uint8_t vendor_specific; 89 } ql_ct_iu_preamble_t; 90 91 #define GS_TYPE_DIR_SERVER 0xFC 92 93 /* 94 * Link Status Counts structure 95 * 96 * Counts are BIG ENDIAN 97 */ 98 typedef struct ql_link_stats { 99 uint32_t link_fail_cnt; 100 uint32_t sync_loss_cnt; 101 uint32_t signal_loss_cnt; 102 uint32_t prot_err_cnt; /* Primitive seq protocol errors */ 103 uint32_t inv_xmit_cnt; /* Invalid transmission word count */ 104 uint32_t inv_crc_cnt; /* Invalid CRC count */ 105 } ql_link_stats_t; 106 107 /* 108 * Report LUN definitions. 109 */ 110 typedef struct ql_rpt_hdr { 111 uint32_t len; 112 uint32_t rsrv; 113 } ql_rpt_hdr_t; 114 115 typedef struct ql_rpt_lun { 116 struct { 117 uint8_t b : 6; 118 uint8_t address_method : 2; 119 } msb; 120 uint8_t lsb; 121 uint8_t unused[6]; 122 } ql_rpt_lun_t; 123 124 typedef struct ql_rpt_lun_lst { 125 ql_rpt_hdr_t hdr; 126 ql_rpt_lun_t lst[MAX_LUNS]; 127 } ql_rpt_lun_lst_t; 128 129 #define INQ_DATA_SIZE 8 130 131 /* 132 * Flash definitions. 133 */ 134 typedef struct ql_flash_info { 135 uint32_t type; /* flash type */ 136 uint32_t size; /* length in bytes of flash */ 137 uint32_t sec_mask; /* sector number mask */ 138 uint8_t man_id; /* flash chip manufacturer id */ 139 uint8_t id; /* flash chip id */ 140 uint8_t cap; /* flash chip capacity */ 141 } ql_flash_info_t; 142 143 /* 144 * Flash Description Table 145 */ 146 #define FLASH_DESC_VERSION 1 147 #define FLASH_DESC_VAILD 0x44494C51 /* "QLID" */ 148 typedef struct flash_desc { 149 uint32_t flash_valid; 150 uint16_t flash_version; 151 uint16_t flash_len; 152 uint16_t flash_checksum; 153 uint16_t flash_unused; 154 uint8_t flash_model[16]; 155 uint16_t flash_manuf; 156 uint16_t flash_id; 157 uint8_t flash_flag; 158 uint8_t erase_cmd; 159 uint8_t alt_erase_cmd; 160 uint8_t write_enable_cmd; 161 uint8_t write_enable_bits; 162 uint8_t write_statusreg_cmd; 163 uint8_t unprotect_sector_cmd; 164 uint8_t read_manuf_cmd; 165 uint32_t block_size; 166 uint32_t alt_block_size; 167 uint32_t flash_size; 168 uint32_t write_enable_data; 169 uint8_t readid_address_len; 170 uint8_t write_disable_bits; 171 uint8_t read_device_id_len; 172 uint8_t chip_erase_cmd; 173 uint16_t read_timeout; 174 uint8_t protect_sector_cmd; 175 uint8_t exp_reserved[65]; 176 } flash_desc_t; 177 178 /* flash manufacturer id's */ 179 #define AMD_FLASH 0x01 /* AMD / Spansion */ 180 #define ST_FLASH 0x20 /* ST Electronics */ 181 #define SST_FLASH 0xbf /* SST Electronics */ 182 #define MXIC_FLASH 0xc2 /* Macronix (MXIC) */ 183 #define ATMEL_FLASH 0x1f /* Atmel (AT26DF081A) */ 184 #define WINBOND_FLASH 0xef /* Winbond (W25X16) */ 185 #define INTEL_FLASH 0x89 /* Intel (QB25F016S33B8) */ 186 187 /* flash id defines */ 188 #define AMD_FLASHID_128K 0x6e /* 128k AMD flash chip */ 189 #define AMD_FLASHID_512K 0x4f /* 512k AMD flash chip */ 190 #define AMD_FLASHID_512Kt 0xb9 /* 512k AMD flash chip - top boot blk */ 191 #define AMD_FLASHID_512Kb 0xba /* 512k AMD flash chip - btm boot blk */ 192 #define AMD_FLASHID_1024K 0x38 /* 1 MB AMD flash chip */ 193 #define ST_FLASHID_128K 0x23 /* 128k ST flash chip */ 194 #define ST_FLASHID_512K 0xe3 /* 512k ST flash chip */ 195 #define ST_FLASHID_M25PXX 0x20 /* M25Pxx ST flash chip */ 196 #define SST_FLASHID_128K 0xd5 /* 128k SST flash chip */ 197 #define SST_FLASHID_1024K 0xd8 /* 1 MB SST flash chip */ 198 #define SST_FLASHID_1024K_A 0x80 /* 1 MB SST 25LF080A flash chip */ 199 #define SST_FLASHID_1024K_B 0x8e /* 1 MB SST 25VF080B flash chip */ 200 #define SST_FLASHID_2048K 0x25 /* 2 MB SST 25VF016B flash chip */ 201 #define MXIC_FLASHID_512K 0x4f /* 512k MXIC flash chip */ 202 #define MXIC_FLASHID_1024K 0x38 /* 1 MB MXIC flash chip */ 203 #define MXIC_FLASHID_25LXX 0x20 /* 25Lxx MXIC flash chip */ 204 #define ATMEL_FLASHID_1024K 0x45 /* 1 MB ATMEL flash chip */ 205 #define SPAN_FLASHID_2048K 0x02 /* 2 MB Spansion flash chip */ 206 #define WINBOND_FLASHID 0x30 /* Winbond W25Xxx flash chip */ 207 #define INTEL_FLASHID 0x89 /* Intel QB25F016S33B8 flash chip */ 208 209 /* flash type defines */ 210 #define FLASH128 BIT_0 211 #define FLASH512 BIT_1 212 #define FLASH512S BIT_2 213 #define FLASH1024 BIT_3 214 #define FLASH2048 BIT_4 215 #define FLASH4096 BIT_5 216 #define FLASH8192 BIT_6 217 #define FLASH_PAGE BIT_31 218 #define FLASH_LEGACY (FLASH128 | FLASH512S) 219 220 typedef struct ql_ledstate { 221 uint32_t BeaconState; 222 uint32_t LEDflags; 223 uint32_t flags; 224 } ql_ledstate_t; 225 226 /* 227 * ledstate flags definitions 228 */ 229 #define LED_ACTIVE BIT_0 230 231 /* 232 * ledstate BeaconState definitions 233 */ 234 #define BEACON_OFF 0 235 #define BEACON_ON BIT_0 236 237 /* 238 * ledstate LEDflags definitions 239 */ 240 #define LED_ALL_OFF 0 241 #define LED_RED BIT_0 242 #define LED_GREEN BIT_6 243 #define LED_AMBER BIT_7 244 #define LED_MASK (LED_AMBER | LED_GREEN | LED_RED) 245 246 /* 247 * 24xx ledstate LEDflags definitions 248 */ 249 #define LED_MASK_UPDATE_24 (BIT_20 | BIT_19 | BIT_18) 250 #define LED_YELLOW_24 BIT_2 251 #define LED_GREEN_24 BIT_3 252 #define LED_AMBER_24 BIT_4 253 #define LED_MASK_COLORS_24 (LED_AMBER_24 | LED_GREEN_24 | LED_YELLOW_24) 254 255 typedef struct { 256 uint8_t signature[2]; 257 uint8_t reserved[0x16]; 258 uint8_t dataoffset[2]; 259 uint8_t pad[6]; 260 } pci_header_t; 261 262 typedef struct { 263 uint8_t signature[4]; 264 uint8_t vid[2]; 265 uint8_t did[2]; 266 uint8_t reserved0[2]; 267 uint8_t pcidatalen[2]; 268 uint8_t pcidatarev; 269 uint8_t classcode[3]; 270 uint8_t imagelength[2]; /* In sectors */ 271 uint8_t revisionlevel[2]; 272 uint8_t codetype; 273 uint8_t indicator; 274 uint8_t reserved1[2]; 275 uint8_t pad[8]; 276 } pci_data_t; 277 278 #define PCI_HEADER0 0x55 279 #define PCI_HEADER1 0xAA 280 #define PCI_DATASIG "PCIR" 281 #define PCI_SECTOR_SIZE 0x200 282 #define PCI_CODE_X86PC 0 283 #define PCI_CODE_FCODE 1 284 #define PCI_CODE_HPPA 2 285 #define PCI_CODE_EFI 3 286 #define PCI_CODE_FW 0xfe 287 #define PCI_IND_LAST_IMAGE 0x80 288 #define SBUS_CODE_FCODE 0xf1 289 290 typedef struct ql_fcache { 291 struct ql_fcache *next; 292 uint32_t type; 293 int8_t verstr[FCHBA_OPTION_ROM_VERSION_LEN]; 294 uint32_t buflen; 295 uint8_t *buf; 296 } ql_fcache_t; 297 298 /* fcache types */ 299 #define FTYPE_UNKNOWN 0 300 #define FTYPE_FCODE BIT_0 301 #define FTYPE_BIOS BIT_1 302 #define FTYPE_EFI BIT_2 303 #define FTYPE_FW BIT_3 304 #define FTYPE_HPPA BIT_4 305 306 #define FBUFSIZE 100 307 308 /* 309 * Per instance XIOCTL context defintions. 310 */ 311 typedef struct ql_xioctl { 312 /* Driver context */ 313 flash_desc_t fdesc; 314 315 /* Adapter I/O statistics */ 316 uint32_t ControllerErrorCount; 317 uint32_t DeviceErrorCount; 318 uint32_t TotalLipResets; 319 uint32_t TotalInterrupts; 320 321 uint64_t BytesRequested; 322 uint64_t IosRequested; 323 324 /* SNIA stat counters */ 325 int64_t IOInputRequests; 326 int64_t IOOutputRequests; 327 int64_t IOControlRequests; 328 int64_t IOOutputMByteCnt; /* # of mb's */ 329 int64_t IOInputMByteCnt; /* # of mb's */ 330 331 /* SNIA intermediate (less than 1mb) counters */ 332 int64_t IOOutputByteCnt; 333 int64_t IOInputByteCnt; 334 335 /* Adapter LED state */ 336 ql_ledstate_t ledstate; 337 338 /* Async event context */ 339 void *aen_tracking_queue; 340 uint8_t aen_q_head; 341 uint8_t aen_q_tail; 342 343 uint32_t flags; 344 } ql_xioctl_t; 345 346 /* 347 * ql adapter flag defintions. 348 */ 349 #define QL_AEN_TRACKING_ENABLE BIT_0 350 #define QL_MGMT_SERVER_LOGIN BIT_1 351 352 /* 353 * Global Data in ql_xioctl.c source file. 354 */ 355 356 /* 357 * Global Function Prototypes in ql_xioctl.c source file. 358 */ 359 int ql_alloc_xioctl_resource(ql_adapter_state_t *); 360 void ql_free_xioctl_resource(ql_adapter_state_t *); 361 int ql_xioctl(ql_adapter_state_t *, int, intptr_t, int, cred_t *, int *); 362 void ql_enqueue_aen(ql_adapter_state_t *, uint16_t, void *); 363 int ql_setup_flash(ql_adapter_state_t *); 364 void ql_setup_fcache(ql_adapter_state_t *); 365 void ql_blink_led(ql_adapter_state_t *); 366 void ql_fcache_rel(ql_fcache_t *); 367 ql_fcache_t *ql_get_fbuf(ql_fcache_t *, uint32_t); 368 int ql_dump_fcode(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t); 369 int ql_pci_dump(ql_adapter_state_t *, uint32_t *, uint32_t, int); 370 371 #ifdef __cplusplus 372 } 373 #endif 374 375 #endif /* _QL_XIOCTL_H */ 376