1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2009 QLogic Corporation */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _QL_INIT_H 30 #define _QL_INIT_H 31 32 /* 33 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 34 * 35 * *********************************************************************** 36 * * ** 37 * * NOTICE ** 38 * * COPYRIGHT (C) 1996-2009 QLOGIC CORPORATION ** 39 * * ALL RIGHTS RESERVED ** 40 * * ** 41 * *********************************************************************** 42 * 43 */ 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /* 50 * ISP2200 NVRAM structure definition. 51 * Little endian except where noted. 52 */ 53 typedef struct nvram { 54 /* 55 * NVRAM header 56 */ 57 uint8_t id[4]; 58 uint8_t nvram_version; 59 uint8_t reserved_0; 60 61 /* 62 * NVRAM RISC parameter block 63 */ 64 uint8_t parameter_block_version; 65 uint8_t reserved_1; 66 67 /* 68 * LSB BIT 0 = enable_hard_loop_id 69 * LSB BIT 1 = enable_fairness 70 * LSB BIT 2 = enable_full_duplex 71 * LSB BIT 3 = enable_fast_posting 72 * LSB BIT 4 = enable_target_mode 73 * LSB BIT 5 = disable_initiator_mode 74 * LSB BIT 6 = enable_adisc 75 * LSB BIT 7 = enable_target_inquiry_data 76 * 77 * MSB BIT 0 = enable_port_update_ae 78 * MSB BIT 1 = disable_initial_lip 79 * MSB BIT 2 = enable_decending_soft_assign 80 * MSB BIT 3 = previous_assigned_addressing 81 * MSB BIT 4 = enable_stop_q_on_full 82 * MSB BIT 5 = enable_full_login_on_lip 83 * MSB BIT 6 = enable_node_name 84 * MSB BIT 7 = extended_control_block 85 */ 86 uint8_t firmware_options[2]; 87 88 uint8_t max_frame_length[2]; 89 uint8_t max_iocb_allocation[2]; 90 uint8_t execution_throttle[2]; 91 uint8_t login_retry_count; 92 uint8_t retry_delay; /* unused */ 93 uint8_t port_name[8]; /* Big endian. */ 94 uint8_t hard_address[2]; 95 uint8_t inquiry; 96 uint8_t login_timeout; 97 uint8_t node_name[8]; /* Big endian. */ 98 99 /* 100 * LSB BIT 0 = Timer operation mode bit 0 101 * LSB BIT 1 = Timer operation mode bit 1 102 * LSB BIT 2 = Timer operation mode bit 2 103 * LSB BIT 3 = Timer operation mode bit 3 104 * LSB BIT 4 = P2P Connection option bit 0 105 * LSB BIT 5 = P2P Connection option bit 1 106 * LSB BIT 6 = P2P Connection option bit 2 107 * LSB BIT 7 = Enable Non part on LIHA failure 108 * 109 * MSB BIT 0 = Enable class 2 110 * MSB BIT 1 = Enable ACK0 111 * MSB BIT 2 = 112 * MSB BIT 3 = 113 * MSB BIT 4 = FC Tape Enable 114 * MSB BIT 5 = Enable FC Confirm 115 * MSB BIT 6 = Enable command queuing in target mode 116 * MSB BIT 7 = No Logo On Link Down 117 */ 118 uint8_t add_fw_opt[2]; 119 uint8_t response_accumulation_timer; 120 uint8_t interrupt_delay_timer; 121 122 /* 123 * LSB BIT 0 = Enable Read xfr_rdy 124 * LSB BIT 1 = Soft ID only 125 * LSB BIT 2 = 126 * LSB BIT 3 = 127 * LSB BIT 4 = FCP RSP Payload [0] 128 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 129 * LSB BIT 6 = 130 * LSB BIT 7 = 131 * 132 * MSB BIT 0 = Sbus enable - 2300 133 * MSB BIT 1 = 134 * MSB BIT 2 = 135 * MSB BIT 3 = 136 * MSB BIT 4 = 137 * MSB BIT 5 = Enable 50 ohm termination 138 * MSB BIT 6 = Data Rate (2300 only) 139 * MSB BIT 7 = Data Rate (2300 only) 140 */ 141 uint8_t special_options[2]; 142 143 /* Reserved for expanded RISC parameter block */ 144 uint8_t reserved_4[26]; 145 146 /* 147 * NVRAM host parameter block 148 * 149 * LSB BIT 0 = unused 150 * LSB BIT 1 = disable_bios 151 * LSB BIT 2 = disable_luns 152 * LSB BIT 3 = enable_selectable_boot 153 * LSB BIT 4 = disable_risc_code_load 154 * LSB BIT 5 = set_cache_line_size_1 155 * LSB BIT 6 = pci_parity_disable 156 * LSB BIT 7 = enable_extended_logging 157 * 158 * MSB BIT 0 = enable_64bit_addressing 159 * MSB BIT 1 = enable_lip_reset 160 * MSB BIT 2 = enable_lip_full_login 161 * MSB BIT 3 = enable_target_reset 162 * MSB BIT 4 = enable_database_storage 163 * MSB BIT 5 = unused 164 * MSB BIT 6 = unused 165 * MSB BIT 7 = unused 166 */ 167 uint8_t host_p[2]; 168 169 uint8_t boot_node_name[8]; 170 uint8_t boot_lun_number; 171 uint8_t reset_delay; 172 uint8_t port_down_retry_count; 173 uint8_t reserved_5; 174 175 uint8_t maximum_luns_per_target[2]; 176 177 uint8_t reserved_6[14]; 178 179 /* Offset 100 */ 180 uint8_t reverved_7[12]; 181 182 /* offset 112 */ 183 uint8_t adapInfo[16]; /* Sun OEM HBA's 23xx only */ 184 185 uint8_t reserved_8[22]; 186 187 /* Offset 150 */ 188 uint8_t reserved_9[50]; 189 190 /* Offset 200 */ 191 uint8_t reserved_10[32]; 192 193 /* 194 * NVRAM Adapter Features offset 232-239 195 * 196 * LSB BIT 0 = External GBIC 197 * LSB BIT 1 = Risc RAM parity 198 * LSB BIT 2 = Buffer Plus Module 199 * LSB BIT 3 = Multi Chip Adapter 200 * LSB BIT 4 = 201 * LSB BIT 5 = 202 * LSB BIT 6 = 203 * LSB BIT 7 = 204 * 205 * MSB BIT 0 = 206 * MSB BIT 1 = 207 * MSB BIT 2 = 208 * MSB BIT 3 = 209 * MSB BIT 4 = 210 * MSB BIT 5 = 211 * MSB BIT 6 = 212 * MSB BIT 7 = 213 */ 214 uint8_t adapter_features[2]; 215 uint8_t reserved_11[6]; 216 217 /* 218 * Resrved for use with ISP2300 - offset 240 219 */ 220 uint8_t reserved_12[4]; 221 222 /* Subsystem ID must be at offset 244 */ 223 uint8_t subsystem_vendor_id[2]; 224 225 uint8_t reserved_13[2]; 226 227 /* Subsystem device ID must be at offset 248 */ 228 uint8_t subsystem_device_id[2]; 229 230 /* Subsystem vendor ID for ISP2200 */ 231 uint8_t subsystem_vendor_id_2200[2]; 232 233 /* Subsystem device ID for ISP2200 */ 234 uint8_t subsystem_device_id_2200[2]; 235 236 uint8_t reserved_14; 237 uint8_t checksum; 238 } nvram_t; 239 240 /* 241 * NVRAM structure definition. 242 */ 243 typedef struct nvram_24xx { 244 /* NVRAM header. */ 245 uint8_t id[4]; 246 uint8_t nvram_version[2]; 247 uint8_t reserved_0[2]; 248 249 /* Firmware Initialization Control Block. */ 250 uint8_t version[2]; 251 uint8_t reserved_1[2]; 252 uint8_t max_frame_length[2]; 253 uint8_t execution_throttle[2]; 254 uint8_t exchange_count[2]; 255 uint8_t hard_address[2]; 256 uint8_t port_name[8]; 257 uint8_t node_name[8]; 258 uint8_t login_retry_count[2]; 259 uint8_t link_down_on_nos[2]; 260 uint8_t interrupt_delay_timer[2]; 261 uint8_t login_timeout[2]; 262 263 /* 264 * BIT 0 = Hard Assigned Loop ID 265 * BIT 1 = Enable Fairness 266 * BIT 2 = Enable Full-Duplex 267 * BIT 3 = Reserved 268 * BIT 4 = Target Mode Enable 269 * BIT 5 = Initiator Mode Disable 270 * BIT 6 = Reserved 271 * BIT 7 = Reserved 272 * 273 * BIT 8 = Reserved 274 * BIT 9 = Disable Initial LIP 275 * BIT 10 = Descending Loop ID Search 276 * BIT 11 = Previous Assigned Loop ID 277 * BIT 12 = Reserved 278 * BIT 13 = Full Login after LIP 279 * BIT 14 = Node Name Option 280 * BIT 15-31 = Reserved 281 */ 282 uint8_t firmware_options_1[4]; 283 284 /* 285 * BIT 0 = Operation Mode bit 0 286 * BIT 1 = Operation Mode bit 1 287 * BIT 2 = Operation Mode bit 2 288 * BIT 3 = Operation Mode bit 3 289 * BIT 4 = Connection Options bit 0 290 * BIT 5 = Connection Options bit 1 291 * BIT 6 = Connection Options bit 2 292 * BIT 7 = Enable Non part on LIHA failure 293 * 294 * BIT 8 = Enable Class 2 295 * BIT 9 = Enable ACK0 296 * BIT 10 = Reserved 297 * BIT 11 = Enable FC-SP Security 298 * BIT 12 = FC Tape Enable 299 * BIT 13-31 = Reserved 300 */ 301 uint8_t firmware_options_2[4]; 302 303 /* 304 * BIT 0 = Reserved 305 * BIT 1 = Soft ID only 306 * BIT 2 = Reserved 307 * BIT 3 = Reserved 308 * BIT 4 = FCP RSP Payload bit 0 309 * BIT 5 = FCP RSP Payload bit 1 310 * BIT 6 = Enable Rec Out-of-Order data frame handling 311 * BIT 7 = Disable Automatic PLOGI on Local Loop 312 * 313 * BIT 8 = Reserved 314 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 315 * offset handling 316 * BIT 10 = Reserved 317 * BIT 11 = Reserved 318 * BIT 12 = Reserved 319 * BIT 13 = Data Rate bit 0 320 * BIT 14 = Data Rate bit 1 321 * BIT 15 = Data Rate bit 2 322 * BIT 16 = 75-ohm Termination Select 323 * BIT 17-31 = Reserved 324 */ 325 uint8_t firmware_options_3[4]; 326 327 /* 328 * Serial Link Control (offset 56) 329 * BIT 0 = control enable 330 * BIT 1-15 = Reserved 331 */ 332 uint8_t swing_opt[2]; 333 334 /* 335 * Serial Link Control 1G (offset 58) 336 * BIT 0-7 = Reserved 337 * 338 * BIT 8-10 = output swing 339 * BIT 11-13 = output emphasis 340 * BIT 14-15 = Reserved 341 */ 342 uint8_t swing_1g[2]; 343 344 /* 345 * Serial Link Control 2G (offset 60) 346 * BIT 0-7 = Reserved 347 * 348 * BIT 8-10 = output swing 349 * BIT 11-13 = output emphasis 350 * BIT 14-15 = Reserved 351 */ 352 uint8_t swing_2g[2]; 353 354 /* 355 * Serial Link Control 4G (offset 62) 356 * BIT 0-7 = Reserved 357 * 358 * BIT 8-10 = output swing 359 * BIT 11-13 = output emphasis 360 * BIT 14-15 = Reserved 361 */ 362 uint8_t swing_4g[2]; 363 364 /* Offset 64. */ 365 uint8_t reserved_2[32]; 366 367 /* Offset 96. */ 368 uint8_t reserved_3[32]; 369 370 /* PCIe table entries. */ 371 uint8_t reserved_4[32]; 372 373 /* Offset 160. */ 374 uint8_t reserved_5[32]; 375 376 /* Offset 192. */ 377 uint8_t reserved_6[32]; 378 379 /* Offset 224. */ 380 uint8_t reserved_7[32]; 381 382 /* 383 * BIT 0 = Enable spinup delay 384 * BIT 1 = Disable BIOS 385 * BIT 2 = Enable Memory Map BIOS 386 * BIT 3 = Enable Selectable Boot 387 * BIT 4 = Disable RISC code load 388 * BIT 5 = Disable serdes 389 * BIT 6 = Enable opt boot mode 390 * BIT 7 = Enable int mode BIOS 391 * 392 * BIT 8 = 393 * BIT 9 = 394 * BIT 10 = Enable lip full login 395 * BIT 11 = Enable target reset 396 * BIT 12 = 397 * BIT 13 = Default Node Name Option 398 * BIT 14 = Default valid 399 * BIT 15 = Enable alternate WWN 400 * 401 * BIT 16-31 = 402 */ 403 uint8_t host_p[4]; 404 405 uint8_t alternate_port_name[8]; 406 uint8_t alternate_node_name[8]; 407 408 uint8_t boot_port_name[8]; 409 uint8_t boot_lun_number[2]; 410 uint8_t reserved_8[2]; 411 412 uint8_t alt1_boot_port_name[8]; 413 uint8_t alt1_boot_lun_number[2]; 414 uint8_t reserved_9[2]; 415 416 uint8_t alt2_boot_port_name[8]; 417 uint8_t alt2_boot_lun_number[2]; 418 uint8_t reserved_10[2]; 419 420 uint8_t alt3_boot_port_name[8]; 421 uint8_t alt3_boot_lun_number[2]; 422 uint8_t reserved_11[2]; 423 424 /* 425 * BIT 0 = Selective Login 426 * BIT 1 = Alt-Boot Enable 427 * BIT 2 = Reserved 428 * BIT 3 = Enable Boot Order List 429 * BIT 4 = Reserved 430 * BIT 5 = Enable Selective LUN 431 * BIT 6 = Reserved 432 * BIT 7-31 = 433 */ 434 uint8_t efi_parameters[4]; 435 436 uint8_t reset_delay; 437 uint8_t reserved_12; 438 uint8_t reserved_13[2]; 439 440 uint8_t boot_id_number[2]; 441 uint8_t reserved_14[2]; 442 443 uint8_t max_luns_per_target[2]; 444 uint8_t reserved_15[2]; 445 446 uint8_t port_down_retry_count[2]; 447 uint8_t link_down_timeout[2]; 448 449 /* 450 * FCode parameters word (offset 344) 451 * 452 * BIT 0 = Enable BIOS pathname 453 * BIT 1 = fcode qlc 454 * BIT 2 = fcode host 455 * BIT 3-7 = 456 */ 457 uint8_t fcode_p0; 458 uint8_t reserved_16[7]; 459 460 /* Offset 352. */ 461 uint8_t prev_drv_ver_major; 462 uint8_t prev_drv_ver_submajob; 463 uint8_t prev_drv_ver_minor; 464 uint8_t prev_drv_ver_subminor; 465 466 uint8_t prev_bios_ver_major[2]; 467 uint8_t prev_bios_ver_minor[2]; 468 469 uint8_t prev_efi_ver_major[2]; 470 uint8_t prev_efi_ver_minor[2]; 471 472 uint8_t prev_fw_ver_major[2]; 473 uint8_t prev_fw_ver_minor; 474 uint8_t prev_fw_ver_subminor; 475 476 uint8_t reserved_17[16]; 477 478 /* Offset 384. */ 479 uint8_t def_port_name[8]; 480 uint8_t def_node_name[8]; 481 482 uint8_t reserved_18[16]; 483 484 /* Offset 416. */ 485 uint8_t reserved_19[32]; 486 487 /* Offset 448. */ 488 uint8_t reserved_20[28]; 489 490 /* Offset 476. */ 491 uint8_t fw_table_offset[2]; 492 uint8_t fw_table_sig[2]; 493 494 /* Offset 480. */ 495 uint8_t model_name[8]; 496 497 /* Offset 488. */ 498 uint8_t power_table[16]; 499 500 uint8_t subsystem_vendor_id[2]; 501 uint8_t subsystem_device_id[2]; 502 503 uint8_t checksum[4]; 504 } nvram_24xx_t; 505 506 /* 507 * Firmware Dump structure definition 508 */ 509 #define QL_2200_FW_DUMP_SIZE 0x68000 /* bytes */ 510 #define QL_2300_FW_DUMP_SIZE 0xE2000 /* bytes */ 511 #define QL_6322_FW_DUMP_SIZE 0xE2000 /* bytes */ 512 #define QL_24XX_FW_DUMP_SIZE 0x0330000 /* bytes */ 513 #define QL_25XX_FW_DUMP_SIZE 0x0330000 /* bytes */ 514 515 #define QL_24XX_VPD_SIZE 0x200 /* bytes */ 516 #define QL_24XX_SFP_SIZE 0x200 /* bytes */ 517 518 /* 519 * firmware dump struct for 2300 is a superset of firmware dump struct 520 * for 2200. Fields which are 2300 only or are enhanced for 2300 are 521 * marked below. 522 */ 523 typedef struct ql_fw_dump { 524 uint16_t pbiu_reg[8]; 525 uint16_t risc_host_reg[8]; /* 2300 only. */ 526 uint16_t mailbox_reg[16]; /* 2200 only needs 8 */ 527 uint16_t resp_dma_reg[32]; /* 2300 only. */ 528 uint16_t dma_reg[48]; 529 uint16_t risc_hdw_reg[16]; 530 uint16_t risc_gp0_reg[16]; 531 uint16_t risc_gp1_reg[16]; 532 uint16_t risc_gp2_reg[16]; 533 uint16_t risc_gp3_reg[16]; 534 uint16_t risc_gp4_reg[16]; 535 uint16_t risc_gp5_reg[16]; 536 uint16_t risc_gp6_reg[16]; 537 uint16_t risc_gp7_reg[16]; 538 uint16_t frame_buf_hdw_reg[64]; /* 2200 has only 16 */ 539 uint16_t fpm_b0_reg[64]; 540 uint16_t fpm_b1_reg[64]; 541 uint16_t risc_ram[0xf800]; /* 2200 needs only 0xf000 */ 542 uint16_t stack_ram[0x800]; /* 2300 only */ 543 uint16_t data_ram[0xf800]; /* 2300 only */ 544 uint32_t req_q[REQUEST_QUEUE_SIZE / 4]; 545 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4]; 546 } ql_fw_dump_t; 547 548 typedef struct ql_24xx_fw_dump { 549 uint32_t hccr; 550 uint32_t host_reg[32]; 551 uint16_t mailbox_reg[32]; 552 uint32_t xseq_gp_reg[128]; 553 uint32_t xseq_0_reg[16]; 554 uint32_t xseq_1_reg[16]; 555 uint32_t rseq_gp_reg[128]; 556 uint32_t rseq_0_reg[16]; 557 uint32_t rseq_1_reg[16]; 558 uint32_t rseq_2_reg[16]; 559 uint32_t cmd_dma_reg[16]; 560 uint32_t req0_dma_reg[15]; 561 uint32_t resp0_dma_reg[15]; 562 uint32_t req1_dma_reg[15]; 563 uint32_t xmt0_dma_reg[32]; 564 uint32_t xmt1_dma_reg[32]; 565 uint32_t xmt2_dma_reg[32]; 566 uint32_t xmt3_dma_reg[32]; 567 uint32_t xmt4_dma_reg[32]; 568 uint32_t xmt_data_dma_reg[16]; 569 uint32_t rcvt0_data_dma_reg[32]; 570 uint32_t rcvt1_data_dma_reg[32]; 571 uint32_t risc_gp_reg[128]; 572 uint32_t shadow_reg[7]; 573 uint32_t lmc_reg[112]; 574 uint32_t fpm_hdw_reg[192]; 575 uint32_t fb_hdw_reg[176]; 576 uint32_t code_ram[0x2000]; 577 uint32_t req_q[REQUEST_QUEUE_SIZE / 4]; 578 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4]; 579 uint32_t ext_trace_buf[FWEXTSIZE / 4]; 580 uint32_t fce_trace_buf[FWFCESIZE / 4]; 581 uint32_t ext_mem[1]; 582 } ql_24xx_fw_dump_t; 583 584 typedef struct ql_25xx_fw_dump { 585 uint32_t r2h_status; 586 uint32_t hostrisc_reg[32]; 587 uint32_t pcie_reg[4]; 588 uint32_t host_reg[32]; 589 uint16_t mailbox_reg[32]; 590 uint32_t xseq_gp_reg[128]; 591 uint32_t xseq_0_reg[48]; 592 uint32_t xseq_1_reg[16]; 593 uint32_t rseq_gp_reg[128]; 594 uint32_t rseq_0_reg[32]; 595 uint32_t rseq_1_reg[16]; 596 uint32_t rseq_2_reg[16]; 597 uint32_t aseq_gp_reg[128]; 598 uint32_t aseq_0_reg[32]; 599 uint32_t aseq_1_reg[16]; 600 uint32_t aseq_2_reg[16]; 601 uint32_t cmd_dma_reg[16]; 602 uint32_t req0_dma_reg[15]; 603 uint32_t resp0_dma_reg[15]; 604 uint32_t req1_dma_reg[15]; 605 uint32_t xmt0_dma_reg[32]; 606 uint32_t xmt1_dma_reg[32]; 607 uint32_t xmt2_dma_reg[32]; 608 uint32_t xmt3_dma_reg[32]; 609 uint32_t xmt4_dma_reg[32]; 610 uint32_t xmt_data_dma_reg[16]; 611 uint32_t rcvt0_data_dma_reg[32]; 612 uint32_t rcvt1_data_dma_reg[32]; 613 uint32_t risc_gp_reg[128]; 614 uint32_t shadow_reg[11]; 615 uint32_t risc_io; 616 uint32_t lmc_reg[128]; 617 uint32_t fpm_hdw_reg[192]; 618 uint32_t fb_hdw_reg[192]; 619 uint32_t code_ram[0x2000]; 620 uint32_t req_q[REQUEST_QUEUE_SIZE / 4]; 621 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4]; 622 uint32_t ext_trace_buf[FWEXTSIZE / 4]; 623 uint32_t fce_trace_buf[FWFCESIZE / 4]; 624 uint32_t ext_mem[1]; 625 } ql_25xx_fw_dump_t; 626 627 #ifdef _KERNEL 628 629 /* 630 * ql_lock_nvram() flags 631 */ 632 #define LNF_NVRAM_DATA BIT_0 /* get nvram */ 633 #define LNF_VPD_DATA BIT_1 /* get vpd data (24xx only) */ 634 635 /* 636 * ISP product identification definitions in mailboxes after reset. 637 */ 638 #define PROD_ID_1 0x4953 639 #define PROD_ID_2 0x0000 640 #define PROD_ID_2a 0x5020 641 #define PROD_ID_3 0x2020 642 643 /* 644 * NVRAM Command values. 645 */ 646 #define NV_START_BIT BIT_2 647 #define NV_WRITE_OP (BIT_26+BIT_24) 648 #define NV_READ_OP (BIT_26+BIT_25) 649 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 650 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 651 #define NV_DELAY_COUNT 10 652 653 union ql_dev_id_list; 654 655 /* 656 * Global Data in ql_init.c source file. 657 */ 658 659 /* 660 * Global Function Prototypes in ql_init.c source file. 661 */ 662 int ql_initialize_adapter(ql_adapter_state_t *); 663 int ql_pci_sbus_config(ql_adapter_state_t *); 664 int ql_nvram_config(ql_adapter_state_t *); 665 uint16_t ql_get_nvram_word(ql_adapter_state_t *, uint32_t); 666 void ql_nv_write(ql_adapter_state_t *, uint16_t); 667 void ql_nv_delay(void); 668 int ql_lock_nvram(ql_adapter_state_t *, uint32_t *, uint32_t); 669 void ql_release_nvram(ql_adapter_state_t *); 670 void ql_common_properties(ql_adapter_state_t *); 671 uint32_t ql_get_prop(ql_adapter_state_t *, char *); 672 int ql_load_isp_firmware(ql_adapter_state_t *); 673 int ql_start_firmware(ql_adapter_state_t *); 674 int ql_set_cache_line(ql_adapter_state_t *); 675 int ql_init_rings(ql_adapter_state_t *); 676 int ql_fw_ready(ql_adapter_state_t *, uint8_t); 677 void ql_dev_list(ql_adapter_state_t *, union ql_dev_id_list *, uint32_t, 678 port_id_t *, uint16_t *); 679 void ql_reset_chip(ql_adapter_state_t *); 680 void ql_reset_24xx_chip(ql_adapter_state_t *); 681 int ql_abort_isp(ql_adapter_state_t *); 682 int ql_vport_control(ql_adapter_state_t *, uint8_t); 683 int ql_vport_modify(ql_adapter_state_t *, uint8_t, uint8_t); 684 int ql_vport_enable(ql_adapter_state_t *); 685 ql_adapter_state_t *ql_vport_create(ql_adapter_state_t *, uint8_t); 686 void ql_vport_destroy(ql_adapter_state_t *); 687 #endif /* _KERNEL */ 688 689 #ifdef __cplusplus 690 } 691 #endif 692 693 #endif /* _QL_INIT_H */ 694