193c20f26SSukumar Swaminathan /* 293c20f26SSukumar Swaminathan * CDDL HEADER START 393c20f26SSukumar Swaminathan * 493c20f26SSukumar Swaminathan * The contents of this file are subject to the terms of the 593c20f26SSukumar Swaminathan * Common Development and Distribution License (the "License"). 693c20f26SSukumar Swaminathan * You may not use this file except in compliance with the License. 793c20f26SSukumar Swaminathan * 893c20f26SSukumar Swaminathan * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 993c20f26SSukumar Swaminathan * or http://www.opensolaris.org/os/licensing. 1093c20f26SSukumar Swaminathan * See the License for the specific language governing permissions 1193c20f26SSukumar Swaminathan * and limitations under the License. 1293c20f26SSukumar Swaminathan * 1393c20f26SSukumar Swaminathan * When distributing Covered Code, include this CDDL HEADER in each 1493c20f26SSukumar Swaminathan * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1593c20f26SSukumar Swaminathan * If applicable, add the following below this CDDL HEADER, with the 1693c20f26SSukumar Swaminathan * fields enclosed by brackets "[]" replaced with your own identifying 1793c20f26SSukumar Swaminathan * information: Portions Copyright [yyyy] [name of copyright owner] 1893c20f26SSukumar Swaminathan * 1993c20f26SSukumar Swaminathan * CDDL HEADER END 2093c20f26SSukumar Swaminathan */ 2193c20f26SSukumar Swaminathan 22*4c3888b8SHans Rosenfeld /* Copyright 2015 QLogic Corporation */ 2393c20f26SSukumar Swaminathan 2493c20f26SSukumar Swaminathan /* 25*4c3888b8SHans Rosenfeld * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 2693c20f26SSukumar Swaminathan */ 2793c20f26SSukumar Swaminathan 2893c20f26SSukumar Swaminathan #ifndef _QL_INIT_H 2993c20f26SSukumar Swaminathan #define _QL_INIT_H 3093c20f26SSukumar Swaminathan 3193c20f26SSukumar Swaminathan /* 3293c20f26SSukumar Swaminathan * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 3393c20f26SSukumar Swaminathan * 3493c20f26SSukumar Swaminathan * *********************************************************************** 3593c20f26SSukumar Swaminathan * * ** 3693c20f26SSukumar Swaminathan * * NOTICE ** 37*4c3888b8SHans Rosenfeld * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION ** 3893c20f26SSukumar Swaminathan * * ALL RIGHTS RESERVED ** 3993c20f26SSukumar Swaminathan * * ** 4093c20f26SSukumar Swaminathan * *********************************************************************** 4193c20f26SSukumar Swaminathan * 4293c20f26SSukumar Swaminathan */ 4393c20f26SSukumar Swaminathan 4493c20f26SSukumar Swaminathan #ifdef __cplusplus 4593c20f26SSukumar Swaminathan extern "C" { 4693c20f26SSukumar Swaminathan #endif 4793c20f26SSukumar Swaminathan 48*4c3888b8SHans Rosenfeld extern uint32_t ql_task_cb_dly; 49*4c3888b8SHans Rosenfeld 5093c20f26SSukumar Swaminathan /* 5193c20f26SSukumar Swaminathan * ISP2200 NVRAM structure definition. 5293c20f26SSukumar Swaminathan * Little endian except where noted. 5393c20f26SSukumar Swaminathan */ 5493c20f26SSukumar Swaminathan typedef struct nvram { 5593c20f26SSukumar Swaminathan /* 5693c20f26SSukumar Swaminathan * NVRAM header 5793c20f26SSukumar Swaminathan */ 5893c20f26SSukumar Swaminathan uint8_t id[4]; 5993c20f26SSukumar Swaminathan uint8_t nvram_version; 6093c20f26SSukumar Swaminathan uint8_t reserved_0; 6193c20f26SSukumar Swaminathan 6293c20f26SSukumar Swaminathan /* 6393c20f26SSukumar Swaminathan * NVRAM RISC parameter block 6493c20f26SSukumar Swaminathan */ 6593c20f26SSukumar Swaminathan uint8_t parameter_block_version; 6693c20f26SSukumar Swaminathan uint8_t reserved_1; 6793c20f26SSukumar Swaminathan 6893c20f26SSukumar Swaminathan /* 6993c20f26SSukumar Swaminathan * LSB BIT 0 = enable_hard_loop_id 7093c20f26SSukumar Swaminathan * LSB BIT 1 = enable_fairness 7193c20f26SSukumar Swaminathan * LSB BIT 2 = enable_full_duplex 7293c20f26SSukumar Swaminathan * LSB BIT 3 = enable_fast_posting 7393c20f26SSukumar Swaminathan * LSB BIT 4 = enable_target_mode 7493c20f26SSukumar Swaminathan * LSB BIT 5 = disable_initiator_mode 7593c20f26SSukumar Swaminathan * LSB BIT 6 = enable_adisc 7693c20f26SSukumar Swaminathan * LSB BIT 7 = enable_target_inquiry_data 7793c20f26SSukumar Swaminathan * 7893c20f26SSukumar Swaminathan * MSB BIT 0 = enable_port_update_ae 7993c20f26SSukumar Swaminathan * MSB BIT 1 = disable_initial_lip 8093c20f26SSukumar Swaminathan * MSB BIT 2 = enable_decending_soft_assign 8193c20f26SSukumar Swaminathan * MSB BIT 3 = previous_assigned_addressing 8293c20f26SSukumar Swaminathan * MSB BIT 4 = enable_stop_q_on_full 8393c20f26SSukumar Swaminathan * MSB BIT 5 = enable_full_login_on_lip 8493c20f26SSukumar Swaminathan * MSB BIT 6 = enable_node_name 8593c20f26SSukumar Swaminathan * MSB BIT 7 = extended_control_block 8693c20f26SSukumar Swaminathan */ 8793c20f26SSukumar Swaminathan uint8_t firmware_options[2]; 8893c20f26SSukumar Swaminathan 8993c20f26SSukumar Swaminathan uint8_t max_frame_length[2]; 9093c20f26SSukumar Swaminathan uint8_t max_iocb_allocation[2]; 9193c20f26SSukumar Swaminathan uint8_t execution_throttle[2]; 9293c20f26SSukumar Swaminathan uint8_t login_retry_count; 9393c20f26SSukumar Swaminathan uint8_t retry_delay; /* unused */ 9493c20f26SSukumar Swaminathan uint8_t port_name[8]; /* Big endian. */ 9593c20f26SSukumar Swaminathan uint8_t hard_address[2]; 9693c20f26SSukumar Swaminathan uint8_t inquiry; 9793c20f26SSukumar Swaminathan uint8_t login_timeout; 9893c20f26SSukumar Swaminathan uint8_t node_name[8]; /* Big endian. */ 9993c20f26SSukumar Swaminathan 10093c20f26SSukumar Swaminathan /* 10193c20f26SSukumar Swaminathan * LSB BIT 0 = Timer operation mode bit 0 10293c20f26SSukumar Swaminathan * LSB BIT 1 = Timer operation mode bit 1 10393c20f26SSukumar Swaminathan * LSB BIT 2 = Timer operation mode bit 2 10493c20f26SSukumar Swaminathan * LSB BIT 3 = Timer operation mode bit 3 10593c20f26SSukumar Swaminathan * LSB BIT 4 = P2P Connection option bit 0 10693c20f26SSukumar Swaminathan * LSB BIT 5 = P2P Connection option bit 1 10793c20f26SSukumar Swaminathan * LSB BIT 6 = P2P Connection option bit 2 10893c20f26SSukumar Swaminathan * LSB BIT 7 = Enable Non part on LIHA failure 10993c20f26SSukumar Swaminathan * 11093c20f26SSukumar Swaminathan * MSB BIT 0 = Enable class 2 11193c20f26SSukumar Swaminathan * MSB BIT 1 = Enable ACK0 11293c20f26SSukumar Swaminathan * MSB BIT 2 = 11393c20f26SSukumar Swaminathan * MSB BIT 3 = 11493c20f26SSukumar Swaminathan * MSB BIT 4 = FC Tape Enable 11593c20f26SSukumar Swaminathan * MSB BIT 5 = Enable FC Confirm 11693c20f26SSukumar Swaminathan * MSB BIT 6 = Enable command queuing in target mode 11793c20f26SSukumar Swaminathan * MSB BIT 7 = No Logo On Link Down 11893c20f26SSukumar Swaminathan */ 11993c20f26SSukumar Swaminathan uint8_t add_fw_opt[2]; 12093c20f26SSukumar Swaminathan uint8_t response_accumulation_timer; 12193c20f26SSukumar Swaminathan uint8_t interrupt_delay_timer; 12293c20f26SSukumar Swaminathan 12393c20f26SSukumar Swaminathan /* 12493c20f26SSukumar Swaminathan * LSB BIT 0 = Enable Read xfr_rdy 12593c20f26SSukumar Swaminathan * LSB BIT 1 = Soft ID only 12693c20f26SSukumar Swaminathan * LSB BIT 2 = 12793c20f26SSukumar Swaminathan * LSB BIT 3 = 12893c20f26SSukumar Swaminathan * LSB BIT 4 = FCP RSP Payload [0] 12993c20f26SSukumar Swaminathan * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 13093c20f26SSukumar Swaminathan * LSB BIT 6 = 13193c20f26SSukumar Swaminathan * LSB BIT 7 = 13293c20f26SSukumar Swaminathan * 13393c20f26SSukumar Swaminathan * MSB BIT 0 = Sbus enable - 2300 13493c20f26SSukumar Swaminathan * MSB BIT 1 = 13593c20f26SSukumar Swaminathan * MSB BIT 2 = 13693c20f26SSukumar Swaminathan * MSB BIT 3 = 13793c20f26SSukumar Swaminathan * MSB BIT 4 = 13893c20f26SSukumar Swaminathan * MSB BIT 5 = Enable 50 ohm termination 13993c20f26SSukumar Swaminathan * MSB BIT 6 = Data Rate (2300 only) 14093c20f26SSukumar Swaminathan * MSB BIT 7 = Data Rate (2300 only) 14193c20f26SSukumar Swaminathan */ 14293c20f26SSukumar Swaminathan uint8_t special_options[2]; 14393c20f26SSukumar Swaminathan 14493c20f26SSukumar Swaminathan /* Reserved for expanded RISC parameter block */ 14593c20f26SSukumar Swaminathan uint8_t reserved_4[26]; 14693c20f26SSukumar Swaminathan 14793c20f26SSukumar Swaminathan /* 14893c20f26SSukumar Swaminathan * NVRAM host parameter block 14993c20f26SSukumar Swaminathan * 15093c20f26SSukumar Swaminathan * LSB BIT 0 = unused 15193c20f26SSukumar Swaminathan * LSB BIT 1 = disable_bios 15293c20f26SSukumar Swaminathan * LSB BIT 2 = disable_luns 15393c20f26SSukumar Swaminathan * LSB BIT 3 = enable_selectable_boot 15493c20f26SSukumar Swaminathan * LSB BIT 4 = disable_risc_code_load 15593c20f26SSukumar Swaminathan * LSB BIT 5 = set_cache_line_size_1 15693c20f26SSukumar Swaminathan * LSB BIT 6 = pci_parity_disable 15793c20f26SSukumar Swaminathan * LSB BIT 7 = enable_extended_logging 15893c20f26SSukumar Swaminathan * 15993c20f26SSukumar Swaminathan * MSB BIT 0 = enable_64bit_addressing 16093c20f26SSukumar Swaminathan * MSB BIT 1 = enable_lip_reset 16193c20f26SSukumar Swaminathan * MSB BIT 2 = enable_lip_full_login 16293c20f26SSukumar Swaminathan * MSB BIT 3 = enable_target_reset 16393c20f26SSukumar Swaminathan * MSB BIT 4 = enable_database_storage 16493c20f26SSukumar Swaminathan * MSB BIT 5 = unused 16593c20f26SSukumar Swaminathan * MSB BIT 6 = unused 16693c20f26SSukumar Swaminathan * MSB BIT 7 = unused 16793c20f26SSukumar Swaminathan */ 16893c20f26SSukumar Swaminathan uint8_t host_p[2]; 16993c20f26SSukumar Swaminathan 17093c20f26SSukumar Swaminathan uint8_t boot_node_name[8]; 17193c20f26SSukumar Swaminathan uint8_t boot_lun_number; 17293c20f26SSukumar Swaminathan uint8_t reset_delay; 17393c20f26SSukumar Swaminathan uint8_t port_down_retry_count; 17493c20f26SSukumar Swaminathan uint8_t reserved_5; 17593c20f26SSukumar Swaminathan 17693c20f26SSukumar Swaminathan uint8_t maximum_luns_per_target[2]; 17793c20f26SSukumar Swaminathan 17893c20f26SSukumar Swaminathan uint8_t reserved_6[14]; 17993c20f26SSukumar Swaminathan 18093c20f26SSukumar Swaminathan /* Offset 100 */ 18193c20f26SSukumar Swaminathan uint8_t reverved_7[12]; 18293c20f26SSukumar Swaminathan 18393c20f26SSukumar Swaminathan /* offset 112 */ 18493c20f26SSukumar Swaminathan uint8_t adapInfo[16]; /* Sun OEM HBA's 23xx only */ 18593c20f26SSukumar Swaminathan 18693c20f26SSukumar Swaminathan uint8_t reserved_8[22]; 18793c20f26SSukumar Swaminathan 18893c20f26SSukumar Swaminathan /* Offset 150 */ 18993c20f26SSukumar Swaminathan uint8_t reserved_9[50]; 19093c20f26SSukumar Swaminathan 19193c20f26SSukumar Swaminathan /* Offset 200 */ 19293c20f26SSukumar Swaminathan uint8_t reserved_10[32]; 19393c20f26SSukumar Swaminathan 19493c20f26SSukumar Swaminathan /* 19593c20f26SSukumar Swaminathan * NVRAM Adapter Features offset 232-239 19693c20f26SSukumar Swaminathan * 19793c20f26SSukumar Swaminathan * LSB BIT 0 = External GBIC 19893c20f26SSukumar Swaminathan * LSB BIT 1 = Risc RAM parity 19993c20f26SSukumar Swaminathan * LSB BIT 2 = Buffer Plus Module 20093c20f26SSukumar Swaminathan * LSB BIT 3 = Multi Chip Adapter 20193c20f26SSukumar Swaminathan * LSB BIT 4 = 20293c20f26SSukumar Swaminathan * LSB BIT 5 = 20393c20f26SSukumar Swaminathan * LSB BIT 6 = 20493c20f26SSukumar Swaminathan * LSB BIT 7 = 20593c20f26SSukumar Swaminathan * 20693c20f26SSukumar Swaminathan * MSB BIT 0 = 20793c20f26SSukumar Swaminathan * MSB BIT 1 = 20893c20f26SSukumar Swaminathan * MSB BIT 2 = 20993c20f26SSukumar Swaminathan * MSB BIT 3 = 21093c20f26SSukumar Swaminathan * MSB BIT 4 = 21193c20f26SSukumar Swaminathan * MSB BIT 5 = 21293c20f26SSukumar Swaminathan * MSB BIT 6 = 21393c20f26SSukumar Swaminathan * MSB BIT 7 = 21493c20f26SSukumar Swaminathan */ 21593c20f26SSukumar Swaminathan uint8_t adapter_features[2]; 21693c20f26SSukumar Swaminathan uint8_t reserved_11[6]; 21793c20f26SSukumar Swaminathan 21893c20f26SSukumar Swaminathan /* 21993c20f26SSukumar Swaminathan * Resrved for use with ISP2300 - offset 240 22093c20f26SSukumar Swaminathan */ 22193c20f26SSukumar Swaminathan uint8_t reserved_12[4]; 22293c20f26SSukumar Swaminathan 22393c20f26SSukumar Swaminathan /* Subsystem ID must be at offset 244 */ 22493c20f26SSukumar Swaminathan uint8_t subsystem_vendor_id[2]; 22593c20f26SSukumar Swaminathan 22693c20f26SSukumar Swaminathan uint8_t reserved_13[2]; 22793c20f26SSukumar Swaminathan 22893c20f26SSukumar Swaminathan /* Subsystem device ID must be at offset 248 */ 22993c20f26SSukumar Swaminathan uint8_t subsystem_device_id[2]; 23093c20f26SSukumar Swaminathan 23193c20f26SSukumar Swaminathan /* Subsystem vendor ID for ISP2200 */ 23293c20f26SSukumar Swaminathan uint8_t subsystem_vendor_id_2200[2]; 23393c20f26SSukumar Swaminathan 23493c20f26SSukumar Swaminathan /* Subsystem device ID for ISP2200 */ 23593c20f26SSukumar Swaminathan uint8_t subsystem_device_id_2200[2]; 23693c20f26SSukumar Swaminathan 23793c20f26SSukumar Swaminathan uint8_t reserved_14; 23893c20f26SSukumar Swaminathan uint8_t checksum; 23993c20f26SSukumar Swaminathan } nvram_t; 24093c20f26SSukumar Swaminathan 24193c20f26SSukumar Swaminathan /* 24293c20f26SSukumar Swaminathan * NVRAM structure definition. 24393c20f26SSukumar Swaminathan */ 24493c20f26SSukumar Swaminathan typedef struct nvram_24xx { 24593c20f26SSukumar Swaminathan /* NVRAM header. */ 24693c20f26SSukumar Swaminathan uint8_t id[4]; 24793c20f26SSukumar Swaminathan uint8_t nvram_version[2]; 24893c20f26SSukumar Swaminathan uint8_t reserved_0[2]; 24993c20f26SSukumar Swaminathan 25093c20f26SSukumar Swaminathan /* Firmware Initialization Control Block. */ 25193c20f26SSukumar Swaminathan uint8_t version[2]; 25293c20f26SSukumar Swaminathan uint8_t reserved_1[2]; 25393c20f26SSukumar Swaminathan uint8_t max_frame_length[2]; 25493c20f26SSukumar Swaminathan uint8_t execution_throttle[2]; 25593c20f26SSukumar Swaminathan uint8_t exchange_count[2]; 25693c20f26SSukumar Swaminathan uint8_t hard_address[2]; 25793c20f26SSukumar Swaminathan uint8_t port_name[8]; 25893c20f26SSukumar Swaminathan uint8_t node_name[8]; 25993c20f26SSukumar Swaminathan uint8_t login_retry_count[2]; 26093c20f26SSukumar Swaminathan uint8_t link_down_on_nos[2]; 26193c20f26SSukumar Swaminathan uint8_t interrupt_delay_timer[2]; 26293c20f26SSukumar Swaminathan uint8_t login_timeout[2]; 26393c20f26SSukumar Swaminathan 26493c20f26SSukumar Swaminathan /* 26593c20f26SSukumar Swaminathan * BIT 0 = Hard Assigned Loop ID 26693c20f26SSukumar Swaminathan * BIT 1 = Enable Fairness 26793c20f26SSukumar Swaminathan * BIT 2 = Enable Full-Duplex 26893c20f26SSukumar Swaminathan * BIT 3 = Reserved 26993c20f26SSukumar Swaminathan * BIT 4 = Target Mode Enable 27093c20f26SSukumar Swaminathan * BIT 5 = Initiator Mode Disable 27193c20f26SSukumar Swaminathan * BIT 6 = Reserved 27293c20f26SSukumar Swaminathan * BIT 7 = Reserved 27393c20f26SSukumar Swaminathan * 27493c20f26SSukumar Swaminathan * BIT 8 = Reserved 27593c20f26SSukumar Swaminathan * BIT 9 = Disable Initial LIP 27693c20f26SSukumar Swaminathan * BIT 10 = Descending Loop ID Search 27793c20f26SSukumar Swaminathan * BIT 11 = Previous Assigned Loop ID 27893c20f26SSukumar Swaminathan * BIT 12 = Reserved 27993c20f26SSukumar Swaminathan * BIT 13 = Full Login after LIP 28093c20f26SSukumar Swaminathan * BIT 14 = Node Name Option 2815dfd244aSDaniel Beauregard * BIT 15 = Reserved 2825dfd244aSDaniel Beauregard * 2835dfd244aSDaniel Beauregard * BIT 16-31 = Reserved 28493c20f26SSukumar Swaminathan */ 28593c20f26SSukumar Swaminathan uint8_t firmware_options_1[4]; 28693c20f26SSukumar Swaminathan 28793c20f26SSukumar Swaminathan /* 28893c20f26SSukumar Swaminathan * BIT 0 = Operation Mode bit 0 28993c20f26SSukumar Swaminathan * BIT 1 = Operation Mode bit 1 29093c20f26SSukumar Swaminathan * BIT 2 = Operation Mode bit 2 29193c20f26SSukumar Swaminathan * BIT 3 = Operation Mode bit 3 29293c20f26SSukumar Swaminathan * BIT 4 = Connection Options bit 0 29393c20f26SSukumar Swaminathan * BIT 5 = Connection Options bit 1 29493c20f26SSukumar Swaminathan * BIT 6 = Connection Options bit 2 29593c20f26SSukumar Swaminathan * BIT 7 = Enable Non part on LIHA failure 29693c20f26SSukumar Swaminathan * 29793c20f26SSukumar Swaminathan * BIT 8 = Enable Class 2 29893c20f26SSukumar Swaminathan * BIT 9 = Enable ACK0 2995dfd244aSDaniel Beauregard * BIT 10 = Enable Virtual Fabric 30093c20f26SSukumar Swaminathan * BIT 11 = Enable FC-SP Security 30193c20f26SSukumar Swaminathan * BIT 12 = FC Tape Enable 3025dfd244aSDaniel Beauregard * BIT 13 = Reserved 3035dfd244aSDaniel Beauregard * BIT 14 = Target PRLI Control 3045dfd244aSDaniel Beauregard * BIT 15 = Reserved 3055dfd244aSDaniel Beauregard * 3065dfd244aSDaniel Beauregard * BIT 16 = Enable Emulated MSIX 3075dfd244aSDaniel Beauregard * BIT 17 = Reserved 3085dfd244aSDaniel Beauregard * BIT 18 = Enable Alternate Device Number 3095dfd244aSDaniel Beauregard * BIT 19 = Enable Alternate Bus Number 3105dfd244aSDaniel Beauregard * BIT 20 = Enable Translated Address 3115dfd244aSDaniel Beauregard * BIT 21 = Enable VM Security 3125dfd244aSDaniel Beauregard * BIT 22 = Enable Interrupt Handshake 3135dfd244aSDaniel Beauregard * BIT 23 = Enable Multiple Queue 3145dfd244aSDaniel Beauregard * 3155dfd244aSDaniel Beauregard * BIT 24 = IOCB Security 3165dfd244aSDaniel Beauregard * BIT 25 = qos 3175dfd244aSDaniel Beauregard * BIT 26-31 = Reserved 31893c20f26SSukumar Swaminathan */ 31993c20f26SSukumar Swaminathan uint8_t firmware_options_2[4]; 32093c20f26SSukumar Swaminathan 32193c20f26SSukumar Swaminathan /* 32293c20f26SSukumar Swaminathan * BIT 0 = Reserved 32393c20f26SSukumar Swaminathan * BIT 1 = Soft ID only 32493c20f26SSukumar Swaminathan * BIT 2 = Reserved 3255dfd244aSDaniel Beauregard * BIT 3 = disable split completion timeout 32693c20f26SSukumar Swaminathan * BIT 4 = FCP RSP Payload bit 0 32793c20f26SSukumar Swaminathan * BIT 5 = FCP RSP Payload bit 1 32893c20f26SSukumar Swaminathan * BIT 6 = Enable Rec Out-of-Order data frame handling 32993c20f26SSukumar Swaminathan * BIT 7 = Disable Automatic PLOGI on Local Loop 33093c20f26SSukumar Swaminathan * 33193c20f26SSukumar Swaminathan * BIT 8 = Reserved 33293c20f26SSukumar Swaminathan * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 33393c20f26SSukumar Swaminathan * offset handling 33493c20f26SSukumar Swaminathan * BIT 10 = Reserved 33593c20f26SSukumar Swaminathan * BIT 11 = Reserved 33693c20f26SSukumar Swaminathan * BIT 12 = Reserved 33793c20f26SSukumar Swaminathan * BIT 13 = Data Rate bit 0 33893c20f26SSukumar Swaminathan * BIT 14 = Data Rate bit 1 33993c20f26SSukumar Swaminathan * BIT 15 = Data Rate bit 2 3405dfd244aSDaniel Beauregard * 34193c20f26SSukumar Swaminathan * BIT 16 = 75-ohm Termination Select 3425dfd244aSDaniel Beauregard * BIT 17 = Enable Multiple FCFs 3435dfd244aSDaniel Beauregard * BIT 18 = MAC Addressing Mode 3445dfd244aSDaniel Beauregard * BIT 19 = MAC Addressing Mode 3455dfd244aSDaniel Beauregard * BIT 20 = MAC Addressing Mode 3465dfd244aSDaniel Beauregard * BIT 21 = Ethernet Data Rate 3475dfd244aSDaniel Beauregard * BIT 22 = Ethernet Data Rate 3485dfd244aSDaniel Beauregard * BIT 23 = Ethernet Data Rate 3495dfd244aSDaniel Beauregard * 3505dfd244aSDaniel Beauregard * BIT 24 = Ethernet Data Rate 3515dfd244aSDaniel Beauregard * BIT 25 = Ethernet Data Rate 3525dfd244aSDaniel Beauregard * BIT 26 = Enable Ethernet Header ATIO Queue 3535dfd244aSDaniel Beauregard * BIT 27 = Enable Ethernet Header Response Queue 3545dfd244aSDaniel Beauregard * BIT 28 = SPMA Selection 3555dfd244aSDaniel Beauregard * BIT 29 = SPMA Selection 3565dfd244aSDaniel Beauregard * BIT 30 = Reserved 3575dfd244aSDaniel Beauregard * BIT 31 = Reserved 35893c20f26SSukumar Swaminathan */ 35993c20f26SSukumar Swaminathan uint8_t firmware_options_3[4]; 36093c20f26SSukumar Swaminathan 3615dfd244aSDaniel Beauregard union { 3625dfd244aSDaniel Beauregard struct { 36393c20f26SSukumar Swaminathan /* 3645dfd244aSDaniel Beauregard * Offset 56 (38h) 3655dfd244aSDaniel Beauregard * Serial Link Control 36693c20f26SSukumar Swaminathan * BIT 0 = control enable 36793c20f26SSukumar Swaminathan * BIT 1-15 = Reserved 36893c20f26SSukumar Swaminathan */ 36993c20f26SSukumar Swaminathan uint8_t swing_opt[2]; 37093c20f26SSukumar Swaminathan /* 3715dfd244aSDaniel Beauregard * Offset 58 (3Ah) 3725dfd244aSDaniel Beauregard * Serial Link Control 1G 37393c20f26SSukumar Swaminathan * BIT 0-7 = Reserved 37493c20f26SSukumar Swaminathan * 37593c20f26SSukumar Swaminathan * BIT 8-10 = output swing 37693c20f26SSukumar Swaminathan * BIT 11-13 = output emphasis 37793c20f26SSukumar Swaminathan * BIT 14-15 = Reserved 37893c20f26SSukumar Swaminathan */ 37993c20f26SSukumar Swaminathan uint8_t swing_1g[2]; 38093c20f26SSukumar Swaminathan /* 3815dfd244aSDaniel Beauregard * Offset 60 (3Ch) 3825dfd244aSDaniel Beauregard * Serial Link Control 2G 38393c20f26SSukumar Swaminathan * BIT 0-7 = Reserved 38493c20f26SSukumar Swaminathan * 38593c20f26SSukumar Swaminathan * BIT 8-10 = output swing 38693c20f26SSukumar Swaminathan * BIT 11-13 = output emphasis 38793c20f26SSukumar Swaminathan * BIT 14-15 = Reserved 38893c20f26SSukumar Swaminathan */ 38993c20f26SSukumar Swaminathan uint8_t swing_2g[2]; 39093c20f26SSukumar Swaminathan /* 3915dfd244aSDaniel Beauregard * Offset 62 (3Eh) 3925dfd244aSDaniel Beauregard * Serial Link Control 4G 39393c20f26SSukumar Swaminathan * BIT 0-7 = Reserved 39493c20f26SSukumar Swaminathan * 39593c20f26SSukumar Swaminathan * BIT 8-10 = output swing 39693c20f26SSukumar Swaminathan * BIT 11-13 = output emphasis 39793c20f26SSukumar Swaminathan * BIT 14-15 = Reserved 39893c20f26SSukumar Swaminathan */ 39993c20f26SSukumar Swaminathan uint8_t swing_4g[2]; 40093c20f26SSukumar Swaminathan 4015dfd244aSDaniel Beauregard /* Offset 64 (40h). */ 4025dfd244aSDaniel Beauregard uint8_t reserved[32]; 4035dfd244aSDaniel Beauregard } isp2400; 4045dfd244aSDaniel Beauregard struct { 4055dfd244aSDaniel Beauregard /* 4065dfd244aSDaniel Beauregard * Offset 56 (38h) 4075dfd244aSDaniel Beauregard * Serial Link Control 4085dfd244aSDaniel Beauregard * BIT 0 = Reserved 4095dfd244aSDaniel Beauregard * BIT 1 = 25xx TX control enable 4105dfd244aSDaniel Beauregard * BIT 2 = 25xx RX control enable (lmtg) 4115dfd244aSDaniel Beauregard * BIT 3 = 25xx RX control enable (linear) 4125dfd244aSDaniel Beauregard * BIT 4 = embedded HBA 4135dfd244aSDaniel Beauregard * BIT 5 = unused 4145dfd244aSDaniel Beauregard * BIT 6 = 25xx E7 Addr27 Preset 4155dfd244aSDaniel Beauregard * BIT 7 = 25xx E6 Addr0 Ch0 enable 4165dfd244aSDaniel Beauregard * 4175dfd244aSDaniel Beauregard * BIT 8-15 = 25xx E6 Addr0 Ch0 4185dfd244aSDaniel Beauregard * 4195dfd244aSDaniel Beauregard * BIT 16-31 = Reserved 4205dfd244aSDaniel Beauregard */ 4215dfd244aSDaniel Beauregard uint8_t swing_opt[4]; 42293c20f26SSukumar Swaminathan 4235dfd244aSDaniel Beauregard /* 4245dfd244aSDaniel Beauregard * Offset 60 (3Ch) 4255dfd244aSDaniel Beauregard * Serial Link TX Parameters 4265dfd244aSDaniel Beauregard * BIT 0 = TX Amplitude 4275dfd244aSDaniel Beauregard * BIT 1 = TX Amplitude 4285dfd244aSDaniel Beauregard * BIT 2 = TX Amplitude 4295dfd244aSDaniel Beauregard * BIT 3 = TX Amplitude 4305dfd244aSDaniel Beauregard * BIT 4 = TX Amplitude 4315dfd244aSDaniel Beauregard * BIT 5 = TX iPost 4325dfd244aSDaniel Beauregard * BIT 6 = TX iPost 4335dfd244aSDaniel Beauregard * BIT 7 = TX iPost 4345dfd244aSDaniel Beauregard * 4355dfd244aSDaniel Beauregard * BIT 8 = TX iPost 4365dfd244aSDaniel Beauregard * BIT 9 = TX iPre 4375dfd244aSDaniel Beauregard * BIT 10 = TX iPre 4385dfd244aSDaniel Beauregard * BIT 11 = TX iPre 4395dfd244aSDaniel Beauregard * BIT 12 = TX iPre 4405dfd244aSDaniel Beauregard * BIT 13 = TX iMain 4415dfd244aSDaniel Beauregard * BIT 14 = TX iMain 4425dfd244aSDaniel Beauregard * BIT 15 = TX iMain 4435dfd244aSDaniel Beauregard * 4445dfd244aSDaniel Beauregard * BIT 16 = TX iMain 4455dfd244aSDaniel Beauregard * BIT 17 = TX iMain 4465dfd244aSDaniel Beauregard * BIT 18-23 = Reserved 4475dfd244aSDaniel Beauregard * 4485dfd244aSDaniel Beauregard * BIT 24-31 = Reserved 4495dfd244aSDaniel Beauregard */ 4505dfd244aSDaniel Beauregard uint8_t tx_8g[4]; 4515dfd244aSDaniel Beauregard /* Offset 64 (40h) */ 4525dfd244aSDaniel Beauregard uint8_t tx_4g[4]; 4535dfd244aSDaniel Beauregard /* Offset 68 (44h) */ 4545dfd244aSDaniel Beauregard uint8_t tx_2g[4]; 45593c20f26SSukumar Swaminathan 4565dfd244aSDaniel Beauregard /* 4575dfd244aSDaniel Beauregard * Offset 72 (48h) 4585dfd244aSDaniel Beauregard * Serial Link RX Parameters 4595dfd244aSDaniel Beauregard * BIT 0 = RX Z1Cnt 4605dfd244aSDaniel Beauregard * BIT 1 = RX Z1Cnt 4615dfd244aSDaniel Beauregard * BIT 2 = RX Z1Cnt 4625dfd244aSDaniel Beauregard * BIT 3 = RX Z1Cnt 4635dfd244aSDaniel Beauregard * BIT 4 = RX G1Cnt 4645dfd244aSDaniel Beauregard * BIT 5 = RX ZCnt 4655dfd244aSDaniel Beauregard * BIT 6 = RX ZCnt 4665dfd244aSDaniel Beauregard * BIT 7 = RX ZCnt 4675dfd244aSDaniel Beauregard * 4685dfd244aSDaniel Beauregard * BIT 8 = RX ZCnt 4695dfd244aSDaniel Beauregard * BIT 9 = RX ZCnt 4705dfd244aSDaniel Beauregard * BIT 10 = RX TLTH 4715dfd244aSDaniel Beauregard * BIT 11 = RX TLTH 4725dfd244aSDaniel Beauregard * BIT 12 = RX TLTH 4735dfd244aSDaniel Beauregard * BIT 13 = RX TLTH 4745dfd244aSDaniel Beauregard * BIT 14 = RX TLTH 4755dfd244aSDaniel Beauregard * BIT 15 = RX TLTH 4765dfd244aSDaniel Beauregard * 4775dfd244aSDaniel Beauregard * BIT 16 = RX DFELTH 4785dfd244aSDaniel Beauregard * BIT 17 = RX DFELTH 4795dfd244aSDaniel Beauregard * BIT 18 = RX DFELTH 4805dfd244aSDaniel Beauregard * BIT 19 = RX DFELTH 4815dfd244aSDaniel Beauregard * BIT 20 = RX DFELTH 4825dfd244aSDaniel Beauregard * BIT 21 = RX DFELTH 4835dfd244aSDaniel Beauregard * BIT 22-23 = Reserved 4845dfd244aSDaniel Beauregard * 4855dfd244aSDaniel Beauregard * BIT 24-31 = Reserved 4865dfd244aSDaniel Beauregard */ 4875dfd244aSDaniel Beauregard uint8_t rx_limit_8g[4]; 4885dfd244aSDaniel Beauregard /* Offset 76 (4Ch) */ 4895dfd244aSDaniel Beauregard uint8_t rx_limit_4g[4]; 4905dfd244aSDaniel Beauregard /* Offset 80 (50h) */ 4915dfd244aSDaniel Beauregard uint8_t rx_limit_2g[4]; 4925dfd244aSDaniel Beauregard /* Offset 84 (54h) */ 4935dfd244aSDaniel Beauregard uint8_t rx_linear_8g[4]; 4945dfd244aSDaniel Beauregard /* Offset 88 (58h) */ 4955dfd244aSDaniel Beauregard uint8_t rx_linear_4g[4]; 4965dfd244aSDaniel Beauregard /* Offset 92 (5Ch) */ 4975dfd244aSDaniel Beauregard uint8_t rx_linear_2g[4]; 4985dfd244aSDaniel Beauregard } isp2500; 4995dfd244aSDaniel Beauregard struct { 5005dfd244aSDaniel Beauregard /* Offset 56 (38h) */ 5015dfd244aSDaniel Beauregard uint8_t reserved[8]; 50293c20f26SSukumar Swaminathan 5035dfd244aSDaniel Beauregard /* Offset 64 (40h). */ 5045dfd244aSDaniel Beauregard uint8_t e_node_mac_addr[6]; 5055dfd244aSDaniel Beauregard 5065dfd244aSDaniel Beauregard /* Offset 70 (46h). */ 5075dfd244aSDaniel Beauregard uint8_t reserved2[26]; 5085dfd244aSDaniel Beauregard } isp8001; 5095dfd244aSDaniel Beauregard } fw; 5105dfd244aSDaniel Beauregard 5115dfd244aSDaniel Beauregard /* 5125dfd244aSDaniel Beauregard * Offset 96 (60h) 5135dfd244aSDaniel Beauregard * BIT 0 = initiator op 5145dfd244aSDaniel Beauregard * BIT 1 = target op 5155dfd244aSDaniel Beauregard * BIT 2 = VI op 5165dfd244aSDaniel Beauregard * BIT 3-7 = Reserved 5175dfd244aSDaniel Beauregard */ 5185dfd244aSDaniel Beauregard uint8_t oem_specific; 5195dfd244aSDaniel Beauregard uint8_t reserved_4[15]; 5205dfd244aSDaniel Beauregard 521*4c3888b8SHans Rosenfeld /* 522*4c3888b8SHans Rosenfeld * Offset 112 (70h). 523*4c3888b8SHans Rosenfeld * BIT 0 = additional receive credits 524*4c3888b8SHans Rosenfeld * BIT 1 = additional receive credits 525*4c3888b8SHans Rosenfeld * BIT 2-15 = Reserved 526*4c3888b8SHans Rosenfeld */ 527*4c3888b8SHans Rosenfeld uint8_t execute_fw_options[2]; 528*4c3888b8SHans Rosenfeld uint8_t reserved_5[14]; 5295dfd244aSDaniel Beauregard 5305dfd244aSDaniel Beauregard /* 5315dfd244aSDaniel Beauregard * Offset 128 (80h). 5325dfd244aSDaniel Beauregard * PCIe table entries. 5335dfd244aSDaniel Beauregard * Firmware Extended Initialization Control Block. 5345dfd244aSDaniel Beauregard */ 5355dfd244aSDaniel Beauregard ql_ext_icb_8100_t ext_blk; 53693c20f26SSukumar Swaminathan 53793c20f26SSukumar Swaminathan /* Offset 192. */ 53893c20f26SSukumar Swaminathan uint8_t reserved_6[32]; 53993c20f26SSukumar Swaminathan 54093c20f26SSukumar Swaminathan /* Offset 224. */ 54193c20f26SSukumar Swaminathan uint8_t reserved_7[32]; 54293c20f26SSukumar Swaminathan 54393c20f26SSukumar Swaminathan /* 54493c20f26SSukumar Swaminathan * BIT 0 = Enable spinup delay 54593c20f26SSukumar Swaminathan * BIT 1 = Disable BIOS 54693c20f26SSukumar Swaminathan * BIT 2 = Enable Memory Map BIOS 54793c20f26SSukumar Swaminathan * BIT 3 = Enable Selectable Boot 54893c20f26SSukumar Swaminathan * BIT 4 = Disable RISC code load 54993c20f26SSukumar Swaminathan * BIT 5 = Disable serdes 55093c20f26SSukumar Swaminathan * BIT 6 = Enable opt boot mode 55193c20f26SSukumar Swaminathan * BIT 7 = Enable int mode BIOS 55293c20f26SSukumar Swaminathan * 5535dfd244aSDaniel Beauregard * BIT 8 = EV control enable 5545dfd244aSDaniel Beauregard * BIT 9 = Enable lip reset 55593c20f26SSukumar Swaminathan * BIT 10 = Enable lip full login 55693c20f26SSukumar Swaminathan * BIT 11 = Enable target reset 5575dfd244aSDaniel Beauregard * BIT 12 = Stop firmware 55893c20f26SSukumar Swaminathan * BIT 13 = Default Node Name Option 5595dfd244aSDaniel Beauregard * BIT 14 = Default WWPN valid 56093c20f26SSukumar Swaminathan * BIT 15 = Enable alternate WWN 56193c20f26SSukumar Swaminathan * 5625dfd244aSDaniel Beauregard * CLP BIOS flags 5635dfd244aSDaniel Beauregard * 5645dfd244aSDaniel Beauregard * BIT 16 = clp lun string 5655dfd244aSDaniel Beauregard * BIT 17 = clp target string 5665dfd244aSDaniel Beauregard * BIT 18 = clp bios enable string 5675dfd244aSDaniel Beauregard * BIT 19 = clp serdes_string 5685dfd244aSDaniel Beauregard * BIT 20 = clp wwpn string 5695dfd244aSDaniel Beauregard * BIT 21 = clp wwnn string 5705dfd244aSDaniel Beauregard * BIT 22 = win reserverd 0 5715dfd244aSDaniel Beauregard * BIT 23 = win reserverd 1 5725dfd244aSDaniel Beauregard * 5735dfd244aSDaniel Beauregard * BIT 24 = keep wwpn 5745dfd244aSDaniel Beauregard * BIT 25 = temp wwpn 5755dfd244aSDaniel Beauregard * BIT 26 = win reserverd 2 5765dfd244aSDaniel Beauregard * BIT 27 = win reserverd 3 5775dfd244aSDaniel Beauregard * BIT 28 = clear WBT in flash (win driver) 5785dfd244aSDaniel Beauregard * BIT 29 = write WBT in flash (win driver) 5795dfd244aSDaniel Beauregard * BIT 30 = load fw from flash (win driver) 5805dfd244aSDaniel Beauregard * BIT 31 = enable alternate WWN (win driver) 58193c20f26SSukumar Swaminathan */ 58293c20f26SSukumar Swaminathan uint8_t host_p[4]; 58393c20f26SSukumar Swaminathan 58493c20f26SSukumar Swaminathan uint8_t alternate_port_name[8]; 58593c20f26SSukumar Swaminathan uint8_t alternate_node_name[8]; 58693c20f26SSukumar Swaminathan 58793c20f26SSukumar Swaminathan uint8_t boot_port_name[8]; 58893c20f26SSukumar Swaminathan uint8_t boot_lun_number[2]; 58993c20f26SSukumar Swaminathan uint8_t reserved_8[2]; 59093c20f26SSukumar Swaminathan 59193c20f26SSukumar Swaminathan uint8_t alt1_boot_port_name[8]; 59293c20f26SSukumar Swaminathan uint8_t alt1_boot_lun_number[2]; 59393c20f26SSukumar Swaminathan uint8_t reserved_9[2]; 59493c20f26SSukumar Swaminathan 59593c20f26SSukumar Swaminathan uint8_t alt2_boot_port_name[8]; 59693c20f26SSukumar Swaminathan uint8_t alt2_boot_lun_number[2]; 59793c20f26SSukumar Swaminathan uint8_t reserved_10[2]; 59893c20f26SSukumar Swaminathan 59993c20f26SSukumar Swaminathan uint8_t alt3_boot_port_name[8]; 60093c20f26SSukumar Swaminathan uint8_t alt3_boot_lun_number[2]; 60193c20f26SSukumar Swaminathan uint8_t reserved_11[2]; 60293c20f26SSukumar Swaminathan 60393c20f26SSukumar Swaminathan /* 60493c20f26SSukumar Swaminathan * BIT 0 = Selective Login 60593c20f26SSukumar Swaminathan * BIT 1 = Alt-Boot Enable 60693c20f26SSukumar Swaminathan * BIT 2 = Reserved 60793c20f26SSukumar Swaminathan * BIT 3 = Enable Boot Order List 60893c20f26SSukumar Swaminathan * BIT 4 = Reserved 60993c20f26SSukumar Swaminathan * BIT 5 = Enable Selective LUN 61093c20f26SSukumar Swaminathan * BIT 6 = Reserved 61193c20f26SSukumar Swaminathan * BIT 7-31 = 61293c20f26SSukumar Swaminathan */ 61393c20f26SSukumar Swaminathan uint8_t efi_parameters[4]; 61493c20f26SSukumar Swaminathan 61593c20f26SSukumar Swaminathan uint8_t reset_delay; 61693c20f26SSukumar Swaminathan uint8_t reserved_12; 61793c20f26SSukumar Swaminathan uint8_t reserved_13[2]; 61893c20f26SSukumar Swaminathan 61993c20f26SSukumar Swaminathan uint8_t boot_id_number[2]; 62093c20f26SSukumar Swaminathan uint8_t reserved_14[2]; 62193c20f26SSukumar Swaminathan 62293c20f26SSukumar Swaminathan uint8_t max_luns_per_target[2]; 62393c20f26SSukumar Swaminathan uint8_t reserved_15[2]; 62493c20f26SSukumar Swaminathan 62593c20f26SSukumar Swaminathan uint8_t port_down_retry_count[2]; 62693c20f26SSukumar Swaminathan uint8_t link_down_timeout[2]; 62793c20f26SSukumar Swaminathan 62893c20f26SSukumar Swaminathan /* 62993c20f26SSukumar Swaminathan * FCode parameters word (offset 344) 63093c20f26SSukumar Swaminathan * 63193c20f26SSukumar Swaminathan * BIT 0 = Enable BIOS pathname 63293c20f26SSukumar Swaminathan * BIT 1 = fcode qlc 63393c20f26SSukumar Swaminathan * BIT 2 = fcode host 6345dfd244aSDaniel Beauregard * BIT 3 = fcode sunid 6355dfd244aSDaniel Beauregard * BIT 4-7 = 63693c20f26SSukumar Swaminathan */ 63793c20f26SSukumar Swaminathan uint8_t fcode_p0; 63893c20f26SSukumar Swaminathan uint8_t reserved_16[7]; 63993c20f26SSukumar Swaminathan 6405dfd244aSDaniel Beauregard /* 6415dfd244aSDaniel Beauregard * Offset 352 (160h). 6425dfd244aSDaniel Beauregard * uint8_t prev_drv_ver_major; 6435dfd244aSDaniel Beauregard * uint8_t prev_drv_ver_submajob; 6445dfd244aSDaniel Beauregard * uint8_t prev_drv_ver_minor; 6455dfd244aSDaniel Beauregard * uint8_t prev_drv_ver_subminor; 6465dfd244aSDaniel Beauregard * uint8_t prev_bios_ver_major[2]; 6475dfd244aSDaniel Beauregard * uint8_t prev_bios_ver_minor[2]; 6485dfd244aSDaniel Beauregard * uint8_t prev_efi_ver_major[2]; 6495dfd244aSDaniel Beauregard * uint8_t prev_efi_ver_minor[2]; 6505dfd244aSDaniel Beauregard * uint8_t prev_fw_ver_major[2]; 6515dfd244aSDaniel Beauregard * uint8_t prev_fw_ver_minor; 6525dfd244aSDaniel Beauregard * uint8_t prev_fw_ver_subminor; 6535dfd244aSDaniel Beauregard * uint8_t reserved[16]; 6545dfd244aSDaniel Beauregard */ 6555dfd244aSDaniel Beauregard uint8_t mac_address[6]; 6565dfd244aSDaniel Beauregard uint8_t clp_flag[2]; 6575dfd244aSDaniel Beauregard uint8_t reserved_18[24]; 65893c20f26SSukumar Swaminathan 6595dfd244aSDaniel Beauregard /* Offset 384 (180h). */ 66093c20f26SSukumar Swaminathan uint8_t def_port_name[8]; 66193c20f26SSukumar Swaminathan uint8_t def_node_name[8]; 6625dfd244aSDaniel Beauregard uint8_t clp_flag1[2]; 6635dfd244aSDaniel Beauregard uint8_t clp_flag2[2]; 66493c20f26SSukumar Swaminathan 6655dfd244aSDaniel Beauregard /* Offset 404 (194h). */ 6665dfd244aSDaniel Beauregard uint8_t default_firmware_options[2]; 66793c20f26SSukumar Swaminathan 6685dfd244aSDaniel Beauregard /* Offset 406 (196h). */ 6695dfd244aSDaniel Beauregard uint8_t enhanced_features[2]; 6705dfd244aSDaniel Beauregard uint8_t serdes_index[2]; 6715dfd244aSDaniel Beauregard uint8_t reserved_19[6]; 67293c20f26SSukumar Swaminathan 6735dfd244aSDaniel Beauregard /* Offset 416 (1A0h). */ 6745dfd244aSDaniel Beauregard uint8_t alt4_boot_port_name[8]; 6755dfd244aSDaniel Beauregard uint8_t alt4_boot_lun_number[2]; 6765dfd244aSDaniel Beauregard uint8_t reserved_20[2]; 67793c20f26SSukumar Swaminathan 6785dfd244aSDaniel Beauregard /* Offset 428 (1ACh). */ 6795dfd244aSDaniel Beauregard uint8_t alt5_boot_port_name[8]; 6805dfd244aSDaniel Beauregard uint8_t alt5_boot_lun_number[2]; 6815dfd244aSDaniel Beauregard uint8_t reserved_21[2]; 6825dfd244aSDaniel Beauregard 6835dfd244aSDaniel Beauregard /* Offset 440 (1B8h). */ 6845dfd244aSDaniel Beauregard uint8_t alt6_boot_port_name[8]; 6855dfd244aSDaniel Beauregard uint8_t alt6_boot_lun_number[2]; 6865dfd244aSDaniel Beauregard uint8_t reserved_22[2]; 6875dfd244aSDaniel Beauregard 6885dfd244aSDaniel Beauregard /* Offset 452 (1C4h). */ 6895dfd244aSDaniel Beauregard uint8_t alt7_boot_port_name[8]; 6905dfd244aSDaniel Beauregard uint8_t alt7_boot_lun_number[2]; 6915dfd244aSDaniel Beauregard uint8_t reserved_23[2]; 6925dfd244aSDaniel Beauregard 6935dfd244aSDaniel Beauregard /* Offset 464 (1D0h). */ 6945dfd244aSDaniel Beauregard uint8_t reserved_24[12]; 6955dfd244aSDaniel Beauregard 6965dfd244aSDaniel Beauregard /* Offset 476 (1DCh). */ 69793c20f26SSukumar Swaminathan uint8_t fw_table_offset[2]; 69893c20f26SSukumar Swaminathan uint8_t fw_table_sig[2]; 69993c20f26SSukumar Swaminathan 7005dfd244aSDaniel Beauregard /* Offset 480 (1E0h). */ 7015dfd244aSDaniel Beauregard int8_t model_name[4]; 7025dfd244aSDaniel Beauregard int8_t model_name1[12]; /* 24xx power_table[8]. */ 70393c20f26SSukumar Swaminathan 7045dfd244aSDaniel Beauregard /* Offset 496 (1F0h). */ 7055dfd244aSDaniel Beauregard uint8_t feature_mask_l[2]; 7065dfd244aSDaniel Beauregard uint8_t feature_mask_h[2]; 7075dfd244aSDaniel Beauregard uint8_t reserved_25[4]; 70893c20f26SSukumar Swaminathan 7095dfd244aSDaniel Beauregard /* Offset 504 (1F8h). */ 71093c20f26SSukumar Swaminathan uint8_t subsystem_vendor_id[2]; 71193c20f26SSukumar Swaminathan uint8_t subsystem_device_id[2]; 71293c20f26SSukumar Swaminathan 71393c20f26SSukumar Swaminathan uint8_t checksum[4]; 71493c20f26SSukumar Swaminathan } nvram_24xx_t; 71593c20f26SSukumar Swaminathan 71693c20f26SSukumar Swaminathan /* 71793c20f26SSukumar Swaminathan * Firmware Dump structure definition 71893c20f26SSukumar Swaminathan */ 719*4c3888b8SHans Rosenfeld #define QL_2200_FW_DUMP_SIZE 0x100000 /* 86e15 bytes */ 720*4c3888b8SHans Rosenfeld #define QL_2300_FW_DUMP_SIZE 0x100000 /* fc6d3 bytes */ 721*4c3888b8SHans Rosenfeld #define QL_6322_FW_DUMP_SIZE 0x100000 /* fc6d8 bytes */ 722*4c3888b8SHans Rosenfeld #define QL_24XX_FW_DUMP_SIZE 0x300000 /* 2cef71 bytes */ 723*4c3888b8SHans Rosenfeld #define QL_25XX_FW_DUMP_SIZE 0x400000 /* 356c97 bytes */ 724*4c3888b8SHans Rosenfeld #define QL_81XX_FW_DUMP_SIZE 0x400000 /* 356c97 bytes */ 725*4c3888b8SHans Rosenfeld #define QL_27XX_FW_DUMP_SIZE 0x600000 /* 5c3e69 bytes */ 726*4c3888b8SHans Rosenfeld #define QL_83XX_FW_DUMP_SIZE 0x400000 /* 372792 bytes */ 72793c20f26SSukumar Swaminathan 72893c20f26SSukumar Swaminathan #define QL_24XX_VPD_SIZE 0x200 /* bytes */ 72993c20f26SSukumar Swaminathan #define QL_24XX_SFP_SIZE 0x200 /* bytes */ 73093c20f26SSukumar Swaminathan 73193c20f26SSukumar Swaminathan /* 73293c20f26SSukumar Swaminathan * firmware dump struct for 2300 is a superset of firmware dump struct 73393c20f26SSukumar Swaminathan * for 2200. Fields which are 2300 only or are enhanced for 2300 are 73493c20f26SSukumar Swaminathan * marked below. 73593c20f26SSukumar Swaminathan */ 73693c20f26SSukumar Swaminathan typedef struct ql_fw_dump { 73793c20f26SSukumar Swaminathan uint16_t pbiu_reg[8]; 73893c20f26SSukumar Swaminathan uint16_t risc_host_reg[8]; /* 2300 only. */ 73993c20f26SSukumar Swaminathan uint16_t mailbox_reg[16]; /* 2200 only needs 8 */ 74093c20f26SSukumar Swaminathan uint16_t resp_dma_reg[32]; /* 2300 only. */ 74193c20f26SSukumar Swaminathan uint16_t dma_reg[48]; 74293c20f26SSukumar Swaminathan uint16_t risc_hdw_reg[16]; 74393c20f26SSukumar Swaminathan uint16_t risc_gp0_reg[16]; 74493c20f26SSukumar Swaminathan uint16_t risc_gp1_reg[16]; 74593c20f26SSukumar Swaminathan uint16_t risc_gp2_reg[16]; 74693c20f26SSukumar Swaminathan uint16_t risc_gp3_reg[16]; 74793c20f26SSukumar Swaminathan uint16_t risc_gp4_reg[16]; 74893c20f26SSukumar Swaminathan uint16_t risc_gp5_reg[16]; 74993c20f26SSukumar Swaminathan uint16_t risc_gp6_reg[16]; 75093c20f26SSukumar Swaminathan uint16_t risc_gp7_reg[16]; 75193c20f26SSukumar Swaminathan uint16_t frame_buf_hdw_reg[64]; /* 2200 has only 16 */ 75293c20f26SSukumar Swaminathan uint16_t fpm_b0_reg[64]; 75393c20f26SSukumar Swaminathan uint16_t fpm_b1_reg[64]; 75493c20f26SSukumar Swaminathan uint16_t risc_ram[0xf800]; /* 2200 needs only 0xf000 */ 75593c20f26SSukumar Swaminathan uint16_t stack_ram[0x800]; /* 2300 only */ 75693c20f26SSukumar Swaminathan uint16_t data_ram[0xf800]; /* 2300 only */ 75716dd44c2SDaniel Beauregard uint32_t req_q[REQUEST_QUEUE_SIZE / 4]; 75816dd44c2SDaniel Beauregard uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4]; 75993c20f26SSukumar Swaminathan } ql_fw_dump_t; 76093c20f26SSukumar Swaminathan 76193c20f26SSukumar Swaminathan typedef struct ql_24xx_fw_dump { 76293c20f26SSukumar Swaminathan uint32_t hccr; 76393c20f26SSukumar Swaminathan uint32_t host_reg[32]; 76493c20f26SSukumar Swaminathan uint16_t mailbox_reg[32]; 76593c20f26SSukumar Swaminathan uint32_t xseq_gp_reg[128]; 76693c20f26SSukumar Swaminathan uint32_t xseq_0_reg[16]; 76793c20f26SSukumar Swaminathan uint32_t xseq_1_reg[16]; 76893c20f26SSukumar Swaminathan uint32_t rseq_gp_reg[128]; 76993c20f26SSukumar Swaminathan uint32_t rseq_0_reg[16]; 77093c20f26SSukumar Swaminathan uint32_t rseq_1_reg[16]; 77193c20f26SSukumar Swaminathan uint32_t rseq_2_reg[16]; 77293c20f26SSukumar Swaminathan uint32_t cmd_dma_reg[16]; 77393c20f26SSukumar Swaminathan uint32_t req0_dma_reg[15]; 77493c20f26SSukumar Swaminathan uint32_t resp0_dma_reg[15]; 77593c20f26SSukumar Swaminathan uint32_t req1_dma_reg[15]; 77693c20f26SSukumar Swaminathan uint32_t xmt0_dma_reg[32]; 77793c20f26SSukumar Swaminathan uint32_t xmt1_dma_reg[32]; 77893c20f26SSukumar Swaminathan uint32_t xmt2_dma_reg[32]; 77993c20f26SSukumar Swaminathan uint32_t xmt3_dma_reg[32]; 78093c20f26SSukumar Swaminathan uint32_t xmt4_dma_reg[32]; 78193c20f26SSukumar Swaminathan uint32_t xmt_data_dma_reg[16]; 78293c20f26SSukumar Swaminathan uint32_t rcvt0_data_dma_reg[32]; 78393c20f26SSukumar Swaminathan uint32_t rcvt1_data_dma_reg[32]; 78493c20f26SSukumar Swaminathan uint32_t risc_gp_reg[128]; 78593c20f26SSukumar Swaminathan uint32_t shadow_reg[7]; 78693c20f26SSukumar Swaminathan uint32_t lmc_reg[112]; 78793c20f26SSukumar Swaminathan uint32_t fpm_hdw_reg[192]; 78893c20f26SSukumar Swaminathan uint32_t fb_hdw_reg[176]; 78993c20f26SSukumar Swaminathan uint32_t code_ram[0x2000]; 79016dd44c2SDaniel Beauregard uint32_t req_q[REQUEST_QUEUE_SIZE / 4]; 79116dd44c2SDaniel Beauregard uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4]; 79216dd44c2SDaniel Beauregard uint32_t ext_trace_buf[FWEXTSIZE / 4]; 79316dd44c2SDaniel Beauregard uint32_t fce_trace_buf[FWFCESIZE / 4]; 79493c20f26SSukumar Swaminathan uint32_t ext_mem[1]; 79593c20f26SSukumar Swaminathan } ql_24xx_fw_dump_t; 79693c20f26SSukumar Swaminathan 79793c20f26SSukumar Swaminathan typedef struct ql_25xx_fw_dump { 798*4c3888b8SHans Rosenfeld uint32_t hccr; 79993c20f26SSukumar Swaminathan uint32_t r2h_status; 800*4c3888b8SHans Rosenfeld uint32_t aer_ues; 80193c20f26SSukumar Swaminathan uint32_t hostrisc_reg[32]; 80293c20f26SSukumar Swaminathan uint32_t pcie_reg[4]; 80393c20f26SSukumar Swaminathan uint32_t host_reg[32]; 80493c20f26SSukumar Swaminathan uint16_t mailbox_reg[32]; 80593c20f26SSukumar Swaminathan uint32_t xseq_gp_reg[128]; 80693c20f26SSukumar Swaminathan uint32_t xseq_0_reg[48]; 80793c20f26SSukumar Swaminathan uint32_t xseq_1_reg[16]; 80893c20f26SSukumar Swaminathan uint32_t rseq_gp_reg[128]; 80993c20f26SSukumar Swaminathan uint32_t rseq_0_reg[32]; 81093c20f26SSukumar Swaminathan uint32_t rseq_1_reg[16]; 81193c20f26SSukumar Swaminathan uint32_t rseq_2_reg[16]; 81293c20f26SSukumar Swaminathan uint32_t aseq_gp_reg[128]; 81393c20f26SSukumar Swaminathan uint32_t aseq_0_reg[32]; 81493c20f26SSukumar Swaminathan uint32_t aseq_1_reg[16]; 81593c20f26SSukumar Swaminathan uint32_t aseq_2_reg[16]; 81693c20f26SSukumar Swaminathan uint32_t cmd_dma_reg[16]; 81793c20f26SSukumar Swaminathan uint32_t req0_dma_reg[15]; 81893c20f26SSukumar Swaminathan uint32_t resp0_dma_reg[15]; 81993c20f26SSukumar Swaminathan uint32_t req1_dma_reg[15]; 82093c20f26SSukumar Swaminathan uint32_t xmt0_dma_reg[32]; 82193c20f26SSukumar Swaminathan uint32_t xmt1_dma_reg[32]; 82293c20f26SSukumar Swaminathan uint32_t xmt2_dma_reg[32]; 82393c20f26SSukumar Swaminathan uint32_t xmt3_dma_reg[32]; 82493c20f26SSukumar Swaminathan uint32_t xmt4_dma_reg[32]; 82593c20f26SSukumar Swaminathan uint32_t xmt_data_dma_reg[16]; 82693c20f26SSukumar Swaminathan uint32_t rcvt0_data_dma_reg[32]; 82793c20f26SSukumar Swaminathan uint32_t rcvt1_data_dma_reg[32]; 82893c20f26SSukumar Swaminathan uint32_t risc_gp_reg[128]; 82993c20f26SSukumar Swaminathan uint32_t shadow_reg[11]; 83093c20f26SSukumar Swaminathan uint32_t risc_io; 83193c20f26SSukumar Swaminathan uint32_t lmc_reg[128]; 83293c20f26SSukumar Swaminathan uint32_t fpm_hdw_reg[192]; 83393c20f26SSukumar Swaminathan uint32_t fb_hdw_reg[192]; 83493c20f26SSukumar Swaminathan uint32_t code_ram[0x2000]; 83516dd44c2SDaniel Beauregard uint32_t ext_trace_buf[FWEXTSIZE / 4]; 83616dd44c2SDaniel Beauregard uint32_t fce_trace_buf[FWFCESIZE / 4]; 837*4c3888b8SHans Rosenfeld uint32_t req_q_size[2]; 838*4c3888b8SHans Rosenfeld uint32_t rsp_q_size; 839*4c3888b8SHans Rosenfeld uint32_t req_rsp_ext_mem[1]; 84093c20f26SSukumar Swaminathan } ql_25xx_fw_dump_t; 84193c20f26SSukumar Swaminathan 842f33c1cdbSDaniel Beauregard typedef struct ql_81xx_fw_dump { 843*4c3888b8SHans Rosenfeld uint32_t hccr; 844f33c1cdbSDaniel Beauregard uint32_t r2h_status; 845*4c3888b8SHans Rosenfeld uint32_t aer_ues; 846f33c1cdbSDaniel Beauregard uint32_t hostrisc_reg[32]; 847f33c1cdbSDaniel Beauregard uint32_t pcie_reg[4]; 848f33c1cdbSDaniel Beauregard uint32_t host_reg[32]; 849f33c1cdbSDaniel Beauregard uint16_t mailbox_reg[32]; 850f33c1cdbSDaniel Beauregard uint32_t xseq_gp_reg[128]; 851f33c1cdbSDaniel Beauregard uint32_t xseq_0_reg[48]; 852f33c1cdbSDaniel Beauregard uint32_t xseq_1_reg[16]; 853f33c1cdbSDaniel Beauregard uint32_t rseq_gp_reg[128]; 854f33c1cdbSDaniel Beauregard uint32_t rseq_0_reg[32]; 855f33c1cdbSDaniel Beauregard uint32_t rseq_1_reg[16]; 856f33c1cdbSDaniel Beauregard uint32_t rseq_2_reg[16]; 857f33c1cdbSDaniel Beauregard uint32_t aseq_gp_reg[128]; 858f33c1cdbSDaniel Beauregard uint32_t aseq_0_reg[32]; 859f33c1cdbSDaniel Beauregard uint32_t aseq_1_reg[16]; 860f33c1cdbSDaniel Beauregard uint32_t aseq_2_reg[16]; 861f33c1cdbSDaniel Beauregard uint32_t cmd_dma_reg[16]; 862f33c1cdbSDaniel Beauregard uint32_t req0_dma_reg[15]; 863f33c1cdbSDaniel Beauregard uint32_t resp0_dma_reg[15]; 864f33c1cdbSDaniel Beauregard uint32_t req1_dma_reg[15]; 865f33c1cdbSDaniel Beauregard uint32_t xmt0_dma_reg[32]; 866f33c1cdbSDaniel Beauregard uint32_t xmt1_dma_reg[32]; 867f33c1cdbSDaniel Beauregard uint32_t xmt2_dma_reg[32]; 868f33c1cdbSDaniel Beauregard uint32_t xmt3_dma_reg[32]; 869f33c1cdbSDaniel Beauregard uint32_t xmt4_dma_reg[32]; 870f33c1cdbSDaniel Beauregard uint32_t xmt_data_dma_reg[16]; 871f33c1cdbSDaniel Beauregard uint32_t rcvt0_data_dma_reg[32]; 872f33c1cdbSDaniel Beauregard uint32_t rcvt1_data_dma_reg[32]; 873f33c1cdbSDaniel Beauregard uint32_t risc_gp_reg[128]; 874f33c1cdbSDaniel Beauregard uint32_t shadow_reg[11]; 875f33c1cdbSDaniel Beauregard uint32_t risc_io; 876f33c1cdbSDaniel Beauregard uint32_t lmc_reg[128]; 877f33c1cdbSDaniel Beauregard uint32_t fpm_hdw_reg[224]; 878f33c1cdbSDaniel Beauregard uint32_t fb_hdw_reg[208]; 879f33c1cdbSDaniel Beauregard uint32_t code_ram[0x2000]; 880f33c1cdbSDaniel Beauregard uint32_t ext_trace_buf[FWEXTSIZE / 4]; 881f33c1cdbSDaniel Beauregard uint32_t fce_trace_buf[FWFCESIZE / 4]; 882*4c3888b8SHans Rosenfeld uint32_t req_q_size[2]; 883*4c3888b8SHans Rosenfeld uint32_t rsp_q_size; 884*4c3888b8SHans Rosenfeld uint32_t req_rsp_ext_mem[1]; 885f33c1cdbSDaniel Beauregard } ql_81xx_fw_dump_t; 886f33c1cdbSDaniel Beauregard 887*4c3888b8SHans Rosenfeld typedef struct ql_83xx_fw_dump { 888*4c3888b8SHans Rosenfeld uint32_t hccr; 889*4c3888b8SHans Rosenfeld uint32_t r2h_status; 890*4c3888b8SHans Rosenfeld uint32_t aer_ues; 891*4c3888b8SHans Rosenfeld uint32_t hostrisc_reg[48]; 892*4c3888b8SHans Rosenfeld uint32_t pcie_reg[4]; 893*4c3888b8SHans Rosenfeld uint32_t host_reg[32]; 894*4c3888b8SHans Rosenfeld uint16_t mailbox_reg[32]; 895*4c3888b8SHans Rosenfeld uint32_t xseq_gp_reg[256]; 896*4c3888b8SHans Rosenfeld uint32_t xseq_0_reg[48]; 897*4c3888b8SHans Rosenfeld uint32_t xseq_1_reg[16]; 898*4c3888b8SHans Rosenfeld uint32_t xseq_2_reg[16]; 899*4c3888b8SHans Rosenfeld uint32_t rseq_gp_reg[256]; 900*4c3888b8SHans Rosenfeld uint32_t rseq_0_reg[32]; 901*4c3888b8SHans Rosenfeld uint32_t rseq_1_reg[16]; 902*4c3888b8SHans Rosenfeld uint32_t rseq_2_reg[16]; 903*4c3888b8SHans Rosenfeld uint32_t rseq_3_reg[16]; 904*4c3888b8SHans Rosenfeld uint32_t aseq_gp_reg[256]; 905*4c3888b8SHans Rosenfeld uint32_t aseq_0_reg[32]; 906*4c3888b8SHans Rosenfeld uint32_t aseq_1_reg[16]; 907*4c3888b8SHans Rosenfeld uint32_t aseq_2_reg[16]; 908*4c3888b8SHans Rosenfeld uint32_t aseq_3_reg[16]; 909*4c3888b8SHans Rosenfeld uint32_t cmd_dma_reg[64]; 910*4c3888b8SHans Rosenfeld uint32_t req0_dma_reg[15]; 911*4c3888b8SHans Rosenfeld uint32_t resp0_dma_reg[15]; 912*4c3888b8SHans Rosenfeld uint32_t req1_dma_reg[15]; 913*4c3888b8SHans Rosenfeld uint32_t xmt0_dma_reg[32]; 914*4c3888b8SHans Rosenfeld uint32_t xmt1_dma_reg[32]; 915*4c3888b8SHans Rosenfeld uint32_t xmt2_dma_reg[32]; 916*4c3888b8SHans Rosenfeld uint32_t xmt3_dma_reg[32]; 917*4c3888b8SHans Rosenfeld uint32_t xmt4_dma_reg[32]; 918*4c3888b8SHans Rosenfeld uint32_t xmt_data_dma_reg[16]; 919*4c3888b8SHans Rosenfeld uint32_t rcvt0_data_dma_reg[32]; 920*4c3888b8SHans Rosenfeld uint32_t rcvt1_data_dma_reg[32]; 921*4c3888b8SHans Rosenfeld uint32_t risc_gp_reg[128]; 922*4c3888b8SHans Rosenfeld uint32_t shadow_reg[11]; 923*4c3888b8SHans Rosenfeld uint32_t risc_io; 924*4c3888b8SHans Rosenfeld uint32_t lmc_reg[128]; 925*4c3888b8SHans Rosenfeld uint32_t fpm_hdw_reg[256]; 926*4c3888b8SHans Rosenfeld uint32_t rq0_array_reg[256]; 927*4c3888b8SHans Rosenfeld uint32_t rq1_array_reg[256]; 928*4c3888b8SHans Rosenfeld uint32_t rp0_array_reg[256]; 929*4c3888b8SHans Rosenfeld uint32_t rp1_array_reg[256]; 930*4c3888b8SHans Rosenfeld uint32_t ato_array_reg[128]; 931*4c3888b8SHans Rosenfeld uint32_t queue_control_reg[16]; 932*4c3888b8SHans Rosenfeld uint32_t fb_hdw_reg[432]; 933*4c3888b8SHans Rosenfeld uint32_t code_ram[0x2400]; 934*4c3888b8SHans Rosenfeld uint32_t ext_trace_buf[FWEXTSIZE / 4]; 935*4c3888b8SHans Rosenfeld uint32_t fce_trace_buf[FWFCESIZE / 4]; 936*4c3888b8SHans Rosenfeld uint32_t req_q_size[2]; 937*4c3888b8SHans Rosenfeld uint32_t rsp_q_size; 938*4c3888b8SHans Rosenfeld uint32_t req_rsp_ext_mem[1]; 939*4c3888b8SHans Rosenfeld } ql_83xx_fw_dump_t; 940*4c3888b8SHans Rosenfeld 94193c20f26SSukumar Swaminathan #ifdef _KERNEL 94293c20f26SSukumar Swaminathan 94393c20f26SSukumar Swaminathan /* 944*4c3888b8SHans Rosenfeld * firmware dump Entry Types 945*4c3888b8SHans Rosenfeld */ 946*4c3888b8SHans Rosenfeld #define DT_NOP 0 947*4c3888b8SHans Rosenfeld #define DT_THDR 99 948*4c3888b8SHans Rosenfeld #define DT_TEND 255 949*4c3888b8SHans Rosenfeld #define DT_RIOB1 256 950*4c3888b8SHans Rosenfeld #define DT_WIOB1 257 951*4c3888b8SHans Rosenfeld #define DT_RIOB2 258 952*4c3888b8SHans Rosenfeld #define DT_WIOB2 259 953*4c3888b8SHans Rosenfeld #define DT_RPCI 260 954*4c3888b8SHans Rosenfeld #define DT_WPCI 261 955*4c3888b8SHans Rosenfeld #define DT_RRAM 262 956*4c3888b8SHans Rosenfeld #define DT_GQUE 263 957*4c3888b8SHans Rosenfeld #define DT_GFCE 264 958*4c3888b8SHans Rosenfeld #define DT_PRISC 265 959*4c3888b8SHans Rosenfeld #define DT_RRISC 266 960*4c3888b8SHans Rosenfeld #define DT_DINT 267 961*4c3888b8SHans Rosenfeld #define DT_GHBD 268 962*4c3888b8SHans Rosenfeld #define DT_SCRA 269 963*4c3888b8SHans Rosenfeld #define DT_RRREG 270 964*4c3888b8SHans Rosenfeld #define DT_WRREG 271 965*4c3888b8SHans Rosenfeld #define DT_RRRAM 272 966*4c3888b8SHans Rosenfeld #define DT_RPCIC 273 967*4c3888b8SHans Rosenfeld #define DT_GQUES 274 968*4c3888b8SHans Rosenfeld #define DT_WDMP 275 969*4c3888b8SHans Rosenfeld 970*4c3888b8SHans Rosenfeld /* 971*4c3888b8SHans Rosenfeld * firmware dump Template Header (Entry Type 99) 972*4c3888b8SHans Rosenfeld */ 973*4c3888b8SHans Rosenfeld typedef struct ql_dt_hdr { 974*4c3888b8SHans Rosenfeld uint32_t type; 975*4c3888b8SHans Rosenfeld uint32_t first_entry_offset; 976*4c3888b8SHans Rosenfeld uint32_t size_of_template; 977*4c3888b8SHans Rosenfeld uint32_t rsv; 978*4c3888b8SHans Rosenfeld uint32_t num_of_entries; 979*4c3888b8SHans Rosenfeld uint32_t version; 980*4c3888b8SHans Rosenfeld uint32_t driver_timestamp; 981*4c3888b8SHans Rosenfeld uint32_t checksum; 982*4c3888b8SHans Rosenfeld uint32_t rsv_1; 983*4c3888b8SHans Rosenfeld uint32_t driver_info[3]; 984*4c3888b8SHans Rosenfeld uint32_t saved_state_area[16]; 985*4c3888b8SHans Rosenfeld uint32_t rsv_2[8]; 986*4c3888b8SHans Rosenfeld uint32_t ver_attr[5]; 987*4c3888b8SHans Rosenfeld } ql_dt_hdr_t; 988*4c3888b8SHans Rosenfeld 989*4c3888b8SHans Rosenfeld /* 990*4c3888b8SHans Rosenfeld * firmware dump Common Entry Header 991*4c3888b8SHans Rosenfeld */ 992*4c3888b8SHans Rosenfeld typedef struct ql_dt_entry_hdr { 993*4c3888b8SHans Rosenfeld uint32_t type; 994*4c3888b8SHans Rosenfeld uint32_t size; 995*4c3888b8SHans Rosenfeld uint32_t rsv; 996*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 997*4c3888b8SHans Rosenfeld uint8_t driver_flags; 998*4c3888b8SHans Rosenfeld uint8_t rsv_2; 999*4c3888b8SHans Rosenfeld uint8_t rsv_1; 1000*4c3888b8SHans Rosenfeld uint8_t capture_flags; 1001*4c3888b8SHans Rosenfeld #else 1002*4c3888b8SHans Rosenfeld uint8_t capture_flags; 1003*4c3888b8SHans Rosenfeld uint8_t rsv_1; 1004*4c3888b8SHans Rosenfeld uint8_t rsv_2; 1005*4c3888b8SHans Rosenfeld uint8_t driver_flags; 1006*4c3888b8SHans Rosenfeld #endif 1007*4c3888b8SHans Rosenfeld } ql_dt_entry_hdr_t; 1008*4c3888b8SHans Rosenfeld 1009*4c3888b8SHans Rosenfeld /* 1010*4c3888b8SHans Rosenfeld * Capture Flags 1011*4c3888b8SHans Rosenfeld */ 1012*4c3888b8SHans Rosenfeld #define PF_ONLY_FLAG BIT_0 /* Physical Function Only */ 1013*4c3888b8SHans Rosenfeld #define PF_VF_FLAG BIT_1 /* Physical and Virtual Functions */ 1014*4c3888b8SHans Rosenfeld 1015*4c3888b8SHans Rosenfeld /* 1016*4c3888b8SHans Rosenfeld * Driver Flags 1017*4c3888b8SHans Rosenfeld */ 1018*4c3888b8SHans Rosenfeld #define SKIPPED_FLAG BIT_7 /* driver skipped this entry */ 1019*4c3888b8SHans Rosenfeld 1020*4c3888b8SHans Rosenfeld /* 1021*4c3888b8SHans Rosenfeld * firmware dump Entry Including Header 1022*4c3888b8SHans Rosenfeld */ 1023*4c3888b8SHans Rosenfeld typedef struct ql_dt_entry { 1024*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1025*4c3888b8SHans Rosenfeld uint32_t data[1]; 1026*4c3888b8SHans Rosenfeld } ql_dt_entry_t; 1027*4c3888b8SHans Rosenfeld 1028*4c3888b8SHans Rosenfeld /* 1029*4c3888b8SHans Rosenfeld * firmware dump Template image 1030*4c3888b8SHans Rosenfeld */ 1031*4c3888b8SHans Rosenfeld typedef struct ql_dmp_template { 1032*4c3888b8SHans Rosenfeld uint32_t rsv[2]; 1033*4c3888b8SHans Rosenfeld uint32_t len; 1034*4c3888b8SHans Rosenfeld uint32_t major_ver; 1035*4c3888b8SHans Rosenfeld uint32_t minor_ver; 1036*4c3888b8SHans Rosenfeld uint32_t subminor_ver; 1037*4c3888b8SHans Rosenfeld uint32_t attribute; 1038*4c3888b8SHans Rosenfeld ql_dt_hdr_t hdr; 1039*4c3888b8SHans Rosenfeld ql_dt_entry_t entries[1]; 1040*4c3888b8SHans Rosenfeld } ql_dmp_template_t; 1041*4c3888b8SHans Rosenfeld 1042*4c3888b8SHans Rosenfeld typedef struct ql_dt_riob1 { 1043*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1044*4c3888b8SHans Rosenfeld uint32_t addr; 1045*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1046*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1047*4c3888b8SHans Rosenfeld uint8_t reg_count_h; 1048*4c3888b8SHans Rosenfeld uint8_t reg_count_l; 1049*4c3888b8SHans Rosenfeld uint8_t reg_size; 1050*4c3888b8SHans Rosenfeld #else 1051*4c3888b8SHans Rosenfeld uint8_t reg_size; 1052*4c3888b8SHans Rosenfeld uint8_t reg_count_l; 1053*4c3888b8SHans Rosenfeld uint8_t reg_count_h; 1054*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1055*4c3888b8SHans Rosenfeld #endif 1056*4c3888b8SHans Rosenfeld } ql_dt_riob1_t; 1057*4c3888b8SHans Rosenfeld 1058*4c3888b8SHans Rosenfeld typedef struct ql_dt_wiob1 { 1059*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1060*4c3888b8SHans Rosenfeld uint32_t addr; 1061*4c3888b8SHans Rosenfeld uint32_t data; 1062*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1063*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1064*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1065*4c3888b8SHans Rosenfeld #else 1066*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1067*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1068*4c3888b8SHans Rosenfeld #endif 1069*4c3888b8SHans Rosenfeld } ql_dt_wiob1_t; 1070*4c3888b8SHans Rosenfeld 1071*4c3888b8SHans Rosenfeld typedef struct ql_dt_riob2 { 1072*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1073*4c3888b8SHans Rosenfeld uint32_t addr; 1074*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1075*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1076*4c3888b8SHans Rosenfeld uint8_t reg_count_h; 1077*4c3888b8SHans Rosenfeld uint8_t reg_count_l; 1078*4c3888b8SHans Rosenfeld uint8_t reg_size; 1079*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1080*4c3888b8SHans Rosenfeld uint8_t bank_sel_offset; 1081*4c3888b8SHans Rosenfeld #else 1082*4c3888b8SHans Rosenfeld uint8_t reg_size; 1083*4c3888b8SHans Rosenfeld uint8_t reg_count_l; 1084*4c3888b8SHans Rosenfeld uint8_t reg_count_h; 1085*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1086*4c3888b8SHans Rosenfeld uint8_t bank_sel_offset; 1087*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1088*4c3888b8SHans Rosenfeld #endif 1089*4c3888b8SHans Rosenfeld uint32_t reg_bank; 1090*4c3888b8SHans Rosenfeld } ql_dt_riob2_t; 1091*4c3888b8SHans Rosenfeld 1092*4c3888b8SHans Rosenfeld typedef struct ql_dt_wiob2 { 1093*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1094*4c3888b8SHans Rosenfeld uint32_t addr; 1095*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1096*4c3888b8SHans Rosenfeld uint8_t rsv[2]; 1097*4c3888b8SHans Rosenfeld uint8_t data_h; 1098*4c3888b8SHans Rosenfeld uint8_t data_l; 1099*4c3888b8SHans Rosenfeld uint8_t bank_sel_offset; 1100*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1101*4c3888b8SHans Rosenfeld uint8_t rsv1[2]; 1102*4c3888b8SHans Rosenfeld #else 1103*4c3888b8SHans Rosenfeld uint8_t data_l; 1104*4c3888b8SHans Rosenfeld uint8_t data_h; 1105*4c3888b8SHans Rosenfeld uint8_t rsv[2]; 1106*4c3888b8SHans Rosenfeld uint8_t rsv1[2]; 1107*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1108*4c3888b8SHans Rosenfeld uint8_t bank_sel_offset; 1109*4c3888b8SHans Rosenfeld #endif 1110*4c3888b8SHans Rosenfeld uint32_t reg_bank; 1111*4c3888b8SHans Rosenfeld } ql_dt_wiob2_t; 1112*4c3888b8SHans Rosenfeld 1113*4c3888b8SHans Rosenfeld typedef struct ql_dt_rpci { 1114*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1115*4c3888b8SHans Rosenfeld uint32_t addr; 1116*4c3888b8SHans Rosenfeld } ql_dt_rpci_t; 1117*4c3888b8SHans Rosenfeld 1118*4c3888b8SHans Rosenfeld typedef struct ql_dt_wpci { 1119*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1120*4c3888b8SHans Rosenfeld uint32_t addr; 1121*4c3888b8SHans Rosenfeld uint32_t data; 1122*4c3888b8SHans Rosenfeld } ql_dt_wpci_t, ql_dt_wrreg_t; 1123*4c3888b8SHans Rosenfeld 1124*4c3888b8SHans Rosenfeld typedef struct ql_dt_rram { 1125*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1126*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1127*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1128*4c3888b8SHans Rosenfeld uint8_t ram_area; 1129*4c3888b8SHans Rosenfeld #else 1130*4c3888b8SHans Rosenfeld uint8_t ram_area; 1131*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1132*4c3888b8SHans Rosenfeld #endif 1133*4c3888b8SHans Rosenfeld uint32_t start_addr; 1134*4c3888b8SHans Rosenfeld uint32_t end_addr; 1135*4c3888b8SHans Rosenfeld } ql_dt_rram_t; 1136*4c3888b8SHans Rosenfeld 1137*4c3888b8SHans Rosenfeld typedef struct ql_dt_gque { 1138*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1139*4c3888b8SHans Rosenfeld uint32_t num_queues; 1140*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1141*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1142*4c3888b8SHans Rosenfeld uint8_t queue_type; 1143*4c3888b8SHans Rosenfeld #else 1144*4c3888b8SHans Rosenfeld uint8_t queue_type; 1145*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1146*4c3888b8SHans Rosenfeld #endif 1147*4c3888b8SHans Rosenfeld } ql_dt_gque_t, ql_dt_gques_t; 1148*4c3888b8SHans Rosenfeld 1149*4c3888b8SHans Rosenfeld typedef struct ql_dt_gfce { 1150*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1151*4c3888b8SHans Rosenfeld uint32_t fce_trace_size; 1152*4c3888b8SHans Rosenfeld uint32_t write_pointer[2]; 1153*4c3888b8SHans Rosenfeld uint32_t base_pointer[2]; 1154*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb0; 1155*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb2; 1156*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb3; 1157*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb4; 1158*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb5; 1159*4c3888b8SHans Rosenfeld uint32_t fce_enable_mb6; 1160*4c3888b8SHans Rosenfeld } ql_dt_gfce_t; 1161*4c3888b8SHans Rosenfeld 1162*4c3888b8SHans Rosenfeld typedef struct ql_dt_prisc { 1163*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1164*4c3888b8SHans Rosenfeld } ql_dt_prisc_t, ql_dt_rrisc_t; 1165*4c3888b8SHans Rosenfeld 1166*4c3888b8SHans Rosenfeld typedef struct ql_dt_dint { 1167*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1168*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1169*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1170*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1171*4c3888b8SHans Rosenfeld #else 1172*4c3888b8SHans Rosenfeld uint8_t pci_offset; 1173*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1174*4c3888b8SHans Rosenfeld #endif 1175*4c3888b8SHans Rosenfeld uint32_t data; 1176*4c3888b8SHans Rosenfeld } ql_dt_dint_t; 1177*4c3888b8SHans Rosenfeld 1178*4c3888b8SHans Rosenfeld typedef struct ql_dt_ghbd { 1179*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1180*4c3888b8SHans Rosenfeld #ifdef _BIG_ENDIAN 1181*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1182*4c3888b8SHans Rosenfeld uint8_t host_buf_type; 1183*4c3888b8SHans Rosenfeld #else 1184*4c3888b8SHans Rosenfeld uint8_t host_buf_type; 1185*4c3888b8SHans Rosenfeld uint8_t rsv[3]; 1186*4c3888b8SHans Rosenfeld #endif 1187*4c3888b8SHans Rosenfeld uint32_t buf_size; 1188*4c3888b8SHans Rosenfeld uint32_t start_addr; 1189*4c3888b8SHans Rosenfeld } ql_dt_ghbd_t; 1190*4c3888b8SHans Rosenfeld 1191*4c3888b8SHans Rosenfeld typedef struct ql_dt_scra { 1192*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1193*4c3888b8SHans Rosenfeld uint32_t scratch_size; 1194*4c3888b8SHans Rosenfeld } ql_dt_scra_t; 1195*4c3888b8SHans Rosenfeld 1196*4c3888b8SHans Rosenfeld typedef struct ql_dt_rrreg { 1197*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1198*4c3888b8SHans Rosenfeld uint32_t addr; 1199*4c3888b8SHans Rosenfeld uint32_t count; 1200*4c3888b8SHans Rosenfeld } ql_dt_rrreg_t, ql_dt_rrram_t, ql_dt_rpcic_t; 1201*4c3888b8SHans Rosenfeld 1202*4c3888b8SHans Rosenfeld typedef struct ql_dt_wdmp { 1203*4c3888b8SHans Rosenfeld ql_dt_entry_hdr_t h; 1204*4c3888b8SHans Rosenfeld uint32_t length; 1205*4c3888b8SHans Rosenfeld uint32_t data[1]; 1206*4c3888b8SHans Rosenfeld } ql_dt_wdmp_t; 1207*4c3888b8SHans Rosenfeld 1208*4c3888b8SHans Rosenfeld /* 120993c20f26SSukumar Swaminathan * ql_lock_nvram() flags 121093c20f26SSukumar Swaminathan */ 121193c20f26SSukumar Swaminathan #define LNF_NVRAM_DATA BIT_0 /* get nvram */ 121293c20f26SSukumar Swaminathan #define LNF_VPD_DATA BIT_1 /* get vpd data (24xx only) */ 121393c20f26SSukumar Swaminathan 121493c20f26SSukumar Swaminathan /* 121593c20f26SSukumar Swaminathan * ISP product identification definitions in mailboxes after reset. 121693c20f26SSukumar Swaminathan */ 121793c20f26SSukumar Swaminathan #define PROD_ID_1 0x4953 121893c20f26SSukumar Swaminathan #define PROD_ID_2 0x0000 121993c20f26SSukumar Swaminathan #define PROD_ID_2a 0x5020 122093c20f26SSukumar Swaminathan #define PROD_ID_3 0x2020 122193c20f26SSukumar Swaminathan 122293c20f26SSukumar Swaminathan /* 122393c20f26SSukumar Swaminathan * NVRAM Command values. 122493c20f26SSukumar Swaminathan */ 122593c20f26SSukumar Swaminathan #define NV_START_BIT BIT_2 122693c20f26SSukumar Swaminathan #define NV_WRITE_OP (BIT_26 + BIT_24) 122793c20f26SSukumar Swaminathan #define NV_READ_OP (BIT_26 + BIT_25) 122893c20f26SSukumar Swaminathan #define NV_ERASE_OP (BIT_26 + BIT_25 + BIT_24) 122993c20f26SSukumar Swaminathan #define NV_MASK_OP (BIT_26 + BIT_25 + BIT_24) 123093c20f26SSukumar Swaminathan #define NV_DELAY_COUNT 10 123193c20f26SSukumar Swaminathan 12325dfd244aSDaniel Beauregard /* 12335dfd244aSDaniel Beauregard * Deivce ID list definitions. 12345dfd244aSDaniel Beauregard */ 12355dfd244aSDaniel Beauregard struct ql_dev_id { 12365dfd244aSDaniel Beauregard uint8_t al_pa; 12375dfd244aSDaniel Beauregard uint8_t area; 12385dfd244aSDaniel Beauregard uint8_t domain; 12395dfd244aSDaniel Beauregard uint8_t loop_id; 12405dfd244aSDaniel Beauregard }; 12415dfd244aSDaniel Beauregard 12425dfd244aSDaniel Beauregard struct ql_ex_dev_id { 12435dfd244aSDaniel Beauregard uint8_t al_pa; 12445dfd244aSDaniel Beauregard uint8_t area; 12455dfd244aSDaniel Beauregard uint8_t domain; 12465dfd244aSDaniel Beauregard uint8_t reserved; 12475dfd244aSDaniel Beauregard uint8_t loop_id_l; 12485dfd244aSDaniel Beauregard uint8_t loop_id_h; 12495dfd244aSDaniel Beauregard }; 12505dfd244aSDaniel Beauregard 12515dfd244aSDaniel Beauregard struct ql_24_dev_id { 12525dfd244aSDaniel Beauregard uint8_t al_pa; 12535dfd244aSDaniel Beauregard uint8_t area; 12545dfd244aSDaniel Beauregard uint8_t domain; 12555dfd244aSDaniel Beauregard uint8_t reserved; 12565dfd244aSDaniel Beauregard uint8_t n_port_hdl_l; 12575dfd244aSDaniel Beauregard uint8_t n_port_hdl_h; 12585dfd244aSDaniel Beauregard uint8_t reserved_1[2]; 12595dfd244aSDaniel Beauregard }; 12605dfd244aSDaniel Beauregard 12615dfd244aSDaniel Beauregard typedef union ql_dev_id_list { 12625dfd244aSDaniel Beauregard struct ql_dev_id d; 12635dfd244aSDaniel Beauregard struct ql_ex_dev_id d_ex; 12645dfd244aSDaniel Beauregard struct ql_24_dev_id d_24; 12655dfd244aSDaniel Beauregard } ql_dev_id_list_t; 12665dfd244aSDaniel Beauregard 12675dfd244aSDaniel Beauregard /* Define maximum number of device list entries.. */ 12685dfd244aSDaniel Beauregard #define DEVICE_LIST_ENTRIES MAX_24_FIBRE_DEVICES 126993c20f26SSukumar Swaminathan 127093c20f26SSukumar Swaminathan /* 127193c20f26SSukumar Swaminathan * Global Data in ql_init.c source file. 127293c20f26SSukumar Swaminathan */ 127393c20f26SSukumar Swaminathan 127493c20f26SSukumar Swaminathan /* 127593c20f26SSukumar Swaminathan * Global Function Prototypes in ql_init.c source file. 127693c20f26SSukumar Swaminathan */ 127793c20f26SSukumar Swaminathan int ql_initialize_adapter(ql_adapter_state_t *); 127893c20f26SSukumar Swaminathan int ql_pci_sbus_config(ql_adapter_state_t *); 127993c20f26SSukumar Swaminathan int ql_nvram_config(ql_adapter_state_t *); 128093c20f26SSukumar Swaminathan uint16_t ql_get_nvram_word(ql_adapter_state_t *, uint32_t); 128193c20f26SSukumar Swaminathan void ql_nv_write(ql_adapter_state_t *, uint16_t); 128293c20f26SSukumar Swaminathan void ql_nv_delay(void); 128393c20f26SSukumar Swaminathan int ql_lock_nvram(ql_adapter_state_t *, uint32_t *, uint32_t); 128493c20f26SSukumar Swaminathan void ql_release_nvram(ql_adapter_state_t *); 128593c20f26SSukumar Swaminathan void ql_common_properties(ql_adapter_state_t *); 128693c20f26SSukumar Swaminathan uint32_t ql_get_prop(ql_adapter_state_t *, char *); 128793c20f26SSukumar Swaminathan int ql_load_isp_firmware(ql_adapter_state_t *); 128893c20f26SSukumar Swaminathan int ql_start_firmware(ql_adapter_state_t *); 128993c20f26SSukumar Swaminathan int ql_set_cache_line(ql_adapter_state_t *); 129093c20f26SSukumar Swaminathan int ql_init_rings(ql_adapter_state_t *); 129193c20f26SSukumar Swaminathan int ql_fw_ready(ql_adapter_state_t *, uint8_t); 12925dfd244aSDaniel Beauregard void ql_dev_list(ql_adapter_state_t *, ql_dev_id_list_t *, uint32_t, 129393c20f26SSukumar Swaminathan port_id_t *, uint16_t *); 129493c20f26SSukumar Swaminathan void ql_reset_chip(ql_adapter_state_t *); 129593c20f26SSukumar Swaminathan int ql_abort_isp(ql_adapter_state_t *); 1296*4c3888b8SHans Rosenfeld void ql_requeue_all_cmds(ql_adapter_state_t *); 129793c20f26SSukumar Swaminathan int ql_vport_control(ql_adapter_state_t *, uint8_t); 129893c20f26SSukumar Swaminathan int ql_vport_modify(ql_adapter_state_t *, uint8_t, uint8_t); 129993c20f26SSukumar Swaminathan int ql_vport_enable(ql_adapter_state_t *); 130093c20f26SSukumar Swaminathan ql_adapter_state_t *ql_vport_create(ql_adapter_state_t *, uint8_t); 130193c20f26SSukumar Swaminathan void ql_vport_destroy(ql_adapter_state_t *); 130293c20f26SSukumar Swaminathan #endif /* _KERNEL */ 130393c20f26SSukumar Swaminathan 130493c20f26SSukumar Swaminathan #ifdef __cplusplus 130593c20f26SSukumar Swaminathan } 130693c20f26SSukumar Swaminathan #endif 130793c20f26SSukumar Swaminathan 130893c20f26SSukumar Swaminathan #endif /* _QL_INIT_H */ 1309