1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2008 QLogic Corporation */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _QL_API_H 30 #define _QL_API_H 31 32 33 /* 34 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 35 * 36 * *********************************************************************** 37 * * ** 38 * * NOTICE ** 39 * * COPYRIGHT (C) 1996-2008 QLOGIC CORPORATION ** 40 * * ALL RIGHTS RESERVED ** 41 * * ** 42 * *********************************************************************** 43 * 44 */ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 /* OS include files. */ 51 #include <sys/scsi/scsi_types.h> 52 #include <sys/byteorder.h> 53 #include <sys/pci.h> 54 #include <sys/utsname.h> 55 #include <sys/file.h> 56 #include <sys/param.h> 57 #include <ql_open.h> 58 59 #include <sys/fibre-channel/fc.h> 60 #include <sys/fibre-channel/impl/fc_fcaif.h> 61 62 #ifndef DDI_INTR_TYPE_FIXED 63 #define DDI_INTR_TYPE_FIXED 0x1 64 #endif 65 #ifndef DDI_INTR_TYPE_MSI 66 #define DDI_INTR_TYPE_MSI 0x2 67 #endif 68 #ifndef DDI_INTR_TYPE_MSIX 69 #define DDI_INTR_TYPE_MSIX 0x4 70 #endif 71 #ifndef DDI_INTR_FLAG_BLOCK 72 #define DDI_INTR_FLAG_BLOCK 0x100 73 #endif 74 #ifndef DDI_INTR_ALLOC_NORMAL 75 #define DDI_INTR_ALLOC_NORMAL 0 76 #endif 77 #ifndef DDI_INTR_ALLOC_STRICT 78 #define DDI_INTR_ALLOC_STRICT 1 79 #endif 80 81 /* 82 * NPIV defines 83 */ 84 #ifndef FC_NPIV_FDISC_FAILED 85 #define FC_NPIV_FDISC_FAILED 0x45 86 #endif 87 #ifndef FC_NPIV_FDISC_WWN_INUSE 88 #define FC_NPIV_FDISC_WWN_INUSE 0x46 89 #endif 90 #ifndef FC_NPIV_NOT_SUPPORTED 91 #define FC_NPIV_NOT_SUPPORTED 0x47 92 #endif 93 #ifndef FC_NPIV_WRONG_TOPOLOGY 94 #define FC_NPIV_WRONG_TOPOLOGY 0x48 95 #endif 96 #ifndef FC_NPIV_NPIV_BOUND 97 #define FC_NPIV_NPIV_BOUND 0x49 98 #endif 99 100 #pragma weak ddi_intr_get_supported_types 101 #pragma weak ddi_intr_get_nintrs 102 #pragma weak ddi_intr_alloc 103 #pragma weak ddi_intr_free 104 #pragma weak ddi_intr_get_pri 105 #pragma weak ddi_intr_add_handler 106 #pragma weak ddi_intr_dup_handler 107 #pragma weak ddi_intr_get_navail 108 #pragma weak ddi_intr_block_disable 109 #pragma weak ddi_intr_block_enable 110 #pragma weak ddi_intr_disable 111 #pragma weak ddi_intr_enable 112 #pragma weak ddi_intr_get_cap 113 #pragma weak ddi_intr_remove_handler 114 extern int ddi_intr_get_supported_types(); 115 extern int ddi_intr_get_nintrs(); 116 extern int ddi_intr_alloc(); 117 extern int ddi_intr_free(); 118 extern int ddi_intr_get_pri(); 119 extern int ddi_intr_add_handler(); 120 extern int ddi_intr_dup_handler(); 121 extern int ddi_intr_get_navail(); 122 extern int ddi_intr_block_disable(); 123 extern int ddi_intr_block_enable(); 124 extern int ddi_intr_disable(); 125 extern int ddi_intr_enable(); 126 extern int ddi_intr_get_cap(); 127 extern int ddi_intr_remove_handler(); 128 129 #ifndef QL_DRV_HARDENING 130 #define ddi_devstate_t int 131 #define DDI_DEVSTATE_UP 0 132 #define ddi_get_devstate(a) DDI_DEVSTATE_UP 133 #define ddi_dev_report_fault(a, b, c, d) 134 #define ddi_check_dma_handle(a) DDI_SUCCESS 135 #define ddi_check_acc_handle(a) DDI_SUCCESS 136 #define QL_CLEAR_DMA_HANDLE(x) 137 #else 138 #define QL_CLEAR_DMA_HANDLE(x) ((ddi_dma_impl_t *)x)->dmai_fault_notify = 0; \ 139 ((ddi_dma_impl_t *)x)->dmai_fault_check = 0; \ 140 ((ddi_dma_impl_t *)x)->dmai_fault = 0 141 #endif 142 143 #ifndef FC_STATE_1GBIT_SPEED 144 #define FC_STATE_1GBIT_SPEED FC_STATE_FULL_SPEED 145 #endif 146 #ifndef FC_STATE_2GBIT_SPEED 147 #define FC_STATE_2GBIT_SPEED FC_STATE_DOUBLE_SPEED 148 #endif 149 #ifndef FC_STATE_4GBIT_SPEED 150 #define FC_STATE_4GBIT_SPEED FC_STATE_DOUBLE_SPEED 151 #endif 152 153 /* 154 * Data bit definitions. 155 */ 156 #define BIT_0 0x1 157 #define BIT_1 0x2 158 #define BIT_2 0x4 159 #define BIT_3 0x8 160 #define BIT_4 0x10 161 #define BIT_5 0x20 162 #define BIT_6 0x40 163 #define BIT_7 0x80 164 #define BIT_8 0x100 165 #define BIT_9 0x200 166 #define BIT_10 0x400 167 #define BIT_11 0x800 168 #define BIT_12 0x1000 169 #define BIT_13 0x2000 170 #define BIT_14 0x4000 171 #define BIT_15 0x8000 172 #define BIT_16 0x10000 173 #define BIT_17 0x20000 174 #define BIT_18 0x40000 175 #define BIT_19 0x80000 176 #define BIT_20 0x100000 177 #define BIT_21 0x200000 178 #define BIT_22 0x400000 179 #define BIT_23 0x800000 180 #define BIT_24 0x1000000 181 #define BIT_25 0x2000000 182 #define BIT_26 0x4000000 183 #define BIT_27 0x8000000 184 #define BIT_28 0x10000000 185 #define BIT_29 0x20000000 186 #define BIT_30 0x40000000 187 #define BIT_31 0x80000000 188 189 /* 190 * Local Macro Definitions. 191 */ 192 #ifndef TRUE 193 #define TRUE B_TRUE 194 #endif 195 196 #ifndef FALSE 197 #define FALSE B_FALSE 198 #endif 199 200 /* 201 * I/O register 202 */ 203 #define RD_REG_BYTE(ha, addr) \ 204 (uint8_t)ddi_get8(ha->dev_handle, (uint8_t *)addr) 205 #define RD_REG_WORD(ha, addr) \ 206 (uint16_t)ddi_get16(ha->dev_handle, (uint16_t *)addr) 207 #define RD_REG_DWORD(ha, addr) \ 208 (uint32_t)ddi_get32(ha->dev_handle, (uint32_t *)addr) 209 210 #define WRT_REG_BYTE(ha, addr, data) \ 211 ddi_put8(ha->dev_handle, (uint8_t *)addr, (uint8_t)data) 212 #define WRT_REG_WORD(ha, addr, data) \ 213 ddi_put16(ha->dev_handle, (uint16_t *)addr, (uint16_t)data) 214 #define WRT_REG_DWORD(ha, addr, data) \ 215 ddi_put32(ha->dev_handle, (uint32_t *)addr, (uint32_t)data) 216 217 #define RD8_IO_REG(ha, regname) \ 218 RD_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname)) 219 #define RD16_IO_REG(ha, regname) \ 220 RD_REG_WORD(ha, (ha->iobase + ha->reg_off->regname)) 221 #define RD32_IO_REG(ha, regname) \ 222 RD_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname)) 223 224 #define WRT8_IO_REG(ha, regname, data) \ 225 WRT_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname), data) 226 #define WRT16_IO_REG(ha, regname, data) \ 227 WRT_REG_WORD(ha, (ha->iobase + ha->reg_off->regname), data) 228 #define WRT32_IO_REG(ha, regname, data) \ 229 WRT_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname), data) 230 231 #define RD_IOREG_BYTE(ha, addr) \ 232 (uint8_t)ddi_get8(ha->iomap_dev_handle, (uint8_t *)addr) 233 #define RD_IOREG_WORD(ha, addr) \ 234 (uint16_t)ddi_get16(ha->iomap_dev_handle, (uint16_t *)addr) 235 #define RD_IOREG_DWORD(ha, addr) \ 236 (uint32_t)ddi_get32(ha->iomap_dev_handle, (uint32_t *)addr) 237 238 #define WRT_IOREG_BYTE(ha, addr, data) \ 239 ddi_put8(ha->iomap_dev_handle, (uint8_t *)addr, (uint8_t)data) 240 #define WRT_IOREG_WORD(ha, addr, data) \ 241 ddi_put16(ha->iomap_dev_handle, (uint16_t *)addr, (uint16_t)data) 242 #define WRT_IOREG_DWORD(ha, addr, data) \ 243 ddi_put32(ha->iomap_dev_handle, (uint32_t *)addr, (uint32_t)data) 244 245 #define RD8_IOMAP_REG(ha, regname) \ 246 RD_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname)) 247 #define RD16_IOMAP_REG(ha, regname) \ 248 RD_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname)) 249 #define RD32_IOMAP_REG(ha, regname) \ 250 RD_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname)) 251 252 #define WRT8_IOMAP_REG(ha, regname, data) \ 253 WRT_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname), data) 254 #define WRT16_IOMAP_REG(ha, regname, data) \ 255 WRT_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname), data) 256 #define WRT32_IOMAP_REG(ha, regname, data) \ 257 WRT_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname), data) 258 259 /* 260 * FCA definitions 261 */ 262 #define MAX_LUNS 16384 263 #define QL_FCA_BRAND 0x0fca2200 264 265 /* Following to be removed when defined by OS. */ 266 /* ************************************************************************ */ 267 #define LA_ELS_FARP_REQ 0x54 268 #define LA_ELS_FARP_REPLY 0x55 269 #define LA_ELS_LPC 0x71 270 #define LA_ELS_LSTS 0x72 271 272 typedef struct { 273 ls_code_t ls_code; 274 uint8_t rsvd[3]; 275 uint8_t port_control; 276 uint8_t lpb[16]; 277 uint8_t lpe[16]; 278 } ql_lpc_t; 279 280 typedef struct { 281 ls_code_t ls_code; 282 } ql_acc_rjt_t; 283 284 typedef fc_linit_resp_t ql_lpc_resp_t; 285 typedef fc_scr_resp_t ql_rscn_resp_t; 286 287 typedef struct { 288 uint16_t class_valid_svc_opt; 289 uint16_t initiator_ctl; 290 uint16_t recipient_ctl; 291 uint16_t rcv_data_size; 292 uint16_t conc_sequences; 293 uint16_t n_port_end_to_end_credit; 294 uint16_t open_sequences_per_exch; 295 uint16_t unused; 296 } class_svc_param_t; 297 298 typedef struct { 299 uint8_t type; 300 uint8_t rsvd; 301 uint16_t process_assoc_flags; 302 uint32_t originator_process; 303 uint32_t responder_process; 304 uint32_t process_flags; 305 } prli_svc_param_t; 306 /* *********************************************************************** */ 307 308 /* 309 * Fibre Channel device definitions. 310 */ 311 #define MAX_22_FIBRE_DEVICES 256 312 #define MAX_24_FIBRE_DEVICES 2048 313 #define MAX_24_VIRTUAL_PORTS 63 314 #define MAX_25_VIRTUAL_PORTS 255 315 316 #define LAST_LOCAL_LOOP_ID 0x7d 317 #define FL_PORT_LOOP_ID 0x7e /* FFFFFE Fabric F_Port */ 318 #define SWITCH_FABRIC_CONTROLLER_LOOP_ID 0x7f /* FFFFFD Fabric Controller */ 319 #define SIMPLE_NAME_SERVER_LOOP_ID 0x80 /* FFFFFC Directory Server */ 320 #define SNS_FIRST_LOOP_ID 0x81 321 #define SNS_LAST_LOOP_ID 0xfe 322 #define IP_BROADCAST_LOOP_ID 0xff /* FFFFFF Broadcast */ 323 #define BROADCAST_ADDR 0xffffff /* FFFFFF Broadcast */ 324 325 /* 326 * Fibre Channel 24xx device definitions. 327 */ 328 #define LAST_N_PORT_HDL 0x7ef 329 #define SNS_24XX_HDL 0x7FC /* SNS FFFFFCh */ 330 #define SFC_24XX_HDL 0x7FD /* fabric controller FFFFFDh */ 331 #define FL_PORT_24XX_HDL 0x7FE /* F_Port FFFFFEh */ 332 #define BROADCAST_24XX_HDL 0x7FF /* IP broadcast FFFFFFh */ 333 334 /* Loop ID's used as flags, must be higher than any valid Loop ID */ 335 #define PORT_NO_LOOP_ID 0x8000 /* Device does not have loop ID. */ 336 #define PORT_LOST_ID 0x4000 /* Device has been lost. */ 337 338 /* Fibre Channel Topoploy. */ 339 #define QL_N_PORT BIT_0 340 #define QL_NL_PORT BIT_1 341 #define QL_F_PORT BIT_2 342 #define QL_FL_PORT BIT_3 343 #define QL_SNS_CONNECTION BIT_4 344 #define QL_LOOP_CONNECTION (QL_NL_PORT | QL_FL_PORT) 345 #define QL_P2P_CONNECTION (QL_F_PORT | QL_N_PORT) 346 347 /* Timeout timer counts in seconds (must greater than 1 second). */ 348 #define WATCHDOG_TIME 5 /* 0 - 255 */ 349 #define PORT_RETRY_TIME 2 /* 0 - 255 */ 350 #define LOOP_DOWN_TIMER_OFF 0 351 #define LOOP_DOWN_TIMER_START 240 /* 0 - 255 */ 352 #define LOOP_DOWN_TIMER_END 1 353 #define LOOP_DOWN_RESET (LOOP_DOWN_TIMER_START - 45) /* 0 - 255 */ 354 #define R_A_TOV_DEFAULT 20 /* 0 - 65535 */ 355 #define IDLE_CHECK_TIMER 300 /* 0 - 65535 */ 356 #define MAX_DEVICE_LOST_RETRY 16 /* 0 - 255 */ 357 358 /* Maximum outstanding commands in ISP queues (1-4095) */ 359 #define MAX_OUTSTANDING_COMMANDS 0x400 360 #define OSC_INDEX_MASK 0xfff 361 #define OSC_INDEX_SHIFT 12 362 363 /* Maximum unsolicited buffers (1-65535) */ 364 #define QL_UB_LIMIT 256 365 366 /* ISP request, response and receive buffer entry counts */ 367 #define REQUEST_ENTRY_CNT 512 /* Request entries (205-65535) */ 368 #define RESPONSE_ENTRY_CNT 256 /* Response entries (1-65535) */ 369 #define RCVBUF_CONTAINER_CNT 64 /* Rcv buffer containers (8-1024) */ 370 371 /* 372 * ISP request, response, mailbox and receive buffer queue sizes 373 */ 374 #define REQUEST_ENTRY_SIZE 64 375 #define REQUEST_QUEUE_SIZE (REQUEST_ENTRY_SIZE * REQUEST_ENTRY_CNT) 376 377 #define RESPONSE_ENTRY_SIZE 64 378 #define RESPONSE_QUEUE_SIZE (RESPONSE_ENTRY_SIZE * RESPONSE_ENTRY_CNT) 379 380 #define MAILBOX_BUFFER_SIZE 0x4000 381 382 #define RCVBUF_CONTAINER_SIZE 12 383 #define RCVBUF_QUEUE_SIZE (RCVBUF_CONTAINER_SIZE * RCVBUF_CONTAINER_CNT) 384 385 386 /* 387 * ISP DMA buffer definitions 388 */ 389 #define REQUEST_Q_BUFFER_OFFSET 0 390 #define RESPONSE_Q_BUFFER_OFFSET (REQUEST_Q_BUFFER_OFFSET + REQUEST_QUEUE_SIZE) 391 #define RCVBUF_Q_BUFFER_OFFSET (RESPONSE_Q_BUFFER_OFFSET + RESPONSE_QUEUE_SIZE) 392 393 /* 394 * DMA attributes definitions. 395 */ 396 #define QL_DMA_LOW_ADDRESS (uint64_t)0 397 #define QL_DMA_HIGH_64BIT_ADDRESS (uint64_t)0xffffffffffffffff 398 #define QL_DMA_HIGH_32BIT_ADDRESS (uint64_t)0xffffffff 399 #define QL_DMA_XFER_COUNTER (uint64_t)0xffffffff 400 #define QL_DMA_ADDRESS_ALIGNMENT (uint64_t)8 401 #define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3 402 #define QL_DMA_RING_ADDRESS_ALIGNMENT (uint64_t)64 403 #define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6 404 #define QL_DMA_BURSTSIZES 0xff 405 #define QL_DMA_MIN_XFER_SIZE 1 406 #define QL_DMA_MAX_XFER_SIZE (uint64_t)0xffffffff 407 #define QL_DMA_SEGMENT_BOUNDARY (uint64_t)0xffffffff 408 409 #ifdef __sparc 410 #define QL_DMA_SG_LIST_LENGTH 1 411 #define QL_FCSM_CMD_SGLLEN 1 412 #define QL_FCSM_RSP_SGLLEN 1 413 #define QL_FCIP_CMD_SGLLEN 1 414 #define QL_FCIP_RSP_SGLLEN 1 415 #define QL_FCP_CMD_SGLLEN 1 416 #define QL_FCP_RSP_SGLLEN 1 417 #else 418 #define QL_DMA_SG_LIST_LENGTH 1024 419 #define QL_FCSM_CMD_SGLLEN 1 420 #define QL_FCSM_RSP_SGLLEN 6 421 /* 422 * QL_FCIP_CMD_SGLLEN needs to be increased as we changed the max fcip packet 423 * size to about 64K. With this, we need to increase the maximum number of 424 * scatter-gather elements allowable from the existing 7. We want it to be more 425 * like 17 (max fragments for an fcip packet that is unaligned). (64K / 4K) + 1 426 * or whatever. Otherwise the DMA breakup routines will give bad results. 427 */ 428 #define QL_FCIP_CMD_SGLLEN 17 429 #define QL_FCIP_RSP_SGLLEN 1 430 #define QL_FCP_CMD_SGLLEN 1 431 #define QL_FCP_RSP_SGLLEN 1 432 #endif 433 434 #ifndef DDI_DMA_RELAXED_ORDERING 435 #define DDI_DMA_RELAXED_ORDERING 0x400 436 #endif 437 438 #define QL_DMA_GRANULARITY 1 439 #define QL_DMA_XFER_FLAGS 0 440 441 typedef union { 442 uint64_t size64; /* 1 X 64 bit number */ 443 uint32_t size32[2]; /* 2 x 32 bit number */ 444 uint16_t size16[4]; /* 4 x 16 bit number */ 445 uint8_t size8[8]; /* 8 x 8 bit number */ 446 } conv_num_t; 447 448 /* 449 * Device register offsets. 450 */ 451 #define MAX_MBOX_COUNT 32 452 typedef struct { 453 uint8_t flash_address; /* Flash BIOS address */ 454 uint8_t flash_data; /* Flash BIOS data */ 455 uint8_t ctrl_status; /* Control/Status */ 456 uint8_t ictrl; /* Interrupt control */ 457 uint8_t istatus; /* Interrupt status */ 458 uint8_t semaphore; /* Semaphore */ 459 uint8_t nvram; /* NVRAM register. */ 460 uint8_t req_in; /* for 2200 MBX 4 Write */ 461 uint8_t req_out; /* for 2200 MBX 4 read */ 462 uint8_t resp_in; /* for 2200 MBX 5 Read */ 463 uint8_t resp_out; /* for 2200 MBX 5 Write */ 464 uint8_t intr_info_lo; 465 uint8_t intr_info_hi; 466 uint8_t mbox_cnt; /* Number of mailboxes */ 467 uint8_t mailbox[MAX_MBOX_COUNT]; /* Mailbox registers */ 468 uint8_t fpm_diag_config; 469 uint8_t pcr; /* Processor Control Register. */ 470 uint8_t mctr; /* Memory Configuration and Timing. */ 471 uint8_t fb_cmd; 472 uint8_t hccr; /* Host command & control register. */ 473 uint8_t gpiod; /* GPIO Data register. */ 474 uint8_t gpioe; /* GPIO Enable register. */ 475 uint8_t host_to_host_sema; /* 2312 resource lock register */ 476 uint8_t pri_req_in; /* 2400 */ 477 uint8_t pri_req_out; /* 2400 */ 478 uint8_t atio_req_in; /* 2400 */ 479 uint8_t atio_req_out; /* 2400 */ 480 uint8_t io_base_addr; /* 2400 */ 481 } reg_off_t; 482 483 /* 484 * Mbox-8 read maximum debounce count. 485 * Reading Mbox-8 could be debouncing, before getting stable value. 486 * This is the recommended driver fix from Qlogic along with firmware fix. 487 * During testing, maximum count did not cross 3. 488 */ 489 #define QL_MAX_DEBOUNCE 10 490 491 /* 492 * Control Status register definitions 493 */ 494 #define ISP_FUNC_NUM_MASK (BIT_15 | BIT_14) 495 #define ISP_FLASH_64K_BANK BIT_3 /* Flash BIOS 64K Bank Select */ 496 #define ISP_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 497 #define ISP_RESET BIT_0 /* ISP soft reset */ 498 499 /* 500 * Control Status 24xx register definitions 501 */ 502 #define FLASH_NVRAM_ACCESS_ERROR BIT_18 503 #define DMA_ACTIVE BIT_17 504 #define DMA_SHUTDOWN BIT_16 505 #define FUNCTION_NUMBER BIT_15 506 507 #define MWB_4096_BYTES (BIT_5 | BIT_4) 508 #define MWB_2048_BYTES BIT_5 509 #define MWB_1024_BYTES BIT_4 510 #define MWB_512_BYTES 0 511 512 /* 513 * Interrupt Control register definitions 514 */ 515 #define ISP_EN_INT BIT_15 /* ISP enable interrupts. */ 516 #define ISP_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 517 518 /* 519 * Interrupt Status register definitions 520 */ 521 #define RISC_INT BIT_3 /* RISC interrupt */ 522 523 /* 524 * NVRAM register definitions. 525 */ 526 #define NV_DESELECT 0 527 #define NV_CLOCK BIT_0 528 #define NV_SELECT BIT_1 529 #define NV_DATA_OUT BIT_2 530 #define NV_DATA_IN BIT_3 531 #define NV_PR_ENABLE BIT_13 /* protection register enable */ 532 #define NV_WR_ENABLE BIT_14 /* write enable */ 533 #define NV_BUSY BIT_15 534 535 /* 536 * Flash/NVRAM 24xx definitions 537 */ 538 #define FLASH_DATA_FLAG BIT_31 539 #define FLASH_CONF_ADDR 0x7FFD0000 540 #define FLASH_DATA_ADDR 0x7FF00000 541 #define FLASH_ADDR_MASK 0x7FFF0000 542 543 #define NVRAM_CONF_ADDR 0x7FFF0000 544 #define NVRAM_DATA_ADDR 0x7FFE0000 545 546 #define NVRAM_24XX_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x80) 547 #define NVRAM_24XX_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x180) 548 #define VPD_24XX_FUNC0_ADDR NVRAM_DATA_ADDR 549 #define VPD_24XX_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x100) 550 551 #define NVRAM_25XX_FUNC0_ADDR FLASH_DATA_ADDR + 0x48080 552 #define NVRAM_25XX_FUNC1_ADDR FLASH_DATA_ADDR + 0x48180 553 #define VPD_25XX_FUNC0_ADDR FLASH_DATA_ADDR + 0x48000 554 #define VPD_25XX_FUNC1_ADDR FLASH_DATA_ADDR + 0x48100 555 556 #define FLASH_2400_ERRLOG_START_ADDR_0 0 /* 0x1f000 */ 557 #define FLASH_2400_ERRLOG_START_ADDR_1 0 /* 0x1f200 */ 558 #define FLASH_2500_ERRLOG_START_ADDR_0 0x54000 559 #define FLASH_2500_ERRLOG_START_ADDR_1 0x54400 560 #define FLASH_ERRLOG_SIZE 0x200 561 #define FLASH_ERRLOG_ENTRY_SIZE 4 562 #define FLASH_2500_DESCRIPTOR_TABLE 0x50000 563 564 /* 565 * Flash Error Log Event Codes. 566 */ 567 #define FLASH_ERRLOG_AEN_8002 0x8002 568 #define FLASH_ERRLOG_AEN_8003 0x8003 569 #define FLASH_ERRLOG_AEN_8004 0x8004 570 #define FLASH_ERRLOG_RESET_ERR 0xF00B 571 #define FLASH_ERRLOG_ISP_ERR 0xF020 572 #define FLASH_ERRLOG_PARITY_ERR 0xF022 573 #define FLASH_ERRLOG_NVRAM_CHKSUM_ERR 0xF023 574 #define FLASH_ERRLOG_FLASH_FW_ERR 0xF024 575 576 #define VPD_TAG_END 0x78 577 #define VPD_TAG_CHKSUM "RV" 578 #define VPD_TAG_SN "SN" 579 #define VPD_TAG_PN "PN" 580 #define VPD_TAG_PRODID "\x82" 581 #define VPD_TAG_LRT 0x90 582 #define VPD_TAG_LRTC 0x91 583 584 #define FLASH_24XX_FIRMWARE_ADDR 0x80000 585 /* 586 * RISC to Host Status register definitions. 587 */ 588 #define RH_RISC_INT BIT_15 /* RISC to Host Intrpt Req */ 589 #define RH_RISC_PAUSED BIT_8 /* RISC Paused bit. */ 590 591 /* 592 * RISC to Host Status register status field definitions. 593 */ 594 #define ROM_MBX_SUCCESS 0x01 595 #define ROM_MBX_ERR 0x02 596 #define MBX_SUCCESS 0x10 597 #define MBX_ERR 0x11 598 #define ASYNC_EVENT 0x12 599 #define RESP_UPDATE 0x13 600 #define REQ_UPDATE 0x14 601 #define SCSI_FAST_POST_16 0x15 602 #define SCSI_FAST_POST_32 0x16 603 #define CTIO_FAST_POST 0x17 604 #define IP_FAST_POST_XMT 0x18 605 #define IP_FAST_POST_RCV 0x19 606 #define IP_FAST_POST_BRD 0x1a 607 #define IP_FAST_POST_RCV_ALN 0x1b 608 #define ATIO_UPDATE 0x1c 609 #define ATIO_RESP_UPDATE 0x1d 610 611 /* 612 * HCCR commands. 613 */ 614 #define HC_RESET_RISC 0x1000 /* Reset RISC */ 615 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */ 616 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 617 #define HC_DISABLE_PARITY_PAUSE 0x4001 /* qla2200/2300 - disable parity err */ 618 /* RISC pause. */ 619 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */ 620 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 621 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 622 #define HC_HOST_INT BIT_7 /* Host interrupt bit */ 623 #define HC_RISC_PAUSE BIT_5 /* Pause mode bit */ 624 625 /* 626 * HCCR commands for 24xx and 25xx. 627 */ 628 #define HC24_RESET_RISC 0x10000000 /* Reset RISC */ 629 #define HC24_CLEAR_RISC_RESET 0x20000000 /* Release RISC from reset. */ 630 #define HC24_PAUSE_RISC 0x30000000 /* Pause RISC */ 631 #define HC24_RELEASE_PAUSE 0x40000000 /* Release RISC from pause */ 632 #define HC24_SET_HOST_INT 0x50000000 /* Set host interrupt */ 633 #define HC24_CLR_HOST_INT 0x60000000 /* Clear HOST interrupt */ 634 #define HC24_CLR_RISC_INT 0xA0000000 /* Clear RISC interrupt */ 635 #define HC24_HOST_INT BIT_6 /* Host to RISC intrpt bit */ 636 #define HC24_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 637 638 /* 639 * ISP Initialization Control Blocks. 640 * Little endian except where noted. 641 */ 642 #define ICB_VERSION 1 643 typedef struct ql_init_cb { 644 uint8_t version; 645 uint8_t reserved; 646 647 /* 648 * LSB BIT 0 = enable_hard_loop_id 649 * LSB BIT 1 = enable_fairness 650 * LSB BIT 2 = enable_full_duplex 651 * LSB BIT 3 = enable_fast_posting 652 * LSB BIT 4 = enable_target_mode 653 * LSB BIT 5 = disable_initiator_mode 654 * LSB BIT 6 = enable_adisc 655 * LSB BIT 7 = enable_target_inquiry_data 656 * 657 * MSB BIT 0 = enable_port_update_ae 658 * MSB BIT 1 = disable_initial_lip 659 * MSB BIT 2 = enable_decending_soft_assign 660 * MSB BIT 3 = previous_assigned_addressing 661 * MSB BIT 4 = enable_stop_q_on_full 662 * MSB BIT 5 = enable_full_login_on_lip 663 * MSB BIT 6 = enable_node_name 664 * MSB BIT 7 = extended_control_block 665 */ 666 uint8_t firmware_options[2]; 667 668 uint8_t max_frame_length[2]; 669 uint8_t max_iocb_allocation[2]; 670 uint8_t execution_throttle[2]; 671 uint8_t login_retry_count; 672 uint8_t retry_delay; /* unused */ 673 uint8_t port_name[8]; /* Big endian. */ 674 uint8_t hard_address[2]; /* option bit 0 */ 675 uint8_t inquiry; /* option bit 7 */ 676 uint8_t login_timeout; 677 uint8_t node_name[8]; /* Big endian */ 678 uint8_t request_q_outpointer[2]; 679 uint8_t response_q_inpointer[2]; 680 uint8_t request_q_length[2]; 681 uint8_t response_q_length[2]; 682 uint8_t request_q_address[8]; 683 uint8_t response_q_address[8]; 684 uint8_t lun_enables[2]; 685 uint8_t command_resouce_count; 686 uint8_t immediate_notify_resouce_count; 687 uint8_t timeout[2]; 688 uint8_t reserved_2[2]; 689 690 /* 691 * LSB BIT 0 = Timer operation mode bit 0 692 * LSB BIT 1 = Timer operation mode bit 1 693 * LSB BIT 2 = Timer operation mode bit 2 694 * LSB BIT 3 = Timer operation mode bit 3 695 * LSB BIT 4 = P2P Connection option bit 0 696 * LSB BIT 5 = P2P Connection option bit 1 697 * LSB BIT 6 = P2P Connection option bit 2 698 * LSB BIT 7 = Enable Non part on LIHA failure 699 * 700 * MSB BIT 0 = Enable class 2 701 * MSB BIT 1 = Enable ACK0 702 * MSB BIT 2 = 703 * MSB BIT 3 = 704 * MSB BIT 4 = FC Tape Enable 705 * MSB BIT 5 = Enable FC Confirm 706 * MSB BIT 6 = Enable CRN 707 * MSB BIT 7 = 708 */ 709 uint8_t add_fw_opt[2]; 710 711 uint8_t response_accumulation_timer; 712 uint8_t interrupt_delay_timer; 713 714 /* 715 * LSB BIT 0 = Enable Read xfr_rdy 716 * LSB BIT 1 = Soft ID only 717 * LSB BIT 2 = 718 * LSB BIT 3 = 719 * LSB BIT 4 = FCP RSP Payload [0] 720 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 721 * LSB BIT 6 = 722 * LSB BIT 7 = 723 * 724 * MSB BIT 0 = Sbus enable - 2300 725 * MSB BIT 1 = 726 * MSB BIT 2 = 727 * MSB BIT 3 = 728 * MSB BIT 4 = 729 * MSB BIT 5 = enable 50 ohm termination 730 * MSB BIT 6 = Data Rate (2300 only) 731 * MSB BIT 7 = Data Rate (2300 only) 732 */ 733 uint8_t special_options[2]; 734 735 uint8_t reserved_3[26]; 736 } ql_init_cb_t; 737 /* 738 * Virtual port definition. 739 */ 740 741 typedef struct ql_vp_cfg { 742 uint8_t reserved[2]; 743 uint8_t options; 744 uint8_t hard_prev_addr; 745 uint8_t port_name[8]; 746 uint8_t node_name[8]; 747 } ql_vp_cfg_t; 748 749 /* 750 * VP options. 751 */ 752 #define VPO_TARGET_MODE_DISABLED BIT_5 753 #define VPO_INITIATOR_MODE_ENABLED BIT_4 754 #define VPO_ENABLED BIT_3 755 #define VPO_ID_NOT_ACQUIRED BIT_2 756 #define VPO_PREVIOUSLY_ASSIGNED_ID BIT_1 757 #define VPO_HARD_ASSIGNED_ID BIT_0 758 759 #define ICB_24XX_VERSION 1 760 typedef struct ql_init_24xx_cb { 761 uint8_t version[2]; 762 uint8_t reserved_1[2]; 763 uint8_t max_frame_length[2]; 764 uint8_t execution_throttle[2]; 765 uint8_t exchange_count[2]; 766 uint8_t hard_address[2]; 767 uint8_t port_name[8]; /* Big endian. */ 768 uint8_t node_name[8]; /* Big endian. */ 769 770 uint8_t response_q_inpointer[2]; 771 uint8_t request_q_outpointer[2]; 772 773 uint8_t login_retry_count[2]; 774 775 uint8_t prio_request_q_outpointer[2]; 776 777 uint8_t response_q_length[2]; 778 uint8_t request_q_length[2]; 779 780 uint8_t link_down_on_nos[2]; 781 782 uint8_t prio_request_q_length[2]; 783 uint8_t request_q_address[8]; 784 uint8_t response_q_address[8]; 785 uint8_t prio_request_q_address[8]; 786 uint8_t reserved_2[8]; 787 uint8_t atio_q_inpointer[2]; 788 uint8_t atio_q_length[2]; 789 uint8_t atio_q_address[8]; 790 791 uint8_t interrupt_delay_timer[2]; /* 100us per */ 792 uint8_t login_timeout[2]; 793 /* 794 * BIT 0 = Hard Assigned Loop ID 795 * BIT 1 = Enable Fairness 796 * BIT 2 = Enable Full-Duplex 797 * BIT 3 = Reserved 798 * BIT 4 = Target Mode Enable 799 * BIT 5 = Initiator Mode Disable 800 * BIT 6 = Reserved 801 * BIT 7 = Reserved 802 * 803 * BIT 8 = Reserved 804 * BIT 9 = Disable Initial LIP 805 * BIT 10 = Descending Loop ID Search 806 * BIT 11 = Previous Assigned Loop ID 807 * BIT 12 = Reserved 808 * BIT 13 = Full Login after LIP 809 * BIT 14 = Node Name Option 810 * BIT 15-31 = Reserved 811 */ 812 uint8_t firmware_options_1[4]; 813 814 /* 815 * BIT 0 = Operation Mode bit 0 816 * BIT 1 = Operation Mode bit 1 817 * BIT 2 = Operation Mode bit 2 818 * BIT 3 = Operation Mode bit 3 819 * BIT 4 = Connection Options bit 0 820 * BIT 5 = Connection Options bit 1 821 * BIT 6 = Connection Options bit 2 822 * BIT 7 = Enable Non part on LIHA failure 823 * 824 * BIT 8 = Enable Class 2 825 * BIT 9 = Enable ACK0 826 * BIT 10 = Reserved 827 * BIT 11 = Enable FC-SP Security 828 * BIT 12 = FC Tape Enable 829 * BIT 13-31 = Reserved 830 */ 831 uint8_t firmware_options_2[4]; 832 833 /* 834 * BIT 0 = Reserved 835 * BIT 1 = Soft ID only 836 * BIT 2 = Reserved 837 * BIT 3 = Reserved 838 * BIT 4 = FCP RSP Payload bit 0 839 * BIT 5 = FCP RSP Payload bit 1 840 * BIT 6 = Enable Rec Out-of-Order data frame handling 841 * BIT 7 = Disable Automatic PLOGI on Local Loop 842 * 843 * BIT 8 = Reserved 844 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 845 * offset handling 846 * BIT 10 = Reserved 847 * BIT 11 = Reserved 848 * BIT 12 = Reserved 849 * BIT 13 = Data Rate bit 0 850 * BIT 14 = Data Rate bit 1 851 * BIT 15 = Data Rate bit 2 852 * BIT 16 = 75-ohm Termination Select 853 * BIT 17-31 = Reserved 854 */ 855 uint8_t firmware_options_3[4]; 856 857 uint8_t reserved_3[24]; 858 859 /* 860 * Multi-ID firmware. 861 */ 862 uint8_t vp_count[2]; 863 864 /* 865 * BIT 1 = Allows mode 2 connection option 866 */ 867 uint8_t global_vp_option[2]; 868 869 ql_vp_cfg_t vpc[MAX_25_VIRTUAL_PORTS]; 870 } ql_init_24xx_cb_t; 871 872 typedef union ql_comb_init_cb { 873 ql_init_cb_t cb; 874 ql_init_24xx_cb_t cb24; 875 } ql_comb_init_cb_t; 876 877 /* 878 * ISP IP Initialization Control Block. 879 * Little endian except where noted. 880 */ 881 #define IP_ICB_VERSION 1 882 typedef struct ql_ip_init_cb { 883 uint8_t version; 884 uint8_t reserved; 885 886 /* 887 * LSB BIT 0 = receive_buffer_address_length 888 * LSB BIT 1 = fast post broadcast received 889 * LSB BIT 2 = allow out of receive buffers AE 890 */ 891 uint8_t ip_firmware_options[2]; 892 uint8_t ip_header_size[2]; 893 uint8_t mtu_size[2]; /* max value is 65280 */ 894 uint8_t buf_size[2]; 895 uint8_t reserved_1[8]; 896 uint8_t queue_size[2]; /* 8-1024 */ 897 uint8_t low_water_mark[2]; 898 uint8_t queue_address[8]; 899 uint8_t queue_inpointer[2]; 900 uint8_t fast_post_reg_count[2]; /* 0-14 */ 901 uint8_t cc[2]; 902 uint8_t reserved_2[28]; 903 } ql_ip_init_cb_t; 904 905 #define IP_ICB_24XX_VERSION 1 906 typedef struct ql_ip_init_24xx_cb { 907 uint8_t version; 908 uint8_t reserved; 909 /* 910 * LSB BIT 2 = allow out of receive buffers AE 911 */ 912 uint8_t ip_firmware_options[2]; 913 uint8_t ip_header_size[2]; 914 uint8_t mtu_size[2]; 915 uint8_t buf_size[2]; 916 uint8_t reserved_1[10]; 917 uint8_t low_water_mark[2]; 918 uint8_t reserved_3[12]; 919 uint8_t cc[2]; 920 uint8_t reserved_2[28]; 921 } ql_ip_init_24xx_cb_t; 922 923 typedef union ql_comb_ip_init_cb { 924 ql_ip_init_cb_t cb; 925 ql_ip_init_24xx_cb_t cb24; 926 } ql_comb_ip_init_cb_t; 927 928 /* 929 * f/w module table 930 */ 931 struct fw_table { 932 uint16_t fw_class; 933 int8_t *fw_version; 934 }; 935 936 /* 937 * aif function table 938 */ 939 typedef struct ql_ifunc { 940 uint_t (*ifunc)(); 941 } ql_ifunc_t; 942 943 #define QL_MSIX_AIF 0x0 944 #define QL_MSIX_RSPQ 0x1 945 #define QL_MSIX_MAXAIF QL_MSIX_RSPQ + 1 946 947 /* 948 * DMA memory type. 949 */ 950 typedef enum mem_alloc_type { 951 UNKNOWN_MEMORY, 952 TASK_MEMORY, 953 LITTLE_ENDIAN_DMA, 954 BIG_ENDIAN_DMA, 955 KERNEL_MEM, 956 NO_SWAP_DMA, 957 STRUCT_BUF_MEMORY 958 } mem_alloc_type_t; 959 960 /* 961 * DMA memory alignment type. 962 */ 963 typedef enum men_align_type { 964 MEM_DATA_ALIGN, 965 MEM_RING_ALIGN 966 } mem_alignment_t; 967 968 /* 969 * DMA memory object. 970 */ 971 typedef struct dma_mem { 972 uint64_t alignment; 973 void *bp; 974 ddi_dma_cookie_t *cookies; 975 ddi_acc_handle_t acc_handle; 976 ddi_dma_handle_t dma_handle; 977 ddi_dma_cookie_t cookie; 978 uint32_t cookie_count; 979 uint32_t size; 980 uint32_t memflags; 981 mem_alloc_type_t type; 982 uint32_t flags; /* Solaris DMA flags. */ 983 } dma_mem_t; 984 985 /* 986 * dma_mem_t memflags defines 987 */ 988 #define MFLG_32BIT_ONLY BIT_0 989 990 /* 991 * 24 bit port ID type definition. 992 */ 993 typedef union { 994 struct { 995 uint8_t d_id[3]; 996 uint8_t rsvd_1; 997 }r; 998 999 uint32_t b24 : 24; 1000 1001 #if defined(_BIT_FIELDS_LTOH) 1002 struct { 1003 uint8_t al_pa; 1004 uint8_t area; 1005 uint8_t domain; 1006 uint8_t rsvd_1; 1007 }b; 1008 #elif defined(_BIT_FIELDS_HTOL) 1009 struct { 1010 uint8_t domain; 1011 uint8_t area; 1012 uint8_t al_pa; 1013 uint8_t rsvd_1; 1014 }b; 1015 #else 1016 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined 1017 #endif 1018 } port_id_t; 1019 1020 /* 1021 * Link list definitions. 1022 */ 1023 typedef struct ql_link { 1024 struct ql_link *prev; 1025 struct ql_link *next; 1026 void *base_address; 1027 struct ql_head *head; /* the queue this link is on */ 1028 } ql_link_t; 1029 1030 typedef struct ql_head { 1031 ql_link_t *first; 1032 ql_link_t *last; 1033 } ql_head_t; 1034 1035 /* 1036 * This is the driver target command structure 1037 */ 1038 typedef struct tgt_cmd { 1039 /* Command link. */ 1040 ql_link_t cmd; 1041 1042 uint8_t type; 1043 uint8_t initiator_id_l; 1044 uint8_t initiator_id_h; 1045 uint16_t rx_id; 1046 1047 uint16_t status; 1048 uint8_t task_flags_l; 1049 uint8_t task_flags_h; 1050 uint8_t execution_codes; 1051 } tgt_cmd_t; 1052 1053 /* Target cmd states */ 1054 #define TGT_CMD_RECEIVED 0x00 1055 #define TGT_CMD_SENT_UP 0x01 1056 #define TGT_CMD_IN_FW 0x02 1057 1058 /* 1059 * This is the per-command structure 1060 */ 1061 typedef struct ql_srb { 1062 /* Command link. */ 1063 ql_link_t cmd; 1064 1065 /* Watchdog link and timer. */ 1066 ql_link_t wdg; 1067 time_t wdg_q_time; 1068 time_t init_wdg_q_time; 1069 uint16_t isp_timeout; 1070 1071 /* FCA and FC Transport data. */ 1072 fc_packet_t *pkt; 1073 struct ql_adapter_state *ha; 1074 uint32_t magic_number; 1075 1076 /* unsolicited buffer context. */ 1077 dma_mem_t ub_buffer; 1078 uint32_t ub_type; 1079 uint32_t ub_size; 1080 1081 /* FCP command. */ 1082 fcp_cmd_t *fcp; 1083 1084 /* Request sense. */ 1085 uint32_t request_sense_length; 1086 caddr_t request_sense_ptr; 1087 1088 /* Device queue pointer. */ 1089 struct ql_lun *lun_queue; 1090 1091 /* Target command pointer. */ 1092 tgt_cmd_t *tgt_cmd; 1093 1094 /* Command state/status flags. */ 1095 volatile uint32_t flags; 1096 1097 /* Command IOCB context. */ 1098 void (*iocb)(struct ql_adapter_state *, 1099 struct ql_srb *, void *); 1100 uint32_t handle; 1101 uint16_t req_cnt; 1102 uint8_t retry_count; 1103 } ql_srb_t; 1104 1105 #define SRB_ISP_STARTED BIT_0 /* Command sent to ISP. */ 1106 #define SRB_ISP_COMPLETED BIT_1 /* ISP finished with command. */ 1107 #define SRB_RETRY BIT_2 /* Driver retrying command. */ 1108 #define SRB_POLL BIT_3 /* Poll for completion. */ 1109 #define SRB_WATCHDOG_ENABLED BIT_4 /* Command on watchdog list. */ 1110 #define SRB_ABORT BIT_5 /* SRB to be aborted. */ 1111 #define SRB_UB_IN_FCA BIT_6 /* FCA holds unsolicited buffer */ 1112 #define SRB_UB_IN_ISP BIT_7 /* ISP holds unsolicited buffer */ 1113 #define SRB_UB_CALLBACK BIT_8 /* Unsolicited callback needed. */ 1114 #define SRB_UB_RSCN BIT_9 /* Unsolicited RSCN callback. */ 1115 #define SRB_UB_FCP BIT_10 /* Unsolicited RSCN callback. */ 1116 #define SRB_FCP_CMD_PKT BIT_11 /* FCP command type packet. */ 1117 #define SRB_FCP_DATA_PKT BIT_12 /* FCP data type packet. */ 1118 #define SRB_FCP_RSP_PKT BIT_13 /* FCP response type packet. */ 1119 #define SRB_IP_PKT BIT_14 /* IP type packet. */ 1120 #define SRB_GENERIC_SERVICES_PKT BIT_15 /* Generic services type packet */ 1121 #define SRB_COMMAND_TIMEOUT BIT_16 /* Command timed out. */ 1122 #define SRB_ABORTING BIT_17 /* SRB aborting. */ 1123 #define SRB_IN_DEVICE_QUEUE BIT_18 /* In Device Queue */ 1124 #define SRB_IN_TOKEN_ARRAY BIT_19 /* In Token Array */ 1125 #define SRB_UB_FREE_REQUESTED BIT_20 /* UB Free requested */ 1126 #define SRB_UB_ACQUIRED BIT_21 /* UB selected for upcall */ 1127 #define SRB_MS_PKT BIT_22 /* Management Service pkt */ 1128 1129 /* 1130 * This byte will be used to define flags for the LUN on the target. 1131 * Presently, we have untagged-command as one flag. Others can be 1132 * added later, if needed. 1133 */ 1134 typedef struct tgt_lun_flags { 1135 uint8_t 1136 untagged_pending:1, 1137 unused_bits:7; 1138 } tgt_lun_flags_t; 1139 1140 #define QL_IS_UNTAGGED_PENDING(q, lun_num) \ 1141 ((q->lun_flags[lun_num].untagged_pending == TRUE) ? 1 : 0) 1142 #define QL_SET_UNTAGGED_PENDING(q, lun_num) \ 1143 (q->lun_flags[lun_num].untagged_pending = TRUE) 1144 #define QL_CLEAR_UNTAGGED_PENDING(q, lun_num) \ 1145 (q->lun_flags[lun_num].untagged_pending = FALSE) 1146 1147 /* 1148 * Fibre Channel LUN Queue structure 1149 */ 1150 typedef struct ql_lun { 1151 /* Head command link. */ 1152 ql_head_t cmd; 1153 1154 struct ql_target *target_queue; 1155 1156 uint32_t flags; 1157 1158 /* LUN execution throttle. */ 1159 uint16_t lun_outcnt; 1160 1161 uint16_t lun_no; 1162 1163 ql_link_t link; 1164 } ql_lun_t; 1165 1166 /* 1167 * LUN Queue flags 1168 */ 1169 #define LQF_UNTAGGED_PENDING BIT_0 1170 1171 /* 1172 * Fibre Channel Device Queue structure 1173 */ 1174 typedef struct ql_target { 1175 /* Device queue lock. */ 1176 kmutex_t mutex; 1177 1178 /* Head target command link. */ 1179 ql_head_t tgt_cmd; 1180 1181 volatile uint32_t flags; 1182 port_id_t d_id; 1183 uint16_t loop_id; 1184 volatile uint16_t outcnt; /* # of cmds running in ISP */ 1185 uint32_t iidma_rate; 1186 1187 1188 /* Device link. */ 1189 ql_link_t device; 1190 1191 /* Head watchdog link. */ 1192 ql_head_t wdg; 1193 1194 /* Unsolicited buffer IP data. */ 1195 uint32_t ub_frame_ro; 1196 uint16_t ub_sequence_length; 1197 uint16_t ub_loop_id; 1198 uint8_t ub_total_seg_cnt; 1199 uint8_t ub_seq_cnt; 1200 uint8_t ub_seq_id; 1201 1202 /* Port down retry counter. */ 1203 uint16_t port_down_retry_count; 1204 uint16_t qfull_retry_count; 1205 1206 /* logout sent state */ 1207 uint8_t logout_sent; 1208 1209 /* Data from Port database matches machine type. */ 1210 uint8_t master_state; 1211 uint8_t slave_state; 1212 port_id_t hard_addr; 1213 uint8_t port_name[8]; 1214 uint8_t node_name[8]; 1215 uint16_t cmn_features; 1216 uint16_t conc_sequences; 1217 uint16_t relative_offset; 1218 uint16_t class3_recipient_ctl; 1219 uint16_t class3_rcv_data_size; 1220 uint16_t class3_conc_sequences; 1221 uint16_t class3_open_sequences_per_exch; 1222 uint16_t prli_payload_length; 1223 uint16_t prli_svc_param_word_0; 1224 uint16_t prli_svc_param_word_3; 1225 1226 /* LUN context. */ 1227 ql_head_t lun_queues; 1228 ql_lun_t *last_lun_queue; 1229 } ql_tgt_t; 1230 1231 /* 1232 * Target Queue flags 1233 */ 1234 #define TQF_TAPE_DEVICE BIT_0 1235 #define TQF_QUEUE_SUSPENDED BIT_1 /* Queue suspended. */ 1236 #define TQF_FABRIC_DEVICE BIT_2 1237 #define TQF_INITIATOR_DEVICE BIT_3 1238 #define TQF_RSCN_RCVD BIT_4 1239 #define TQF_NEED_AUTHENTICATION BIT_5 1240 #define TQF_PLOGI_PROGRS BIT_6 1241 #define TQF_IIDMA_NEEDED BIT_7 1242 1243 /* 1244 * iiDMA 1245 */ 1246 #define IIDMA_RATE_INIT 0xffffffff /* init state */ 1247 #define IIDMA_RATE_NDEF 0xfffffffe /* not defined in conf file */ 1248 #define IIDMA_RATE_1GB 0x0 1249 #define IIDMA_RATE_2GB 0x1 1250 #define IIDMA_RATE_4GB 0x3 1251 #define IIDMA_RATE_8GB 0x4 1252 #define IIDMA_RATE_MAX IIDMA_RATE_8GB 1253 1254 /* 1255 * Kernel statistic structure definitions. 1256 */ 1257 typedef struct ql_device_stat { 1258 int logouts_recvd; 1259 int task_mgmt_failures; 1260 int data_ro_mismatches; 1261 int dl_len_mismatches; 1262 } ql_device_stat_t; 1263 1264 typedef struct ql_adapter_24xx_stat { 1265 int version; /* version of this struct */ 1266 int lip_count; /* lips forced */ 1267 int ncmds; /* outstanding commands */ 1268 ql_adapter_revlvl_t revlvl; /* adapter revision levels */ 1269 ql_device_stat_t d_stats[MAX_24_FIBRE_DEVICES]; /* per device stats */ 1270 } ql_adapter_stat_t; 1271 1272 /* 1273 * Firmware code segment. 1274 */ 1275 #define MAX_RISC_CODE_SEGMENTS 3 1276 typedef struct fw_code { 1277 caddr_t code; 1278 uint32_t addr; 1279 uint32_t length; 1280 } ql_fw_code_t; 1281 1282 /* diagnostic els ECHO defines */ 1283 #define QL_ECHO_CMD 0x10000000 /* echo opcode */ 1284 #define QL_ECHO_CMD_LENGTH 220 /* command length */ 1285 1286 /* DUMP state flags. */ 1287 #define QL_DUMPING BIT_0 1288 #define QL_DUMP_VALID BIT_1 1289 #define QL_DUMP_UPLOADED BIT_2 1290 1291 /* f/w trace sizes */ 1292 #define FWEXTSIZE (0x4000 * 4) /* bytes - 16kb multiples */ 1293 #define FWFCESIZE (0x4000 * 4) /* bytes - 16kb multiples */ 1294 1295 /* 1296 * ql attach progress indication 1297 */ 1298 #define QL_SOFT_STATE_ALLOCED BIT_0 1299 #define QL_REGS_MAPPED BIT_1 1300 #define QL_HBA_BUFFER_SETUP BIT_2 1301 #define QL_MUTEX_CV_INITED BIT_3 1302 #define QL_INTR_ADDED BIT_4 1303 #define QL_CONFIG_SPACE_SETUP BIT_5 1304 #define QL_TASK_DAEMON_STARTED BIT_6 1305 #define QL_KSTAT_CREATED BIT_7 1306 #define QL_MINOR_NODE_CREATED BIT_8 1307 #define QL_FCA_TRAN_ALLOCED BIT_9 1308 #define QL_FCA_ATTACH_DONE BIT_10 1309 #define QL_IOMAP_IOBASE_MAPPED BIT_11 1310 1311 /* Device queue head list size (based on AL_PA address). */ 1312 #define DEVICE_HEAD_LIST_SIZE 0x81 1313 1314 /* 1315 * Adapter state structure. 1316 */ 1317 typedef struct ql_adapter_state { 1318 ql_link_t hba; 1319 1320 kmutex_t mutex; 1321 volatile uint32_t flags; /* State flags. */ 1322 uint32_t state; 1323 port_id_t d_id; 1324 uint16_t loop_id; 1325 uint8_t topology; 1326 uint16_t sfp_stat; 1327 1328 uint16_t idle_timer; 1329 uint8_t loop_down_abort_time; 1330 uint8_t port_retry_timer; 1331 uint8_t loop_down_timer; 1332 uint8_t watchdog_timer; 1333 uint16_t r_a_tov; /* 2 * R_A_TOV + 5 */ 1334 1335 /* Task Daemon context. */ 1336 callb_cpr_t cprinfo; 1337 kmutex_t task_daemon_mutex; 1338 kcondvar_t cv_dr_suspended; 1339 kcondvar_t cv_task_daemon; 1340 volatile uint32_t task_daemon_flags; 1341 ql_head_t callback_queue; 1342 1343 /* Interrupt context. */ 1344 kmutex_t intr_mutex; 1345 uint8_t *iobase; 1346 uint8_t rev_id; 1347 uint16_t device_id; 1348 uint16_t subsys_id; 1349 uint16_t subven_id; 1350 uint16_t ven_id; 1351 uint16_t fw_class; 1352 ql_srb_t *status_srb; 1353 volatile uint8_t intr_claimed; 1354 1355 /* 1356 * ISP request queue, response queue, mailbox buffer and 1357 * IP receive queue buffer. 1358 */ 1359 dma_mem_t hba_buf; 1360 1361 /* ISP request queue context. */ 1362 kmutex_t req_ring_mutex; 1363 struct cmd_entry *request_ring_bp; 1364 struct cmd_entry *request_ring_ptr; 1365 uint64_t request_dvma; 1366 uint16_t req_ring_index; 1367 uint16_t req_q_cnt; /* # of available entries. */ 1368 ql_head_t pending_cmds; 1369 ql_srb_t **outstanding_cmds; 1370 uint16_t osc_index; 1371 1372 /* ISP response queue context. */ 1373 struct sts_entry *response_ring_bp; 1374 struct sts_entry *response_ring_ptr; 1375 uint64_t response_dvma; 1376 uint16_t rsp_ring_index; 1377 uint16_t isp_rsp_index; 1378 1379 /* Mailbox context. */ 1380 kmutex_t mbx_mutex; 1381 caddr_t mbx_bp; 1382 struct mbx_cmd *mcp; 1383 kcondvar_t cv_mbx_wait; 1384 kcondvar_t cv_mbx_intr; 1385 volatile uint8_t mailbox_flags; 1386 1387 /* ISP receive buffer queue context. */ 1388 ql_tgt_t *rcv_dev_q; 1389 struct rcvbuf *rcvbuf_ring_bp; 1390 struct rcvbuf *rcvbuf_ring_ptr; 1391 uint64_t rcvbuf_dvma; 1392 uint16_t rcvbuf_ring_index; 1393 1394 /* Unsolicited buffer data. */ 1395 uint16_t ub_outcnt; 1396 uint8_t ub_seq_id; 1397 uint8_t ub_command_count; 1398 uint8_t ub_notify_count; 1399 uint32_t ub_allocated; 1400 kmutex_t ub_mutex; 1401 kcondvar_t cv_ub; 1402 fc_unsol_buf_t **ub_array; 1403 1404 /* Head of device queue list. */ 1405 ql_head_t *dev; 1406 1407 /* Kernel statistics. */ 1408 kstat_t *k_stats; 1409 ql_adapter_stat_t *adapter_stats; 1410 1411 /* Solaris adapter configuration data */ 1412 ddi_acc_handle_t dev_handle; 1413 ddi_acc_handle_t pci_handle; /* config space */ 1414 ddi_acc_handle_t iomap_dev_handle; 1415 caddr_t iomap_iobase; 1416 dev_info_t *dip; 1417 ddi_iblock_cookie_t iblock_cookie; 1418 fc_fca_tran_t *tran; 1419 int instance; 1420 int8_t *devpath; 1421 uint32_t fru_hba_index; 1422 uint32_t fru_port_index; 1423 uint8_t adapInfo[18]; 1424 1425 /* Adapter context */ 1426 la_els_logi_t loginparams; 1427 fc_fca_bind_info_t bind_info; 1428 ddi_modhandle_t fw_module; 1429 uint16_t fw_major_version; 1430 uint16_t fw_minor_version; 1431 uint16_t fw_subminor_version; 1432 uint16_t fw_attributes; 1433 uint32_t fw_ext_memory_size; 1434 uint32_t parity_pause_errors; 1435 uint16_t parity_hccr_err; 1436 uint32_t parity_stat_err; 1437 reg_off_t *reg_off; 1438 caddr_t risc_code; 1439 uint32_t risc_code_size; 1440 ql_fw_code_t risc_fw[MAX_RISC_CODE_SEGMENTS]; 1441 uint32_t risc_dump_size; 1442 void (*fcp_cmd)(struct ql_adapter_state *, 1443 ql_srb_t *, void *); 1444 void (*ip_cmd)(struct ql_adapter_state *, 1445 ql_srb_t *, void *); 1446 void (*ms_cmd)(struct ql_adapter_state *, 1447 ql_srb_t *, void *); 1448 void (*ctio_cmd)(struct ql_adapter_state *, 1449 ql_srb_t *, void *); 1450 uint8_t cmd_segs; 1451 uint8_t cmd_cont_segs; 1452 1453 /* Target mode context. */ 1454 tgt_cmd_t *ql_nack; 1455 kmutex_t ql_nack_mtx; 1456 1457 /* NVRAM configuration data */ 1458 uint32_t cfg_flags; 1459 ql_comb_init_cb_t init_ctrl_blk; 1460 ql_comb_ip_init_cb_t ip_init_ctrl_blk; 1461 uint16_t nvram_version; 1462 uint16_t adapter_features; 1463 uint32_t fw_transfer_size; 1464 uint16_t execution_throttle; 1465 uint16_t port_down_retry_count; 1466 uint8_t port_down_retry_delay; 1467 uint8_t qfull_retry_count; 1468 uint8_t qfull_retry_delay; 1469 uint16_t serdes_param[4]; 1470 uint8_t loop_reset_delay; 1471 1472 /* Power management context. */ 1473 kmutex_t pm_mutex; 1474 uint32_t busy; 1475 uint8_t power_level; 1476 uint8_t pm_capable; 1477 uint8_t config_saved; 1478 uint8_t lip_on_panic; 1479 port_id_t port_hard_address; 1480 1481 /* sbus card data */ 1482 caddr_t sbus_fpga_iobase; 1483 ddi_acc_handle_t sbus_fpga_dev_handle; 1484 ddi_acc_handle_t sbus_config_handle; 1485 caddr_t sbus_config_base; 1486 1487 /* XIOCTL context pointer. */ 1488 struct ql_xioctl *xioctl; 1489 1490 kmutex_t cache_mutex; 1491 struct ql_fcache *fcache; 1492 int8_t *vcache; 1493 1494 /* AIF (Advanced Interrupt Framework) support */ 1495 ddi_intr_handle_t *htable; 1496 uint32_t hsize; 1497 int32_t intr_cnt; 1498 uint32_t intr_pri; 1499 int32_t intr_cap; 1500 uint32_t iflags; 1501 1502 /* PCI maximum read request override */ 1503 uint16_t pci_max_read_req; 1504 1505 /* port manage mutex */ 1506 kmutex_t portmutex; 1507 uint16_t maximum_luns_per_target; 1508 1509 uint8_t fwwait; 1510 dma_mem_t fwexttracebuf; 1511 dma_mem_t fwfcetracebuf; 1512 uint32_t fwfcetraceopt; 1513 uint32_t flash_errlog_start; /* 32bit word addr */ 1514 uint32_t flash_errlog_ptr; /* 32bit word addr */ 1515 1516 /* Virtual port context. */ 1517 fca_port_attrs_t *pi_attrs; 1518 struct ql_adapter_state *pha; 1519 struct ql_adapter_state *vp_next; 1520 uint8_t vp_index; 1521 1522 uint16_t free_loop_id; 1523 1524 } ql_adapter_state_t; 1525 1526 /* 1527 * adapter state flags 1528 */ 1529 #define FCA_BOUND BIT_0 1530 #define QL_OPENED BIT_1 1531 #define ONLINE BIT_2 1532 #define INTERRUPTS_ENABLED BIT_3 1533 #define COMMAND_ABORT_TIMEOUT BIT_4 1534 #define POINT_TO_POINT BIT_5 1535 #define IP_ENABLED BIT_6 1536 #define IP_INITIALIZED BIT_7 1537 #define TARGET_MODE_INITIALIZED BIT_8 1538 #define ADAPTER_SUSPENDED BIT_9 1539 #define ADAPTER_TIMER_BUSY BIT_10 1540 #define PARITY_ERROR BIT_11 1541 #define FLASH_ERRLOG_MARKER BIT_12 1542 #define VP_ENABLED BIT_13 1543 #define FDISC_ENABLED BIT_14 1544 #define MENLO_LOGIN_OPERATIONAL BIT_15 1545 1546 /* 1547 * task daemon flags 1548 */ 1549 #define TASK_DAEMON_STOP_FLG BIT_0 1550 #define TASK_DAEMON_SLEEPING_FLG BIT_1 1551 #define TASK_DAEMON_ALIVE_FLG BIT_2 1552 #define TASK_DAEMON_IDLE_CHK_FLG BIT_3 1553 #define SUSPENDED_WAKEUP_FLG BIT_4 1554 #define FC_STATE_CHANGE BIT_5 1555 #define NEED_UNSOLICITED_BUFFERS BIT_6 1556 #define RESET_MARKER_NEEDED BIT_7 1557 #define RESET_ACTIVE BIT_8 1558 #define ISP_ABORT_NEEDED BIT_9 1559 #define ABORT_ISP_ACTIVE BIT_10 1560 #define LOOP_RESYNC_NEEDED BIT_11 1561 #define LOOP_RESYNC_ACTIVE BIT_12 1562 #define LOOP_DOWN BIT_13 1563 #define DRIVER_STALL BIT_14 1564 #define COMMAND_WAIT_NEEDED BIT_15 1565 #define COMMAND_WAIT_ACTIVE BIT_16 1566 #define STATE_ONLINE BIT_17 1567 #define ABORT_QUEUES_NEEDED BIT_18 1568 #define TASK_DAEMON_STALLED_FLG BIT_19 1569 #define TASK_THREAD_CALLED BIT_20 1570 #define FIRMWARE_UP BIT_21 1571 #define LIP_RESET_PENDING BIT_22 1572 #define FIRMWARE_LOADED BIT_23 1573 #define RSCN_UPDATE_NEEDED BIT_24 1574 #define HANDLE_PORT_BYPASS_CHANGE BIT_25 1575 #define PORT_RETRY_NEEDED BIT_26 1576 #define TASK_DAEMON_POWERING_DOWN BIT_27 1577 #define TD_IIDMA_NEEDED BIT_28 1578 1579 /* 1580 * Mailbox flags 1581 */ 1582 #define MBX_WANT_FLG BIT_0 1583 #define MBX_BUSY_FLG BIT_1 1584 #define MBX_INTERRUPT BIT_2 1585 #define MBX_ABORT BIT_3 1586 1587 /* 1588 * Configuration flags 1589 */ 1590 #define CFG_ENABLE_HARD_ADDRESS BIT_0 1591 #define CFG_ENABLE_64BIT_ADDRESSING BIT_1 1592 #define CFG_ENABLE_LIP_RESET BIT_2 1593 #define CFG_ENABLE_FULL_LIP_LOGIN BIT_3 1594 #define CFG_ENABLE_TARGET_RESET BIT_4 1595 #define CFG_ENABLE_LINK_DOWN_REPORTING BIT_5 1596 #define CFG_ENABLE_TARGET_MODE BIT_6 1597 #define CFG_ENABLE_FCP_2_SUPPORT BIT_7 1598 #define CFG_MULTI_CHIP_ADAPTER BIT_8 1599 #define CFG_SBUS_CARD BIT_9 1600 #define CFG_CTRL_2300 BIT_10 1601 #define CFG_CTRL_6322 BIT_11 1602 #define CFG_CTRL_2200 BIT_12 1603 #define CFG_CTRL_2422 BIT_13 1604 #define CFG_CTRL_25XX BIT_14 1605 #define CFG_ENABLE_EXTENDED_LOGGING BIT_15 1606 #define CFG_DISABLE_RISC_CODE_LOAD BIT_16 1607 #define CFG_SET_CACHE_LINE_SIZE_1 BIT_17 1608 #define CFG_TARGET_MODE_ENABLE BIT_18 1609 #define CFG_EXT_FW_INTERFACE BIT_19 1610 #define CFG_LOAD_FLASH_FW BIT_20 1611 #define CFG_DUMP_MAILBOX_TIMEOUT BIT_21 1612 #define CFG_DUMP_ISP_SYSTEM_ERROR BIT_22 1613 #define CFG_DUMP_DRIVER_COMMAND_TIMEOUT BIT_23 1614 #define CFG_DUMP_LOOP_OFFLINE_TIMEOUT BIT_24 1615 #define CFG_ENABLE_FWEXTTRACE BIT_25 1616 #define CFG_ENABLE_FWFCETRACE BIT_26 1617 #define CFG_FW_MISMATCH BIT_27 1618 #define CFG_CTRL_MENLO BIT_28 1619 1620 #define CFG_CTRL_2425 (CFG_CTRL_2422 | CFG_CTRL_25XX) 1621 #define CFG_IST(ha, cfgflags) (ha->cfg_flags & cfgflags) 1622 1623 /* 1624 * Interrupt configuration flags 1625 */ 1626 #define IFLG_INTR_LEGACY BIT_0 1627 #define IFLG_INTR_FIXED BIT_1 1628 #define IFLG_INTR_MSI BIT_2 1629 #define IFLG_INTR_MSIX BIT_3 1630 1631 #define IFLG_INTR_AIF (IFLG_INTR_MSI | IFLG_INTR_FIXED | IFLG_INTR_MSIX) 1632 1633 /* 1634 * Macros to help code, maintain, etc. 1635 */ 1636 #define LSB(x) (uint8_t)(x) 1637 #define MSB(x) (uint8_t)((uint16_t)(x) >> 8) 1638 #define MSW(x) (uint16_t)((uint32_t)(x) >> 16) 1639 #define LSW(x) (uint16_t)(x) 1640 #define LSD(x) (uint32_t)(x) 1641 #define MSD(x) (uint32_t)((uint64_t)(x) >> 32) 1642 1643 #define SHORT_TO_LONG(lsw, msw) (uint32_t)((uint16_t)msw << 16 | (uint16_t)lsw) 1644 #define CHAR_TO_SHORT(lsb, msb) (uint16_t)((uint8_t)msb << 8 | (uint8_t)lsb) 1645 #define CHAR_TO_LONG(lsb, b1, b2, msb) \ 1646 (uint32_t)(SHORT_TO_LONG(CHAR_TO_SHORT(lsb, b1), \ 1647 CHAR_TO_SHORT(b2, msb))) 1648 1649 /* Little endian machine correction defines. */ 1650 #ifdef _LITTLE_ENDIAN 1651 #define LITTLE_ENDIAN_16(x) 1652 #define LITTLE_ENDIAN_24(x) 1653 #define LITTLE_ENDIAN_32(x) 1654 #define LITTLE_ENDIAN_64(x) 1655 #define LITTLE_ENDIAN(bp, bytes) 1656 #define BIG_ENDIAN_16(x) ql_chg_endian((uint8_t *)x, 2) 1657 #define BIG_ENDIAN_24(x) ql_chg_endian((uint8_t *)x, 3) 1658 #define BIG_ENDIAN_32(x) ql_chg_endian((uint8_t *)x, 4) 1659 #define BIG_ENDIAN_64(x) ql_chg_endian((uint8_t *)x, 8) 1660 #define BIG_ENDIAN(bp, bytes) ql_chg_endian((uint8_t *)bp, bytes) 1661 #endif /* _LITTLE_ENDIAN */ 1662 1663 /* Big endian machine correction defines. */ 1664 #ifdef _BIG_ENDIAN 1665 #define LITTLE_ENDIAN_16(x) ql_chg_endian((uint8_t *)x, 2) 1666 #define LITTLE_ENDIAN_24(x) ql_chg_endian((uint8_t *)x, 3) 1667 #define LITTLE_ENDIAN_32(x) ql_chg_endian((uint8_t *)x, 4) 1668 #define LITTLE_ENDIAN_64(x) ql_chg_endian((uint8_t *)x, 8) 1669 #define LITTLE_ENDIAN(bp, bytes) ql_chg_endian((uint8_t *)bp, bytes) 1670 #define BIG_ENDIAN_16(x) 1671 #define BIG_ENDIAN_24(x) 1672 #define BIG_ENDIAN_32(x) 1673 #define BIG_ENDIAN_64(x) 1674 #define BIG_ENDIAN(bp, bytes) 1675 #endif /* _BIG_ENDIAN */ 1676 1677 #define LOCAL_LOOP_ID(x) (x <= LAST_LOCAL_LOOP_ID) 1678 1679 #define FABRIC_LOOP_ID(x) (x == FL_PORT_LOOP_ID || \ 1680 x == SIMPLE_NAME_SERVER_LOOP_ID) 1681 1682 #define SNS_LOOP_ID(x) (x >= SNS_FIRST_LOOP_ID && \ 1683 x <= SNS_LAST_LOOP_ID) 1684 1685 #define BROADCAST_LOOP_ID(x) (x == IP_BROADCAST_LOOP_ID) 1686 1687 #define VALID_LOOP_ID(x) (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x) || \ 1688 FABRIC_LOOP_ID(x) || BROADCAST_LOOP_ID(x)) 1689 1690 #define VALID_N_PORT_HDL(x) (x <= LAST_N_PORT_HDL || \ 1691 (x >= SNS_24XX_HDL && x <= BROADCAST_24XX_HDL)) 1692 1693 #define VALID_DEVICE_ID(ha, x) \ 1694 (ha->cfg_flags & (CFG_CTRL_2422 | CFG_CTRL_25XX) ? \ 1695 VALID_N_PORT_HDL(x) : VALID_LOOP_ID(x)) 1696 1697 #define VALID_TARGET_ID(ha, x) \ 1698 (ha->cfg_flags & (CFG_CTRL_2422 | CFG_CTRL_25XX) ? \ 1699 (x <= LAST_N_PORT_HDL) : (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x))) 1700 1701 #define RESERVED_LOOP_ID(ha, x) \ 1702 (ha->cfg_flags & (CFG_CTRL_2422 | CFG_CTRL_25XX) ? \ 1703 (x > LAST_N_PORT_HDL && x <= FL_PORT_24XX_HDL) : \ 1704 (x >= FL_PORT_LOOP_ID && x <= SIMPLE_NAME_SERVER_LOOP_ID)) 1705 1706 #define QL_LOOP_TRANSITION (RESET_MARKER_NEEDED | RESET_ACTIVE | \ 1707 ISP_ABORT_NEEDED | ABORT_ISP_ACTIVE | \ 1708 LOOP_RESYNC_NEEDED | LOOP_RESYNC_ACTIVE | \ 1709 COMMAND_WAIT_NEEDED | COMMAND_WAIT_ACTIVE) 1710 1711 #define QL_SUSPENDED (QL_LOOP_TRANSITION | LOOP_DOWN | DRIVER_STALL) 1712 1713 #define LOOP_RECONFIGURE(ha) (ha->task_daemon_flags & (QL_LOOP_TRANSITION | \ 1714 DRIVER_STALL)) 1715 1716 #define DRIVER_SUSPENDED(ha) (ha->task_daemon_flags & QL_SUSPENDED) 1717 1718 #define LOOP_NOT_READY(ha) (ha->task_daemon_flags & (QL_LOOP_TRANSITION | \ 1719 LOOP_DOWN)) 1720 1721 #define LOOP_READY(ha) (LOOP_NOT_READY(ha) == 0) 1722 1723 #define QL_TASK_PENDING(ha) ( \ 1724 ha->task_daemon_flags & (QL_LOOP_TRANSITION | ABORT_QUEUES_NEEDED | \ 1725 PORT_RETRY_NEEDED) || ha->callback_queue.first != NULL) 1726 1727 #define QL_DAEMON_NOT_ACTIVE(ha) ( \ 1728 !(ha->task_daemon_flags & TASK_DAEMON_ALIVE_FLG) || \ 1729 ha->task_daemon_flags & (TASK_DAEMON_SLEEPING_FLG | \ 1730 TASK_DAEMON_STOP_FLG)) 1731 1732 #define QL_DAEMON_SUSPENDED(ha) (\ 1733 (((ha)->cprinfo.cc_events & CALLB_CPR_START) ||\ 1734 ((ha)->flags & ADAPTER_SUSPENDED))) 1735 1736 /* 1737 * Locking Macro Definitions 1738 */ 1739 #define GLOBAL_STATE_LOCK() mutex_enter(&ql_global_mutex) 1740 #define GLOBAL_STATE_UNLOCK() mutex_exit(&ql_global_mutex) 1741 1742 #define TRY_DEVICE_QUEUE_LOCK(q) mutex_tryenter(&q->mutex) 1743 #define DEVICE_QUEUE_LOCK(q) mutex_enter(&q->mutex) 1744 #define DEVICE_QUEUE_UNLOCK(q) mutex_exit(&q->mutex) 1745 1746 #define MBX_REGISTER_LOCK(ha) mutex_enter(&ha->pha->mbx_mutex) 1747 #define MBX_REGISTER_UNLOCK(ha) mutex_exit(&ha->pha->mbx_mutex) 1748 1749 #define INTR_LOCK(ha) mutex_enter(&ha->pha->intr_mutex) 1750 #define INTR_UNLOCK(ha) mutex_exit(&ha->pha->intr_mutex) 1751 1752 #define TASK_DAEMON_LOCK(ha) mutex_enter(&ha->pha->task_daemon_mutex) 1753 #define TASK_DAEMON_UNLOCK(ha) mutex_exit(&ha->pha->task_daemon_mutex) 1754 1755 #define REQUEST_RING_LOCK(ha) mutex_enter(&ha->pha->req_ring_mutex) 1756 #define REQUEST_RING_UNLOCK(ha) mutex_exit(&ha->pha->req_ring_mutex) 1757 1758 #define CACHE_LOCK(ha) mutex_enter(&ha->pha->cache_mutex); 1759 #define CACHE_UNLOCK(ha) mutex_exit(&ha->pha->cache_mutex); 1760 1761 #define PORTMANAGE_LOCK(ha) mutex_enter(&ha->pha->portmutex); 1762 #define PORTMANAGE_UNLOCK(ha) mutex_exit(&ha->pha->portmutex); 1763 1764 #define ADAPTER_STATE_LOCK(ha) mutex_enter(&ha->pha->mutex) 1765 #define ADAPTER_STATE_UNLOCK(ha) mutex_exit(&ha->pha->mutex) 1766 1767 #define QL_PM_LOCK(ha) mutex_enter(&ha->pha->pm_mutex) 1768 #define QL_PM_UNLOCK(ha) mutex_exit(&ha->pha->pm_mutex) 1769 1770 #define QL_UB_LOCK(ha) mutex_enter(&ha->pha->ub_mutex) 1771 #define QL_UB_UNLOCK(ha) mutex_exit(&ha->pha->ub_mutex) 1772 1773 #define GLOBAL_HW_LOCK() mutex_enter(&ql_global_hw_mutex) 1774 #define GLOBAL_HW_UNLOCK() mutex_exit(&ql_global_hw_mutex) 1775 1776 /* 1777 * PCI power management control/status register location 1778 */ 1779 #define QL_PM_CS_REG 0x48 1780 1781 /* 1782 * ql component 1783 */ 1784 #define QL_POWER_COMPONENT 0 1785 1786 typedef struct ql_config_space { 1787 uint16_t chs_command; 1788 uint8_t chs_cache_line_size; 1789 uint8_t chs_latency_timer; 1790 uint8_t chs_header_type; 1791 uint8_t chs_sec_latency_timer; 1792 uint8_t chs_bridge_control; 1793 uint32_t chs_base0; 1794 uint32_t chs_base1; 1795 uint32_t chs_base2; 1796 uint32_t chs_base3; 1797 uint32_t chs_base4; 1798 uint32_t chs_base5; 1799 } ql_config_space_t; 1800 1801 #ifdef USE_DDI_INTERFACES 1802 1803 #define QL_SAVE_CONFIG_REGS(dip) pci_save_config_regs(dip) 1804 #define QL_RESTORE_CONFIG_REGS(dip) pci_restore_config_regs(dip) 1805 1806 #else /* USE_DDI_INTERFACES */ 1807 1808 #define QL_SAVE_CONFIG_REGS(dip) ql_save_config_regs(dip) 1809 #define QL_RESTORE_CONFIG_REGS(dip) ql_restore_config_regs(dip) 1810 1811 #endif /* USE_DDI_INTERFACES */ 1812 1813 #define QL_IS_SET(x, y) (((x) & (y)) == (y)) 1814 1815 /* 1816 * QL local function return status codes 1817 */ 1818 #define QL_SUCCESS 0x4000 1819 #define QL_INVALID_COMMAND 0x4001 1820 #define QL_INTERFACE_ERROR 0x4002 1821 #define QL_TEST_FAILED 0x4003 1822 #define QL_COMMAND_ERROR 0x4005 1823 #define QL_PARAMETER_ERROR 0x4006 1824 #define QL_PORT_ID_USED 0x4007 1825 #define QL_LOOP_ID_USED 0x4008 1826 #define QL_ALL_IDS_IN_USE 0x4009 1827 #define QL_NOT_LOGGED_IN 0x400A 1828 #define QL_LOOP_DOWN 0x400B 1829 #define QL_LOOP_BACK_ERROR 0x400C 1830 #define QL_CHECKSUM_ERROR 0x4010 1831 1832 #define QL_FUNCTION_TIMEOUT 0x100 1833 #define QL_FUNCTION_PARAMETER_ERROR 0x101 1834 #define QL_FUNCTION_FAILED 0x102 1835 #define QL_MEMORY_ALLOC_FAILED 0x103 1836 #define QL_FABRIC_NOT_INITIALIZED 0x104 1837 #define QL_LOCK_TIMEOUT 0x105 1838 #define QL_ABORTED 0x106 1839 #define QL_FUNCTION_SUSPENDED 0x107 1840 #define QL_END_OF_DATA 0x108 1841 #define QL_IP_UNSUPPORTED 0x109 1842 #define QL_PM_ERROR 0x10a 1843 #define QL_DATA_EXISTS 0x10b 1844 #define QL_NOT_SUPPORTED 0x10c 1845 #define QL_MEMORY_FULL 0x10d 1846 #define QL_FW_NOT_SUPPORTED 0x10e 1847 #define QL_FWMODLOAD_FAILED 0x10f 1848 #define QL_FWSYM_NOT_FOUND 0x10e 1849 1850 /* 1851 * SBus card FPGA register offsets. 1852 */ 1853 #define FPGA_CONF 0x100 1854 #define FPGA_EEPROM_LOADDR 0x102 1855 #define FPGA_EEPROM_HIADDR 0x104 1856 #define FPGA_EEPROM_DATA 0x106 1857 #define FPGA_REVISION 0x108 1858 1859 #define SBUS_FLASH_WRITE_ENABLE 0x0080 1860 #define QL_SBUS_FCODE_SIZE 0x30000 1861 #define QL_FCODE_OFFSET 0 1862 #define QL_FPGA_SIZE 0x40000 1863 #define QL_FPGA_OFFSET 0x40000 1864 1865 #define READ_PORT_ID(addr) ((uint32_t)((((uint32_t)((addr)[0])) << 16) | \ 1866 (((uint32_t)((addr)[1])) << 8) | \ 1867 (((uint32_t)((addr)[2]))))) 1868 #define READ_PORT_NAME(addr) ((u_longlong_t)((((uint64_t)((addr)[0])) << 56) | \ 1869 (((uint64_t)((addr)[1])) << 48) | \ 1870 (((uint64_t)((addr)[2])) << 40) | \ 1871 (((uint64_t)((addr)[3])) << 32) | \ 1872 (((uint64_t)((addr)[4])) << 24) | \ 1873 (((uint64_t)((addr)[5])) << 16) | \ 1874 (((uint64_t)((addr)[6])) << 8) | \ 1875 (((uint64_t)((addr)[7]))))) 1876 1877 /* 1878 * Global Data in ql_api.c source file. 1879 */ 1880 extern void *ql_state; /* for soft state routine */ 1881 extern uint32_t ql_os_release_level; 1882 extern ql_head_t ql_hba; 1883 extern kmutex_t ql_global_mutex; 1884 extern kmutex_t ql_global_hw_mutex; 1885 extern kmutex_t ql_global_el_mutex; 1886 extern volatile uint32_t ql_dump_state; 1887 extern uint8_t ql_ip_fast_post_count; 1888 extern uint32_t ql_ip_buffer_count; 1889 extern uint32_t ql_ip_low_water; 1890 extern uint8_t ql_alpa_to_index[]; 1891 extern uint32_t ql_gfru_hba_index; 1892 1893 /* 1894 * Global Function Prototypes in ql_api.c source file. 1895 */ 1896 void ql_chg_endian(uint8_t *, size_t); 1897 void ql_populate_hba_fru_details(ql_adapter_state_t *, fc_fca_port_info_t *); 1898 void ql_setup_fruinfo(ql_adapter_state_t *); 1899 uint16_t ql_pci_config_get16(ql_adapter_state_t *, off_t); 1900 uint32_t ql_pci_config_get32(ql_adapter_state_t *, off_t); 1901 void ql_pci_config_put8(ql_adapter_state_t *, off_t, uint8_t); 1902 void ql_pci_config_put16(ql_adapter_state_t *, off_t, uint16_t); 1903 void ql_delay(ql_adapter_state_t *, clock_t); 1904 void ql_awaken_task_daemon(ql_adapter_state_t *, ql_srb_t *, uint32_t, 1905 uint32_t); 1906 int ql_abort_device(ql_adapter_state_t *, ql_tgt_t *, int); 1907 int ql_binary_fw_dump(ql_adapter_state_t *, int); 1908 void ql_done(ql_link_t *); 1909 int ql_24xx_flash_id(ql_adapter_state_t *); 1910 int ql_24xx_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t); 1911 int ql_poll_flash(ql_adapter_state_t *, uint32_t, uint8_t); 1912 void ql_flash_disable(ql_adapter_state_t *); 1913 void ql_flash_enable(ql_adapter_state_t *); 1914 int ql_erase_flash(ql_adapter_state_t *, int); 1915 void ql_write_flash_byte(ql_adapter_state_t *, uint32_t, uint8_t); 1916 uint8_t ql_read_flash_byte(ql_adapter_state_t *, uint32_t); 1917 int ql_24xx_read_flash(ql_adapter_state_t *, uint32_t, uint32_t *); 1918 int ql_24xx_write_flash(ql_adapter_state_t *, uint32_t, uint32_t); 1919 fc_unsol_buf_t *ql_get_unsolicited_buffer(ql_adapter_state_t *, uint32_t); 1920 size_t ql_ascii_fw_dump(ql_adapter_state_t *, caddr_t); 1921 void ql_add_link_b(ql_head_t *, ql_link_t *); 1922 void ql_add_link_t(ql_head_t *, ql_link_t *); 1923 void ql_remove_link(ql_head_t *, ql_link_t *); 1924 void ql_next(ql_adapter_state_t *, ql_lun_t *); 1925 void ql_send_logo(ql_adapter_state_t *, ql_tgt_t *, ql_head_t *); 1926 void ql_cthdr_endian(ddi_acc_handle_t, caddr_t, boolean_t); 1927 ql_tgt_t *ql_d_id_to_queue(ql_adapter_state_t *, port_id_t); 1928 ql_tgt_t *ql_loop_id_to_queue(ql_adapter_state_t *, uint16_t); 1929 void ql_cmd_wait(ql_adapter_state_t *); 1930 void ql_loop_online(ql_adapter_state_t *); 1931 ql_tgt_t *ql_dev_init(ql_adapter_state_t *, port_id_t, uint16_t); 1932 int ql_ub_frame_hdr(ql_adapter_state_t *, ql_tgt_t *, uint16_t, ql_head_t *); 1933 void ql_rcv_rscn_els(ql_adapter_state_t *, uint16_t *, ql_head_t *); 1934 int ql_stall_driver(ql_adapter_state_t *, uint32_t); 1935 void ql_restart_driver(ql_adapter_state_t *); 1936 int ql_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t); 1937 int ql_get_dma_mem(ql_adapter_state_t *, dma_mem_t *, uint32_t, 1938 mem_alloc_type_t, mem_alignment_t); 1939 int ql_alloc_phys(ql_adapter_state_t *, dma_mem_t *, int); 1940 void ql_free_phys(ql_adapter_state_t *, dma_mem_t *); 1941 void ql_24xx_protect_flash(ql_adapter_state_t *); 1942 void ql_free_dma_resource(ql_adapter_state_t *, dma_mem_t *); 1943 uint8_t ql_pci_config_get8(ql_adapter_state_t *, off_t); 1944 void ql_pci_config_put32(ql_adapter_state_t *, off_t, uint32_t); 1945 void ql_24xx_unprotect_flash(ql_adapter_state_t *); 1946 uint32_t ql_fwmodule_resolve(ql_adapter_state_t *); 1947 void ql_port_state(ql_adapter_state_t *, uint32_t, uint32_t); 1948 1949 #ifdef __cplusplus 1950 } 1951 #endif 1952 1953 #endif /* _QL_API_H */ 1954