1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_QUEUE_H 28 #define _EMLXS_QUEUE_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 /* Queue entry defines */ 36 37 /* EQ entries */ 38 typedef struct EQE 39 { 40 #ifdef EMLXS_BIG_ENDIAN 41 uint32_t CQId: 16; 42 uint32_t MinorCode: 12; 43 uint32_t MajorCode: 3; 44 uint32_t Valid: 1; 45 #endif 46 #ifdef EMLXS_LITTLE_ENDIAN 47 uint32_t Valid: 1; 48 uint32_t MajorCode: 3; 49 uint32_t MinorCode: 12; 50 uint32_t CQId: 16; 51 #endif 52 53 } EQE_t; 54 55 typedef union 56 { 57 uint32_t word; 58 EQE_t entry; 59 60 } EQE_u; 61 62 #define EQE_VALID 0x00000001 /* Mask for EQE valid */ 63 #define EQE_CQID 0xFFFF0000 /* Mask for EQE CQID */ 64 65 /* CQ entries */ 66 typedef struct CQE_CmplWQ 67 { 68 #ifdef EMLXS_BIG_ENDIAN 69 uint16_t RequestTag; /* Word 0 */ 70 uint8_t Status; 71 uint8_t hw_status; 72 73 uint32_t CmdSpecific; /* Word 1 */ 74 uint32_t Parameter; /* Word 2 */ 75 76 uint32_t Valid: 1; /* Word 3 */ 77 uint32_t Rsvd1: 2; 78 uint32_t XB: 1; 79 uint32_t PV: 1; 80 uint32_t Priority: 3; 81 uint32_t Code: 8; 82 uint32_t Rsvd2: 16; 83 #endif 84 #ifdef EMLXS_LITTLE_ENDIAN 85 uint8_t hw_status; 86 uint8_t Status; 87 uint16_t RequestTag; /* Word 0 */ 88 89 uint32_t CmdSpecific; /* Word 1 */ 90 uint32_t Parameter; /* Word 2 */ 91 92 uint32_t Rsvd2: 16; 93 uint32_t Code: 8; 94 uint32_t Priority: 3; 95 uint32_t PV: 1; 96 uint32_t XB: 1; 97 uint32_t Rsvd1: 2; 98 uint32_t Valid: 1; /* Word 3 */ 99 #endif 100 } CQE_CmplWQ_t; 101 102 typedef struct CQE_RelWQ 103 { 104 #ifdef EMLXS_BIG_ENDIAN 105 uint32_t Reserved1; /* Word 0 */ 106 uint32_t Reserved2; /* Word 1 */ 107 108 uint16_t WQid; /* Word 2 */ 109 uint16_t WQindex; 110 111 uint32_t Valid: 1; /* Word 3 */ 112 uint32_t Rsvd1: 7; 113 uint32_t Code: 8; 114 uint32_t Rsvd2: 16; 115 #endif 116 #ifdef EMLXS_LITTLE_ENDIAN 117 uint32_t Reserved1; /* Word 0 */ 118 uint32_t Reserved2; /* Word 1 */ 119 120 uint16_t WQindex; 121 uint16_t WQid; /* Word 2 */ 122 123 uint32_t Rsvd2: 16; 124 uint32_t Code: 8; 125 uint32_t Rsvd1: 7; 126 uint32_t Valid: 1; /* Word 3 */ 127 #endif 128 } CQE_RelWQ_t; 129 130 typedef struct CQE_UnsolRcv 131 { 132 #ifdef EMLXS_BIG_ENDIAN 133 uint16_t RQindex; /* Word 0 */ 134 uint8_t Status; 135 uint8_t Rsvd1; 136 137 uint32_t Rsvd2; /* Word 1 */ 138 139 uint32_t data_size: 16; /* Word 2 */ 140 uint32_t RQid: 10; 141 uint32_t FCFId: 6; 142 143 uint32_t Valid: 1; /* Word 3 */ 144 uint32_t port: 1; 145 uint32_t hdr_size: 6; 146 uint32_t Code: 8; 147 uint32_t eof: 8; 148 uint32_t sof: 8; 149 #endif 150 #ifdef EMLXS_LITTLE_ENDIAN 151 uint8_t Rsvd1; 152 uint8_t Status; 153 uint16_t RQindex; /* Word 0 */ 154 155 uint32_t Rsvd2; /* Word 1 */ 156 157 uint32_t FCFId: 6; 158 uint32_t RQid: 10; 159 uint32_t data_size: 16; /* Word 2 */ 160 161 uint32_t sof: 8; 162 uint32_t eof: 8; 163 uint32_t Code: 8; 164 uint32_t hdr_size: 6; 165 uint32_t port: 1; 166 uint32_t Valid: 1; /* Word 3 */ 167 #endif 168 } CQE_UnsolRcv_t; 169 170 /* Status defines */ 171 #define RQ_STATUS_SUCCESS 0x10 172 #define RQ_STATUS_BUFLEN_EXCEEDED 0x11 173 #define RQ_STATUS_NEED_BUFFER 0x12 174 #define RQ_STATUS_FRAME_DISCARDED 0x13 175 176 177 typedef struct CQE_XRI_Abort 178 { 179 #ifdef EMLXS_BIG_ENDIAN 180 uint16_t Rsvd1; /* Word 0 */ 181 uint8_t Status; 182 uint8_t Rsvd2; 183 184 uint32_t rjtStatus; /* Word 1 */ 185 186 uint16_t RemoteXID; /* Word 2 */ 187 uint16_t XRI; 188 189 uint32_t Valid: 1; /* Word 3 */ 190 uint32_t IA: 1; 191 uint32_t BR: 1; 192 uint32_t EO: 1; 193 uint32_t Rsvd3: 4; 194 uint32_t Code: 8; 195 uint32_t Rsvd4: 16; 196 #endif 197 #ifdef EMLXS_LITTLE_ENDIAN 198 uint8_t Rsvd2; 199 uint8_t Status; 200 uint16_t Rsvd1; /* Word 0 */ 201 202 uint32_t rjtStatus; /* Word 1 */ 203 204 uint16_t XRI; 205 uint16_t RemoteXID; /* Word 2 */ 206 207 uint32_t Rsvd4: 16; 208 uint32_t Code: 8; 209 uint32_t Rsvd3: 4; 210 uint32_t EO: 1; 211 uint32_t BR: 1; 212 uint32_t IA: 1; 213 uint32_t Valid: 1; /* Word 3 */ 214 #endif 215 } CQE_XRI_Abort_t; 216 217 218 219 #define CQE_VALID 0x80000000 /* Mask for CQE valid */ 220 221 /* Defines for CQE Codes */ 222 #define CQE_TYPE_WQ_COMPLETION 1 223 #define CQE_TYPE_RELEASE_WQE 2 224 #define CQE_TYPE_UNSOL_RCV 4 225 #define CQE_TYPE_XRI_ABORTED 5 226 227 228 typedef struct CQE_ASYNC_FCOE 229 { 230 #ifdef EMLXS_BIG_ENDIAN 231 uint32_t ref_index; /* Word 0 */ 232 233 uint16_t evt_type; /* Word 1 */ 234 uint16_t fcf_count; 235 236 uint32_t event_tag; /* Word 2 */ 237 #endif 238 #ifdef EMLXS_LITTLE_ENDIAN 239 uint32_t ref_index; /* Word 0 */ 240 241 uint16_t fcf_count; 242 uint16_t evt_type; /* Word 1 */ 243 244 uint32_t event_tag; /* Word 2 */ 245 #endif 246 } CQE_ASYNC_FCOE_t; 247 248 typedef struct CQE_ASYNC_LINK_STATE 249 { 250 #ifdef EMLXS_BIG_ENDIAN 251 uint8_t port_speed; /* Word 0 */ 252 uint8_t port_duplex; 253 uint8_t link_status; 254 uint8_t phys_port; 255 256 uint16_t qos_link_speed; /* Word 1 */ 257 uint8_t Rsvd1; 258 uint8_t port_fault; 259 260 uint32_t event_tag; /* Word 2 */ 261 #endif 262 #ifdef EMLXS_LITTLE_ENDIAN 263 uint8_t phys_port; 264 uint8_t link_status; 265 uint8_t port_duplex; 266 uint8_t port_speed; /* Word 0 */ 267 268 uint8_t port_fault; /* Word 1 */ 269 uint8_t Rsvd1; 270 uint16_t qos_link_speed; 271 272 uint32_t event_tag; /* Word 2 */ 273 #endif 274 } CQE_ASYNC_LINK_STATE_t; 275 276 typedef struct CQE_ASYNC_GRP_5_QOS 277 { 278 #ifdef EMLXS_BIG_ENDIAN 279 uint8_t Rsvd2; 280 uint8_t Rsvd1; 281 uint8_t Rsvd0; 282 uint8_t phys_port; /* Word 0 */ 283 284 uint16_t qos_link_speed; 285 uint8_t Rsvd4; 286 uint8_t Rsvd3; /* Word 1 */ 287 288 uint32_t event_tag; /* Word 2 */ 289 #endif 290 #ifdef EMLXS_LITTLE_ENDIAN 291 uint8_t phys_port; 292 uint8_t Rsvd0; 293 uint8_t Rsvd1; 294 uint8_t Rsvd2; /* Word 0 */ 295 296 uint8_t Rsvd3; 297 uint8_t Rsvd4; 298 uint16_t qos_link_speed; /* Word 1 */ 299 300 uint32_t event_tag; /* Word 2 */ 301 #endif 302 } CQE_ASYNC_GRP_5_QOS_t; 303 304 typedef struct CQE_ASYNC 305 { 306 /* Words 0-2 */ 307 union 308 { 309 CQE_ASYNC_LINK_STATE_t link; 310 CQE_ASYNC_FCOE_t fcoe; 311 CQE_ASYNC_GRP_5_QOS_t qos; 312 } un; 313 314 #ifdef EMLXS_BIG_ENDIAN 315 uint32_t valid: 1; 316 uint32_t async_evt: 1; 317 uint32_t Rsvd2: 6; 318 uint32_t event_type: 8; 319 uint32_t event_code: 8; 320 uint32_t Rsvd3: 8; /* Word 3 */ 321 #endif 322 #ifdef EMLXS_LITTLE_ENDIAN 323 uint32_t Rsvd3: 8; 324 uint32_t event_code: 8; 325 uint32_t event_type: 8; 326 uint32_t Rsvd2: 6; 327 uint32_t async_evt: 1; 328 uint32_t valid: 1; /* Word 3 */ 329 #endif 330 } CQE_ASYNC_t; 331 332 /* port_speed defines */ 333 #define PHY_1GHZ_LINK 3 334 #define PHY_10GHZ_LINK 4 335 336 /* event_code defines */ 337 #define ASYNC_EVENT_CODE_LINK_STATE 1 338 #define ASYNC_EVENT_CODE_FCOE_FIP 2 339 #define ASYNC_EVENT_CODE_DCBX 3 340 #define ASYNC_EVENT_CODE_GRP_5 5 341 342 /* LINK_STATE - link_status defines */ 343 #define ASYNC_EVENT_PHYS_LINK_DOWN 0 344 #define ASYNC_EVENT_PHYS_LINK_UP 1 345 #define ASYNC_EVENT_LOGICAL_LINK_DOWN 2 346 #define ASYNC_EVENT_LOGICAL_LINK_UP 3 347 348 /* FCOE_FIP - evt_type defines */ 349 #define ASYNC_EVENT_NEW_FCF_DISC 1 350 #define ASYNC_EVENT_FCF_TABLE_FULL 2 351 #define ASYNC_EVENT_FCF_DEAD 3 352 #define ASYNC_EVENT_VIRT_LINK_CLEAR 4 353 #define ASYNC_EVENT_FCF_MODIFIED 5 354 355 /* GRP_5 - evt_type defines */ 356 #define ASYNC_EVENT_QOS_SPEED 1 357 358 typedef struct CQE_MBOX 359 { 360 #ifdef EMLXS_BIG_ENDIAN 361 uint16_t extend_status; /* Word 0 */ 362 uint16_t cmpl_status; 363 364 uint32_t tag_low; /* Word 1 */ 365 uint32_t tag_high; /* Word 2 */ 366 367 uint32_t valid: 1; /* Word 3 */ 368 uint32_t async_evt: 1; 369 uint32_t hpi: 1; 370 uint32_t completed: 1; 371 uint32_t consumed: 1; 372 uint32_t Rsvd1: 27; 373 #endif 374 #ifdef EMLXS_LITTLE_ENDIAN 375 uint16_t cmpl_status; 376 uint16_t extend_status; /* Word 0 */ 377 378 uint32_t tag_low; /* Word 1 */ 379 uint32_t tag_high; /* Word 2 */ 380 381 uint32_t Rsvd1: 27; 382 uint32_t consumed: 1; 383 uint32_t completed: 1; 384 uint32_t hpi: 1; 385 uint32_t async_evt: 1; 386 uint32_t valid: 1; /* Word 3 */ 387 #endif 388 } CQE_MBOX_t; 389 390 typedef union 391 { 392 uint32_t word[4]; 393 394 /* Group 1 types */ 395 CQE_ASYNC_t cqAsyncEntry; 396 CQE_ASYNC_FCOE_t cqAsyncFCOEEntry; 397 CQE_MBOX_t cqMboxEntry; 398 399 /* Group 2 types */ 400 CQE_CmplWQ_t cqCmplEntry; 401 CQE_RelWQ_t cqRelEntry; 402 CQE_UnsolRcv_t cqUnsolRcvEntry; 403 CQE_XRI_Abort_t cqXRIEntry; 404 } CQE_u; 405 406 /* RQ entries */ 407 typedef struct RQE 408 { 409 uint32_t AddrHi; 410 uint32_t AddrLo; 411 412 } RQE_t; 413 414 415 /* Definitions for WQEs */ 416 typedef struct 417 { 418 ULP_BDE64 Payload; 419 uint32_t PayloadLength; 420 421 #ifdef EMLXS_BIG_ENDIAN 422 uint32_t Rsvd1: 6; 423 uint32_t VF: 1; 424 uint32_t SP: 1; 425 uint32_t LocalId: 24; 426 427 uint32_t Rsvd2: 8; 428 uint32_t RemoteId: 24; 429 #endif 430 #ifdef EMLXS_LITTLE_ENDIAN 431 uint32_t LocalId: 24; 432 uint32_t SP: 1; 433 uint32_t VF: 1; 434 uint32_t Rsvd1: 6; 435 436 uint32_t RemoteId: 24; 437 uint32_t Rsvd2: 8; 438 #endif 439 440 } ELS_REQ_WQE; 441 442 typedef struct 443 { 444 ULP_BDE64 Payload; 445 uint32_t Rsvd1[2]; 446 447 #ifdef EMLXS_BIG_ENDIAN 448 uint32_t Rsvd2: 8; 449 uint32_t RemoteId: 24; 450 #endif 451 #ifdef EMLXS_LITTLE_ENDIAN 452 uint32_t RemoteId: 24; 453 uint32_t Rsvd2: 8; 454 #endif 455 456 } ELS_RSP_WQE; 457 458 typedef struct 459 { 460 ULP_BDE64 Payload; 461 uint32_t PayloadLength; 462 463 uint32_t Parameter; 464 465 #ifdef EMLXS_BIG_ENDIAN 466 uint32_t Rctl: 8; 467 uint32_t Type: 8; 468 uint32_t DFctl: 8; 469 uint32_t Rsvd1: 4; 470 uint32_t la: 1; 471 uint32_t Rsvd2: 3; 472 #endif 473 #ifdef EMLXS_LITTLE_ENDIAN 474 uint32_t Rsvd2: 3; 475 uint32_t la: 1; 476 uint32_t Rsvd1: 4; 477 uint32_t DFctl: 8; 478 uint32_t Type: 8; 479 uint32_t Rctl: 8; 480 #endif 481 482 } GEN_REQ_WQE; 483 484 typedef struct 485 { 486 ULP_BDE64 Payload; 487 uint32_t PayloadLength; 488 489 uint32_t Parameter; 490 491 #ifdef EMLXS_BIG_ENDIAN 492 uint32_t Rctl: 8; 493 uint32_t Type: 8; 494 uint32_t DFctl: 8; 495 uint32_t ls: 1; 496 uint32_t Rsvd1: 3; 497 uint32_t la: 1; 498 uint32_t si: 1; 499 uint32_t Rsvd2: 2; 500 #endif 501 #ifdef EMLXS_LITTLE_ENDIAN 502 uint32_t Rsvd2: 2; 503 uint32_t si: 1; 504 uint32_t la: 1; 505 uint32_t Rsvd1: 3; 506 uint32_t ls: 1; 507 uint32_t DFctl: 8; 508 uint32_t Type: 8; 509 uint32_t Rctl: 8; 510 #endif 511 512 } XMIT_SEQ_WQE; 513 514 typedef struct 515 { 516 ULP_BDE64 Payload; 517 uint32_t PayloadLength; 518 519 uint32_t TotalTransferCount; 520 uint32_t Rsvd1; 521 522 } FCP_WQE; 523 524 525 typedef struct 526 { 527 uint32_t Rsvd1[3]; 528 529 #ifdef EMLXS_BIG_ENDIAN 530 uint32_t Rsvd2: 16; 531 uint32_t Criteria: 8; 532 uint32_t Rsvd3: 7; 533 uint32_t IA: 1; 534 #endif 535 #ifdef EMLXS_LITTLE_ENDIAN 536 uint32_t IA: 1; 537 uint32_t Rsvd3: 7; 538 uint32_t Criteria: 8; 539 uint32_t Rsvd2: 16; 540 #endif 541 542 uint32_t Rsvd4[2]; 543 544 } ABORT_WQE; 545 546 #define ABORT_XRI_TAG 1 /* Abort tag is a XRITag */ 547 #define ABORT_ABT_TAG 2 /* Abort tag is a AbortTag */ 548 #define ABORT_REQ_TAG 3 /* Abort tag is a RequestTag */ 549 550 typedef struct 551 { 552 #ifdef EMLXS_BIG_ENDIAN 553 uint8_t Payload0; 554 uint8_t Payload1; 555 uint8_t Payload2; 556 uint8_t Payload3; 557 558 uint32_t OXId: 16; 559 uint32_t RXId: 16; 560 561 uint32_t SeqCntLow: 16; 562 uint32_t SeqCntHigh: 16; 563 #endif 564 #ifdef EMLXS_LITTLE_ENDIAN 565 uint8_t Payload3; 566 uint8_t Payload2; 567 uint8_t Payload1; 568 uint8_t Payload0; 569 570 uint32_t RXId: 16; 571 uint32_t OXId: 16; 572 573 uint32_t SeqCntHigh: 16; 574 uint32_t SeqCntLow: 16; 575 #endif 576 uint32_t Rsvd1[2]; 577 #ifdef EMLXS_BIG_ENDIAN 578 uint32_t XO: 1; 579 uint32_t AR: 1; 580 uint32_t PT: 1; 581 uint32_t Rsvd2: 5; 582 uint32_t RemoteId: 24; 583 #endif 584 #ifdef EMLXS_LITTLE_ENDIAN 585 uint32_t RemoteId: 24; 586 uint32_t Rsvd2: 5; 587 uint32_t PT: 1; 588 uint32_t AR: 1; 589 uint32_t XO: 1; 590 #endif 591 592 } BLS_WQE; 593 594 595 typedef struct 596 { 597 uint32_t Rsvd1[5]; 598 599 #ifdef EMLXS_BIG_ENDIAN 600 uint32_t XO: 1; 601 uint32_t Rsvd2: 7; 602 uint32_t RemoteId: 24; 603 #endif 604 #ifdef EMLXS_LITTLE_ENDIAN 605 uint32_t RemoteId: 24; 606 uint32_t Rsvd2: 7; 607 uint32_t XO: 1; 608 #endif 609 610 } CREATE_XRI_WQE; 611 612 typedef struct emlxs_wqe 613 { 614 /* Words 0-5 */ 615 union 616 { 617 uint32_t word[6]; /* Words 0-5: cmd specific */ 618 ELS_REQ_WQE ElsCmd; /* ELS command overlay */ 619 GEN_REQ_WQE GenReq; /* CT command overlay */ 620 FCP_WQE FcpCmd; /* FCP command overlay */ 621 ELS_RSP_WQE ElsRsp; /* ELS response overlay */ 622 ABORT_WQE Abort; /* Abort overlay */ 623 BLS_WQE BlsRsp; /* BLS overlay */ 624 CREATE_XRI_WQE CreateXri; /* Create XRI */ 625 XMIT_SEQ_WQE XmitSeq; /* Xmit Sequence */ 626 } un; 627 628 #ifdef EMLXS_BIG_ENDIAN 629 /* Word 6 */ 630 uint16_t ContextTag; /* Context Tag */ 631 uint16_t XRITag; /* XRItag */ 632 /* Word 7 */ 633 uint32_t Timer: 8; /* TOV */ 634 uint32_t Rsvd2: 1; 635 uint32_t ERP: 1; /* ERP */ 636 uint32_t PU: 2; /* PU */ 637 uint32_t Rsvd1: 1; 638 uint32_t Class: 3; /* COS */ 639 uint32_t Command: 8; /* Command Code */ 640 uint32_t Status: 4; /* Final Status */ 641 uint32_t ContextType: 2; /* Context Type */ 642 uint32_t Rsvd0: 2; 643 /* Word 8 */ 644 uint32_t AbortTag; /* Abort Tag */ 645 /* Word 9 */ 646 uint16_t OXId; /* OXId on xmitted rsp */ 647 uint16_t RequestTag; /* Request Tag */ 648 /* Word 10 */ 649 uint32_t CCP: 8; /* CCP */ 650 uint32_t CCPE: 1; /* CCPEnabled */ 651 uint32_t Rsvd6: 1; 652 uint32_t XC: 1; /* Exchange Create */ 653 uint32_t Rsvd5: 1; 654 uint32_t PV: 1; /* PRIValid */ 655 uint32_t PRI: 3; /* PRI */ 656 uint32_t Rsvd4: 16; 657 /* Word 11 */ 658 uint32_t Rsvd9: 6; 659 uint32_t CQId: 10; /* CompletionQueueID */ 660 uint32_t Rsvd8: 8; 661 uint32_t WQEC: 1; /* Request WQE consumed CQE */ 662 uint32_t Rsvd7: 1; 663 uint32_t ELSId: 2; 664 uint32_t CmdType: 4; /* Command Type */ 665 #endif 666 #ifdef EMLXS_LITTLE_ENDIAN 667 /* Word 6 */ 668 uint16_t XRITag; /* XRItag */ 669 uint16_t ContextTag; /* Context Tag */ 670 /* Word 7 */ 671 uint32_t Rsvd0: 2; 672 uint32_t ContextType: 2; /* Context Type */ 673 uint32_t Status: 4; /* Final Status */ 674 uint32_t Command: 8; /* Command Code */ 675 uint32_t Class: 3; /* COS */ 676 uint32_t Rsvd1: 1; 677 uint32_t PU: 2; /* PU */ 678 uint32_t ERP: 1; /* ERP */ 679 uint32_t Rsvd2: 1; 680 uint32_t Timer: 8; /* TOV */ 681 /* Word 8 */ 682 uint32_t AbortTag; /* Abort Tag */ 683 /* Word 9 */ 684 uint16_t RequestTag; /* Request Tag */ 685 uint16_t OXId; /* OXId on xmitted rsp */ 686 /* Word 10 */ 687 uint32_t Rsvd4: 16; 688 uint32_t PRI: 3; /* PRI */ 689 uint32_t PV: 1; /* PRIValid */ 690 uint32_t Rsvd5: 1; 691 uint32_t XC: 1; /* Exchange Create */ 692 uint32_t Rsvd6: 1; 693 uint32_t CCPE: 1; /* CCPEnabled */ 694 uint32_t CCP: 8; /* CCP */ 695 /* Word 11 */ 696 uint32_t CmdType: 4; /* Command Type */ 697 uint32_t ELSId: 2; 698 uint32_t Rsvd7: 1; 699 uint32_t WQEC: 1; /* Request WQE consumed CQE */ 700 uint32_t Rsvd8: 8; 701 uint32_t CQId: 10; /* CompletionQueueID */ 702 uint32_t Rsvd9: 6; 703 #endif 704 705 /* Words 12-15 */ 706 uint32_t CmdSpecific[4]; /* Word12-15: commandspecific */ 707 } emlxs_wqe_t; 708 709 /* Defines for ContextType */ 710 #define WQE_RPI_CONTEXT 0 711 #define WQE_VPI_CONTEXT 1 712 #define WQE_VFI_CONTEXT 2 713 #define WQE_FCFI_CONTEXT 3 714 715 /* Defines for CmdType */ 716 #define WQE_TYPE_FCP_DATA_IN 0x00 717 #define WQE_TYPE_FCP_DATA_OUT 0x01 718 #define WQE_TYPE_ELS 0x0C 719 #define WQE_TYPE_GEN 0x08 720 #define WQE_TYPE_ABORT 0x08 721 #define WQE_TYPE_MASK_FIP 0x01 722 723 /* Defines for ELSId */ 724 #define WQE_ELSID_FLOGI 0x03 725 #define WQE_ELSID_FDISC 0x02 726 #define WQE_ELSID_LOGO 0x01 727 #define WQE_ELSID_CMD 0x0 728 729 /* RQB */ 730 #define RQB_HEADER_SIZE 32 731 #define RQB_DATA_SIZE 2048 732 #define RQB_COUNT 256 733 734 #define EMLXS_NUM_WQ_PAGES 4 735 736 #define EQ_DEPTH 1024 737 #define CQ_DEPTH 256 738 #define WQ_DEPTH (64 * EMLXS_NUM_WQ_PAGES) 739 #define MQ_DEPTH 16 740 #define RQ_DEPTH 512 /* Multiple of RQB_COUNT */ 741 #define RQ_DEPTH_EXPONENT 9 742 743 744 /* Principal doorbell register layouts */ 745 typedef struct emlxs_rqdb 746 { 747 #ifdef EMLXS_BIG_ENDIAN 748 uint32_t Rsvd2:2; 749 uint32_t NumPosted:14; /* Number of entries posted */ 750 uint32_t Rsvd1:6; 751 uint32_t Qid:10; /* RQ id for posted RQE */ 752 #endif /* EMLXS_BIG_ENDIAN */ 753 754 #ifdef EMLXS_LITTLE_ENDIAN 755 uint32_t Qid:10; /* RQ id for posted RQE */ 756 uint32_t Rsvd1:6; 757 uint32_t NumPosted:14; /* Number of entries posted */ 758 uint32_t Rsvd2:2; 759 #endif /* EMLXS_LITTLE_ENDIAN */ 760 761 } emlxs_rqdb_t; 762 763 764 typedef union emlxs_rqdbu 765 { 766 uint32_t word; 767 emlxs_rqdb_t db; 768 769 } emlxs_rqdbu_t; 770 771 772 typedef struct emlxs_wqdb 773 { 774 #ifdef EMLXS_BIG_ENDIAN 775 uint32_t NumPosted:8; /* Number of entries posted */ 776 uint32_t Index:8; /* Queue index for posted command */ 777 uint32_t Rsvd1:6; 778 uint32_t Qid:10; /* WQ id for posted WQE */ 779 #endif /* EMLXS_BIG_ENDIAN */ 780 781 #ifdef EMLXS_LITTLE_ENDIAN 782 uint32_t Qid:10; /* WQ id for posted WQE */ 783 uint32_t Rsvd1:6; 784 uint32_t Index:8; /* Queue index for posted command */ 785 uint32_t NumPosted:8; /* Number of entries posted */ 786 #endif /* EMLXS_LITTLE_ENDIAN */ 787 788 } emlxs_wqdb_t; 789 790 791 typedef union emlxs_wqdbu 792 { 793 uint32_t word; 794 emlxs_wqdb_t db; 795 796 } emlxs_wqdbu_t; 797 798 799 typedef struct emlxs_cqdb 800 { 801 #ifdef EMLXS_BIG_ENDIAN 802 uint32_t NumPosted:2; /* Number of entries posted */ 803 uint32_t Rearm:1; /* Rearm CQ */ 804 uint32_t NumPopped:13; /* Number of CQ entries processed */ 805 uint32_t Rsvd1:5; 806 uint32_t Event:1; /* 1 if processed entry is EQE */ 807 /* 0 if processed entry is CQE */ 808 uint32_t Qid:10; /* CQ id for posted CQE */ 809 #endif /* EMLXS_BIG_ENDIAN */ 810 811 #ifdef EMLXS_LITTLE_ENDIAN 812 uint32_t Qid:10; /* CQ id for posted CQE */ 813 uint32_t Event:1; /* 1 if processed entry is EQE */ 814 /* 0 if processed entry is CQE */ 815 uint32_t Rsvd1:5; 816 uint32_t NumPopped:13; /* Number of CQ entries processed */ 817 uint32_t Rearm:1; /* Rearm CQ */ 818 uint32_t NumPosted:2; /* Number of entries posted */ 819 #endif /* EMLXS_LITTLE_ENDIAN */ 820 821 } emlxs_cqdb_t; 822 823 824 typedef union emlxs_cqdbu 825 { 826 uint32_t word; 827 emlxs_cqdb_t db; 828 829 } emlxs_cqdbu_t; 830 831 typedef struct emlxs_eqdb 832 { 833 #ifdef EMLXS_BIG_ENDIAN 834 uint32_t Rsvd2:2; 835 uint32_t Rearm:1; /* Rearm EQ */ 836 uint32_t NumPopped:13; /* Number of CQ entries processed */ 837 uint32_t Rsvd1:5; 838 uint32_t Event:1; /* True iff processed entry is EQE */ 839 uint32_t Clear:1; /* clears EQ interrupt when set */ 840 uint32_t Qid:9; /* EQ id for posted EQE */ 841 #endif /* EMLXS_BIG_ENDIAN */ 842 843 #ifdef EMLXS_LITTLE_ENDIAN 844 uint32_t Qid:9; /* EQ id for posted EQE */ 845 uint32_t Clear:1; /* clears EQ interrupt when set */ 846 uint32_t Event:1; /* True iff processed entry is EQE */ 847 uint32_t Rsvd1:5; 848 uint32_t NumPopped:13; /* Number of CQ entries processed */ 849 uint32_t Rearm:1; /* Rearm EQ */ 850 uint32_t Rsvd2:2; 851 #endif /* EMLXS_LITTLE_ENDIAN */ 852 853 } emlxs_eqdb_t; 854 855 856 typedef union emlxs_eqdbu 857 { 858 uint32_t word; 859 emlxs_eqdb_t db; 860 861 } emlxs_eqdbu_t; 862 863 864 typedef struct emlxs_mqdb 865 { 866 #ifdef EMLXS_BIG_ENDIAN 867 uint32_t Rsvd2:2; 868 uint32_t NumPosted:14; /* Number of entries posted */ 869 uint32_t Rsvd1:5; 870 uint32_t Qid:11; /* MQ id for posted MQE */ 871 #endif /* EMLXS_BIG_ENDIAN */ 872 873 #ifdef EMLXS_LITTLE_ENDIAN 874 uint32_t Qid:11; /* MQ id for posted MQE */ 875 uint32_t Rsvd1:5; 876 uint32_t NumPosted:14; /* Number of entries posted */ 877 uint32_t Rsvd2:2; 878 #endif /* EMLXS_LITTLE_ENDIAN */ 879 880 } emlxs_mqdb_t; 881 882 883 typedef union emlxs_mqdbu 884 { 885 uint32_t word; 886 emlxs_mqdb_t db; 887 888 } emlxs_mqdbu_t; 889 890 891 #ifdef __cplusplus 892 } 893 #endif 894 895 #endif /* _EMLXS_QUEUE_H */ 896