1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_QUEUE_H 28 #define _EMLXS_QUEUE_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 /* Queue entry defines */ 36 37 /* EQ entries */ 38 typedef struct EQE 39 { 40 #ifdef EMLXS_BIG_ENDIAN 41 uint32_t CQId: 16; 42 uint32_t MinorCode: 12; 43 uint32_t MajorCode: 3; 44 uint32_t Valid: 1; 45 #endif 46 #ifdef EMLXS_LITTLE_ENDIAN 47 uint32_t Valid: 1; 48 uint32_t MajorCode: 3; 49 uint32_t MinorCode: 12; 50 uint32_t CQId: 16; 51 #endif 52 53 } EQE_t; 54 55 typedef union 56 { 57 uint32_t word; 58 EQE_t entry; 59 60 } EQE_u; 61 62 #define EQE_VALID 0x00000001 /* Mask for EQE valid */ 63 #define EQE_CQID 0xFFFF0000 /* Mask for EQE CQID */ 64 65 /* CQ entries */ 66 typedef struct CQE_CmplWQ 67 { 68 #ifdef EMLXS_BIG_ENDIAN 69 uint16_t RequestTag; /* Word 0 */ 70 uint8_t Status; 71 uint8_t hw_status; 72 73 uint32_t CmdSpecific; /* Word 1 */ 74 uint32_t Parameter; /* Word 2 */ 75 76 uint32_t Valid: 1; /* Word 3 */ 77 uint32_t Rsvd1: 2; 78 uint32_t XB: 1; 79 uint32_t PV: 1; 80 uint32_t Priority: 3; 81 uint32_t Code: 8; 82 uint32_t Rsvd2: 16; 83 #endif 84 #ifdef EMLXS_LITTLE_ENDIAN 85 uint8_t hw_status; 86 uint8_t Status; 87 uint16_t RequestTag; /* Word 0 */ 88 89 uint32_t CmdSpecific; /* Word 1 */ 90 uint32_t Parameter; /* Word 2 */ 91 92 uint32_t Rsvd2: 16; 93 uint32_t Code: 8; 94 uint32_t Priority: 3; 95 uint32_t PV: 1; 96 uint32_t XB: 1; 97 uint32_t Rsvd1: 2; 98 uint32_t Valid: 1; /* Word 3 */ 99 #endif 100 } CQE_CmplWQ_t; 101 102 typedef struct CQE_RelWQ 103 { 104 #ifdef EMLXS_BIG_ENDIAN 105 uint32_t Reserved1; /* Word 0 */ 106 uint32_t Reserved2; /* Word 1 */ 107 108 uint16_t WQid; /* Word 2 */ 109 uint16_t WQindex; 110 111 uint32_t Valid: 1; /* Word 3 */ 112 uint32_t Rsvd1: 7; 113 uint32_t Code: 8; 114 uint32_t Rsvd2: 16; 115 #endif 116 #ifdef EMLXS_LITTLE_ENDIAN 117 uint32_t Reserved1; /* Word 0 */ 118 uint32_t Reserved2; /* Word 1 */ 119 120 uint16_t WQindex; 121 uint16_t WQid; /* Word 2 */ 122 123 uint32_t Rsvd2: 16; 124 uint32_t Code: 8; 125 uint32_t Rsvd1: 7; 126 uint32_t Valid: 1; /* Word 3 */ 127 #endif 128 } CQE_RelWQ_t; 129 130 typedef struct CQE_UnsolRcv 131 { 132 #ifdef EMLXS_BIG_ENDIAN 133 uint16_t RQindex; /* Word 0 */ 134 uint8_t Status; 135 uint8_t Rsvd1; 136 137 uint32_t Rsvd2; /* Word 1 */ 138 139 uint32_t data_size: 16; /* Word 2 */ 140 uint32_t RQid: 10; 141 uint32_t FCFId: 6; 142 143 uint32_t Valid: 1; /* Word 3 */ 144 uint32_t port: 1; 145 uint32_t hdr_size: 6; 146 uint32_t Code: 8; 147 uint32_t eof: 8; 148 uint32_t sof: 8; 149 #endif 150 #ifdef EMLXS_LITTLE_ENDIAN 151 uint8_t Rsvd1; 152 uint8_t Status; 153 uint16_t RQindex; /* Word 0 */ 154 155 uint32_t Rsvd2; /* Word 1 */ 156 157 uint32_t FCFId: 6; 158 uint32_t RQid: 10; 159 uint32_t data_size: 16; /* Word 2 */ 160 161 uint32_t sof: 8; 162 uint32_t eof: 8; 163 uint32_t Code: 8; 164 uint32_t hdr_size: 6; 165 uint32_t port: 1; 166 uint32_t Valid: 1; /* Word 3 */ 167 #endif 168 } CQE_UnsolRcv_t; 169 170 /* Status defines */ 171 #define RQ_STATUS_SUCCESS 0x10 172 #define RQ_STATUS_BUFLEN_EXCEEDED 0x11 173 #define RQ_STATUS_NEED_BUFFER 0x12 174 #define RQ_STATUS_FRAME_DISCARDED 0x13 175 176 177 typedef struct CQE_XRI_Abort 178 { 179 #ifdef EMLXS_BIG_ENDIAN 180 uint16_t Rsvd1; /* Word 0 */ 181 uint8_t Status; 182 uint8_t Rsvd2; 183 184 uint32_t rjtStatus; /* Word 1 */ 185 186 uint16_t RemoteXID; /* Word 2 */ 187 uint16_t XRI; 188 189 uint32_t Valid: 1; /* Word 3 */ 190 uint32_t IA: 1; 191 uint32_t BR: 1; 192 uint32_t EO: 1; 193 uint32_t Rsvd3: 4; 194 uint32_t Code: 8; 195 uint32_t Rsvd4: 16; 196 #endif 197 #ifdef EMLXS_LITTLE_ENDIAN 198 uint8_t Rsvd2; 199 uint8_t Status; 200 uint16_t Rsvd1; /* Word 0 */ 201 202 uint32_t rjtStatus; /* Word 1 */ 203 204 uint16_t XRI; 205 uint16_t RemoteXID; /* Word 2 */ 206 207 uint32_t Rsvd4: 16; 208 uint32_t Code: 8; 209 uint32_t Rsvd3: 4; 210 uint32_t EO: 1; 211 uint32_t BR: 1; 212 uint32_t IA: 1; 213 uint32_t Valid: 1; /* Word 3 */ 214 #endif 215 } CQE_XRI_Abort_t; 216 217 218 219 #define CQE_VALID 0x80000000 /* Mask for CQE valid */ 220 221 /* Defines for CQE Codes */ 222 #define CQE_TYPE_WQ_COMPLETION 1 223 #define CQE_TYPE_RELEASE_WQE 2 224 #define CQE_TYPE_UNSOL_RCV 4 225 #define CQE_TYPE_XRI_ABORTED 5 226 227 228 typedef struct CQE_ASYNC_FCOE 229 { 230 #ifdef EMLXS_BIG_ENDIAN 231 uint32_t ref_index; /* Word 0 */ 232 233 uint16_t evt_type; /* Word 1 */ 234 uint16_t fcf_count; 235 236 uint32_t event_tag; /* Word 2 */ 237 238 uint32_t valid: 1; /* Word 3 */ 239 uint32_t async_evt: 1; 240 uint32_t Rsvd2: 6; 241 uint32_t event_type: 8; 242 uint32_t event_code: 8; 243 uint32_t Rsvd3: 8; 244 #endif 245 #ifdef EMLXS_LITTLE_ENDIAN 246 uint32_t ref_index; /* Word 0 */ 247 248 uint16_t fcf_count; 249 uint16_t evt_type; /* Word 1 */ 250 251 uint32_t event_tag; /* Word 2 */ 252 253 uint32_t Rsvd3: 8; 254 uint32_t event_code: 8; 255 uint32_t event_type: 8; 256 uint32_t Rsvd2: 6; 257 uint32_t async_evt: 1; 258 uint32_t valid: 1; /* Word 3 */ 259 #endif 260 } CQE_ASYNC_FCOE_t; 261 262 typedef struct CQE_ASYNC 263 { 264 #ifdef EMLXS_BIG_ENDIAN 265 uint8_t port_speed; /* Word 0 */ 266 uint8_t port_duplex; 267 uint8_t link_status; 268 uint8_t phys_port; 269 270 uint32_t Rsvd1: 24; /* Word 1 */ 271 uint32_t port_fault: 8; 272 273 uint32_t event_tag; /* Word 2 */ 274 275 uint32_t valid: 1; /* Word 3 */ 276 uint32_t async_evt: 1; 277 uint32_t Rsvd2: 6; 278 uint32_t event_type: 8; 279 uint32_t event_code: 8; 280 uint32_t Rsvd3: 8; 281 #endif 282 #ifdef EMLXS_LITTLE_ENDIAN 283 uint8_t phys_port; 284 uint8_t link_status; 285 uint8_t port_duplex; 286 uint8_t port_speed; /* Word 0 */ 287 288 uint32_t port_fault: 8; 289 uint32_t Rsvd1: 24; /* Word 1 */ 290 291 uint32_t event_tag; /* Word 2 */ 292 293 uint32_t Rsvd3: 8; 294 uint32_t event_code: 8; 295 uint32_t event_type: 8; 296 uint32_t Rsvd2: 6; 297 uint32_t async_evt: 1; 298 uint32_t valid: 1; /* Word 3 */ 299 #endif 300 } CQE_ASYNC_t; 301 302 /* port_speed defines */ 303 #define PHY_1GHZ_LINK 3 304 #define PHY_10GHZ_LINK 4 305 306 /* event_code defines */ 307 #define ASYNC_EVENT_CODE_LINK_STATE 1 308 #define ASYNC_EVENT_CODE_FCOE_FIP 2 309 #define ASYNC_EVENT_CODE_DCBX 3 310 311 /* LINK_STATE - link_status defines */ 312 #define ASYNC_EVENT_PHYS_LINK_DOWN 0 313 #define ASYNC_EVENT_PHYS_LINK_UP 1 314 #define ASYNC_EVENT_LOGICAL_LINK_DOWN 2 315 #define ASYNC_EVENT_LOGICAL_LINK_UP 3 316 317 /* FCOE_FIP - evt_type defines */ 318 #define ASYNC_EVENT_NEW_FCF_DISC 1 319 #define ASYNC_EVENT_FCF_TABLE_FULL 2 320 #define ASYNC_EVENT_FCF_DEAD 3 321 #define ASYNC_EVENT_VIRT_LINK_CLEAR 4 322 323 typedef struct CQE_MBOX 324 { 325 #ifdef EMLXS_BIG_ENDIAN 326 uint16_t extend_status; /* Word 0 */ 327 uint16_t cmpl_status; 328 329 uint32_t tag_low; /* Word 1 */ 330 uint32_t tag_high; /* Word 2 */ 331 332 uint32_t valid: 1; /* Word 3 */ 333 uint32_t async_evt: 1; 334 uint32_t hpi: 1; 335 uint32_t completed: 1; 336 uint32_t consumed: 1; 337 uint32_t Rsvd1: 27; 338 #endif 339 #ifdef EMLXS_LITTLE_ENDIAN 340 uint16_t cmpl_status; 341 uint16_t extend_status; /* Word 0 */ 342 343 uint32_t tag_low; /* Word 1 */ 344 uint32_t tag_high; /* Word 2 */ 345 346 uint32_t Rsvd1: 27; 347 uint32_t consumed: 1; 348 uint32_t completed: 1; 349 uint32_t hpi: 1; 350 uint32_t async_evt: 1; 351 uint32_t valid: 1; /* Word 3 */ 352 #endif 353 } CQE_MBOX_t; 354 355 typedef union 356 { 357 uint32_t word[4]; 358 359 /* Group 1 types */ 360 CQE_ASYNC_t cqAsyncEntry; 361 CQE_ASYNC_FCOE_t cqAsyncFCOEEntry; 362 CQE_MBOX_t cqMboxEntry; 363 364 /* Group 2 types */ 365 CQE_CmplWQ_t cqCmplEntry; 366 CQE_RelWQ_t cqRelEntry; 367 CQE_UnsolRcv_t cqUnsolRcvEntry; 368 CQE_XRI_Abort_t cqXRIEntry; 369 } CQE_u; 370 371 /* RQ entries */ 372 typedef struct RQE 373 { 374 uint32_t AddrHi; 375 uint32_t AddrLo; 376 377 } RQE_t; 378 379 380 /* Definitions for WQEs */ 381 typedef struct 382 { 383 ULP_BDE64 Payload; 384 uint32_t PayloadLength; 385 386 #ifdef EMLXS_BIG_ENDIAN 387 uint32_t Rsvd1: 6; 388 uint32_t VF: 1; 389 uint32_t SP: 1; 390 uint32_t LocalId: 24; 391 392 uint32_t Rsvd2: 8; 393 uint32_t RemoteId: 24; 394 #endif 395 #ifdef EMLXS_LITTLE_ENDIAN 396 uint32_t LocalId: 24; 397 uint32_t SP: 1; 398 uint32_t VF: 1; 399 uint32_t Rsvd1: 6; 400 401 uint32_t RemoteId: 24; 402 uint32_t Rsvd2: 8; 403 #endif 404 405 } ELS_REQ_WQE; 406 407 typedef struct 408 { 409 ULP_BDE64 Payload; 410 uint32_t Rsvd1[2]; 411 412 #ifdef EMLXS_BIG_ENDIAN 413 uint32_t Rsvd2: 8; 414 uint32_t RemoteId: 24; 415 #endif 416 #ifdef EMLXS_LITTLE_ENDIAN 417 uint32_t RemoteId: 24; 418 uint32_t Rsvd2: 8; 419 #endif 420 421 } ELS_RSP_WQE; 422 423 typedef struct 424 { 425 ULP_BDE64 Payload; 426 uint32_t PayloadLength; 427 428 uint32_t Parameter; 429 430 #ifdef EMLXS_BIG_ENDIAN 431 uint32_t Rctl: 8; 432 uint32_t Type: 8; 433 uint32_t DFctl: 8; 434 uint32_t Rsvd1: 4; 435 uint32_t la: 1; 436 uint32_t Rsvd2: 3; 437 #endif 438 #ifdef EMLXS_LITTLE_ENDIAN 439 uint32_t Rsvd2: 3; 440 uint32_t la: 1; 441 uint32_t Rsvd1: 4; 442 uint32_t DFctl: 8; 443 uint32_t Type: 8; 444 uint32_t Rctl: 8; 445 #endif 446 447 } GEN_REQ_WQE; 448 449 typedef struct 450 { 451 ULP_BDE64 Payload; 452 uint32_t PayloadLength; 453 454 uint32_t Parameter; 455 456 #ifdef EMLXS_BIG_ENDIAN 457 uint32_t Rctl: 8; 458 uint32_t Type: 8; 459 uint32_t DFctl: 8; 460 uint32_t ls: 1; 461 uint32_t Rsvd1: 3; 462 uint32_t la: 1; 463 uint32_t si: 1; 464 uint32_t Rsvd2: 2; 465 #endif 466 #ifdef EMLXS_LITTLE_ENDIAN 467 uint32_t Rsvd2: 2; 468 uint32_t si: 1; 469 uint32_t la: 1; 470 uint32_t Rsvd1: 3; 471 uint32_t ls: 1; 472 uint32_t DFctl: 8; 473 uint32_t Type: 8; 474 uint32_t Rctl: 8; 475 #endif 476 477 } XMIT_SEQ_WQE; 478 479 typedef struct 480 { 481 ULP_BDE64 Payload; 482 uint32_t PayloadLength; 483 484 uint32_t TotalTransferCount; 485 uint32_t Rsvd1; 486 487 } FCP_WQE; 488 489 490 typedef struct 491 { 492 uint32_t Rsvd1[3]; 493 494 #ifdef EMLXS_BIG_ENDIAN 495 uint32_t Rsvd2: 16; 496 uint32_t Criteria: 8; 497 uint32_t Rsvd3: 7; 498 uint32_t IA: 1; 499 #endif 500 #ifdef EMLXS_LITTLE_ENDIAN 501 uint32_t IA: 1; 502 uint32_t Rsvd3: 7; 503 uint32_t Criteria: 8; 504 uint32_t Rsvd2: 16; 505 #endif 506 507 uint32_t Rsvd4[2]; 508 509 } ABORT_WQE; 510 511 #define ABORT_XRI_TAG 1 /* Abort tag is a XRITag */ 512 #define ABORT_ABT_TAG 2 /* Abort tag is a AbortTag */ 513 #define ABORT_REQ_TAG 3 /* Abort tag is a RequestTag */ 514 515 typedef struct 516 { 517 #ifdef EMLXS_BIG_ENDIAN 518 uint8_t Payload0; 519 uint8_t Payload1; 520 uint8_t Payload2; 521 uint8_t Payload3; 522 523 uint32_t OXId: 16; 524 uint32_t RXId: 16; 525 526 uint32_t SeqCntLow: 16; 527 uint32_t SeqCntHigh: 16; 528 #endif 529 #ifdef EMLXS_LITTLE_ENDIAN 530 uint8_t Payload3; 531 uint8_t Payload2; 532 uint8_t Payload1; 533 uint8_t Payload0; 534 535 uint32_t RXId: 16; 536 uint32_t OXId: 16; 537 538 uint32_t SeqCntHigh: 16; 539 uint32_t SeqCntLow: 16; 540 #endif 541 uint32_t Rsvd1[2]; 542 #ifdef EMLXS_BIG_ENDIAN 543 uint32_t XO: 1; 544 uint32_t AR: 1; 545 uint32_t PT: 1; 546 uint32_t Rsvd2: 5; 547 uint32_t RemoteId: 24; 548 #endif 549 #ifdef EMLXS_LITTLE_ENDIAN 550 uint32_t RemoteId: 24; 551 uint32_t Rsvd2: 5; 552 uint32_t PT: 1; 553 uint32_t AR: 1; 554 uint32_t XO: 1; 555 #endif 556 557 } BLS_WQE; 558 559 560 typedef struct 561 { 562 uint32_t Rsvd1[5]; 563 564 #ifdef EMLXS_BIG_ENDIAN 565 uint32_t XO: 1; 566 uint32_t Rsvd2: 7; 567 uint32_t RemoteId: 24; 568 #endif 569 #ifdef EMLXS_LITTLE_ENDIAN 570 uint32_t RemoteId: 24; 571 uint32_t Rsvd2: 7; 572 uint32_t XO: 1; 573 #endif 574 575 } CREATE_XRI_WQE; 576 577 typedef struct emlxs_wqe 578 { 579 /* Words 0-5 */ 580 union 581 { 582 uint32_t word[6]; /* Words 0-5: cmd specific */ 583 ELS_REQ_WQE ElsCmd; /* ELS command overlay */ 584 GEN_REQ_WQE GenReq; /* CT command overlay */ 585 FCP_WQE FcpCmd; /* FCP command overlay */ 586 ELS_RSP_WQE ElsRsp; /* ELS response overlay */ 587 ABORT_WQE Abort; /* Abort overlay */ 588 BLS_WQE BlsRsp; /* BLS overlay */ 589 CREATE_XRI_WQE CreateXri; /* Create XRI */ 590 XMIT_SEQ_WQE XmitSeq; /* Xmit Sequence */ 591 } un; 592 593 #ifdef EMLXS_BIG_ENDIAN 594 /* Word 6 */ 595 uint16_t ContextTag; /* Context Tag */ 596 uint16_t XRITag; /* XRItag */ 597 /* Word 7 */ 598 uint32_t Timer: 8; /* TOV */ 599 uint32_t Rsvd2: 1; 600 uint32_t ERP: 1; /* ERP */ 601 uint32_t PU: 2; /* PU */ 602 uint32_t Rsvd1: 1; 603 uint32_t Class: 3; /* COS */ 604 uint32_t Command: 8; /* Command Code */ 605 uint32_t Status: 4; /* Final Status */ 606 uint32_t ContextType: 2; /* Context Type */ 607 uint32_t Rsvd0: 2; 608 /* Word 8 */ 609 uint32_t AbortTag; /* Abort Tag */ 610 /* Word 9 */ 611 uint16_t OXId; /* OXId on xmitted rsp */ 612 uint16_t RequestTag; /* Request Tag */ 613 /* Word 10 */ 614 uint32_t CCP: 8; /* CCP */ 615 uint32_t CCPE: 1; /* CCPEnabled */ 616 uint32_t Rsvd6: 1; 617 uint32_t XC: 1; /* Exchange Create */ 618 uint32_t Rsvd5: 1; 619 uint32_t PV: 1; /* PRIValid */ 620 uint32_t PRI: 3; /* PRI */ 621 uint32_t Rsvd4: 16; 622 /* Word 11 */ 623 uint32_t Rsvd9: 6; 624 uint32_t CQId: 10; /* CompletionQueueID */ 625 uint32_t Rsvd8: 8; 626 uint32_t WQEC: 1; /* Request WQE consumed CQE */ 627 uint32_t Rsvd7: 1; 628 uint32_t ELSId: 2; 629 uint32_t CmdType: 4; /* Command Type */ 630 #endif 631 #ifdef EMLXS_LITTLE_ENDIAN 632 /* Word 6 */ 633 uint16_t XRITag; /* XRItag */ 634 uint16_t ContextTag; /* Context Tag */ 635 /* Word 7 */ 636 uint32_t Rsvd0: 2; 637 uint32_t ContextType: 2; /* Context Type */ 638 uint32_t Status: 4; /* Final Status */ 639 uint32_t Command: 8; /* Command Code */ 640 uint32_t Class: 3; /* COS */ 641 uint32_t Rsvd1: 1; 642 uint32_t PU: 2; /* PU */ 643 uint32_t ERP: 1; /* ERP */ 644 uint32_t Rsvd2: 1; 645 uint32_t Timer: 8; /* TOV */ 646 /* Word 8 */ 647 uint32_t AbortTag; /* Abort Tag */ 648 /* Word 9 */ 649 uint16_t RequestTag; /* Request Tag */ 650 uint16_t OXId; /* OXId on xmitted rsp */ 651 /* Word 10 */ 652 uint32_t Rsvd4: 16; 653 uint32_t PRI: 3; /* PRI */ 654 uint32_t PV: 1; /* PRIValid */ 655 uint32_t Rsvd5: 1; 656 uint32_t XC: 1; /* Exchange Create */ 657 uint32_t Rsvd6: 1; 658 uint32_t CCPE: 1; /* CCPEnabled */ 659 uint32_t CCP: 8; /* CCP */ 660 /* Word 11 */ 661 uint32_t CmdType: 4; /* Command Type */ 662 uint32_t ELSId: 2; 663 uint32_t Rsvd7: 1; 664 uint32_t WQEC: 1; /* Request WQE consumed CQE */ 665 uint32_t Rsvd8: 8; 666 uint32_t CQId: 10; /* CompletionQueueID */ 667 uint32_t Rsvd9: 6; 668 #endif 669 670 /* Words 12-15 */ 671 uint32_t CmdSpecific[4]; /* Word12-15: commandspecific */ 672 } emlxs_wqe_t; 673 674 /* Defines for ContextType */ 675 #define WQE_RPI_CONTEXT 0 676 #define WQE_VPI_CONTEXT 1 677 #define WQE_VFI_CONTEXT 2 678 #define WQE_FCFI_CONTEXT 3 679 680 /* Defines for CmdType */ 681 #define WQE_TYPE_FCP_DATA_IN 0x00 682 #define WQE_TYPE_FCP_DATA_OUT 0x01 683 #define WQE_TYPE_ELS 0x0C 684 #define WQE_TYPE_GEN 0x08 685 #define WQE_TYPE_ABORT 0x08 686 #define WQE_TYPE_MASK_FIP 0x01 687 688 /* Defines for ELSId */ 689 #define WQE_ELSID_FLOGI 0x03 690 #define WQE_ELSID_FDISC 0x02 691 #define WQE_ELSID_LOGO 0x01 692 #define WQE_ELSID_CMD 0x0 693 694 /* RQB */ 695 #define RQB_HEADER_SIZE 32 696 #define RQB_DATA_SIZE 2048 697 #define RQB_COUNT 256 698 699 #define EMLXS_NUM_WQ_PAGES 4 700 701 #define EQ_DEPTH 1024 702 #define CQ_DEPTH 256 703 #define WQ_DEPTH (64 * EMLXS_NUM_WQ_PAGES) 704 #define MQ_DEPTH 16 705 #define RQ_DEPTH 512 /* Multiple of RQB_COUNT */ 706 #define RQ_DEPTH_EXPONENT 9 707 708 709 /* Principal doorbell register layouts */ 710 typedef struct emlxs_rqdb 711 { 712 #ifdef EMLXS_BIG_ENDIAN 713 uint32_t Rsvd2:2; 714 uint32_t NumPosted:14; /* Number of entries posted */ 715 uint32_t Rsvd1:6; 716 uint32_t Qid:10; /* RQ id for posted RQE */ 717 #endif /* EMLXS_BIG_ENDIAN */ 718 719 #ifdef EMLXS_LITTLE_ENDIAN 720 uint32_t Qid:10; /* RQ id for posted RQE */ 721 uint32_t Rsvd1:6; 722 uint32_t NumPosted:14; /* Number of entries posted */ 723 uint32_t Rsvd2:2; 724 #endif /* EMLXS_LITTLE_ENDIAN */ 725 726 } emlxs_rqdb_t; 727 728 729 typedef union emlxs_rqdbu 730 { 731 uint32_t word; 732 emlxs_rqdb_t db; 733 734 } emlxs_rqdbu_t; 735 736 737 typedef struct emlxs_wqdb 738 { 739 #ifdef EMLXS_BIG_ENDIAN 740 uint32_t NumPosted:8; /* Number of entries posted */ 741 uint32_t Index:8; /* Queue index for posted command */ 742 uint32_t Rsvd1:6; 743 uint32_t Qid:10; /* WQ id for posted WQE */ 744 #endif /* EMLXS_BIG_ENDIAN */ 745 746 #ifdef EMLXS_LITTLE_ENDIAN 747 uint32_t Qid:10; /* WQ id for posted WQE */ 748 uint32_t Rsvd1:6; 749 uint32_t Index:8; /* Queue index for posted command */ 750 uint32_t NumPosted:8; /* Number of entries posted */ 751 #endif /* EMLXS_LITTLE_ENDIAN */ 752 753 } emlxs_wqdb_t; 754 755 756 typedef union emlxs_wqdbu 757 { 758 uint32_t word; 759 emlxs_wqdb_t db; 760 761 } emlxs_wqdbu_t; 762 763 764 typedef struct emlxs_cqdb 765 { 766 #ifdef EMLXS_BIG_ENDIAN 767 uint32_t NumPosted:2; /* Number of entries posted */ 768 uint32_t Rearm:1; /* Rearm CQ */ 769 uint32_t NumPopped:13; /* Number of CQ entries processed */ 770 uint32_t Rsvd1:5; 771 uint32_t Event:1; /* 1 if processed entry is EQE */ 772 /* 0 if processed entry is CQE */ 773 uint32_t Qid:10; /* CQ id for posted CQE */ 774 #endif /* EMLXS_BIG_ENDIAN */ 775 776 #ifdef EMLXS_LITTLE_ENDIAN 777 uint32_t Qid:10; /* CQ id for posted CQE */ 778 uint32_t Event:1; /* 1 if processed entry is EQE */ 779 /* 0 if processed entry is CQE */ 780 uint32_t Rsvd1:5; 781 uint32_t NumPopped:13; /* Number of CQ entries processed */ 782 uint32_t Rearm:1; /* Rearm CQ */ 783 uint32_t NumPosted:2; /* Number of entries posted */ 784 #endif /* EMLXS_LITTLE_ENDIAN */ 785 786 } emlxs_cqdb_t; 787 788 789 typedef union emlxs_cqdbu 790 { 791 uint32_t word; 792 emlxs_cqdb_t db; 793 794 } emlxs_cqdbu_t; 795 796 typedef struct emlxs_eqdb 797 { 798 #ifdef EMLXS_BIG_ENDIAN 799 uint32_t Rsvd2:2; 800 uint32_t Rearm:1; /* Rearm EQ */ 801 uint32_t NumPopped:13; /* Number of CQ entries processed */ 802 uint32_t Rsvd1:5; 803 uint32_t Event:1; /* True iff processed entry is EQE */ 804 uint32_t Clear:1; /* clears EQ interrupt when set */ 805 uint32_t Qid:9; /* EQ id for posted EQE */ 806 #endif /* EMLXS_BIG_ENDIAN */ 807 808 #ifdef EMLXS_LITTLE_ENDIAN 809 uint32_t Qid:9; /* EQ id for posted EQE */ 810 uint32_t Clear:1; /* clears EQ interrupt when set */ 811 uint32_t Event:1; /* True iff processed entry is EQE */ 812 uint32_t Rsvd1:5; 813 uint32_t NumPopped:13; /* Number of CQ entries processed */ 814 uint32_t Rearm:1; /* Rearm EQ */ 815 uint32_t Rsvd2:2; 816 #endif /* EMLXS_LITTLE_ENDIAN */ 817 818 } emlxs_eqdb_t; 819 820 821 typedef union emlxs_eqdbu 822 { 823 uint32_t word; 824 emlxs_eqdb_t db; 825 826 } emlxs_eqdbu_t; 827 828 829 typedef struct emlxs_mqdb 830 { 831 #ifdef EMLXS_BIG_ENDIAN 832 uint32_t Rsvd2:2; 833 uint32_t NumPosted:14; /* Number of entries posted */ 834 uint32_t Rsvd1:5; 835 uint32_t Qid:11; /* MQ id for posted MQE */ 836 #endif /* EMLXS_BIG_ENDIAN */ 837 838 #ifdef EMLXS_LITTLE_ENDIAN 839 uint32_t Qid:11; /* MQ id for posted MQE */ 840 uint32_t Rsvd1:5; 841 uint32_t NumPosted:14; /* Number of entries posted */ 842 uint32_t Rsvd2:2; 843 #endif /* EMLXS_LITTLE_ENDIAN */ 844 845 } emlxs_mqdb_t; 846 847 848 typedef union emlxs_mqdbu 849 { 850 uint32_t word; 851 emlxs_mqdb_t db; 852 853 } emlxs_mqdbu_t; 854 855 856 #ifdef __cplusplus 857 } 858 #endif 859 860 #endif /* _EMLXS_QUEUE_H */ 861