1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_QUEUE_H 28 #define _EMLXS_QUEUE_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 /* Queue entry defines */ 36 37 /* EQ entries */ 38 typedef struct EQE 39 { 40 #ifdef EMLXS_BIG_ENDIAN 41 uint32_t CQId: 16; 42 uint32_t MinorCode: 12; 43 uint32_t MajorCode: 3; 44 uint32_t Valid: 1; 45 #endif 46 #ifdef EMLXS_LITTLE_ENDIAN 47 uint32_t Valid: 1; 48 uint32_t MajorCode: 3; 49 uint32_t MinorCode: 12; 50 uint32_t CQId: 16; 51 #endif 52 53 } EQE_t; 54 55 typedef union 56 { 57 uint32_t word; 58 EQE_t entry; 59 60 } EQE_u; 61 62 #define EQE_VALID 0x00000001 /* Mask for EQE valid */ 63 #define EQE_CQID 0xFFFF0000 /* Mask for EQE CQID */ 64 65 /* CQ entries */ 66 typedef struct CQE_CmplWQ 67 { 68 #ifdef EMLXS_BIG_ENDIAN 69 uint16_t RequestTag; /* Word 0 */ 70 uint8_t Status; 71 uint8_t hw_status; 72 73 uint32_t CmdSpecific; /* Word 1 */ 74 uint32_t Parameter; /* Word 2 */ 75 76 uint32_t Valid: 1; /* Word 3 */ 77 uint32_t Rsvd1: 2; 78 uint32_t XB: 1; 79 uint32_t PV: 1; 80 uint32_t Priority: 3; 81 uint32_t Code: 8; 82 uint32_t Rsvd2: 16; 83 #endif 84 #ifdef EMLXS_LITTLE_ENDIAN 85 uint8_t hw_status; 86 uint8_t Status; 87 uint16_t RequestTag; /* Word 0 */ 88 89 uint32_t CmdSpecific; /* Word 1 */ 90 uint32_t Parameter; /* Word 2 */ 91 92 uint32_t Rsvd2: 16; 93 uint32_t Code: 8; 94 uint32_t Priority: 3; 95 uint32_t PV: 1; 96 uint32_t XB: 1; 97 uint32_t Rsvd1: 2; 98 uint32_t Valid: 1; /* Word 3 */ 99 #endif 100 } CQE_CmplWQ_t; 101 102 typedef struct CQE_RelWQ 103 { 104 #ifdef EMLXS_BIG_ENDIAN 105 uint32_t Reserved1; /* Word 0 */ 106 uint32_t Reserved2; /* Word 1 */ 107 108 uint16_t WQid; /* Word 2 */ 109 uint16_t WQindex; 110 111 uint32_t Valid: 1; /* Word 3 */ 112 uint32_t Rsvd1: 7; 113 uint32_t Code: 8; 114 uint32_t Rsvd2: 16; 115 #endif 116 #ifdef EMLXS_LITTLE_ENDIAN 117 uint32_t Reserved1; /* Word 0 */ 118 uint32_t Reserved2; /* Word 1 */ 119 120 uint16_t WQindex; 121 uint16_t WQid; /* Word 2 */ 122 123 uint32_t Rsvd2: 16; 124 uint32_t Code: 8; 125 uint32_t Rsvd1: 7; 126 uint32_t Valid: 1; /* Word 3 */ 127 #endif 128 } CQE_RelWQ_t; 129 130 typedef struct CQE_UnsolRcv 131 { 132 #ifdef EMLXS_BIG_ENDIAN 133 uint16_t RQindex; /* Word 0 */ 134 uint8_t Status; 135 uint8_t Rsvd1; 136 137 uint32_t Rsvd2; /* Word 1 */ 138 139 uint32_t data_size: 16; /* Word 2 */ 140 uint32_t RQid: 10; 141 uint32_t FCFId: 6; 142 143 uint32_t Valid: 1; /* Word 3 */ 144 uint32_t port: 1; 145 uint32_t hdr_size: 6; 146 uint32_t Code: 8; 147 uint32_t eof: 8; 148 uint32_t sof: 8; 149 #endif 150 #ifdef EMLXS_LITTLE_ENDIAN 151 uint8_t Rsvd1; 152 uint8_t Status; 153 uint16_t RQindex; /* Word 0 */ 154 155 uint32_t Rsvd2; /* Word 1 */ 156 157 uint32_t FCFId: 6; 158 uint32_t RQid: 10; 159 uint32_t data_size: 16; /* Word 2 */ 160 161 uint32_t sof: 8; 162 uint32_t eof: 8; 163 uint32_t Code: 8; 164 uint32_t hdr_size: 6; 165 uint32_t port: 1; 166 uint32_t Valid: 1; /* Word 3 */ 167 #endif 168 } CQE_UnsolRcv_t; 169 170 /* Status defines */ 171 #define RQ_STATUS_SUCCESS 0x10 172 #define RQ_STATUS_BUFLEN_EXCEEDED 0x11 173 #define RQ_STATUS_NEED_BUFFER 0x12 174 #define RQ_STATUS_FRAME_DISCARDED 0x13 175 176 177 typedef struct CQE_XRI_Abort 178 { 179 #ifdef EMLXS_BIG_ENDIAN 180 uint16_t Rsvd1; /* Word 0 */ 181 uint8_t Status; 182 uint8_t Rsvd2; 183 184 uint32_t rjtStatus; /* Word 1 */ 185 186 uint16_t RemoteXID; /* Word 2 */ 187 uint16_t XRI; 188 189 uint32_t Valid: 1; /* Word 3 */ 190 uint32_t IA: 1; 191 uint32_t BR: 1; 192 uint32_t EO: 1; 193 uint32_t Rsvd3: 4; 194 uint32_t Code: 8; 195 uint32_t Rsvd4: 16; 196 #endif 197 #ifdef EMLXS_LITTLE_ENDIAN 198 uint8_t Rsvd2; 199 uint8_t Status; 200 uint16_t Rsvd1; /* Word 0 */ 201 202 uint32_t rjtStatus; /* Word 1 */ 203 204 uint16_t XRI; 205 uint16_t RemoteXID; /* Word 2 */ 206 207 uint32_t Rsvd4: 16; 208 uint32_t Code: 8; 209 uint32_t Rsvd3: 4; 210 uint32_t EO: 1; 211 uint32_t BR: 1; 212 uint32_t IA: 1; 213 uint32_t Valid: 1; /* Word 3 */ 214 #endif 215 } CQE_XRI_Abort_t; 216 217 218 219 #define CQE_VALID 0x80000000 /* Mask for CQE valid */ 220 221 /* Defines for CQE Codes */ 222 #define CQE_TYPE_WQ_COMPLETION 1 223 #define CQE_TYPE_RELEASE_WQE 2 224 #define CQE_TYPE_UNSOL_RCV 4 225 #define CQE_TYPE_XRI_ABORTED 5 226 227 228 typedef struct CQE_ASYNC_FCOE 229 { 230 #ifdef EMLXS_BIG_ENDIAN 231 uint32_t ref_index; /* Word 0 */ 232 233 uint16_t evt_type; /* Word 1 */ 234 uint16_t fcf_count; 235 236 uint32_t event_tag; /* Word 2 */ 237 238 uint32_t valid: 1; /* Word 3 */ 239 uint32_t async_evt: 1; 240 uint32_t Rsvd2: 6; 241 uint32_t event_type: 8; 242 uint32_t event_code: 8; 243 uint32_t Rsvd3: 8; 244 #endif 245 #ifdef EMLXS_LITTLE_ENDIAN 246 uint32_t ref_index; /* Word 0 */ 247 248 uint16_t fcf_count; 249 uint16_t evt_type; /* Word 1 */ 250 251 uint32_t event_tag; /* Word 2 */ 252 253 uint32_t Rsvd3: 8; 254 uint32_t event_code: 8; 255 uint32_t event_type: 8; 256 uint32_t Rsvd2: 6; 257 uint32_t async_evt: 1; 258 uint32_t valid: 1; /* Word 3 */ 259 #endif 260 } CQE_ASYNC_FCOE_t; 261 262 typedef struct CQE_ASYNC 263 { 264 #ifdef EMLXS_BIG_ENDIAN 265 uint8_t port_speed; /* Word 0 */ 266 uint8_t port_duplex; 267 uint8_t link_status; 268 uint8_t phys_port; 269 270 uint16_t qos_link_speed; /* Word 1 */ 271 uint8_t Rsvd1; 272 uint8_t port_fault; 273 274 uint32_t event_tag; /* Word 2 */ 275 276 uint32_t valid: 1; /* Word 3 */ 277 uint32_t async_evt: 1; 278 uint32_t Rsvd2: 6; 279 uint32_t event_type: 8; 280 uint32_t event_code: 8; 281 uint32_t Rsvd3: 8; 282 #endif 283 #ifdef EMLXS_LITTLE_ENDIAN 284 uint8_t phys_port; 285 uint8_t link_status; 286 uint8_t port_duplex; 287 uint8_t port_speed; /* Word 0 */ 288 289 uint8_t port_fault; /* Word 1 */ 290 uint8_t Rsvd1; 291 uint16_t qos_link_speed; 292 293 uint32_t event_tag; /* Word 2 */ 294 295 uint32_t Rsvd3: 8; 296 uint32_t event_code: 8; 297 uint32_t event_type: 8; 298 uint32_t Rsvd2: 6; 299 uint32_t async_evt: 1; 300 uint32_t valid: 1; /* Word 3 */ 301 #endif 302 } CQE_ASYNC_t; 303 304 /* port_speed defines */ 305 #define PHY_1GHZ_LINK 3 306 #define PHY_10GHZ_LINK 4 307 308 /* event_code defines */ 309 #define ASYNC_EVENT_CODE_LINK_STATE 1 310 #define ASYNC_EVENT_CODE_FCOE_FIP 2 311 #define ASYNC_EVENT_CODE_DCBX 3 312 313 /* LINK_STATE - link_status defines */ 314 #define ASYNC_EVENT_PHYS_LINK_DOWN 0 315 #define ASYNC_EVENT_PHYS_LINK_UP 1 316 #define ASYNC_EVENT_LOGICAL_LINK_DOWN 2 317 #define ASYNC_EVENT_LOGICAL_LINK_UP 3 318 319 /* FCOE_FIP - evt_type defines */ 320 #define ASYNC_EVENT_NEW_FCF_DISC 1 321 #define ASYNC_EVENT_FCF_TABLE_FULL 2 322 #define ASYNC_EVENT_FCF_DEAD 3 323 #define ASYNC_EVENT_VIRT_LINK_CLEAR 4 324 325 typedef struct CQE_MBOX 326 { 327 #ifdef EMLXS_BIG_ENDIAN 328 uint16_t extend_status; /* Word 0 */ 329 uint16_t cmpl_status; 330 331 uint32_t tag_low; /* Word 1 */ 332 uint32_t tag_high; /* Word 2 */ 333 334 uint32_t valid: 1; /* Word 3 */ 335 uint32_t async_evt: 1; 336 uint32_t hpi: 1; 337 uint32_t completed: 1; 338 uint32_t consumed: 1; 339 uint32_t Rsvd1: 27; 340 #endif 341 #ifdef EMLXS_LITTLE_ENDIAN 342 uint16_t cmpl_status; 343 uint16_t extend_status; /* Word 0 */ 344 345 uint32_t tag_low; /* Word 1 */ 346 uint32_t tag_high; /* Word 2 */ 347 348 uint32_t Rsvd1: 27; 349 uint32_t consumed: 1; 350 uint32_t completed: 1; 351 uint32_t hpi: 1; 352 uint32_t async_evt: 1; 353 uint32_t valid: 1; /* Word 3 */ 354 #endif 355 } CQE_MBOX_t; 356 357 typedef union 358 { 359 uint32_t word[4]; 360 361 /* Group 1 types */ 362 CQE_ASYNC_t cqAsyncEntry; 363 CQE_ASYNC_FCOE_t cqAsyncFCOEEntry; 364 CQE_MBOX_t cqMboxEntry; 365 366 /* Group 2 types */ 367 CQE_CmplWQ_t cqCmplEntry; 368 CQE_RelWQ_t cqRelEntry; 369 CQE_UnsolRcv_t cqUnsolRcvEntry; 370 CQE_XRI_Abort_t cqXRIEntry; 371 } CQE_u; 372 373 /* RQ entries */ 374 typedef struct RQE 375 { 376 uint32_t AddrHi; 377 uint32_t AddrLo; 378 379 } RQE_t; 380 381 382 /* Definitions for WQEs */ 383 typedef struct 384 { 385 ULP_BDE64 Payload; 386 uint32_t PayloadLength; 387 388 #ifdef EMLXS_BIG_ENDIAN 389 uint32_t Rsvd1: 6; 390 uint32_t VF: 1; 391 uint32_t SP: 1; 392 uint32_t LocalId: 24; 393 394 uint32_t Rsvd2: 8; 395 uint32_t RemoteId: 24; 396 #endif 397 #ifdef EMLXS_LITTLE_ENDIAN 398 uint32_t LocalId: 24; 399 uint32_t SP: 1; 400 uint32_t VF: 1; 401 uint32_t Rsvd1: 6; 402 403 uint32_t RemoteId: 24; 404 uint32_t Rsvd2: 8; 405 #endif 406 407 } ELS_REQ_WQE; 408 409 typedef struct 410 { 411 ULP_BDE64 Payload; 412 uint32_t Rsvd1[2]; 413 414 #ifdef EMLXS_BIG_ENDIAN 415 uint32_t Rsvd2: 8; 416 uint32_t RemoteId: 24; 417 #endif 418 #ifdef EMLXS_LITTLE_ENDIAN 419 uint32_t RemoteId: 24; 420 uint32_t Rsvd2: 8; 421 #endif 422 423 } ELS_RSP_WQE; 424 425 typedef struct 426 { 427 ULP_BDE64 Payload; 428 uint32_t PayloadLength; 429 430 uint32_t Parameter; 431 432 #ifdef EMLXS_BIG_ENDIAN 433 uint32_t Rctl: 8; 434 uint32_t Type: 8; 435 uint32_t DFctl: 8; 436 uint32_t Rsvd1: 4; 437 uint32_t la: 1; 438 uint32_t Rsvd2: 3; 439 #endif 440 #ifdef EMLXS_LITTLE_ENDIAN 441 uint32_t Rsvd2: 3; 442 uint32_t la: 1; 443 uint32_t Rsvd1: 4; 444 uint32_t DFctl: 8; 445 uint32_t Type: 8; 446 uint32_t Rctl: 8; 447 #endif 448 449 } GEN_REQ_WQE; 450 451 typedef struct 452 { 453 ULP_BDE64 Payload; 454 uint32_t PayloadLength; 455 456 uint32_t Parameter; 457 458 #ifdef EMLXS_BIG_ENDIAN 459 uint32_t Rctl: 8; 460 uint32_t Type: 8; 461 uint32_t DFctl: 8; 462 uint32_t ls: 1; 463 uint32_t Rsvd1: 3; 464 uint32_t la: 1; 465 uint32_t si: 1; 466 uint32_t Rsvd2: 2; 467 #endif 468 #ifdef EMLXS_LITTLE_ENDIAN 469 uint32_t Rsvd2: 2; 470 uint32_t si: 1; 471 uint32_t la: 1; 472 uint32_t Rsvd1: 3; 473 uint32_t ls: 1; 474 uint32_t DFctl: 8; 475 uint32_t Type: 8; 476 uint32_t Rctl: 8; 477 #endif 478 479 } XMIT_SEQ_WQE; 480 481 typedef struct 482 { 483 ULP_BDE64 Payload; 484 uint32_t PayloadLength; 485 486 uint32_t TotalTransferCount; 487 uint32_t Rsvd1; 488 489 } FCP_WQE; 490 491 492 typedef struct 493 { 494 uint32_t Rsvd1[3]; 495 496 #ifdef EMLXS_BIG_ENDIAN 497 uint32_t Rsvd2: 16; 498 uint32_t Criteria: 8; 499 uint32_t Rsvd3: 7; 500 uint32_t IA: 1; 501 #endif 502 #ifdef EMLXS_LITTLE_ENDIAN 503 uint32_t IA: 1; 504 uint32_t Rsvd3: 7; 505 uint32_t Criteria: 8; 506 uint32_t Rsvd2: 16; 507 #endif 508 509 uint32_t Rsvd4[2]; 510 511 } ABORT_WQE; 512 513 #define ABORT_XRI_TAG 1 /* Abort tag is a XRITag */ 514 #define ABORT_ABT_TAG 2 /* Abort tag is a AbortTag */ 515 #define ABORT_REQ_TAG 3 /* Abort tag is a RequestTag */ 516 517 typedef struct 518 { 519 #ifdef EMLXS_BIG_ENDIAN 520 uint8_t Payload0; 521 uint8_t Payload1; 522 uint8_t Payload2; 523 uint8_t Payload3; 524 525 uint32_t OXId: 16; 526 uint32_t RXId: 16; 527 528 uint32_t SeqCntLow: 16; 529 uint32_t SeqCntHigh: 16; 530 #endif 531 #ifdef EMLXS_LITTLE_ENDIAN 532 uint8_t Payload3; 533 uint8_t Payload2; 534 uint8_t Payload1; 535 uint8_t Payload0; 536 537 uint32_t RXId: 16; 538 uint32_t OXId: 16; 539 540 uint32_t SeqCntHigh: 16; 541 uint32_t SeqCntLow: 16; 542 #endif 543 uint32_t Rsvd1[2]; 544 #ifdef EMLXS_BIG_ENDIAN 545 uint32_t XO: 1; 546 uint32_t AR: 1; 547 uint32_t PT: 1; 548 uint32_t Rsvd2: 5; 549 uint32_t RemoteId: 24; 550 #endif 551 #ifdef EMLXS_LITTLE_ENDIAN 552 uint32_t RemoteId: 24; 553 uint32_t Rsvd2: 5; 554 uint32_t PT: 1; 555 uint32_t AR: 1; 556 uint32_t XO: 1; 557 #endif 558 559 } BLS_WQE; 560 561 562 typedef struct 563 { 564 uint32_t Rsvd1[5]; 565 566 #ifdef EMLXS_BIG_ENDIAN 567 uint32_t XO: 1; 568 uint32_t Rsvd2: 7; 569 uint32_t RemoteId: 24; 570 #endif 571 #ifdef EMLXS_LITTLE_ENDIAN 572 uint32_t RemoteId: 24; 573 uint32_t Rsvd2: 7; 574 uint32_t XO: 1; 575 #endif 576 577 } CREATE_XRI_WQE; 578 579 typedef struct emlxs_wqe 580 { 581 /* Words 0-5 */ 582 union 583 { 584 uint32_t word[6]; /* Words 0-5: cmd specific */ 585 ELS_REQ_WQE ElsCmd; /* ELS command overlay */ 586 GEN_REQ_WQE GenReq; /* CT command overlay */ 587 FCP_WQE FcpCmd; /* FCP command overlay */ 588 ELS_RSP_WQE ElsRsp; /* ELS response overlay */ 589 ABORT_WQE Abort; /* Abort overlay */ 590 BLS_WQE BlsRsp; /* BLS overlay */ 591 CREATE_XRI_WQE CreateXri; /* Create XRI */ 592 XMIT_SEQ_WQE XmitSeq; /* Xmit Sequence */ 593 } un; 594 595 #ifdef EMLXS_BIG_ENDIAN 596 /* Word 6 */ 597 uint16_t ContextTag; /* Context Tag */ 598 uint16_t XRITag; /* XRItag */ 599 /* Word 7 */ 600 uint32_t Timer: 8; /* TOV */ 601 uint32_t Rsvd2: 1; 602 uint32_t ERP: 1; /* ERP */ 603 uint32_t PU: 2; /* PU */ 604 uint32_t Rsvd1: 1; 605 uint32_t Class: 3; /* COS */ 606 uint32_t Command: 8; /* Command Code */ 607 uint32_t Status: 4; /* Final Status */ 608 uint32_t ContextType: 2; /* Context Type */ 609 uint32_t Rsvd0: 2; 610 /* Word 8 */ 611 uint32_t AbortTag; /* Abort Tag */ 612 /* Word 9 */ 613 uint16_t OXId; /* OXId on xmitted rsp */ 614 uint16_t RequestTag; /* Request Tag */ 615 /* Word 10 */ 616 uint32_t CCP: 8; /* CCP */ 617 uint32_t CCPE: 1; /* CCPEnabled */ 618 uint32_t Rsvd6: 1; 619 uint32_t XC: 1; /* Exchange Create */ 620 uint32_t Rsvd5: 1; 621 uint32_t PV: 1; /* PRIValid */ 622 uint32_t PRI: 3; /* PRI */ 623 uint32_t Rsvd4: 16; 624 /* Word 11 */ 625 uint32_t Rsvd9: 6; 626 uint32_t CQId: 10; /* CompletionQueueID */ 627 uint32_t Rsvd8: 8; 628 uint32_t WQEC: 1; /* Request WQE consumed CQE */ 629 uint32_t Rsvd7: 1; 630 uint32_t ELSId: 2; 631 uint32_t CmdType: 4; /* Command Type */ 632 #endif 633 #ifdef EMLXS_LITTLE_ENDIAN 634 /* Word 6 */ 635 uint16_t XRITag; /* XRItag */ 636 uint16_t ContextTag; /* Context Tag */ 637 /* Word 7 */ 638 uint32_t Rsvd0: 2; 639 uint32_t ContextType: 2; /* Context Type */ 640 uint32_t Status: 4; /* Final Status */ 641 uint32_t Command: 8; /* Command Code */ 642 uint32_t Class: 3; /* COS */ 643 uint32_t Rsvd1: 1; 644 uint32_t PU: 2; /* PU */ 645 uint32_t ERP: 1; /* ERP */ 646 uint32_t Rsvd2: 1; 647 uint32_t Timer: 8; /* TOV */ 648 /* Word 8 */ 649 uint32_t AbortTag; /* Abort Tag */ 650 /* Word 9 */ 651 uint16_t RequestTag; /* Request Tag */ 652 uint16_t OXId; /* OXId on xmitted rsp */ 653 /* Word 10 */ 654 uint32_t Rsvd4: 16; 655 uint32_t PRI: 3; /* PRI */ 656 uint32_t PV: 1; /* PRIValid */ 657 uint32_t Rsvd5: 1; 658 uint32_t XC: 1; /* Exchange Create */ 659 uint32_t Rsvd6: 1; 660 uint32_t CCPE: 1; /* CCPEnabled */ 661 uint32_t CCP: 8; /* CCP */ 662 /* Word 11 */ 663 uint32_t CmdType: 4; /* Command Type */ 664 uint32_t ELSId: 2; 665 uint32_t Rsvd7: 1; 666 uint32_t WQEC: 1; /* Request WQE consumed CQE */ 667 uint32_t Rsvd8: 8; 668 uint32_t CQId: 10; /* CompletionQueueID */ 669 uint32_t Rsvd9: 6; 670 #endif 671 672 /* Words 12-15 */ 673 uint32_t CmdSpecific[4]; /* Word12-15: commandspecific */ 674 } emlxs_wqe_t; 675 676 /* Defines for ContextType */ 677 #define WQE_RPI_CONTEXT 0 678 #define WQE_VPI_CONTEXT 1 679 #define WQE_VFI_CONTEXT 2 680 #define WQE_FCFI_CONTEXT 3 681 682 /* Defines for CmdType */ 683 #define WQE_TYPE_FCP_DATA_IN 0x00 684 #define WQE_TYPE_FCP_DATA_OUT 0x01 685 #define WQE_TYPE_ELS 0x0C 686 #define WQE_TYPE_GEN 0x08 687 #define WQE_TYPE_ABORT 0x08 688 #define WQE_TYPE_MASK_FIP 0x01 689 690 /* Defines for ELSId */ 691 #define WQE_ELSID_FLOGI 0x03 692 #define WQE_ELSID_FDISC 0x02 693 #define WQE_ELSID_LOGO 0x01 694 #define WQE_ELSID_CMD 0x0 695 696 /* RQB */ 697 #define RQB_HEADER_SIZE 32 698 #define RQB_DATA_SIZE 2048 699 #define RQB_COUNT 256 700 701 #define EMLXS_NUM_WQ_PAGES 4 702 703 #define EQ_DEPTH 1024 704 #define CQ_DEPTH 256 705 #define WQ_DEPTH (64 * EMLXS_NUM_WQ_PAGES) 706 #define MQ_DEPTH 16 707 #define RQ_DEPTH 512 /* Multiple of RQB_COUNT */ 708 #define RQ_DEPTH_EXPONENT 9 709 710 711 /* Principal doorbell register layouts */ 712 typedef struct emlxs_rqdb 713 { 714 #ifdef EMLXS_BIG_ENDIAN 715 uint32_t Rsvd2:2; 716 uint32_t NumPosted:14; /* Number of entries posted */ 717 uint32_t Rsvd1:6; 718 uint32_t Qid:10; /* RQ id for posted RQE */ 719 #endif /* EMLXS_BIG_ENDIAN */ 720 721 #ifdef EMLXS_LITTLE_ENDIAN 722 uint32_t Qid:10; /* RQ id for posted RQE */ 723 uint32_t Rsvd1:6; 724 uint32_t NumPosted:14; /* Number of entries posted */ 725 uint32_t Rsvd2:2; 726 #endif /* EMLXS_LITTLE_ENDIAN */ 727 728 } emlxs_rqdb_t; 729 730 731 typedef union emlxs_rqdbu 732 { 733 uint32_t word; 734 emlxs_rqdb_t db; 735 736 } emlxs_rqdbu_t; 737 738 739 typedef struct emlxs_wqdb 740 { 741 #ifdef EMLXS_BIG_ENDIAN 742 uint32_t NumPosted:8; /* Number of entries posted */ 743 uint32_t Index:8; /* Queue index for posted command */ 744 uint32_t Rsvd1:6; 745 uint32_t Qid:10; /* WQ id for posted WQE */ 746 #endif /* EMLXS_BIG_ENDIAN */ 747 748 #ifdef EMLXS_LITTLE_ENDIAN 749 uint32_t Qid:10; /* WQ id for posted WQE */ 750 uint32_t Rsvd1:6; 751 uint32_t Index:8; /* Queue index for posted command */ 752 uint32_t NumPosted:8; /* Number of entries posted */ 753 #endif /* EMLXS_LITTLE_ENDIAN */ 754 755 } emlxs_wqdb_t; 756 757 758 typedef union emlxs_wqdbu 759 { 760 uint32_t word; 761 emlxs_wqdb_t db; 762 763 } emlxs_wqdbu_t; 764 765 766 typedef struct emlxs_cqdb 767 { 768 #ifdef EMLXS_BIG_ENDIAN 769 uint32_t NumPosted:2; /* Number of entries posted */ 770 uint32_t Rearm:1; /* Rearm CQ */ 771 uint32_t NumPopped:13; /* Number of CQ entries processed */ 772 uint32_t Rsvd1:5; 773 uint32_t Event:1; /* 1 if processed entry is EQE */ 774 /* 0 if processed entry is CQE */ 775 uint32_t Qid:10; /* CQ id for posted CQE */ 776 #endif /* EMLXS_BIG_ENDIAN */ 777 778 #ifdef EMLXS_LITTLE_ENDIAN 779 uint32_t Qid:10; /* CQ id for posted CQE */ 780 uint32_t Event:1; /* 1 if processed entry is EQE */ 781 /* 0 if processed entry is CQE */ 782 uint32_t Rsvd1:5; 783 uint32_t NumPopped:13; /* Number of CQ entries processed */ 784 uint32_t Rearm:1; /* Rearm CQ */ 785 uint32_t NumPosted:2; /* Number of entries posted */ 786 #endif /* EMLXS_LITTLE_ENDIAN */ 787 788 } emlxs_cqdb_t; 789 790 791 typedef union emlxs_cqdbu 792 { 793 uint32_t word; 794 emlxs_cqdb_t db; 795 796 } emlxs_cqdbu_t; 797 798 typedef struct emlxs_eqdb 799 { 800 #ifdef EMLXS_BIG_ENDIAN 801 uint32_t Rsvd2:2; 802 uint32_t Rearm:1; /* Rearm EQ */ 803 uint32_t NumPopped:13; /* Number of CQ entries processed */ 804 uint32_t Rsvd1:5; 805 uint32_t Event:1; /* True iff processed entry is EQE */ 806 uint32_t Clear:1; /* clears EQ interrupt when set */ 807 uint32_t Qid:9; /* EQ id for posted EQE */ 808 #endif /* EMLXS_BIG_ENDIAN */ 809 810 #ifdef EMLXS_LITTLE_ENDIAN 811 uint32_t Qid:9; /* EQ id for posted EQE */ 812 uint32_t Clear:1; /* clears EQ interrupt when set */ 813 uint32_t Event:1; /* True iff processed entry is EQE */ 814 uint32_t Rsvd1:5; 815 uint32_t NumPopped:13; /* Number of CQ entries processed */ 816 uint32_t Rearm:1; /* Rearm EQ */ 817 uint32_t Rsvd2:2; 818 #endif /* EMLXS_LITTLE_ENDIAN */ 819 820 } emlxs_eqdb_t; 821 822 823 typedef union emlxs_eqdbu 824 { 825 uint32_t word; 826 emlxs_eqdb_t db; 827 828 } emlxs_eqdbu_t; 829 830 831 typedef struct emlxs_mqdb 832 { 833 #ifdef EMLXS_BIG_ENDIAN 834 uint32_t Rsvd2:2; 835 uint32_t NumPosted:14; /* Number of entries posted */ 836 uint32_t Rsvd1:5; 837 uint32_t Qid:11; /* MQ id for posted MQE */ 838 #endif /* EMLXS_BIG_ENDIAN */ 839 840 #ifdef EMLXS_LITTLE_ENDIAN 841 uint32_t Qid:11; /* MQ id for posted MQE */ 842 uint32_t Rsvd1:5; 843 uint32_t NumPosted:14; /* Number of entries posted */ 844 uint32_t Rsvd2:2; 845 #endif /* EMLXS_LITTLE_ENDIAN */ 846 847 } emlxs_mqdb_t; 848 849 850 typedef union emlxs_mqdbu 851 { 852 uint32_t word; 853 emlxs_mqdb_t db; 854 855 } emlxs_mqdbu_t; 856 857 858 #ifdef __cplusplus 859 } 860 #endif 861 862 #endif /* _EMLXS_QUEUE_H */ 863