1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to License terms. 25 */ 26 27 28 #ifndef _EMLXS_MENLO_H 29 #define _EMLXS_MENLO_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #ifdef MENLO_SUPPORT 36 37 /* 38 * COMMANDS 39 */ 40 41 typedef struct menlo_init_cmd 42 { 43 uint32_t code; /* Command code = MENLO_CMD_INITIALIZE */ 44 uint32_t bb_credit; /* Menlo FC BB Credit */ 45 uint32_t frame_size; /* Menlo FC receive frame size */ 46 47 } menlo_init_cmd_t; 48 49 50 typedef struct menlo_fw_download_cmd 51 { 52 uint32_t code; /* Command code = MENLO_CMD_FW_DOWNLOAD */ 53 uint32_t length; /* Firmware image length in bytes */ 54 /* (4 byte aligned) */ 55 uint32_t type; /* Firmware image type */ 56 57 #define MENLO_IMAGE_TYPE_OP 1 58 #define MENLO_IMAGE_TYPE_DIAG 2 59 60 /* Followed by length bytes of firmware image */ 61 /* Firmware image will be in Little Endian format */ 62 63 } menlo_fw_download_cmd_t; 64 65 66 typedef struct menlo_memory_cmd 67 { 68 uint32_t code; /* Command code */ 69 uint32_t address; /* Menlo memory address */ 70 uint32_t length; /* Number of words */ 71 72 } menlo_memory_cmd_t; 73 74 75 typedef struct menlo_fte_insert_cmd 76 { 77 uint32_t code; /* Command code = MENLO_CMD_FTE_INSERT */ 78 uint32_t mask; /* mask = True or False */ 79 80 #define MENLO_SRC_MASK_FALSE 0 81 #define MENLO_SRC_MASK_TRUE 1 82 83 uint32_t fcid; /* FCID of remote port */ 84 uint8_t wwpn[8]; /* WWPN of remote port */ 85 86 } menlo_fte_insert_cmd_t; 87 88 89 typedef struct menlo_fte_delete_cmd 90 { 91 uint32_t code; /* Command code = MENLO_CMD_FTE_DELETE */ 92 uint32_t fcid; /* FCID of remote port */ 93 uint8_t wwpn[8]; /* WWPN of remote port */ 94 95 } menlo_fte_delete_cmd_t; 96 97 98 typedef struct menlo_get_cmd 99 { 100 uint32_t code; /* Command code */ 101 uint32_t context; /* Context */ 102 103 /* MENLO_CMD_GET_PORT_STATS */ 104 #define MENLO_PORT_ETH0 0 105 #define MENLO_PORT_ETH1 1 106 #define MENLO_PORT_NSL0 2 107 #define MENLO_PORT_NSL1 3 108 #define MENLO_PORT_FC0 4 109 #define MENLO_PORT_FC1 5 110 111 /* MENLO_CMD_GET_LIF_STATS */ 112 #define MENLO_LIF_ETH0 0 113 #define MENLO_LIF_ETH1 1 114 #define MENLO_LIF_FC0 2 115 #define MENLO_LIF_FC1 3 116 117 /* MENLO_CMD_GET_LB_MODE */ 118 #define MENLO_NSL_PORT_ID_0 0 119 #define MENLO_NSL_PORT_ID_1 1 120 121 uint32_t length; /* Max response length */ 122 123 } menlo_get_cmd_t; 124 125 126 typedef struct menlo_set_cmd 127 { 128 uint32_t code; /* Command code = MENLO_CMD_SET_PAUSE */ 129 uint32_t value1; /* value1 */ 130 uint32_t value2; /* value2 */ 131 132 /* MENLO_CMD_SET_PAUSE values */ 133 #define MENLO_PAUSE_TYPE_SP 1 134 #define MENLO_PAUSE_TYPE_PPP 2 135 136 /* PPP Priority bits : [ ][ ][ ][ ][X][ ][ ][ ] */ 137 /* COS : 7 6 5 4 3 2 1 0 */ 138 #define MENLO_PPP_COS0 0x01 139 #define MENLO_PPP_COS1 0x02 140 #define MENLO_PPP_COS2 0x04 141 #define MENLO_PPP_COS3 0x08 142 #define MENLO_PPP_COS4 0x10 143 #define MENLO_PPP_COS5 0x20 144 #define MENLO_PPP_COS6 0x40 145 #define MENLO_PPP_COS7 0x80 146 147 /* MENLO_CMD_SET_FCOE_COS values */ 148 #define MENLO_FCOE_COS 3 149 150 /* MENLO_CMD_SET_UIF_PORT_TYPE values */ 151 #define MENLO_PORT_TYPE_ACCESS 1 152 #define MENLO_PORT_TYPE_TRUNK 2 153 154 /* MENLO_CMD_SET_MODE values */ 155 #define MENLO_MAINTENANCE_MODE_DISABLE 0 156 #define MENLO_MAINTENANCE_MODE_ENABLE 1 157 158 } menlo_set_cmd_t; 159 160 161 typedef struct menlo_loopback_cmd 162 { 163 uint32_t code; /* Command code = MENLO_CMD_LOOPBACK */ 164 uint32_t context; /* context = NSL port 0 or 1 */ 165 166 #define MENLO_NSL_PORT_ID_0 0 167 #define MENLO_NSL_PORT_ID_1 1 168 169 uint32_t type; /* type = loopback mode enable or disable */ 170 171 #define MENLO_LOOPBACK_DISABLE 0 172 #define MENLO_LOOPBACK_ENABLE 1 173 174 } menlo_loopback_cmd_t; 175 176 177 typedef struct menlo_reset_cmd 178 { 179 uint32_t code; /* Command code = MENLO_CMD_RESET */ 180 uint32_t firmware; 181 182 #define MENLO_FW_OPERATIONAL 0 183 #define MENLO_FW_GOLDEN 1 184 185 } menlo_reset_cmd_t; 186 187 typedef struct menlo_fru_data_cmd 188 { 189 uint32_t code; /* Response code */ 190 uint8_t mac0[8]; /* MAC address of port 0 */ 191 uint8_t mac1[8]; /* MAC address of port 1 */ 192 uint32_t flags; 193 194 /* Valid flags */ 195 #define MENLO_FLAG_SINGLE_CHANNEL 0x00000001 196 #define MENLO_FLAG_DUAL_CHANNEL 0x00000002 197 198 } menlo_fru_data_cmd_t; 199 200 201 typedef struct menlo_diag_cmd 202 { 203 uint32_t code; /* Response code */ 204 uint32_t loop_count; /* loop_count = 0 indicates loop forever */ 205 /* loop_count > 0 indicates number of test */ 206 /* iterations */ 207 /* NOTE : one test iteration takes */ 208 /* approximately 2-3 seconds */ 209 uint32_t test_bitmap; /* Each bit represents a separate test to be */ 210 /* performed */ 211 /* test_bitmap = 0 will result in a */ 212 /* MENLO_ERR_INVALID_FLAG error */ 213 } menlo_diag_cmd_t; 214 215 216 /* Hornet 2 */ 217 218 #define MAX_SUPPORTED_VLANS 4 219 220 typedef struct fip_params 221 { 222 uint8_t sw_name[8]; /* Switch name */ 223 uint8_t fabric_name[8]; /* Fabric name */ 224 uint8_t sup_addr_mode; /* Support addressing modes */ 225 226 /* FCoE Addressing Mode */ 227 #define SPMA_ADDR_MODE 1 228 #define FPMA_ADDR_MODE 2 229 230 uint8_t pref_addr_mode; /* Preferred addressing modes */ 231 uint16_t fcf_disc_tov; /* Discovery tmo period (multiple 500ms) */ 232 uint16_t vlan_id[MAX_SUPPORTED_VLANS]; /* VLAN list */ 233 234 } fip_params_t; 235 236 typedef struct non_fip_params 237 { 238 uint32_t fc_map; /* Configured FC_MAP */ 239 240 } non_fip_params_t; 241 242 typedef union menlo_fcoe_params 243 { 244 fip_params_t fip; /* FIP specific parameters */ 245 non_fip_params_t non_fip; /* Non-FIP specific parameters */ 246 } menlo_fcoe_params_t; 247 248 typedef struct menlo_set_fcoe_params_cmd 249 { 250 uint32_t code; /* Command code=MENLO_CMD_SET_FCOE_PARAMS */ 251 uint32_t fcoe_mode; /* FIP or Non-FIP */ 252 253 /* FCoE Operation Mode */ 254 #define FCOE_MODE_NON_FIP 0 255 #define FCOE_MODE_FIP 1 256 257 uint32_t lport_id; /* Logical port identification */ 258 menlo_fcoe_params_t params; /* Specific FCoE parameters */ 259 260 } menlo_set_fcoe_params_cmd_t; 261 262 263 typedef struct set_facl_cmd 264 { 265 uint32_t code; /* Command code = MENLO_CMD_SET_FACL */ 266 uint32_t lport_id; /* Logical port identification */ 267 uint32_t num_acls; /* Number of ACL entries */ 268 uint32_t facl_list; /* List of returned Fabric ACL, facl_t */ 269 } set_facl_cmd_t; 270 271 typedef struct facl 272 { 273 uint8_t fabric_name[8]; /* Fabric name */ 274 uint8_t sw_name[8]; /* Switch name */ 275 uint32_t acc_ctrl; /* PERMIT or DENY */ 276 } facl_t; 277 278 typedef struct fcf_id 279 { 280 uint8_t sw_name[8]; /* Switch name */ 281 uint8_t fabric_name[8]; /* Fabric name */ 282 283 } fcf_id_t; 284 285 typedef struct create_vl_cmd 286 { 287 uint32_t code; /* Command code = MENLO_CMD_CREATE_VL */ 288 uint32_t lport_id; /* Logical port identification */ 289 fcf_id_t fcf; /* Specific FCF */ 290 291 } create_vl_cmd_t; 292 293 typedef struct delete_vl_cmd 294 { 295 uint32_t code; /* Command code = MENLO_CMD_CREATE_VL */ 296 uint32_t vl_handle; /* Handle of created VL */ 297 298 } delete_vl_cmd_t; 299 300 #define MAX_GROUPS 8 /* Max supported by hardware */ 301 302 typedef struct menlo_pg_info 303 { 304 uint32_t num_pg; /* Number of PGs specified */ 305 uint8_t pg_ids[MAX_GROUPS]; /* PG membership bitmaps */ 306 uint8_t pg_bw[MAX_GROUPS]; /* BW for each PG in 10% gran. */ 307 308 } menlo_pg_info_t; 309 310 typedef struct menlo_set_pg_info_cmd 311 { 312 uint32_t code; /* Command code = MENLO_CMD_SET_PG */ 313 menlo_pg_info_t pg_info; /* PG information */ 314 315 } menlo_set_pg_info_cmd_t; 316 317 318 typedef struct menlo_set_host_eth_pfc_flag 319 { 320 uint32_t code; /* Command code=MENLO_CMD_SET_HOST_ETH_PFC_FLAG */ 321 uint32_t host_pfc_enable; /* 1 = PFC on Host if enabled */ 322 323 /* Host PFC Flag Definitions */ 324 #define MENLO_HOST_PFC_DISABLE 0x0 325 #define MENLO_HOST_PFC_ENABLE 0x1 326 327 } menlo_set_host_eth_pfc_flag_t; 328 329 330 331 typedef union menlo_cmd 332 { 333 uint32_t word[5]; 334 uint32_t code; /* Command code */ 335 336 /* Command codes */ 337 #define MENLO_CMD_INITIALIZE 0x00000001 338 #define MENLO_CMD_FW_DOWNLOAD 0x00000002 339 #define MENLO_CMD_READ_MEMORY 0x00000003 340 #define MENLO_CMD_WRITE_MEMORY 0x00000004 341 #define MENLO_CMD_FTE_INSERT 0x00000005 342 #define MENLO_CMD_FTE_DELETE 0x00000006 343 344 #define MENLO_CMD_GET_INIT 0x00000007 345 #define MENLO_CMD_GET_CONFIG 0x00000008 346 #define MENLO_CMD_GET_PORT_STATS 0x00000009 347 #define MENLO_CMD_GET_LIF_STATS 0x0000000A 348 #define MENLO_CMD_GET_ASIC_STATS 0x0000000B 349 #define MENLO_CMD_GET_LOG_CONFIG 0x0000000C 350 #define MENLO_CMD_GET_LOG_DATA 0x0000000D 351 #define MENLO_CMD_GET_PANIC_LOG 0x0000000E 352 #define MENLO_CMD_GET_LB_MODE 0x0000000F 353 354 #define MENLO_CMD_SET_PAUSE 0x00000010 355 #define MENLO_CMD_SET_FCOE_COS 0x00000011 356 #define MENLO_CMD_SET_UIF_PORT_TYPE 0x00000012 357 358 #define MENLO_CMD_DIAGNOSTICS 0x00000013 359 #define MENLO_CMD_LOOPBACK 0x00000014 360 #define MENLO_CMD_GET_FTABLE 0x00000015 361 #define MENLO_CMD_GET_SFP_DATA 0x00000016 362 #define MENLO_CMD_SET_FRU_DATA 0x00000017 363 #define MENLO_CMD_GET_FRU_DATA 0x00000018 364 #define MENLO_CMD_SET_FCOE_FORMAT 0x00000019 365 #define MENLO_CMD_GET_DIAG_LOG 0x00000020 366 #define MENLO_CMD_PANIC 0x00000021 367 #define MENLO_CMD_SET_FCOE_PARAMS 0x00000022 368 #define MENLO_CMD_GET_FCOE_PARAMS 0x00000023 369 #define MENLO_CMD_GET_FCF_LIST 0x00000024 370 #define MENLO_CMD_SET_FACL 0x00000025 371 #define MENLO_CMD_GET_FACL 0x00000026 372 #define MENLO_CMD_CREATE_VL 0x00000027 373 #define MENLO_CMD_DELETE_VL 0x00000028 374 #define MENLO_CMD_SET_PG 0x00000029 375 #define MENLO_CMD_GET_PG 0x0000002A 376 #define MENLO_CMD_SET_HOST_ETH_PFC_FLAG 0x0000002B 377 #define MENLO_CMD_GET_HOST_ETH_PFC_FLAG 0x0000002C 378 #define MENLO_CMD_GET_DCBX_MODE 0x0000002D 379 380 381 /* Zephyr specific Menlo commands */ 382 #define MENLO_CMD_RESET 0x80000001 383 #define MENLO_CMD_SET_MODE 0x80000002 384 385 menlo_init_cmd_t init; 386 menlo_fw_download_cmd_t fw; 387 menlo_memory_cmd_t mem; 388 menlo_fte_insert_cmd_t fte_insert; 389 menlo_fte_delete_cmd_t fte_delete; 390 menlo_get_cmd_t get; 391 menlo_set_cmd_t set; 392 menlo_loopback_cmd_t lb; 393 menlo_reset_cmd_t reset; 394 menlo_fru_data_cmd_t fru; 395 menlo_diag_cmd_t diag; 396 menlo_set_host_eth_pfc_flag_t pfc; 397 } menlo_cmd_t; 398 399 400 /* 401 * RESPONSES 402 */ 403 404 typedef struct menlo_init_rsp 405 { 406 uint32_t code; 407 uint32_t bb_credit; /* Menlo FC BB Credit */ 408 uint32_t frame_size; /* Menlo FC receive frame size */ 409 uint32_t fw_version; /* Menlo firmware version */ 410 uint32_t reset_status; /* Reason for previous reset */ 411 412 #define MENLO_RESET_STATUS_NORMAL 0 413 #define MENLO_RESET_STATUS_PANIC 1 414 415 uint32_t maint_status; /* Menlo Maintenance Mode status at link up */ 416 417 #define MENLO_MAINTENANCE_MODE_DISABLE 0 418 #define MENLO_MAINTENANCE_MODE_ENABLE 1 419 420 uint32_t fw_type; 421 422 #define MENLO_FW_TYPE_OPERATIONAL 0xABCD0001 423 #define MENLO_FW_TYPE_GOLDEN 0xABCD0002 424 #define MENLO_FW_TYPE_DIAG 0xABCD0003 425 426 uint32_t fru_data_valid; /* 0=invalid, 1=valid */ 427 } menlo_init_rsp_t; 428 429 430 #define MENLO_MAX_FC_PORTS 2 431 #define MENLO_MAX_UIF_PORTS 2 432 433 typedef struct menlo_get_config_rsp 434 { 435 uint32_t code; 436 437 uint32_t pause_type[MENLO_MAX_UIF_PORTS]; 438 uint32_t priority[MENLO_MAX_UIF_PORTS]; 439 uint32_t fcoe_cos[MENLO_MAX_FC_PORTS]; 440 uint32_t uif_port_type[MENLO_MAX_UIF_PORTS]; 441 442 uint32_t log_cfg_size; /* Size of log config region. */ 443 /* Needed for */ 444 /* MENLO_CMD_GET_LOG_CONFIG */ 445 uint32_t panic_log_size; /* Size of panic log region. */ 446 /* Needed for MENLO_CMD_GET_PANIC_LOG */ 447 448 uint32_t dcx_present[MENLO_MAX_UIF_PORTS]; 449 450 uint32_t current_pause_type[MENLO_MAX_UIF_PORTS]; 451 uint32_t current_priority[MENLO_MAX_UIF_PORTS]; 452 uint32_t current_fcoe_cos[MENLO_MAX_FC_PORTS]; 453 uint32_t current_uif_port_type[MENLO_MAX_UIF_PORTS]; 454 455 uint32_t fcoe_format; /* Bit field - single bit will be set */ 456 /* (See below) */ 457 uint32_t current_fcoe_format; /* Bit field - single bit will be set */ 458 /* (See below) */ 459 uint32_t supported_fcoe_format; /* Bit field - multiple bits may be */ 460 /* set (See below) */ 461 462 #define FCOE_FRAME_FORMAT_P0 0x00010000 /* Pre-T11 format */ 463 #define FCOE_FRAME_FORMAT_T0 0x00000001 /* T11 format Rev 0 */ 464 #define FCOE_FRAME_FORMAT_T1 0x00000002 465 #define FCOE_FRAME_FORMAT_T2 0x00000004 466 #define FCOE_FRAME_FORMAT_T3 0x00000008 467 #define FCOE_FRAME_FORMAT_T4 0x00000010 468 #define FCOE_FRAME_FORMAT_T5 0x00000020 469 #define FCOE_FRAME_FORMAT_T6 0x00000040 470 #define FCOE_FRAME_FORMAT_T7 0x00000080 471 #define FCOE_FRAME_FORMAT_T8 0x00000100 472 #define FCOE_FRAME_FORMAT_T9 0x00000200 473 #define FCOE_FRAME_FORMAT_T10 0x00000400 474 #define FCOE_FRAME_FORMAT_T11 0x00000800 475 #define FCOE_FRAME_FORMAT_T12 0x00001000 476 #define FCOE_FRAME_FORMAT_T13 0x00002000 477 #define FCOE_FRAME_FORMAT_T14 0x00004000 478 #define FCOE_FRAME_FORMAT_T15 0x00008000 479 } menlo_get_config_rsp_t; 480 481 482 typedef struct menlo_fc_stats_rsp 483 { 484 uint32_t code; 485 486 uint64_t rx_class_2_frames; 487 uint64_t rx_class_3_frames; 488 uint64_t rx_class_F_frames; 489 uint64_t rx_class_other_frames; 490 491 uint64_t tx_class_2_frames; 492 uint64_t tx_class_3_frames; 493 uint64_t tx_class_F_frames; 494 uint64_t tx_class_other_frames; 495 496 uint64_t rx_class_2_words; 497 uint64_t rx_class_3_words; 498 uint64_t rx_class_F_words; 499 uint64_t rx_class_other_words; 500 501 uint64_t tx_class_2_words; 502 uint64_t tx_class_3_words; 503 uint64_t tx_class_F_words; 504 uint64_t tx_class_other_words; 505 506 uint64_t rx_class_2_frames_bad; 507 uint64_t rx_class_3_frames_bad; 508 uint64_t rx_class_F_frames_bad; 509 uint64_t rx_class_other_frames_bad; 510 511 uint64_t tx_class_2_frames_bad; 512 uint64_t tx_class_3_frames_bad; 513 uint64_t tx_class_F_frames_bad; 514 uint64_t tx_class_other_frames_bad; 515 } menlo_fc_stats_rsp_t; 516 517 518 typedef struct menlo_network_stats_rsp 519 { 520 uint32_t code; 521 522 uint64_t tx_pkt_lt64; 523 uint64_t tx_pkt_64; 524 uint64_t tx_pkt_65; 525 uint64_t tx_pkt_128; 526 uint64_t tx_pkt_256; 527 uint64_t tx_pkt_512; 528 uint64_t tx_pkt_1024; 529 uint64_t tx_pkt_1519; 530 uint64_t tx_pkt_2048; 531 uint64_t tx_pkt_4096; 532 uint64_t tx_pkt_8192; 533 uint64_t tx_pkt_gt9216; 534 uint64_t tx_pkt_total; 535 uint64_t tx_octet_sok; 536 uint64_t tx_pkt_ok; 537 uint64_t tx_ucast; 538 uint64_t tx_mcast; 539 uint64_t tx_bcast; 540 uint64_t tx_vlan; 541 uint64_t tx_pause; 542 uint64_t tx_priority_pause; 543 uint64_t tx_frame_error; 544 545 uint64_t rx_pkt_lt64; 546 uint64_t rx_pkt_64; 547 uint64_t rx_pkt_65; 548 uint64_t rx_pkt_128; 549 uint64_t rx_pkt_256; 550 uint64_t rx_pkt_512; 551 uint64_t rx_pkt_1024; 552 uint64_t rx_pkt_1519; 553 uint64_t rx_pkt_2048; 554 uint64_t rx_pkt_4096; 555 uint64_t rx_pkt_8192; 556 uint64_t rx_pkt_gt9216; 557 uint64_t rx_pkt_total; 558 uint64_t rx_octet_sok; 559 uint64_t rx_pkt_ok; 560 uint64_t rx_ucast; 561 uint64_t rx_mcast; 562 uint64_t rx_bcast; 563 uint64_t rx_vlan; 564 uint64_t rx_oversize; 565 uint64_t rx_toolong; 566 uint64_t rx_discard; 567 uint64_t rx_undersize; 568 uint64_t rx_fragment; 569 uint64_t rx_crc_err; 570 uint64_t rx_inrange_err; 571 uint64_t rx_jabber; 572 uint64_t rx_pause; 573 uint64_t rx_priority_pause; 574 } menlo_network_stats_rsp_t; 575 576 577 typedef struct menlo_lif_stats_rsp 578 { 579 uint32_t code; 580 581 uint64_t eg_pkt_count; 582 uint64_t ig_pkt_count; 583 584 uint64_t eg_byte_count; 585 uint64_t ig_byte_count; 586 587 uint64_t eg_error_count; 588 uint64_t ig_error_count; 589 590 uint64_t eg_drop_count; 591 uint64_t ig_drop_count; 592 } menlo_lif_stats_rsp_t; 593 594 595 typedef struct menlo_asic_stats_rsp 596 { 597 uint32_t code; 598 599 uint64_t eq_cputx0_cecount; 600 uint64_t eq_cputx0_dropacl; 601 uint64_t eq_cputx0_dropovr; 602 uint64_t eq_cputx0_droprunt; 603 uint64_t eq_cputx0_poperr; 604 uint64_t eq_cputx0_pusherr; 605 uint64_t eq_cputx0_truncovr; 606 uint64_t eq_cputx0_uecount; 607 608 uint64_t eq_cputx1_cecount; 609 uint64_t eq_cputx1_dropacl; 610 uint64_t eq_cputx1_dropovr; 611 uint64_t eq_cputx1_droprunt; 612 uint64_t eq_cputx1_poperr; 613 uint64_t eq_cputx1_pusherr; 614 uint64_t eq_cputx1_truncovr; 615 uint64_t eq_cputx1_uecount; 616 617 uint64_t eq_eth0_dropovr; 618 uint64_t eq_eth0_droprunt; 619 uint64_t eq_eth0_truncovr; 620 621 uint64_t eq_eth0a_cecount; 622 uint64_t eq_eth0a_dropacl; 623 uint64_t eq_eth0a_poperr; 624 uint64_t eq_eth0a_pusherr; 625 uint64_t eq_eth0a_uecount; 626 627 uint64_t eq_eth0b_cecount; 628 uint64_t eq_eth0b_dropacl; 629 uint64_t eq_eth0b_poperr; 630 uint64_t eq_eth0b_pusherr; 631 uint64_t eq_eth0b_uecount; 632 633 uint64_t eq_eth1_dropovr; 634 uint64_t eq_eth1_droprunt; 635 uint64_t eq_eth1_truncovr; 636 637 uint64_t eq_eth1a_cecount; 638 uint64_t eq_eth1a_dropacl; 639 uint64_t eq_eth1a_poperr; 640 uint64_t eq_eth1a_pusherr; 641 uint64_t eq_eth1a_uecount; 642 643 uint64_t eq_eth1b_cecount; 644 uint64_t eq_eth1b_dropacl; 645 uint64_t eq_eth1b_poperr; 646 uint64_t eq_eth1b_pusherr; 647 uint64_t eq_eth1b_uecount; 648 649 uint64_t eq_fc0_cecount; 650 uint64_t eq_fc0_dropacl; 651 uint64_t eq_fc0_dropovr; 652 uint64_t eq_fc0_droprunt; 653 uint64_t eq_fc0_poperr; 654 uint64_t eq_fc0_pusherr; 655 uint64_t eq_fc0_truncovr; 656 uint64_t eq_fc0_uecount; 657 658 uint64_t eq_fc1_cecount; 659 uint64_t eq_fc1_dropacl; 660 uint64_t eq_fc1_dropovr; 661 uint64_t eq_fc1_droprunt; 662 uint64_t eq_fc1_poperr; 663 uint64_t eq_fc1_pusherr; 664 uint64_t eq_fc1_truncovr; 665 uint64_t eq_fc1_uecount; 666 667 uint64_t eq_fl_cecount; 668 uint64_t eq_fl_uecount; 669 670 uint64_t eq_pkt_buf_cecount; 671 uint64_t eq_pkt_buf_uecount; 672 673 uint64_t iq_cpurx0_cecount; 674 uint64_t iq_cpurx0_n0_dropovr; 675 uint64_t iq_cpurx0_n0_truncovr; 676 uint64_t iq_cpurx0_n1_dropovr; 677 uint64_t iq_cpurx0_n1_truncovr; 678 uint64_t iq_cpurx0_poperr; 679 uint64_t iq_cpurx0_pusherr; 680 uint64_t iq_cpurx0_uecount; 681 682 uint64_t iq_cpurx1_cecount; 683 uint64_t iq_cpurx1_n0_dropovr; 684 uint64_t iq_cpurx1_n0_truncovr; 685 uint64_t iq_cpurx1_n1_dropovr; 686 uint64_t iq_cpurx1_n1_truncovr; 687 uint64_t iq_cpurx1_poperr; 688 uint64_t iq_cpurx1_pusherr; 689 uint64_t iq_cpurx1_uecount; 690 691 uint64_t iq_cputx_cecount; 692 uint64_t iq_cputx_dropovr; 693 uint64_t iq_cputx_droprunt; 694 uint64_t iq_cputx_poperr; 695 uint64_t iq_cputx_pusherr; 696 uint64_t iq_cputx_truncovr; 697 uint64_t iq_cputx_uecount; 698 699 uint64_t iq_eth0a_cecount; 700 uint64_t iq_eth0a_n0_dropovr; 701 uint64_t iq_eth0a_n0_truncovr; 702 uint64_t iq_eth0a_n1_dropovr; 703 uint64_t iq_eth0a_n1_truncovr; 704 uint64_t iq_eth0a_poperr; 705 uint64_t iq_eth0a_pusherr; 706 uint64_t iq_eth0a_uecount; 707 708 uint64_t iq_eth0b_cecount; 709 uint64_t iq_eth0b_n0_dropovr; 710 uint64_t iq_eth0b_n0_truncovr; 711 uint64_t iq_eth0b_n1_dropovr; 712 uint64_t iq_eth0b_n1_truncovr; 713 uint64_t iq_eth0b_poperr; 714 uint64_t iq_eth0b_pusherr; 715 uint64_t iq_eth0b_uecount; 716 717 uint64_t iq_eth1a_cecount; 718 uint64_t iq_eth1a_n0_dropovr; 719 uint64_t iq_eth1a_n0_truncovr; 720 uint64_t iq_eth1a_n1_dropovr; 721 uint64_t iq_eth1a_n1_truncovr; 722 uint64_t iq_eth1a_poperr; 723 uint64_t iq_eth1a_pusherr; 724 uint64_t iq_eth1a_uecount; 725 726 uint64_t iq_eth1b_cecount; 727 uint64_t iq_eth1b_n0_dropovr; 728 uint64_t iq_eth1b_n0_truncovr; 729 uint64_t iq_eth1b_n1_dropovr; 730 uint64_t iq_eth1b_n1_truncovr; 731 uint64_t iq_eth1b_poperr; 732 uint64_t iq_eth1b_pusherr; 733 uint64_t iq_eth1b_uecount; 734 735 uint64_t iq_fc0_cecount; 736 uint64_t iq_fc0_n0_dropovr; 737 uint64_t iq_fc0_n0_truncovr; 738 uint64_t iq_fc0_n1_dropovr; 739 uint64_t iq_fc0_n1_truncovr; 740 uint64_t iq_fc0_poperr; 741 uint64_t iq_fc0_pusherr; 742 uint64_t iq_fc0_uecount; 743 744 uint64_t iq_fc1_cecount; 745 uint64_t iq_fc1_n0_dropovr; 746 uint64_t iq_fc1_n0_truncovr; 747 uint64_t iq_fc1_n1_dropovr; 748 uint64_t iq_fc1_n1_truncovr; 749 uint64_t iq_fc1_poperr; 750 uint64_t iq_fc1_pusherr; 751 uint64_t iq_fc1_uecount; 752 753 uint64_t iq_fl_cecount; 754 uint64_t iq_fl_uecount; 755 756 uint64_t iq_n0_cecount; 757 uint64_t iq_n0_dropacl; 758 uint64_t iq_n0_dropovr; 759 uint64_t iq_n0_droprunt; 760 uint64_t iq_n0_poperr; 761 uint64_t iq_n0_pusherr; 762 uint64_t iq_n0_truncovr; 763 uint64_t iq_n0_uecount; 764 765 uint64_t iq_n1_cecount; 766 uint64_t iq_n1_dropacl; 767 uint64_t iq_n1_dropovr; 768 uint64_t iq_n1_droprunt; 769 uint64_t iq_n1_poperr; 770 uint64_t iq_n1_pusherr; 771 uint64_t iq_n1_truncovr; 772 uint64_t iq_n1_uecount; 773 774 uint64_t iq_pkt_buf_cecount; 775 uint64_t iq_pkt_buf_uecount; 776 777 uint64_t iq_rc_cecount; 778 uint64_t iq_rc_uecount; 779 780 uint64_t misc_mmem_cecount; 781 uint64_t misc_mmem_uecount; 782 783 uint64_t net_eg0_learn_req_drop; 784 uint64_t net_eg0_pkt_drop_cmd; 785 uint64_t net_eg0_pkt_drop_lifcfg_invalid; 786 uint64_t net_eg0_pkt_drop_lifmap_no_hit; 787 uint64_t net_eg0_pkt_drop_src_bind; 788 789 uint64_t net_eg1_learn_req_drop; 790 uint64_t net_eg1_pkt_drop_cmd; 791 uint64_t net_eg1_pkt_drop_lifcfg_invalid; 792 uint64_t net_eg1_pkt_drop_lifmap_no_hit; 793 uint64_t net_eg1_pkt_drop_src_bind; 794 795 uint64_t net_ig0_fwd_lookup_no_hit; 796 uint64_t net_ig0_pkt_drop_fc_multicast; 797 uint64_t net_ig0_pkt_drop_invalid_fc_lif; 798 uint64_t net_ig0_pkt_null_pif; 799 800 uint64_t net_ig1_fwd_lookup_no_hit; 801 uint64_t net_ig1_pkt_drop_fc_multicast; 802 uint64_t net_ig1_pkt_drop_invalid_fc_lif; 803 uint64_t net_ig1_pkt_null_pif; 804 805 uint64_t host10gbe_port0_rx_pause_cfc; 806 uint64_t host10gbe_port0_rx_pause_pfc; 807 uint64_t host10gbe_port0_tx_pause_cfc; 808 uint64_t host10gbe_port0_tx_pause_pfc; 809 810 uint64_t host10gbe_port1_rx_pause_cfc; 811 uint64_t host10gbe_port1_rx_pause_pfc; 812 uint64_t host10gbe_port1_tx_pause_cfc; 813 uint64_t host10gbe_port1_tx_pause_pfc; 814 815 uint64_t dce_port0_rx_pause_cfc; 816 uint64_t dce_port0_rx_pause_pfc; 817 uint64_t dce_port0_tx_pause_cfc; 818 uint64_t dce_port0_tx_pause_pfc; 819 820 uint64_t dce_port1_rx_pause_cfc; 821 uint64_t dce_port1_rx_pause_pfc; 822 uint64_t dce_port1_tx_pause_cfc; 823 uint64_t dce_port1_tx_pause_pfc; 824 } menlo_asic_stats_rsp_t; 825 826 827 #define MENLO_LOG_NAME_SIZE 20 828 829 typedef struct menlo_log 830 { 831 #ifdef EMLXS_BIG_ENDIAN 832 uint16_t num_entries; 833 uint16_t id; 834 835 uint16_t rsvd; 836 uint16_t entry_size; 837 #endif /* EMLXS_BIG_ENDIAN */ 838 839 #ifdef EMLXS_LITTLE_ENDIAN 840 uint16_t id; 841 uint16_t num_entries; 842 843 uint16_t entry_size; 844 uint16_t rsvd; 845 #endif /* EMLXS_LITTLE_ENDIAN */ 846 847 char name[MENLO_LOG_NAME_SIZE]; 848 } menlo_log_t; 849 850 851 typedef struct menlo_log_config_rsp 852 { 853 uint32_t code; 854 855 #ifdef EMLXS_BIG_ENDIAN 856 uint16_t rsvd; 857 uint16_t num_logs; /* Number of logs in log array */ 858 #endif /* EMLXS_BIG_ENDIAN */ 859 860 #ifdef EMLXS_LITTLE_ENDIAN 861 uint16_t num_logs; /* Number of logs in log array */ 862 uint16_t rsvd; 863 #endif /* EMLXS_LITTLE_ENDIAN */ 864 865 uint32_t data; /* First word of array: */ 866 /* menlo_log_t log[num_logs] */ 867 } menlo_log_config_rsp_t; 868 869 870 typedef struct menlo_log_data_rsp 871 { 872 uint32_t code; 873 874 #ifdef EMLXS_BIG_ENDIAN 875 uint16_t rsvd; 876 uint16_t head; /* Index of oldest log entry in circular */ 877 /* data array */ 878 #endif /* EMLXS_BIG_ENDIAN */ 879 880 #ifdef EMLXS_LITTLE_ENDIAN 881 uint16_t head; /* Index of oldest log entry in circular */ 882 /* data array */ 883 uint16_t rsvd; 884 #endif /* EMLXS_LITTLE_ENDIAN */ 885 886 uint32_t data; /* char array[num_entries][entry_size] */ 887 } menlo_log_data_rsp_t; 888 889 890 #define MENLO_NUM_GP_REGS 32 891 892 typedef struct menlo_panic_log_data_rsp 893 { 894 uint32_t code; 895 uint32_t rsvd_flag; /* N/A to mgmt utility */ 896 uint32_t type; /* Panic type (See beleow) */ 897 898 #define MENLO_PANIC_TYPE_SOLICITED 0xdead0001 899 #define MENLO_PANIC_TYPE_EXCEPTION 0xdead0002 900 901 uint32_t regs_epc; 902 uint32_t regs_cp0_cause; 903 uint32_t regs_cp0_status; 904 uint32_t regs_gp[MENLO_NUM_GP_REGS]; 905 906 #ifdef EMLXS_BIG_ENDIAN 907 uint16_t num_entries; /* Number of entries in data array */ 908 uint16_t log_present; /* Number of entries in data array */ 909 910 uint16_t head; /* Index of oldest log entry in circular */ 911 /* data buffer */ 912 uint16_t entry_size; /* Size of each entry */ 913 #endif /* EMLXS_BIG_ENDIAN */ 914 915 #ifdef EMLXS_LITTLE_ENDIAN 916 uint16_t log_present; /* Number of entries in data array */ 917 uint16_t num_entries; /* Number of entries in data array */ 918 919 uint16_t entry_size; /* Size of each entry */ 920 uint16_t head; /* Index of oldest log entry in circular */ 921 /* data buffer */ 922 #endif /* EMLXS_LITTLE_ENDIAN */ 923 924 uint32_t data; /* char array[num_entries][entry_size] */ 925 } menlo_panic_log_data_rsp_t; 926 927 928 typedef struct menlo_lb_mode_rsp 929 { 930 uint32_t code; 931 uint32_t mode; /* Menlo loopback mode */ 932 } menlo_lb_mode_rsp_t; 933 934 935 #define MENLO_MAX_FTABLE_ENTRIES 256 936 937 typedef struct menlo_fte 938 { 939 #ifdef EMLXS_BIG_ENDIAN 940 uint8_t type_mask; 941 uint8_t type; 942 uint16_t flags; 943 944 uint16_t tag_mask; 945 uint16_t tag; /* Ehternet VLAN tag */ 946 #endif /* EMLXS_BIG_ENDIAN */ 947 948 #ifdef EMLXS_LITTLE_ENDIAN 949 uint16_t flags; 950 uint8_t type; 951 uint8_t type_mask; 952 953 uint16_t tag; /* Ehternet VLAN tag */ 954 uint16_t tag_mask; 955 #endif /* EMLXS_LITTLE_ENDIAN */ 956 957 #define MENLO_FTABLE_ENTRY_VALID 0x8000 /* flags field */ 958 959 uint8_t mac_addr[8]; /* mac addr */ 960 uint8_t mac_addr_mask[8]; /* mac addr mask */ 961 uint8_t fc_wwpn[8]; /* wwpn */ 962 963 uint32_t lif_bitmap; /* forwarding vector */ 964 uint32_t rsvd; 965 } menlo_fte_t; 966 967 typedef struct menlo_ftable_rsp 968 { 969 uint32_t code; /* Response code */ 970 971 menlo_fte_t entry[MENLO_MAX_FTABLE_ENTRIES]; 972 } menlo_ftable_rsp_t; 973 974 975 #define MENLO_SFP_PAGE_SIZE 256 976 977 typedef struct menlo_sfp_rsp 978 { 979 uint32_t code; /* Response code */ 980 uint8_t page_a0[MENLO_SFP_PAGE_SIZE]; 981 uint8_t page_a2[MENLO_SFP_PAGE_SIZE]; 982 } menlo_sfp_rsp_t; 983 984 985 typedef struct menlo_fru_data_rsp 986 { 987 uint32_t code; /* Response code */ 988 uint8_t mac0[8]; /* MAC address of port 0 */ 989 uint8_t mac1[8]; /* MAC address of port 1 */ 990 uint32_t flags; 991 } menlo_fru_data_rsp_t; 992 993 994 typedef struct menlo_diag_log_data_rsp 995 { 996 uint32_t code; /* Response code */ 997 uint32_t data_length; /* Length of the diagnostic log */ 998 /* buffer (bytes) */ 999 uint32_t data; /* menlo_diag_log_t log of size */ 1000 /* data_length bytes */ 1001 } menlo_diag_log_data_rsp_t; 1002 1003 1004 typedef struct menlo_diag_log 1005 { 1006 uint32_t num_tests; /* Number of entries in data array */ 1007 uint32_t status_length; /* Size (words) of the */ 1008 /* menlo_diag_log_entry_t.data array */ 1009 uint32_t requested_loop_cnt; /* Number of test iterations */ 1010 /* requested */ 1011 uint32_t completed_loop_cnt; /* Number of test iterations actually */ 1012 /* completed */ 1013 uint32_t test_summary; /* Overal test status */ 1014 1015 #define DIAG_TEST_STATUS_SUCCESS 0xD0000001 1016 #define DIAG_TEST_STATUS_FAIL 0xD0000002 1017 #define DIAG_TEST_STATUS_ABORT 0xD0000003 1018 1019 uint32_t data; /* menlo_diag_log_entry_t */ 1020 /* entry[num_tests] */ 1021 } menlo_diag_log_t; 1022 1023 typedef struct menlo_diag_log_entry 1024 { 1025 uint32_t status; /* Test status See */ 1026 /* DIAG_TEST_STATUS_XXXXX above */ 1027 uint32_t data; /* uint32_t array[status_length] */ 1028 } menlo_diag_log_entry_t; 1029 1030 1031 /* Hornet 2 */ 1032 1033 typedef struct menlo_get_fcoe_params_rsp 1034 { 1035 uint32_t code; /* Response code */ 1036 1037 uint32_t fcoe_mode; /* FIP or Non-FIP */ 1038 1039 /* FCoE Operation Mode */ 1040 #define FCOE_MODE_NON_FIP 0 1041 #define FCOE_MODE_FIP 1 1042 1043 menlo_fcoe_params_t params; /* Specific FCoE parameters */ 1044 1045 } menlo_get_fcoe_params_rsp_t; 1046 1047 typedef struct fcf_info 1048 { 1049 uint32_t handle; /* Handle of the subject FCF */ 1050 uint8_t mac[6]; /* FCF MAC */ 1051 uint16_t vlan_id; /* vlan_id */ 1052 uint8_t sw_name[8]; /* Switch name */ 1053 uint8_t fabric_name[8]; /* Fabric name */ 1054 uint32_t fc_map; /* FC map (not applicable for SPMA) */ 1055 uint32_t lka_period; /* Periodic LKA */ 1056 1057 uint16_t state; /* FCF state */ 1058 1059 /* FCF State Definitions */ 1060 #define FCF_CREATE_STATE 1 /* FCF is discovered but path not qualified */ 1061 #define FCF_READY_STATE 2 /* FCF is ready for LOGI */ 1062 #define FCF_AVAILABLE_STATE 4 /* FCF is available for FLOGI & FDISC */ 1063 #define FCF_OFFLINE 0x8000 /* Error or Set Offline */ 1064 1065 uint16_t ctrl_flags; /* FIP header flags */ 1066 uint16_t sup_addr_mode; /* FCoE addressing mode capability */ 1067 1068 /* FCoE Addressing Mode */ 1069 #define SPMA_ADDR_MODE 1 1070 #define FPMA_ADDR_MODE 2 1071 1072 uint16_t priority; /* Priority of FCF */ 1073 1074 } fcf_info_t; 1075 1076 typedef struct menlo_get_fcf_list_rsp 1077 { 1078 uint32_t code; /* Response code */ 1079 1080 uint32_t returned_fcfs; /* Number of returned FCFs */ 1081 uint32_t total_fcfs; /* Total number of discovered FCFs */ 1082 uint32_t active_fcfs; /* Number of active FCFs */ 1083 uint32_t fcf_list; /* List of returned FCFs' information, fcf_info_t */ 1084 1085 } menlo_get_fcf_list_rsp_t; 1086 1087 typedef struct menlo_get_facl_rsp 1088 { 1089 uint32_t code; /* Response code */ 1090 1091 uint32_t returned_facls; /* Number of returned ACLs */ 1092 uint32_t total_facls; /* Total number of configured ACLs */ 1093 uint32_t facl_list; /* List of returned ACL entry, facl_t */ 1094 1095 } menlo_get_facl_rsp_t; 1096 1097 typedef struct create_vl_rsp 1098 { 1099 uint32_t code; /* Response code */ 1100 1101 uint32_t vl_handle; /* Handle of created VL */ 1102 } create_vl_rsp_t; 1103 1104 typedef struct menlo_get_pg_info_rsp 1105 { 1106 uint32_t code; /* Response code */ 1107 1108 uint32_t max_supported_pg; /* Max PG supported by hardware */ 1109 uint32_t dcbx_feature_syncd; /* indicate DCBX feature syncd with peer */ 1110 menlo_pg_info_t curr_pg_info; /* Current PG settings */ 1111 menlo_pg_info_t def_pg_info; /* Default PG settings */ 1112 uint32_t max_bg_bw[MAX_GROUPS]; /* Max bandwidth allowed per group */ 1113 1114 } menlo_get_pg_info_rsp_t; 1115 1116 typedef struct menlo_get_host_eth_pfc_flag_rsp 1117 { 1118 uint32_t code; /* Response code */ 1119 1120 uint32_t host_pfc_enable; /* 1 = PFC on Host i/f enabled */ 1121 1122 /* Host PFC Flag Definitions */ 1123 #define MENLO_HOST_PFC_DISABLE 0x0 1124 #define MENLO_HOST_PFC_ENABLE 0x1 1125 1126 } menlo_get_host_eth_pfc_flag_rsp_t; 1127 1128 typedef struct menlo_get_dcbx_mode_rsp 1129 { 1130 uint32_t code; /* Response code */ 1131 1132 uint32_t mode; /* Mode value. See below */ 1133 1134 #define MENLO_DCBX_MODE_PRE_CEE 0x80000000 1135 #define MENLO_DCBX_MODE_CEE_VER_01 0x00000001 1136 #define MENLO_DCBX_MODE_CEE_VER_02 0x00000002 1137 #define MENLO_DCBX_MODE_CEE_VER_03 0x00000003 1138 #define MENLO_DCBX_MODE_CEE_VER_04 0x00000004 1139 1140 } menlo_get_dcbx_mode_rsp_t; 1141 1142 1143 1144 typedef union menlo_rsp 1145 { 1146 uint32_t word[32]; 1147 uint32_t code; 1148 1149 /* Response codes */ 1150 #define MENLO_RSP_SUCCESS 0x00000000 1151 #define MENLO_ERR_FAILED 0x00000001 1152 #define MENLO_ERR_INVALID_CMD 0x00000002 1153 #define MENLO_ERR_INVALID_CREDIT 0x00000003 1154 #define MENLO_ERR_INVALID_SIZE 0x00000004 1155 #define MENLO_ERR_INVALID_ADDRESS 0x00000005 1156 #define MENLO_ERR_INVALID_CONTEXT 0x00000006 1157 #define MENLO_ERR_INVALID_LENGTH 0x00000007 1158 #define MENLO_ERR_INVALID_TYPE 0x00000008 1159 #define MENLO_ERR_INVALID_DATA 0x00000009 1160 #define MENLO_ERR_INVALID_VALUE1 0x0000000A 1161 #define MENLO_ERR_INVALID_VALUE2 0x0000000B 1162 #define MENLO_ERR_INVALID_MASK 0x0000000C 1163 #define MENLO_ERR_CHECKSUM 0x0000000D 1164 #define MENLO_ERR_UNKNOWN_FCID 0x0000000E 1165 #define MENLO_ERR_UNKNOWN_WWN 0x0000000F 1166 #define MENLO_ERR_BUSY 0x00000010 1167 #define MENLO_ERR_INVALID_FLAG 0x00000011 1168 #define MENLO_ERR_SFP_ABSENT 0x00000012 1169 1170 menlo_init_rsp_t init; 1171 menlo_get_config_rsp_t config; 1172 menlo_fc_stats_rsp_t fc_stats; 1173 menlo_network_stats_rsp_t net_stats; 1174 menlo_lif_stats_rsp_t lif_stats; 1175 menlo_log_config_rsp_t log_cfg; 1176 menlo_log_data_rsp_t log; 1177 menlo_panic_log_data_rsp_t panic_log; 1178 menlo_lb_mode_rsp_t lb_mode; 1179 menlo_asic_stats_rsp_t asic_stats; 1180 menlo_ftable_rsp_t ftable; 1181 menlo_sfp_rsp_t sfp; 1182 menlo_fru_data_rsp_t fru; 1183 menlo_diag_log_data_rsp_t diag_log; 1184 } menlo_rsp_t; 1185 1186 1187 /* 1188 * FIRMWARE IMAGE 1189 */ 1190 1191 typedef struct menlo_image_hdr 1192 { 1193 uint32_t rsvd1; 1194 uint32_t rsvd2; 1195 uint32_t version; 1196 uint32_t file_length; /* Length of entire file */ 1197 uint32_t image_length; /* length of the image without */ 1198 /* padding */ 1199 uint32_t rsvd3; 1200 uint32_t rsvd4; 1201 uint32_t checksum_offset; /* Byte offset to image checksum */ 1202 } menlo_image_hdr_t; 1203 1204 1205 /* The version header structure needs to be a multiple of 4 bytes */ 1206 typedef struct menlo_version_hdr 1207 { 1208 uint32_t padded; /* 1 = Image padded, 0 = Image not padded */ 1209 1210 uint32_t type; 1211 1212 /* Type */ 1213 #define MENLO_IMAGE_TYPE_FIRMWARE 1 1214 #define MENLO_IMAGE_TYPE_DIAGNOSTICS 2 1215 1216 uint32_t version; /* fw or diag version */ 1217 uint32_t checksum; /* 32bit XOR checksum -- needs to be at the end */ 1218 } menlo_version_hdr_t; 1219 1220 1221 #endif /* MENLO_SUPPORT */ 1222 1223 #ifdef __cplusplus 1224 } 1225 #endif 1226 1227 #endif /* _EMLXS_MENLO_H */ 1228