1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Emulex. All rights reserved. 24 * Use is subject to License terms. 25 */ 26 27 28 #ifndef _EMLXS_HW_H 29 #define _EMLXS_HW_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #ifdef NPIV_SUPPORT 36 /* Maximum virtual ports per HBA (includes physical port) */ 37 #define MAX_VPORTS 256 38 39 #define MAX_VPORTS_LIMITED 101 40 #else 41 /* Maximum virtual ports per HBA (includes physical port) */ 42 #define MAX_VPORTS 1 43 #define MAX_VPORTS_LIMITED 1 44 #endif /* NPIV_SUPPORT */ 45 46 47 /* Maximum transfer size per operation */ 48 #define FC_MAX_TRANSFER 0x40000 49 50 #define MAX_RINGS_AVAILABLE 4 /* # rings available */ 51 #define MAX_RINGS 4 /* Max # rings used */ 52 53 54 #define PCB_SIZE 128 55 #define MBOX_SIZE 256 56 #define MBOX_EXTENSION_OFFSET MBOX_SIZE 57 58 59 #ifdef MBOX_EXT_SUPPORT 60 #define MBOX_EXTENSION_SIZE 1024 61 #else 62 #define MBOX_EXTENSION_SIZE 0 63 #endif /* MBOX_EXT_SUPPORT */ 64 65 66 #define SLIM_IOCB_CMD_R0_ENTRIES 128 /* SLI FCP cmd ring entries */ 67 #define SLIM_IOCB_RSP_R0_ENTRIES 128 /* SLI FCP rsp ring entries */ 68 #define SLIM_IOCB_CMD_R1_ENTRIES 32 /* SLI IP cmd ring entries */ 69 #define SLIM_IOCB_RSP_R1_ENTRIES 32 /* SLI IP rsp ring entries */ 70 #define SLIM_IOCB_CMD_R2_ENTRIES 16 /* SLI ELS cmd ring entries */ 71 #define SLIM_IOCB_RSP_R2_ENTRIES 16 /* SLI ELS rsp ring entries */ 72 #define SLIM_IOCB_CMD_R3_ENTRIES 8 /* SLI CT cmd ring entries */ 73 #define SLIM_IOCB_RSP_R3_ENTRIES 8 /* SLI CT rsp ring entries */ 74 /* ------------------------------------------------------------------------- */ 75 /* Total: 184 Cmd's + 184 Rsp's = 368 */ 76 /* Command and response entry counts are not required to be equal */ 77 78 #define SLIM_IOCB_CMD_ENTRIES \ 79 (SLIM_IOCB_CMD_R0_ENTRIES + SLIM_IOCB_CMD_R1_ENTRIES + \ 80 SLIM_IOCB_CMD_R2_ENTRIES + SLIM_IOCB_CMD_R3_ENTRIES) 81 82 #define SLIM_IOCB_RSP_ENTRIES \ 83 (SLIM_IOCB_RSP_R0_ENTRIES + SLIM_IOCB_RSP_R1_ENTRIES + \ 84 SLIM_IOCB_RSP_R2_ENTRIES + SLIM_IOCB_RSP_R3_ENTRIES) 85 86 #define SLIM_IOCB_ENTRIES \ 87 (SLIM_IOCB_CMD_ENTRIES + SLIM_IOCB_RSP_ENTRIES) 88 89 90 /* SLI1 Definitions */ 91 #define SLI_SLIM1_SIZE 4096 /* Fixed size memory */ 92 93 94 /* SLI2 Definitions */ 95 #define SLI2_IOCB_CMD_SIZE 32 96 #define SLI2_IOCB_RSP_SIZE 32 97 #define SLI2_IOCB_MAX_SIZE \ 98 ((SLI2_IOCB_CMD_SIZE * SLIM_IOCB_CMD_ENTRIES)+ \ 99 (SLI2_IOCB_RSP_SIZE * SLIM_IOCB_RSP_ENTRIES)) 100 #define SLI2_SLIM2_SIZE \ 101 (MBOX_SIZE + MBOX_EXTENSION_SIZE + PCB_SIZE + SLI2_IOCB_MAX_SIZE) 102 103 /* SLI3 Definitions */ 104 #define SLI3_MAX_BDE 7 105 #define SLI3_IOCB_CMD_SIZE 128 106 #define SLI3_IOCB_RSP_SIZE 64 107 #define SLI3_IOCB_MAX_SIZE \ 108 ((SLI3_IOCB_CMD_SIZE * SLIM_IOCB_CMD_ENTRIES) + \ 109 (SLI3_IOCB_RSP_SIZE * SLIM_IOCB_RSP_ENTRIES)) 110 #define SLI3_SLIM2_SIZE \ 111 (MBOX_SIZE + MBOX_EXTENSION_SIZE + PCB_SIZE + SLI3_IOCB_MAX_SIZE) 112 113 114 #ifdef SLI3_SUPPORT 115 #define SLI_SLIM2_SIZE SLI3_SLIM2_SIZE 116 #define SLI_IOCB_MAX_SIZE SLI3_IOCB_MAX_SIZE 117 #else /* SLI2_SUPPORT */ 118 #define SLI_SLIM2_SIZE SLI2_SLIM2_SIZE 119 #define SLI_IOCB_MAX_SIZE SLI2_IOCB_MAX_SIZE 120 #endif /* SLI3_SUPPORT */ 121 122 123 124 #define FC_MAXRETRY 3 /* max retries for ELS commands */ 125 #define FC_FCP_RING 0 /* use ring 0 for FCP initiator cmd */ 126 #define FC_FCT_RING 0 /* use ring 0 for FCP target cmd */ 127 128 #define FC_IP_RING 1 /* use ring 1 for IP commands */ 129 #define FC_ELS_RING 2 /* use ring 2 for ELS commands */ 130 #define FC_CT_RING 3 /* use ring 3 for CT commands */ 131 132 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 133 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 134 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 135 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 136 137 /* max msg data in CMD_ADAPTER_MSG iocb */ 138 #define MAX_MSG_DATA 28 139 140 #define FF_REG_AREA_SIZE 256 /* size in bytes of i/o reg area */ 141 142 /* 143 * Miscellaneous stuff.... 144 */ 145 /* HBA Mgmt */ 146 #define FDMI_DID ((uint32_t)0xfffffa) 147 #define NameServer_DID ((uint32_t)0xfffffc) 148 #define SCR_DID ((uint32_t)0xfffffd) 149 #define Fabric_DID ((uint32_t)0xfffffe) 150 #define Bcast_DID ((uint32_t)0xffffff) 151 #define Mask_DID ((uint32_t)0xffffff) 152 #define CT_DID_MASK ((uint32_t)0xffff00) 153 #define Fabric_DID_MASK ((uint32_t)0xfff000) 154 #define WELL_KNOWN_DID_MASK ((uint32_t)0xfffff0) 155 156 #define EMLXS_MENLO_DID ((uint32_t)0x00fc0e) 157 158 159 #define PT2PT_LocalID ((uint32_t)1) 160 #define PT2PT_RemoteID ((uint32_t)2) 161 162 #define OWN_CHIP 1 /* IOCB / Mailbox is owned by FireFly */ 163 #define OWN_HOST 0 /* IOCB / Mailbox is owned by Host */ 164 #define END_OF_CHAIN 0 165 166 167 168 /* defines for type field in fc header */ 169 #define FC_ELS_DATA 0x01 170 #define FC_LLC_SNAP 0x05 171 #define FC_FCP_DATA 0x08 172 #define FC_CT_TYPE 0x20 173 #define EMLXS_MENLO_TYPE 0xFE 174 175 176 /* defines for rctl field in fc header */ 177 #define FC_DEV_DATA 0x0 178 #define FC_UNSOL_CTL 0x2 179 #define FC_SOL_CTL 0x3 180 #define FC_UNSOL_DATA 0x4 181 #define FC_FCP_CMND 0x6 182 #define FC_ELS_REQ 0x22 183 #define FC_ELS_RSP 0x23 184 #define FC_NET_HDR 0x20 /* network headers for Dfctl field */ 185 186 /* 187 * Common Transport structures and definitions 188 * 189 */ 190 #define EMLXS_COMMAND 0 191 #define EMLXS_RESPONSE 1 192 193 typedef union CtRevisionId { 194 /* Structure is in Big Endian format */ 195 struct { 196 uint32_t Revision:8; 197 uint32_t InId:24; 198 } bits; 199 uint32_t word; 200 201 } CtRevisionId_t; 202 203 typedef union CtCommandResponse { 204 /* Structure is in Big Endian format */ 205 struct { 206 uint32_t CmdRsp:16; 207 uint32_t Size:16; 208 } bits; 209 uint32_t word; 210 211 } CtCommandResponse_t; 212 213 typedef struct SliCtRequest { 214 /* Structure is in Big Endian format */ 215 CtRevisionId_t RevisionId; 216 uint8_t FsType; 217 uint8_t FsSubType; 218 uint8_t Options; 219 uint8_t Rsrvd1; 220 CtCommandResponse_t CommandResponse; 221 uint8_t Rsrvd2; 222 uint8_t ReasonCode; 223 uint8_t Explanation; 224 uint8_t VendorUnique; 225 226 union { 227 uint32_t data; 228 uint32_t PortID; 229 230 struct gid { 231 uint8_t PortType; /* for GID_PT requests */ 232 uint8_t DomainScope; 233 uint8_t AreaScope; 234 uint8_t Fc4Type; /* for GID_FT requests */ 235 } gid; 236 struct rft { 237 uint32_t PortId; /* For RFT_ID requests */ 238 #ifdef EMLXS_BIG_ENDIAN 239 uint32_t rsvd0:16; 240 uint32_t rsvd1:7; 241 uint32_t fcpReg:1; /* Type 8 */ 242 uint32_t rsvd2:2; 243 uint32_t ipReg:1; /* Type 5 */ 244 uint32_t rsvd3:5; 245 #endif 246 #ifdef EMLXS_LITTLE_ENDIAN 247 uint32_t rsvd0:16; 248 uint32_t fcpReg:1; /* Type 8 */ 249 uint32_t rsvd1:7; 250 uint32_t rsvd3:5; 251 uint32_t ipReg:1; /* Type 5 */ 252 uint32_t rsvd2:2; 253 #endif 254 uint32_t rsvd[7]; 255 } rft; 256 257 struct rsnn { 258 uint8_t wwnn[8]; 259 uint8_t snn_len; 260 char snn[256]; 261 } rsnn; 262 263 struct rspn { 264 uint32_t PortId; 265 uint8_t spn_len; 266 char spn[256]; 267 } rspn; 268 269 } un; 270 271 272 } SliCtRequest_t; 273 typedef SliCtRequest_t SLI_CT_REQUEST; 274 275 #define SLI_CT_REVISION 1 276 277 278 /* 279 * FsType Definitions 280 */ 281 282 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 283 #define SLI_CT_TIME_SERVICE 0xFB 284 #define SLI_CT_DIRECTORY_SERVICE 0xFC 285 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 286 287 /* 288 * Directory Service Subtypes 289 */ 290 291 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 292 293 /* 294 * Response Codes 295 */ 296 297 #define SLI_CT_RESPONSE_FS_RJT 0x8001 298 #define SLI_CT_RESPONSE_FS_ACC 0x8002 299 300 /* 301 * Reason Codes 302 */ 303 304 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 305 #define SLI_CT_INVALID_COMMAND 0x01 306 #define SLI_CT_INVALID_VERSION 0x02 307 #define SLI_CT_LOGICAL_ERROR 0x03 308 #define SLI_CT_INVALID_IU_SIZE 0x04 309 #define SLI_CT_LOGICAL_BUSY 0x05 310 #define SLI_CT_PROTOCOL_ERROR 0x07 311 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 312 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 313 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 314 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 315 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 316 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 317 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 318 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 319 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 320 #define SLI_CT_VENDOR_UNIQUE 0xff 321 322 /* 323 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 324 */ 325 326 #define SLI_CT_NO_PORT_ID 0x01 327 #define SLI_CT_NO_PORT_NAME 0x02 328 #define SLI_CT_NO_NODE_NAME 0x03 329 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 330 #define SLI_CT_NO_IP_ADDRESS 0x05 331 #define SLI_CT_NO_IPA 0x06 332 #define SLI_CT_NO_FC4_TYPES 0x07 333 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 334 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 335 #define SLI_CT_NO_PORT_TYPE 0x0A 336 #define SLI_CT_ACCESS_DENIED 0x10 337 #define SLI_CT_INVALID_PORT_ID 0x11 338 #define SLI_CT_DATABASE_EMPTY 0x12 339 340 #ifdef EMLXS_BIG_ENDIAN 341 #define CT_CMD_MASK 0xffff0000 342 #endif 343 344 #ifdef EMLXS_LITTLE_ENDIAN 345 #define CT_CMD_MASK 0xffff 346 #endif 347 348 /* 349 * Management Server Interface Command Codes 350 */ 351 352 #define MS_GTIN 0x0100 353 #define MS_GIEL 0x0101 354 #define MS_GIET 0x0111 355 #define MS_GDID 0x0112 356 #define MS_GMID 0x0113 357 #define MS_GFN 0x0114 358 #define MS_GIELN 0x0115 359 #define MS_GMAL 0x0116 360 #define MS_GIEIL 0x0117 361 #define MS_GPL 0x0118 362 #define MS_GPT 0x0121 363 #define MS_GPPN 0x0122 364 #define MS_GAPNL 0x0124 365 #define MS_GPS 0x0126 366 #define MS_GPSC 0x0127 367 #define MS_GATIN 0x0128 368 #define MS_GSES 0x0130 369 #define MS_GPLNL 0x0191 370 #define MS_GPLT 0x0192 371 #define MS_GPLML 0x0193 372 #define MS_GPAB 0x0197 373 #define MS_GNPL 0x01A1 374 #define MS_GPNL 0x01A2 375 #define MS_GPFCP 0x01A4 376 #define MS_GPLI 0x01A5 377 #define MS_GNID 0x01B1 378 #define MS_RIELN 0x0215 379 #define MS_RPL 0x0280 380 #define MS_RPLN 0x0291 381 #define MS_RPLT 0x0292 382 #define MS_RPLM 0x0293 383 #define MS_RPAB 0x0298 384 #define MS_RPFCP 0x029A 385 #define MS_RPLI 0x029B 386 #define MS_DPL 0x0380 387 #define MS_DPLN 0x0391 388 #define MS_DPLM 0x0392 389 #define MS_DPLML 0x0393 390 #define MS_DPLI 0x0394 391 #define MS_DPAB 0x0395 392 #define MS_DPALL 0x039F 393 394 395 /* 396 * Name Server Command Codes 397 */ 398 #define SLI_CTNS_GA_NXT 0x0100 399 #define SLI_CTNS_GPN_ID 0x0112 400 #define SLI_CTNS_GNN_ID 0x0113 401 #define SLI_CTNS_GCS_ID 0x0114 402 #define SLI_CTNS_GFT_ID 0x0117 403 #define SLI_CTNS_GSPN_ID 0x0118 404 #define SLI_CTNS_GPT_ID 0x011A 405 #define SLI_CTNS_GID_PN 0x0121 406 #define SLI_CTNS_GID_NN 0x0131 407 #define SLI_CTNS_GIP_NN 0x0135 408 #define SLI_CTNS_GIPA_NN 0x0136 409 #define SLI_CTNS_GSNN_NN 0x0139 410 #define SLI_CTNS_GNN_IP 0x0153 411 #define SLI_CTNS_GIPA_IP 0x0156 412 #define SLI_CTNS_GID_FT 0x0171 413 #define SLI_CTNS_GID_PT 0x01A1 414 #define SLI_CTNS_RPN_ID 0x0212 415 #define SLI_CTNS_RNN_ID 0x0213 416 #define SLI_CTNS_RCS_ID 0x0214 417 #define SLI_CTNS_RFT_ID 0x0217 418 #define SLI_CTNS_RSPN_ID 0x0218 419 #define SLI_CTNS_RPT_ID 0x021A 420 #define SLI_CTNS_RIP_NN 0x0235 421 #define SLI_CTNS_RIPA_NN 0x0236 422 #define SLI_CTNS_RSNN_NN 0x0239 423 #define SLI_CTNS_DA_ID 0x0300 424 425 #define SLI_CT_LOOPBACK 0xFCFC 426 427 428 /* 429 * Port Types 430 */ 431 432 #define SLI_CTPT_N_PORT 0x01 433 #define SLI_CTPT_NL_PORT 0x02 434 #define SLI_CTPT_FNL_PORT 0x03 435 #define SLI_CTPT_IP 0x04 436 #define SLI_CTPT_FCP 0x08 437 #define SLI_CTPT_NX_PORT 0x7F 438 #define SLI_CTPT_F_PORT 0x81 439 #define SLI_CTPT_FL_PORT 0x82 440 #define SLI_CTPT_E_PORT 0x84 441 442 #define SLI_CT_LAST_ENTRY 0x80000000 443 444 /* ===================================================================== */ 445 446 /* 447 * Start FireFly Register definitions 448 */ 449 450 /* PCI register offsets */ 451 #define MEM_ADDR_OFFSET 0x10 /* SLIM base memory address */ 452 #define MEMH_OFFSET 0x14 /* SLIM base memory high address */ 453 #define REG_ADDR_OFFSET 0x18 /* REGISTER base memory address */ 454 #define REGH_OFFSET 0x1c /* REGISTER base memory high address */ 455 #define IO_ADDR_OFFSET 0x20 /* BIU I/O registers */ 456 #define REGIOH_OFFSET 0x24 /* REGISTER base io high address */ 457 458 #define CMD_REG_OFFSET 0x4 /* PCI command configuration */ 459 460 /* General PCI Register Definitions */ 461 /* Refer To The PCI Specification For Detailed Explanations */ 462 463 /* Register Offsets in little endian format */ 464 #define PCI_VENDOR_ID_REGISTER 0x00 /* PCI Vendor ID Register */ 465 #define PCI_DEVICE_ID_REGISTER 0x02 /* PCI Device ID Register */ 466 #define PCI_CONFIG_ID_REGISTER 0x00 /* PCI Configuration ID Reg */ 467 #define PCI_COMMAND_REGISTER 0x04 /* PCI Command Register */ 468 #define PCI_STATUS_REGISTER 0x06 /* PCI Status Register */ 469 #define PCI_REV_ID_REGISTER 0x08 /* PCI Revision ID Register */ 470 #define PCI_CLASS_CODE_REGISTER 0x09 /* PCI Class Code Register */ 471 #define PCI_CACHE_LINE_REGISTER 0x0C /* PCI Cache Line Register */ 472 #define PCI_LATENCY_TMR_REGISTER 0x0D /* PCI Latency Timer Register */ 473 #define PCI_HEADER_TYPE_REGISTER 0x0E /* PCI Header Type Register */ 474 #define PCI_BIST_REGISTER 0x0F /* PCI Built-In SelfTest Reg */ 475 #define PCI_BAR_0_REGISTER 0x10 /* PCI Base Address Reg 0 */ 476 #define PCI_BAR_1_REGISTER 0x14 /* PCI Base Address Reg 1 */ 477 #define PCI_BAR_2_REGISTER 0x18 /* PCI Base Address Reg 2 */ 478 #define PCI_BAR_3_REGISTER 0x1C /* PCI Base Address Reg 3 */ 479 #define PCI_BAR_4_REGISTER 0x20 /* PCI Base Address Reg 4 */ 480 #define PCI_BAR_5_REGISTER 0x24 /* PCI Base Address Reg 5 */ 481 #define PCI_SSID_REGISTER 0x2C 482 #define PCI_SSVID_REGISTER 0x2C 483 #define PCI_SSDID_REGISTER 0x2E 484 #define PCI_EXPANSION_ROM 0x30 /* PCI Expansion ROM Base Reg */ 485 #define PCI_CAP_POINTER 0x34 486 #define PCI_INTR_LINE_REGISTER 0x3C /* PCI Interrupt Line Reg */ 487 #define PCI_INTR_PIN_REGISTER 0x3D /* PCI Interrupt Pin Register */ 488 #define PCI_MIN_GNT_REGISTER 0x3E /* PCI Min-Gnt Register */ 489 #define PCI_MAX_LAT_REGISTER 0x3F /* PCI Max_Lat Register */ 490 #define PCI_NODE_ADDR_REGISTER 0x40 /* PCI Node Address Register */ 491 492 #define PCI_PM_CONTROL_REGISTER 0x50 /* PCI Power Mgmt Ctrl Reg */ 493 494 /* PCIe adapters only */ 495 #define PCIe_MSI_CONTROL_REG0 0x60 /* MSI Control */ 496 #define PCIe_MSI_CONTROL_REG1 0x62 /* MSI Control */ 497 498 /* Power management command states */ 499 #define PCI_PM_D0_STATE 0x00 /* Power up state */ 500 #define PCI_PM_D3_STATE 0x03 /* Power down state */ 501 502 503 /* PCI access methods */ 504 #define P_CONF_T1 1 505 #define P_CONF_T2 2 506 507 /* max number of pci buses */ 508 #define MAX_PCI_BUSES 0xFF 509 510 /* number of PCI config bytes to access */ 511 #define PCI_BYTE 1 512 #define PCI_WORD 2 513 #define PCI_DWORD 4 514 515 /* PCI related constants */ 516 #define CMD_IO_ENBL 0x0001 517 #define CMD_MEM_ENBL 0x0002 518 #define CMD_BUS_MASTER 0x0004 519 #define CMD_MWI 0x0010 520 #define CMD_PARITY_CHK 0x0040 521 #define CMD_SERR_ENBL 0x0100 522 523 #define CMD_CFG_VALUE 0x156 /* mem enable, master, MWI, SERR, PERR */ 524 525 /* PCI addresses */ 526 #define PCI_SPACE_ENABLE 0x0CF8 527 #define CF1_CONFIG_ADDR_REGISTER 0x0CF8 528 #define CF1_CONFIG_DATA_REGISTER 0x0CFC 529 #define CF2_FORWARD_REGISTER 0x0CFA 530 #define CF2_BASE_ADDRESS 0xC000 531 532 533 /* 534 * 0xF8 is a special value for FF11.1N6 firmware. 535 * Use 0x80 for pre-FF11.1N6 &N7, etc 536 */ 537 #define DEFAULT_PCI_LATENCY_CLOCKS 0xf8 538 #define PCI_LATENCY_VALUE 0xf8 539 540 541 542 /* ==== Register Bit Definitions ==== */ 543 544 /* Used by SBUS adapter */ 545 /* SBUS Control Register */ 546 #define SBUS_CTRL_REG_OFFSET 0 /* Word offset from reg base addr */ 547 548 #define SBUS_CTRL_SBRST 0x00000001 /* Bit 0 */ 549 #define SBUS_CTRL_BKOFF 0x00000002 /* Bit 1 */ 550 #define SBUS_CTRL_ENP 0x00000004 /* Bit 2 */ 551 #define SBUS_CTRL_EN64 0x00000008 /* Bit 3 */ 552 /* Bit [6:4] IRL 1, lowset priority */ 553 #define SBUS_CTRL_SIR_1 0x00000010 554 555 #define SBUS_CTRL_SIR_2 0x00000020 556 #define SBUS_CTRL_SIR_3 0x00000030 557 #define SBUS_CTRL_SIR_4 0x00000040 558 #define SBUS_CTRL_SIR_5 0x00000050 559 #define SBUS_CTRL_SIR_6 0x00000060 560 #define SBUS_CTRL_SIR_7 0x00000070 /* IRL 7, highest priority */ 561 562 /* SBUS Status Register */ 563 #define SBUS_STAT_REG_OFFSET 1 /* Word offset from reg base addr */ 564 #define SBUS_STAT_IP 0x00000001 /* Bit 0 */ 565 #define SBUS_STAT_LERR 0x00000002 /* Bit 1 */ 566 #define SBUS_STAT_SBPE 0x00000004 /* Bit 2 */ 567 #define SBUS_STAT_TE 0x00000008 /* Bit 3 */ 568 #define SBUS_STAT_WPE 0x00000010 /* Bit 4 */ 569 #define SBUS_STAT_PERR 0x00000020 /* Bit 5 */ 570 #define SBUS_STAT_SERR 0x00000040 /* Bit 6 */ 571 #define SBUS_STAT_PTA 0x00000080 /* Bit 7 */ 572 573 /* SBUS Update Register */ 574 #define SBUS_UPDATE_REG_OFFSET 2 /* Word offfset from reg base addr */ 575 576 #define SBUS_UPDATE_DATA 0x00000001 /* Bit 0 */ 577 #define SBUS_UPDATE_SPCLK 0x00000002 /* Bit 1 */ 578 #define SBUS_UPDATE_SPCE 0x00000004 /* Bit 2 */ 579 #define SBUS_UPDATE_SPRST 0x00000008 /* Bit 3 */ 580 #define SBUS_UPDATE_SPWE 0x00000010 /* Bit 4 */ 581 #define SBUS_UPDATE_LDFPGA 0x00000080 /* Bit 7 */ 582 583 /* Host Attention Register */ 584 585 #define HA_REG_OFFSET 0 /* Word offset from register base address */ 586 587 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 588 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 589 #define HA_R0ATT 0x00000008 /* Bit 3 */ 590 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 591 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 592 #define HA_R1ATT 0x00000080 /* Bit 7 */ 593 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 594 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 595 #define HA_R2ATT 0x00000800 /* Bit 11 */ 596 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 597 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 598 #define HA_R3ATT 0x00008000 /* Bit 15 */ 599 #define HA_LATT 0x20000000 /* Bit 29 */ 600 #define HA_MBATT 0x40000000 /* Bit 30 */ 601 #define HA_ERATT 0x80000000 /* Bit 31 */ 602 603 604 #ifdef MSI_SUPPORT 605 606 /* Host attention interrupt map */ 607 #define EMLXS_MSI_MAP8 \ 608 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, HA_R3ATT, HA_LATT, HA_MBATT, HA_ERATT} 609 #define EMLXS_MSI_MAP4 \ 610 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, 0, 0, 0, 0} 611 #define EMLXS_MSI_MAP2 {0, HA_R0ATT, 0, 0, 0, 0, 0, 0} 612 #define EMLXS_MSI_MAP1 {0, 0, 0, 0, 0, 0, 0, 0} 613 614 /* MSI 0 interrupt mask */ 615 #define EMLXS_MSI0_MASK8 0 616 #define EMLXS_MSI0_MASK4 (HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA|HC_ERINT_ENA) 617 #define EMLXS_MSI0_MASK2 \ 618 (HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA|HC_MBINT_ENA| \ 619 HC_LAINT_ENA|HC_ERINT_ENA) 620 #define EMLXS_MSI0_MASK1 \ 621 (HC_R0INT_ENA|HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA| \ 622 HC_MBINT_ENA|HC_LAINT_ENA|HC_ERINT_ENA) 623 624 625 #define EMLXS_MSI_MAX_INTRS 8 626 627 #define EMLXS_MSI_MODE1 0 628 #define EMLXS_MSI_MODE2 1 629 #define EMLXS_MSI_MODE4 2 630 #define EMLXS_MSI_MODE8 3 631 #define EMLXS_MSI_MODES 4 632 633 #endif /* MSI_SUPPORT */ 634 635 636 #define IO_THROTTLE_RESERVE 12 637 638 639 640 641 /* Chip Attention Register */ 642 643 #define CA_REG_OFFSET 1 /* Word offset from register base address */ 644 645 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 646 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 647 #define CA_R0ATT 0x00000008 /* Bit 3 */ 648 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 649 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 650 #define CA_R1ATT 0x00000080 /* Bit 7 */ 651 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 652 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 653 #define CA_R2ATT 0x00000800 /* Bit 11 */ 654 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 655 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 656 #define CA_R3ATT 0x00008000 /* Bit 15 */ 657 #define CA_MBATT 0x40000000 /* Bit 30 */ 658 659 660 /* Host Status Register */ 661 662 #define HS_REG_OFFSET 2 /* Word offset from register base address */ 663 664 #define HS_OVERTEMP 0x00000100 /* Bit 8 */ 665 #define HS_MBRDY 0x00400000 /* Bit 22 */ 666 #define HS_FFRDY 0x00800000 /* Bit 23 */ 667 #define HS_FFER8 0x01000000 /* Bit 24 */ 668 #define HS_FFER7 0x02000000 /* Bit 25 */ 669 #define HS_FFER6 0x04000000 /* Bit 26 */ 670 #define HS_FFER5 0x08000000 /* Bit 27 */ 671 #define HS_FFER4 0x10000000 /* Bit 28 */ 672 #define HS_FFER3 0x20000000 /* Bit 29 */ 673 #define HS_FFER2 0x40000000 /* Bit 30 */ 674 #define HS_FFER1 0x80000000 /* Bit 31 */ 675 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */ 676 677 /* Host Control Register */ 678 679 #define HC_REG_OFFSET 3 /* Word offset from register base address */ 680 681 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 682 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 683 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 684 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 685 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 686 #define HC_INITHBI 0x02000000 /* Bit 25 */ 687 #define HC_INITMB 0x04000000 /* Bit 26 */ 688 #define HC_INITFF 0x08000000 /* Bit 27 */ 689 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 690 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 691 692 /* BIU Configuration Register */ 693 694 #define BC_REG_OFFSET 4 /* Word offset from register base address */ 695 696 #define BC_BSE 0x00000001 /* Bit 0 */ 697 #define BC_BSE_SWAP 0x01000000 /* Bit 0 - swapped */ 698 699 700 /* 701 * End FireFly Register definitions 702 */ 703 704 /* ===================================================================== */ 705 706 /* 707 * Start of FCP specific structures 708 */ 709 710 typedef struct emlxs_fcp_rsp { 711 uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 712 uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 713 714 uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 715 uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 716 uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 717 #define RSP_LEN_VALID 0x01 /* bit 0 */ 718 #define SNS_LEN_VALID 0x02 /* bit 1 */ 719 #define RESID_OVER 0x04 /* bit 2 */ 720 #define RESID_UNDER 0x08 /* bit 3 */ 721 uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 722 #define SCSI_STAT_GOOD 0x00 723 #define SCSI_STAT_CHECK_COND 0x02 724 #define SCSI_STAT_COND_MET 0x04 725 #define SCSI_STAT_BUSY 0x08 726 #define SCSI_STAT_INTERMED 0x10 727 #define SCSI_STAT_INTERMED_CM 0x14 728 #define SCSI_STAT_RES_CNFLCT 0x18 729 #define SCSI_STAT_CMD_TERM 0x22 730 #define SCSI_STAT_QUE_FULL 0x28 731 #define SCSI_STAT_ACA_ACTIVE 0x30 732 #define SCSI_STAT_TASK_ABORT 0x40 733 734 uint32_t rspResId; /* Resid xfer if RESID_xxxx set in fcpStatus2 */ 735 /* Received in Big Endian format */ 736 uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 737 /* Received in Big Endian format */ 738 uint32_t rspRspLen; /* Length of FCP response data in fcpRspInfo */ 739 /* Received in Big Endian format */ 740 741 uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 742 uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 743 uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 744 uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 745 746 #define RSP_NO_FAILURE 0x00 747 #define RSP_DATA_BURST_ERR 0x01 748 #define RSP_CMD_FIELD_ERR 0x02 749 #define RSP_RO_MISMATCH_ERR 0x03 750 #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 751 #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 752 753 uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 754 755 /* 756 * Define maximum size of SCSI Sense buffer. Seagate never issues 757 * more than 18 bytes of Sense data 758 */ 759 #define MAX_FCP_SNS 128 760 uint8_t rspSnsInfo[MAX_FCP_SNS]; 761 762 } emlxs_fcp_rsp; 763 typedef emlxs_fcp_rsp FCP_RSP; 764 765 766 typedef struct emlxs_fcp_cmd { 767 uint32_t fcpLunMsl; /* most significant lun word (32 bits) */ 768 uint32_t fcpLunLsl; /* least significant lun word (32 bits) */ 769 770 /* 771 * # of bits to shift lun id to end up in right payload word, little 772 * endian = 8, big = 16. 773 */ 774 #ifdef EMLXS_LITTLE_ENDIAN 775 #define FC_LUN_SHIFT 8 776 #define FC_ADDR_MODE_SHIFT 0 777 #endif 778 #ifdef EMLXS_BIG_ENDIAN 779 #define FC_LUN_SHIFT 16 780 #define FC_ADDR_MODE_SHIFT 24 781 #endif 782 783 uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 784 uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 785 #define SIMPLE_Q 0x00 786 #define HEAD_OF_Q 0x01 787 #define ORDERED_Q 0x02 788 #define ACA_Q 0x04 789 #define UNTAGGED 0x05 790 uint8_t fcpCntl2; /* FCP_CTL byte 2 task management codes */ 791 #define ABORT_TASK_SET 0x02 /* Bit 1 */ 792 #define CLEAR_TASK_SET 0x04 /* bit 2 */ 793 #define LUN_RESET 0x10 /* bit 4 */ 794 #define TARGET_RESET 0x20 /* bit 5 */ 795 #define CLEAR_ACA 0x40 /* bit 6 */ 796 #define TERMINATE_TASK 0x80 /* bit 7 */ 797 uint8_t fcpCntl3; 798 #define WRITE_DATA 0x01 /* Bit 0 */ 799 #define READ_DATA 0x02 /* Bit 1 */ 800 801 uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 802 uint32_t fcpDl; /* Total transfer length */ 803 804 } emlxs_fcp_cmd_t; 805 typedef emlxs_fcp_cmd_t FCP_CMND; 806 807 808 809 810 811 812 813 814 815 816 /* SCSI INQUIRY Command Structure */ 817 818 typedef struct emlxs_inquiryDataType { 819 uint8_t DeviceType:5; 820 uint8_t DeviceTypeQualifier:3; 821 822 uint8_t DeviceTypeModifier:7; 823 uint8_t RemovableMedia:1; 824 825 uint8_t Versions; 826 uint8_t ResponseDataFormat; 827 uint8_t AdditionalLength; 828 uint8_t Reserved[2]; 829 830 uint8_t SoftReset:1; 831 uint8_t CommandQueue:1; 832 uint8_t Reserved2:1; 833 uint8_t LinkedCommands:1; 834 uint8_t Synchronous:1; 835 uint8_t Wide16Bit:1; 836 uint8_t Wide32Bit:1; 837 uint8_t RelativeAddressing:1; 838 839 uint8_t VendorId[8]; 840 uint8_t ProductId[16]; 841 uint8_t ProductRevisionLevel[4]; 842 uint8_t VendorSpecific[20]; 843 uint8_t Reserved3[40]; 844 845 } emlxs_inquiry_data_type_t; 846 typedef emlxs_inquiry_data_type_t INQUIRY_DATA_DEF; 847 848 849 typedef struct emlxs_read_capacity_data { 850 uint32_t LogicalBlockAddress; 851 uint32_t BytesPerBlock; 852 853 } emlxs_read_capacity_data_t; 854 typedef emlxs_read_capacity_data_t READ_CAPACITY_DATA_DEF; 855 856 857 /* SCSI CDB command codes */ 858 #define FCP_SCSI_FORMAT_UNIT 0x04 859 #define FCP_SCSI_INQUIRY 0x12 860 #define FCP_SCSI_MODE_SELECT 0x15 861 #define FCP_SCSI_MODE_SENSE 0x1A 862 #define FCP_SCSI_PAUSE_RESUME 0x4B 863 #define FCP_SCSI_PLAY_AUDIO 0x45 864 #define FCP_SCSI_PLAY_AUDIO_EXT 0xA5 865 #define FCP_SCSI_PLAY_AUDIO_MSF 0x47 866 #define FCP_SCSI_PLAY_AUDIO_TRK_INDX 0x48 867 #define FCP_SCSI_PREVENT_ALLOW_REMOVAL 0x1E 868 #define FCP_SCSI_READ_CMD 0x08 869 #define FCP_SCSI_READ_BUFFER 0x3C 870 #define FCP_SCSI_READ_CAPACITY 0x25 871 #define FCP_SCSI_READ_DEFECT_LIST 0x37 872 #define FCP_SCSI_READ_EXTENDED 0x28 873 #define FCP_SCSI_READ_HEADER 0x44 874 #define FCP_SCSI_READ_LONG 0xE8 875 #define FCP_SCSI_READ_SUB_CHANNEL 0x42 876 #define FCP_SCSI_READ_TOC 0x43 877 #define FCP_SCSI_REASSIGN_BLOCK 0x07 878 #define FCP_SCSI_RECEIVE_DIAGNOSTIC_RESULTS 0x1C 879 #define FCP_SCSI_RELEASE_UNIT 0x17 880 #define FCP_SCSI_REPORT_LUNS 0xa0 881 #define FCP_SCSI_REQUEST_SENSE 0x03 882 #define FCP_SCSI_RESERVE_UNIT 0x16 883 #define FCP_SCSI_REZERO_UNIT 0x01 884 #define FCP_SCSI_SEEK 0x0B 885 #define FCP_SCSI_SEEK_EXTENDED 0x2B 886 #define FCP_SCSI_SEND_DIAGNOSTIC 0x1D 887 #define FCP_SCSI_START_STOP_UNIT 0x1B 888 #define FCP_SCSI_TEST_UNIT_READY 0x00 889 #define FCP_SCSI_VERIFY 0x2F 890 #define FCP_SCSI_WRITE_CMD 0x0A 891 #define FCP_SCSI_WRITE_AND_VERIFY 0x2E 892 #define FCP_SCSI_WRITE_BUFFER 0x3B 893 #define FCP_SCSI_WRITE_EXTENDED 0x2A 894 #define FCP_SCSI_WRITE_LONG 0xEA 895 #define FCP_SCSI_RELEASE_LUNR 0xBB 896 #define FCP_SCSI_RELEASE_LUNV 0xBF 897 898 #define HPVA_SETPASSTHROUGHMODE 0x27 899 #define HPVA_EXECUTEPASSTHROUGH 0x29 900 #define HPVA_CREATELUN 0xE2 901 #define HPVA_SETLUNSECURITYLIST 0xED 902 #define HPVA_SETCLOCK 0xF9 903 #define HPVA_RECOVER 0xFA 904 #define HPVA_GENERICSERVICEOUT 0xFD 905 906 #define DMEP_EXPORT_IN 0x85 907 #define DMEP_EXPORT_OUT 0x89 908 909 #define MDACIOCTL_DIRECT_CMD 0x22 910 #define MDACIOCTL_STOREIMAGE 0x2C 911 #define MDACIOCTL_WRITESIGNATURE 0xA6 912 #define MDACIOCTL_SETREALTIMECLOCK 0xAC 913 #define MDACIOCTL_PASS_THRU_CDB 0xAD 914 #define MDACIOCTL_PASS_THRU_INITIATE 0xAE 915 #define MDACIOCTL_CREATENEWCONF 0xC0 916 #define MDACIOCTL_ADDNEWCONF 0xC4 917 #define MDACIOCTL_MORE 0xC6 918 #define MDACIOCTL_SETPHYSDEVPARAMETER 0xC8 919 #define MDACIOCTL_SETLOGDEVPARAMETER 0xCF 920 #define MDACIOCTL_SETCONTROLLERPARAMETER 0xD1 921 #define MDACIOCTL_WRITESANMAP 0xD4 922 #define MDACIOCTL_SETMACADDRESS 0xD5 923 924 /* 925 * End of FCP specific structures 926 */ 927 928 #define FL_ALPA 0x00 /* AL_PA of FL_Port */ 929 930 /* Fibre Channel Service Parameter definitions */ 931 932 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 933 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 934 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 935 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 936 937 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 938 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 939 #define FC_PH3 0x20 /* FC-PH-3 version */ 940 941 #define FF_FRAME_SIZE 2048 942 943 944 /* ==== Mailbox Commands ==== */ 945 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 946 #define MBX_LOAD_SM 0x01 947 #define MBX_READ_NV 0x02 948 #define MBX_WRITE_NV 0x03 949 #define MBX_RUN_BIU_DIAG 0x04 950 #define MBX_INIT_LINK 0x05 951 #define MBX_DOWN_LINK 0x06 952 #define MBX_CONFIG_LINK 0x07 953 #define MBX_PART_SLIM 0x08 954 #define MBX_CONFIG_RING 0x09 955 #define MBX_RESET_RING 0x0A 956 #define MBX_READ_CONFIG 0x0B 957 #define MBX_READ_RCONFIG 0x0C 958 #define MBX_READ_SPARM 0x0D 959 #define MBX_READ_STATUS 0x0E 960 #define MBX_READ_RPI 0x0F 961 #define MBX_READ_XRI 0x10 962 #define MBX_READ_REV 0x11 963 #define MBX_READ_LNK_STAT 0x12 964 #define MBX_REG_LOGIN 0x13 965 #define MBX_UNREG_LOGIN 0x14 966 #define MBX_READ_LA 0x15 967 #define MBX_CLEAR_LA 0x16 968 #define MBX_DUMP_MEMORY 0x17 969 #define MBX_DUMP_CONTEXT 0x18 970 #define MBX_RUN_DIAGS 0x19 971 #define MBX_RESTART 0x1A 972 #define MBX_UPDATE_CFG 0x1B 973 #define MBX_DOWN_LOAD 0x1C 974 #define MBX_DEL_LD_ENTRY 0x1D 975 #define MBX_RUN_PROGRAM 0x1E 976 #define MBX_SET_MASK 0x20 977 #define MBX_SET_VARIABLE 0x21 978 #define MBX_UNREG_D_ID 0x23 979 #define MBX_KILL_BOARD 0x24 980 #define MBX_CONFIG_FARP 0x25 981 #define MBX_BEACON 0x2A 982 #define MBX_CONFIG_MSIX 0x30 983 #define MBX_HEARTBEAT 0x31 984 #define MBX_WRITE_VPARMS 0x32 985 #define MBX_ASYNC_EVENT 0x33 986 987 #define MBX_READ_EVENT_LOG_STATUS 0x37 988 #define MBX_READ_EVENT_LOG 0x38 989 #define MBX_WRITE_EVENT_LOG 0x39 990 #define MBX_NV_LOG 0x3A 991 992 993 #define MBX_CONFIG_HBQ 0x7C /* SLI3 */ 994 #define MBX_LOAD_AREA 0x81 995 #define MBX_RUN_BIU_DIAG64 0x84 996 #define MBX_GET_DEBUG 0x86 997 #define MBX_CONFIG_PORT 0x88 998 #define MBX_READ_SPARM64 0x8D 999 #define MBX_READ_RPI64 0x8F 1000 #define MBX_CONFIG_MSI 0x90 1001 #define MBX_REG_LOGIN64 0x93 1002 #define MBX_READ_LA64 0x95 1003 #define MBX_REG_VPI 0x96 /* NPIV */ 1004 #define MBX_UNREG_VPI 0x97 /* NPIV */ 1005 #define MBX_FLASH_WR_ULA 0x98 1006 #define MBX_SET_DEBUG 0x99 1007 #define MBX_LOAD_EXP_ROM 0x9C 1008 #define MBX_MAX_CMDS 0x9D 1009 #define MBX_SLI2_CMD_MASK 0x80 1010 1011 1012 /* ==== IOCB Commands ==== */ 1013 1014 #define CMD_RCV_SEQUENCE_CX 0x01 1015 #define CMD_XMIT_SEQUENCE_CR 0x02 1016 #define CMD_XMIT_SEQUENCE_CX 0x03 1017 #define CMD_XMIT_BCAST_CN 0x04 1018 #define CMD_XMIT_BCAST_CX 0x05 1019 #define CMD_QUE_RING_BUF_CN 0x06 1020 #define CMD_QUE_XRI_BUF_CX 0x07 1021 #define CMD_IOCB_CONTINUE_CN 0x08 1022 #define CMD_RET_XRI_BUF_CX 0x09 1023 #define CMD_ELS_REQUEST_CR 0x0A 1024 #define CMD_ELS_REQUEST_CX 0x0B 1025 #define CMD_RCV_ELS_REQ_CX 0x0D 1026 #define CMD_ABORT_XRI_CN 0x0E 1027 #define CMD_ABORT_XRI_CX 0x0F 1028 #define CMD_CLOSE_XRI_CN 0x10 1029 #define CMD_CLOSE_XRI_CX 0x11 1030 #define CMD_CREATE_XRI_CR 0x12 1031 #define CMD_CREATE_XRI_CX 0x13 1032 #define CMD_GET_RPI_CN 0x14 1033 #define CMD_XMIT_ELS_RSP_CX 0x15 1034 #define CMD_GET_RPI_CR 0x16 1035 #define CMD_XRI_ABORTED_CX 0x17 1036 #define CMD_FCP_IWRITE_CR 0x18 1037 #define CMD_FCP_IWRITE_CX 0x19 1038 #define CMD_FCP_IREAD_CR 0x1A 1039 #define CMD_FCP_IREAD_CX 0x1B 1040 #define CMD_FCP_ICMND_CR 0x1C 1041 #define CMD_FCP_ICMND_CX 0x1D 1042 #define CMD_FCP_TSEND_CX 0x1F /* FCP_TARGET_MODE */ 1043 #define CMD_ADAPTER_MSG 0x20 1044 #define CMD_FCP_TRECEIVE_CX 0x21 /* FCP_TARGET_MODE */ 1045 #define CMD_ADAPTER_DUMP 0x22 1046 #define CMD_FCP_TRSP_CX 0x23 /* FCP_TARGET_MODE */ 1047 #define CMD_FCP_AUTO_TRSP_CX 0x29 /* FCP_TARGET_MODE */ 1048 1049 /* LP3000 gasket IOCB Command Set */ 1050 1051 #define CMD_BPL_IWRITE_CR 0x48 1052 #define CMD_BPL_IWRITE_CX 0x49 1053 #define CMD_BPL_IREAD_CR 0x4A 1054 #define CMD_BPL_IREAD_CX 0x4B 1055 #define CMD_BPL_ICMND_CR 0x4C 1056 #define CMD_BPL_ICMND_CX 0x4D 1057 1058 #define CMD_ASYNC_STATUS 0x7C 1059 1060 /* SLI_2 IOCB Command Set */ 1061 #define CMD_RCV_SEQUENCE64_CX 0x81 1062 #define CMD_XMIT_SEQUENCE64_CR 0x82 1063 #define CMD_XMIT_SEQUENCE64_CX 0x83 1064 #define CMD_XMIT_BCAST64_CN 0x84 1065 #define CMD_XMIT_BCAST64_CX 0x85 1066 #define CMD_QUE_RING_BUF64_CN 0x86 1067 #define CMD_QUE_XRI_BUF64_CX 0x87 1068 #define CMD_IOCB_CONTINUE64_CN 0x88 1069 #define CMD_RET_XRI_BUF64_CX 0x89 1070 #define CMD_ELS_REQUEST64_CR 0x8A 1071 #define CMD_ELS_REQUEST64_CX 0x8B 1072 #define CMD_RCV_ELS_REQ64_CX 0x8D 1073 #define CMD_XMIT_ELS_RSP64_CX 0x95 1074 #define CMD_FCP_IWRITE64_CR 0x98 1075 #define CMD_FCP_IWRITE64_CX 0x99 1076 #define CMD_FCP_IREAD64_CR 0x9A 1077 #define CMD_FCP_IREAD64_CX 0x9B 1078 #define CMD_FCP_ICMND64_CR 0x9C 1079 #define CMD_FCP_ICMND64_CX 0x9D 1080 #define CMD_FCP_TSEND64_CX 0x9F /* FCP_TARGET_MODE */ 1081 #define CMD_FCP_TRECEIVE64_CX 0xA1 /* FCP_TARGET_MODE */ 1082 #define CMD_FCP_TRSP64_CX 0xA3 /* FCP_TARGET_MODE */ 1083 #define CMD_RCV_SEQ64_CX 0xB5 /* SLI3 */ 1084 #define CMD_RCV_ELS64_CX 0xB7 /* SLI3 */ 1085 #define CMD_RCV_CONT64_CX 0xBB /* SLI3 */ 1086 #define CMD_RCV_SEQ_LIST64_CX 0xC1 1087 #define CMD_GEN_REQUEST64_CR 0xC2 1088 #define CMD_GEN_REQUEST64_CX 0xC3 1089 #define CMD_QUE_RING_LIST64_CN 0xC6 1090 1091 /* 1092 * Define Status 1093 */ 1094 #define MBX_SUCCESS 0 1095 #define MBX_FAILURE 1 1096 #define MBXERR_NUM_IOCBS 2 1097 #define MBXERR_IOCBS_EXCEEDED 3 1098 #define MBXERR_BAD_RING_NUMBER 4 1099 #define MBXERR_MASK_ENTRIES_RANGE 5 1100 #define MBXERR_MASKS_EXCEEDED 6 1101 #define MBXERR_BAD_PROFILE 7 1102 #define MBXERR_BAD_DEF_CLASS 8 1103 #define MBXERR_BAD_MAX_RESPONDER 9 1104 #define MBXERR_BAD_MAX_ORIGINATOR 0xA 1105 #define MBXERR_RPI_REGISTERED 0xB 1106 #define MBXERR_RPI_FULL 0xC 1107 #define MBXERR_NO_RESOURCES 0xD 1108 #define MBXERR_BAD_RCV_LENGTH 0xE 1109 #define MBXERR_DMA_ERROR 0xF 1110 #define MBXERR_NOT_SUPPORTED 0x10 1111 #define MBXERR_UNSUPPORTED_FEATURE 0x11 1112 #define MBXERR_UNKNOWN_COMMAND 0x12 1113 1114 /* Driver special codes */ 1115 #define MBX_OVERTEMP_ERROR 0xFA 1116 #define MBX_HARDWARE_ERROR 0xFB 1117 #define MBX_DRVR_ERROR 0xFC 1118 #define MBX_BUSY 0xFD 1119 #define MBX_TIMEOUT 0xFE 1120 #define MBX_NOT_FINISHED 0xFF 1121 1122 1123 /* 1124 * flags for emlxs_mb_issue_cmd() 1125 */ 1126 #define MBX_POLL 0x01 /* poll mbx till cmd done, then return */ 1127 #define MBX_SLEEP 0x02 /* sleep till mbx intr cmpl wakes thread up */ 1128 #define MBX_WAIT 0x03 /* wait for comand done, then return */ 1129 #define MBX_NOWAIT 0x04 /* issue command then return immediately */ 1130 1131 typedef struct emlxs_rings { 1132 #ifdef EMLXS_BIG_ENDIAN 1133 uint32_t crReserved:16; 1134 uint32_t crBegin:8; 1135 uint32_t crEnd:8; /* Low order bit first word */ 1136 uint32_t rrReserved:16; 1137 uint32_t rrBegin:8; 1138 uint32_t rrEnd:8; /* Low order bit second word */ 1139 #endif 1140 #ifdef EMLXS_LITTLE_ENDIAN 1141 uint32_t crEnd:8; /* Low order bit first word */ 1142 uint32_t crBegin:8; 1143 uint32_t crReserved:16; 1144 uint32_t rrEnd:8; /* Low order bit second word */ 1145 uint32_t rrBegin:8; 1146 uint32_t rrReserved:16; 1147 #endif 1148 } emlxs_rings_t; 1149 typedef emlxs_rings_t RINGS; 1150 1151 1152 typedef struct emlxs_ring_def { 1153 #ifdef EMLXS_BIG_ENDIAN 1154 uint16_t offCiocb; 1155 uint16_t numCiocb; 1156 uint16_t offRiocb; 1157 uint16_t numRiocb; 1158 #endif 1159 #ifdef EMLXS_LITTLE_ENDIAN 1160 uint16_t numCiocb; 1161 uint16_t offCiocb; 1162 uint16_t numRiocb; 1163 uint16_t offRiocb; 1164 #endif 1165 } emlxs_ring_def_t; 1166 typedef emlxs_ring_def_t RING_DEF; 1167 1168 1169 /* 1170 * The following F.C. frame stuctures are defined in Big Endian format. 1171 */ 1172 1173 typedef struct emlxs_name_type { 1174 #ifdef EMLXS_BIG_ENDIAN 1175 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1176 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 of IEEE ext */ 1177 #endif 1178 #ifdef EMLXS_LITTLE_ENDIAN 1179 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 of IEEE ext */ 1180 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1181 #endif 1182 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 1183 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 1184 #define NAME_FC_TYPE 0x3 /* FC native name type */ 1185 #define NAME_IP_TYPE 0x4 /* IP address */ 1186 #define NAME_CCITT_TYPE 0xC 1187 #define NAME_CCITT_GR_TYPE 0xE 1188 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE extended Lsb */ 1189 uint8_t IEEE[6]; /* FC IEEE address */ 1190 1191 } emlxs_name_type_t; 1192 typedef emlxs_name_type_t NAME_TYPE; 1193 1194 1195 typedef struct emlxs_csp { 1196 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 1197 uint8_t fcphLow; 1198 uint8_t bbCreditMsb; 1199 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 1200 #ifdef EMLXS_BIG_ENDIAN 1201 uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1202 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1203 uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1204 uint16_t fPort:1; /* FC Word 1, bit 28 */ 1205 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1206 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1207 uint16_t multicast:1; /* FC Word 1, bit 25 */ 1208 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1209 1210 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1211 uint16_t simplex:1; /* FC Word 1, bit 22 */ 1212 1213 uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1214 uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1215 uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1216 1217 uint16_t dhd:1; /* FC Word 1, bit 18 */ 1218 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1219 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1220 #endif 1221 #ifdef EMLXS_LITTLE_ENDIAN 1222 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1223 uint16_t multicast:1; /* FC Word 1, bit 25 */ 1224 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1225 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1226 uint16_t fPort:1; /* FC Word 1, bit 28 */ 1227 uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1228 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1229 uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1230 1231 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1232 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1233 uint16_t dhd:1; /* FC Word 1, bit 18 */ 1234 1235 uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1236 uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1237 uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1238 1239 uint16_t simplex:1; /* FC Word 1, bit 22 */ 1240 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1241 #endif 1242 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 1243 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 1244 union { 1245 struct { 1246 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 1247 1248 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 1249 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 1250 1251 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 1252 } nPort; 1253 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 1254 } w2; 1255 1256 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 1257 1258 } emlxs_csp_t; 1259 typedef emlxs_csp_t CSP; 1260 1261 1262 typedef struct emlxs_class_parms { 1263 #ifdef EMLXS_BIG_ENDIAN 1264 uint8_t classValid:1; /* FC Word 0, bit 31 */ 1265 uint8_t intermix:1; /* FC Word 0, bit 30 */ 1266 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1267 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1268 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1269 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1270 #endif 1271 #ifdef EMLXS_LITTLE_ENDIAN 1272 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1273 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1274 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1275 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1276 uint8_t intermix:1; /* FC Word 0, bit 30 */ 1277 uint8_t classValid:1; /* FC Word 0, bit 31 */ 1278 1279 #endif 1280 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 1281 #ifdef EMLXS_BIG_ENDIAN 1282 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1283 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1284 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1285 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1286 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1287 #endif 1288 #ifdef EMLXS_LITTLE_ENDIAN 1289 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1290 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1291 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1292 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1293 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1294 #endif 1295 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 1296 #ifdef EMLXS_BIG_ENDIAN 1297 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1298 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1299 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1300 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1301 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1302 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1303 #endif 1304 #ifdef EMLXS_LITTLE_ENDIAN 1305 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1306 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1307 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1308 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1309 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1310 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1311 #endif 1312 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 1313 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 1314 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 1315 1316 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 1317 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 1318 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 1319 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 1320 1321 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 1322 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 1323 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 1324 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 1325 1326 } emlxs_class_parms_t; 1327 typedef emlxs_class_parms_t CLASS_PARMS; 1328 1329 1330 typedef struct emlxs_serv_parms { /* Structure is in Big Endian format */ 1331 CSP cmn; 1332 NAME_TYPE portName; 1333 NAME_TYPE nodeName; 1334 CLASS_PARMS cls1; 1335 CLASS_PARMS cls2; 1336 CLASS_PARMS cls3; 1337 CLASS_PARMS cls4; 1338 uint8_t vendorVersion[16]; 1339 1340 } emlxs_serv_parms_t; 1341 typedef emlxs_serv_parms_t SERV_PARM; 1342 1343 typedef struct { 1344 union { 1345 uint32_t word0; 1346 struct { 1347 #ifdef EMLXS_BIG_ENDIAN 1348 uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1349 /* Emulex Organization Unique ID (00-00-C9) */ 1350 uint32_t oui:24; 1351 #endif 1352 #ifdef EMLXS_LITTLE_ENDIAN 1353 /* Emulex Organization Unique ID (00-00-C9) */ 1354 uint32_t oui:24; 1355 uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1356 #endif 1357 } w0; 1358 } un0; 1359 union { 1360 uint32_t word1; 1361 struct { 1362 #ifdef EMLXS_BIG_ENDIAN 1363 uint32_t vport:1; /* Word 1, Bit 31 */ 1364 uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1365 #endif 1366 #ifdef EMLXS_LITTLE_ENDIAN 1367 uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1368 uint32_t vport:1; /* Word 1, Bit 31 */ 1369 #endif 1370 } w1; 1371 } un1; 1372 uint8_t rsvd2[8]; 1373 } emlxs_vvl_fmt_t; 1374 1375 #define valid_vendor_version cmn.rspMultipleNPort 1376 1377 1378 1379 /* 1380 * Extended Link Service LS_COMMAND codes (Payload BYTE 0) 1381 */ 1382 #ifdef EMLXS_BIG_ENDIAN 1383 #define ELS_CMD_SHIFT 24 1384 #define ELS_CMD_MASK 0xff000000 1385 #define ELS_RSP_MASK 0xff000000 1386 #define ELS_CMD_LS_RJT 0x01000000 1387 #define ELS_CMD_ACC 0x02000000 1388 #define ELS_CMD_PLOGI 0x03000000 1389 #define ELS_CMD_FLOGI 0x04000000 1390 #define ELS_CMD_LOGO 0x05000000 1391 #define ELS_CMD_ABTX 0x06000000 1392 #define ELS_CMD_RCS 0x07000000 1393 #define ELS_CMD_RES 0x08000000 1394 #define ELS_CMD_RSS 0x09000000 1395 #define ELS_CMD_RSI 0x0A000000 1396 #define ELS_CMD_ESTS 0x0B000000 1397 #define ELS_CMD_ESTC 0x0C000000 1398 #define ELS_CMD_ADVC 0x0D000000 1399 #define ELS_CMD_RTV 0x0E000000 1400 #define ELS_CMD_RLS 0x0F000000 1401 #define ELS_CMD_ECHO 0x10000000 1402 #define ELS_CMD_TEST 0x11000000 1403 #define ELS_CMD_RRQ 0x12000000 1404 #define ELS_CMD_PRLI 0x20000000 1405 #define ELS_CMD_PRLO 0x21000000 1406 #define ELS_CMD_SCN 0x22000000 1407 #define ELS_CMD_TPLS 0x23000000 1408 #define ELS_CMD_GPRLO 0x24000000 1409 #define ELS_CMD_GAID 0x30000000 1410 #define ELS_CMD_FACT 0x31000000 1411 #define ELS_CMD_FDACT 0x32000000 1412 #define ELS_CMD_NACT 0x33000000 1413 #define ELS_CMD_NDACT 0x34000000 1414 #define ELS_CMD_QoSR 0x40000000 1415 #define ELS_CMD_RVCS 0x41000000 1416 #define ELS_CMD_PDISC 0x50000000 1417 #define ELS_CMD_FDISC 0x51000000 1418 #define ELS_CMD_ADISC 0x52000000 1419 #define ELS_CMD_FARP 0x54000000 1420 #define ELS_CMD_FARPR 0x55000000 1421 #define ELS_CMD_FAN 0x60000000 1422 #define ELS_CMD_RSCN 0x61000000 1423 #define ELS_CMD_SCR 0x62000000 1424 #define ELS_CMD_LINIT 0x70000000 1425 #define ELS_CMD_RNID 0x78000000 1426 #define ELS_CMD_AUTH 0x90000000 1427 #endif 1428 1429 #ifdef EMLXS_LITTLE_ENDIAN 1430 #define ELS_CMD_SHIFT 0 1431 #define ELS_CMD_MASK 0xff 1432 #define ELS_RSP_MASK 0xff 1433 #define ELS_CMD_LS_RJT 0x01 1434 #define ELS_CMD_ACC 0x02 1435 #define ELS_CMD_PLOGI 0x03 1436 #define ELS_CMD_FLOGI 0x04 1437 #define ELS_CMD_LOGO 0x05 1438 #define ELS_CMD_ABTX 0x06 1439 #define ELS_CMD_RCS 0x07 1440 #define ELS_CMD_RES 0x08 1441 #define ELS_CMD_RSS 0x09 1442 #define ELS_CMD_RSI 0x0A 1443 #define ELS_CMD_ESTS 0x0B 1444 #define ELS_CMD_ESTC 0x0C 1445 #define ELS_CMD_ADVC 0x0D 1446 #define ELS_CMD_RTV 0x0E 1447 #define ELS_CMD_RLS 0x0F 1448 #define ELS_CMD_ECHO 0x10 1449 #define ELS_CMD_TEST 0x11 1450 #define ELS_CMD_RRQ 0x12 1451 #define ELS_CMD_PRLI 0x20 1452 #define ELS_CMD_PRLO 0x21 1453 #define ELS_CMD_SCN 0x22 1454 #define ELS_CMD_TPLS 0x23 1455 #define ELS_CMD_GPRLO 0x24 1456 #define ELS_CMD_GAID 0x30 1457 #define ELS_CMD_FACT 0x31 1458 #define ELS_CMD_FDACT 0x32 1459 #define ELS_CMD_NACT 0x33 1460 #define ELS_CMD_NDACT 0x34 1461 #define ELS_CMD_QoSR 0x40 1462 #define ELS_CMD_RVCS 0x41 1463 #define ELS_CMD_PDISC 0x50 1464 #define ELS_CMD_FDISC 0x51 1465 #define ELS_CMD_ADISC 0x52 1466 #define ELS_CMD_FARP 0x54 1467 #define ELS_CMD_FARPR 0x55 1468 #define ELS_CMD_FAN 0x60 1469 #define ELS_CMD_RSCN 0x61 1470 #define ELS_CMD_SCR 0x62 1471 #define ELS_CMD_LINIT 0x70 1472 #define ELS_CMD_RNID 0x78 1473 #define ELS_CMD_AUTH 0x90 1474 #endif 1475 1476 1477 /* 1478 * LS_RJT Payload Definition 1479 */ 1480 1481 typedef struct _LS_RJT { /* Structure is in Big Endian format */ 1482 union { 1483 uint32_t lsRjtError; 1484 struct { 1485 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 1486 1487 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 1488 /* LS_RJT reason codes */ 1489 #define LSRJT_INVALID_CMD 0x01 1490 #define LSRJT_LOGICAL_ERR 0x03 1491 #define LSRJT_LOGICAL_BSY 0x05 1492 #define LSRJT_PROTOCOL_ERR 0x07 1493 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 1494 #define LSRJT_CMD_UNSUPPORTED 0x0B 1495 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 1496 1497 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 1498 /* LS_RJT reason explanation */ 1499 #define LSEXP_NOTHING_MORE 0x00 1500 #define LSEXP_SPARM_OPTIONS 0x01 1501 #define LSEXP_SPARM_ICTL 0x03 1502 #define LSEXP_SPARM_RCTL 0x05 1503 #define LSEXP_SPARM_RCV_SIZE 0x07 1504 #define LSEXP_SPARM_CONCUR_SEQ 0x09 1505 #define LSEXP_SPARM_CREDIT 0x0B 1506 #define LSEXP_INVALID_PNAME 0x0D 1507 #define LSEXP_INVALID_NNAME 0x0E 1508 #define LSEXP_INVALID_CSP 0x0F 1509 #define LSEXP_INVALID_ASSOC_HDR 0x11 1510 #define LSEXP_ASSOC_HDR_REQ 0x13 1511 #define LSEXP_INVALID_O_SID 0x15 1512 #define LSEXP_INVALID_OX_RX 0x17 1513 #define LSEXP_CMD_IN_PROGRESS 0x19 1514 #define LSEXP_INVALID_NPORT_ID 0x1F 1515 #define LSEXP_INVALID_SEQ_ID 0x21 1516 #define LSEXP_INVALID_XCHG 0x23 1517 #define LSEXP_INACTIVE_XCHG 0x25 1518 #define LSEXP_RQ_REQUIRED 0x27 1519 #define LSEXP_OUT_OF_RESOURCE 0x29 1520 #define LSEXP_CANT_GIVE_DATA 0x2A 1521 #define LSEXP_REQ_UNSUPPORTED 0x2C 1522 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 1523 } b; 1524 } un; 1525 } LS_RJT; 1526 1527 1528 /* 1529 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 1530 */ 1531 1532 typedef struct _LOGO { /* Structure is in Big Endian format */ 1533 union { 1534 uint32_t nPortId32; /* Access nPortId as a word */ 1535 struct { 1536 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 1537 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 1538 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 1539 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 1540 } b; 1541 } un; 1542 NAME_TYPE portName; /* N_port name field */ 1543 } LOGO; 1544 1545 1546 /* 1547 * FCP Login (PRLI Request / ACC) Payload Definition 1548 */ 1549 1550 #define PRLX_PAGE_LEN 0x10 1551 #define TPRLO_PAGE_LEN 0x14 1552 1553 typedef struct _PRLI { /* Structure is in Big Endian format */ 1554 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 1555 1556 #define PRLI_FCP_TYPE 0x08 1557 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1558 1559 #ifdef EMLXS_BIG_ENDIAN 1560 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1561 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1562 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1563 1564 /* ACC = imagePairEstablished */ 1565 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1566 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 1567 #endif 1568 #ifdef EMLXS_LITTLE_ENDIAN 1569 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 1570 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1571 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1572 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1573 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1574 /* ACC = imagePairEstablished */ 1575 #endif 1576 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 1577 #define PRLI_NO_RESOURCES 0x2 1578 #define PRLI_INIT_INCOMPLETE 0x3 1579 #define PRLI_NO_SUCH_PA 0x4 1580 #define PRLI_PREDEF_CONFIG 0x5 1581 #define PRLI_PARTIAL_SUCCESS 0x6 1582 #define PRLI_INVALID_PAGE_CNT 0x7 1583 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1584 1585 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1586 1587 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1588 1589 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 1590 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 1591 #ifdef EMLXS_BIG_ENDIAN 1592 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1593 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1594 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1595 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1596 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1597 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1598 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1599 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1600 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1601 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1602 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1603 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1604 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1605 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1606 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1607 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1608 #endif 1609 #ifdef EMLXS_LITTLE_ENDIAN 1610 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1611 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1612 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1613 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1614 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1615 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1616 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1617 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1618 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1619 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1620 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1621 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1622 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1623 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1624 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1625 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1626 #endif 1627 } PRLI; 1628 1629 /* 1630 * FCP Logout (PRLO Request / ACC) Payload Definition 1631 */ 1632 1633 typedef struct _PRLO { /* Structure is in Big Endian format */ 1634 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 1635 1636 #define PRLO_FCP_TYPE 0x08 1637 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1638 1639 #ifdef EMLXS_BIG_ENDIAN 1640 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1641 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1642 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1643 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 1644 #endif 1645 #ifdef EMLXS_LITTLE_ENDIAN 1646 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 1647 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1648 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1649 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1650 #endif 1651 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 1652 #define PRLO_NO_SUCH_IMAGE 0x4 1653 #define PRLO_INVALID_PAGE_CNT 0x7 1654 1655 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1656 1657 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1658 1659 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1660 1661 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 1662 } PRLO; 1663 1664 1665 typedef struct _ADISC { /* Structure is in Big Endian format */ 1666 uint32_t hardAL_PA; 1667 NAME_TYPE portName; 1668 NAME_TYPE nodeName; 1669 uint32_t DID; 1670 } ADISC; 1671 1672 1673 typedef struct _FARP { /* Structure is in Big Endian format */ 1674 uint32_t Mflags:8; 1675 uint32_t Odid:24; 1676 #define FARP_NO_ACTION 0 /* FARP info enclosed, no action */ 1677 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 1678 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 1679 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 1680 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 addr, not supported */ 1681 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 addr, not supported */ 1682 uint32_t Rflags:8; 1683 uint32_t Rdid:24; 1684 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 1685 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 1686 NAME_TYPE OportName; 1687 NAME_TYPE OnodeName; 1688 NAME_TYPE RportName; 1689 NAME_TYPE RnodeName; 1690 uint8_t Oipaddr[16]; 1691 uint8_t Ripaddr[16]; 1692 } FARP; 1693 1694 typedef struct _FAN { /* Structure is in Big Endian format */ 1695 uint32_t Fdid; 1696 NAME_TYPE FportName; 1697 NAME_TYPE FnodeName; 1698 } FAN; 1699 1700 typedef struct _SCR { /* Structure is in Big Endian format */ 1701 uint8_t resvd1; 1702 uint8_t resvd2; 1703 uint8_t resvd3; 1704 uint8_t Function; 1705 #define SCR_FUNC_FABRIC 0x01 1706 #define SCR_FUNC_NPORT 0x02 1707 #define SCR_FUNC_FULL 0x03 1708 #define SCR_CLEAR 0xff 1709 } SCR; 1710 1711 typedef struct _RNID_TOP_DISC { 1712 NAME_TYPE portName; 1713 uint8_t resvd[8]; 1714 uint32_t unitType; 1715 #define RNID_HBA 0x7 1716 #define RNID_HOST 0xa 1717 #define RNID_DRIVER 0xd 1718 uint32_t physPort; 1719 uint32_t attachedNodes; 1720 uint16_t ipVersion; 1721 #define RNID_IPV4 0x1 1722 #define RNID_IPV6 0x2 1723 uint16_t UDPport; 1724 uint8_t ipAddr[16]; 1725 uint16_t resvd1; 1726 uint16_t flags; 1727 #define RNID_TD_SUPPORT 0x1 1728 #define RNID_LP_VALID 0x2 1729 } RNID_TOP_DISC; 1730 1731 typedef struct _RNID { /* Structure is in Big Endian format */ 1732 uint8_t Format; 1733 #define RNID_TOPOLOGY_DISC 0xdf 1734 uint8_t CommonLen; 1735 uint8_t resvd1; 1736 uint8_t SpecificLen; 1737 NAME_TYPE portName; 1738 NAME_TYPE nodeName; 1739 union { 1740 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 1741 } un; 1742 } RNID; 1743 1744 typedef struct _RRQ { /* Structure is in Big Endian format */ 1745 uint32_t SID; 1746 uint16_t Oxid; 1747 uint16_t Rxid; 1748 uint8_t resv[32]; /* optional association hdr */ 1749 } RRQ; 1750 1751 1752 /* This is used for RSCN command */ 1753 typedef struct _D_ID { /* Structure is in Big Endian format */ 1754 union { 1755 uint32_t word; 1756 struct { 1757 #ifdef EMLXS_BIG_ENDIAN 1758 uint8_t resv; 1759 uint8_t domain; 1760 uint8_t area; 1761 uint8_t id; 1762 #endif 1763 #ifdef EMLXS_LITTLE_ENDIAN 1764 uint8_t id; 1765 uint8_t area; 1766 uint8_t domain; 1767 uint8_t resv; 1768 #endif 1769 } b; 1770 } un; 1771 } D_ID; 1772 1773 /* 1774 * Structure to define all ELS Payload types 1775 */ 1776 1777 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 1778 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1779 uint8_t elsByte1; 1780 uint8_t elsByte2; 1781 uint8_t elsByte3; 1782 union { 1783 LS_RJT lsRjt; /* Payload for LS_RJT ELS response */ 1784 SERV_PARM logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 1785 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 1786 PRLI prli; /* Payload for PRLI/ACC */ 1787 PRLO prlo; /* Payload for PRLO/ACC */ 1788 ADISC adisc; /* Payload for ADISC/ACC */ 1789 FARP farp; /* Payload for FARP/ACC */ 1790 FAN fan; /* Payload for FAN */ 1791 SCR scr; /* Payload for SCR/ACC */ 1792 RRQ rrq; /* Payload for RRQ */ 1793 RNID rnid; /* Payload for RNID */ 1794 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1795 } un; 1796 } ELS_PKT; 1797 1798 1799 /* 1800 * Begin Structure Definitions for Mailbox Commands 1801 */ 1802 1803 typedef struct revcompat { 1804 #ifdef EMLXS_BIG_ENDIAN 1805 uint32_t ldflag:1; /* Set in SRAM descriptor */ 1806 uint32_t ldcount:7; /* For use by program load */ 1807 uint32_t kernel:4; /* Kernel ID */ 1808 uint32_t kver:4; /* Kernel compatibility version */ 1809 uint32_t SMver:4; /* Sequence Manager version, 0 if none */ 1810 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */ 1811 uint32_t BIUtype:4; /* PCI = 0 */ 1812 uint32_t BIUver:4; /* BIU version, 0 if none */ 1813 #endif 1814 #ifdef EMLXS_LITTLE_ENDIAN 1815 uint32_t BIUver:4; /* BIU version, 0 if none */ 1816 uint32_t BIUtype:4; /* PCI = 0 */ 1817 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */ 1818 uint32_t SMver:4; /* Sequence Manager version, 0 if none */ 1819 uint32_t kver:4; /* Kernel compatibility version */ 1820 uint32_t kernel:4; /* Kernel ID */ 1821 uint32_t ldcount:7; /* For use by program load */ 1822 uint32_t ldflag:1; /* Set in SRAM descriptor */ 1823 #endif 1824 } REVCOMPAT; 1825 1826 typedef struct id_word { 1827 #ifdef EMLXS_BIG_ENDIAN 1828 uint8_t Type; 1829 uint8_t Id; 1830 uint8_t Ver; 1831 uint8_t Rev; 1832 #endif 1833 #ifdef EMLXS_LITTLE_ENDIAN 1834 uint8_t Rev; 1835 uint8_t Ver; 1836 uint8_t Id; 1837 uint8_t Type; 1838 #endif 1839 union { 1840 REVCOMPAT cp; 1841 uint32_t revcomp; 1842 } un; 1843 } PROG_ID; 1844 1845 typedef struct { 1846 #ifdef EMLXS_BIG_ENDIAN 1847 uint8_t tval; 1848 uint8_t tmask; 1849 uint8_t rval; 1850 uint8_t rmask; 1851 #endif 1852 #ifdef EMLXS_LITTLE_ENDIAN 1853 uint8_t rmask; 1854 uint8_t rval; 1855 uint8_t tmask; 1856 uint8_t tval; 1857 #endif 1858 } RR_REG; 1859 1860 typedef struct { 1861 uint32_t bdeAddress; 1862 #ifdef EMLXS_BIG_ENDIAN 1863 uint32_t bdeReserved:4; 1864 uint32_t bdeAddrHigh:4; 1865 uint32_t bdeSize:24; 1866 #endif 1867 #ifdef EMLXS_LITTLE_ENDIAN 1868 uint32_t bdeSize:24; 1869 uint32_t bdeAddrHigh:4; 1870 uint32_t bdeReserved:4; 1871 #endif 1872 } ULP_BDE; 1873 1874 typedef struct ULP_BDE_64 { /* SLI-2 */ 1875 union ULP_BDE_TUS { 1876 uint32_t w; 1877 struct { 1878 #ifdef EMLXS_BIG_ENDIAN 1879 uint32_t bdeFlags:8; /* BDE Flags 0 IS SUPPORTED */ 1880 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1881 #endif 1882 #ifdef EMLXS_LITTLE_ENDIAN 1883 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1884 uint32_t bdeFlags:8; /* BDE Flags 0 IS SUPPORTED */ 1885 #endif 1886 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 1887 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 1888 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buf */ 1889 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buf, 0=xmit buf */ 1890 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit addr */ 1891 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 1892 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 1893 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 1894 1895 } f; 1896 } tus; 1897 uint32_t addrLow; 1898 uint32_t addrHigh; 1899 } ULP_BDE64; 1900 1901 #define BDE64_SIZE_WORD 0 1902 #define BPL64_SIZE_WORD 0x40 1903 1904 /* ULP */ 1905 typedef struct ULP_BPL_64 { 1906 ULP_BDE64 fccmd_payload; 1907 ULP_BDE64 fcrsp_payload; 1908 ULP_BDE64 fcdat_payload; 1909 ULP_BDE64 pat0; 1910 } ULP_BPL64; 1911 1912 typedef struct ULP_BDL { /* SLI-2 */ 1913 #ifdef EMLXS_BIG_ENDIAN 1914 uint32_t bdeFlags:8; /* BDL Flags */ 1915 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1916 #endif 1917 #ifdef EMLXS_LITTLE_ENDIAN 1918 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1919 uint32_t bdeFlags:8; /* BDL Flags */ 1920 #endif 1921 uint32_t addrLow; /* Address 0:31 */ 1922 uint32_t addrHigh; /* Address 32:63 */ 1923 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1924 } ULP_BDL; 1925 1926 typedef struct { 1927 uint8_t *fc_mptr; 1928 uint8_t *virt; /* virtual address ptr */ 1929 uint64_t phys; /* mapped address */ 1930 uint32_t size; 1931 void *data_handle; 1932 void *dma_handle; 1933 uint32_t tag; 1934 uint32_t flag; 1935 1936 #define MAP_POOL_ALLOCATED 0x00000001 1937 #define MAP_BUF_ALLOCATED 0x00000002 1938 #define MAP_TABLE_ALLOCATED 0x00000004 1939 1940 } MATCHMAP; 1941 1942 /* Structure used for a HBQ entry */ 1943 typedef struct { 1944 ULP_BDE64 bde; 1945 union UN_TAG { 1946 uint32_t w; 1947 struct { 1948 #ifdef EMLXS_BIG_ENDIAN 1949 uint32_t HBQ_tag:4; 1950 uint32_t HBQE_tag:28; 1951 #endif 1952 #ifdef EMLXS_LITTLE_ENDIAN 1953 uint32_t HBQE_tag:28; 1954 uint32_t HBQ_tag:4; 1955 #endif 1956 } ext; 1957 } unt; 1958 1959 } HBQE_t; 1960 1961 typedef struct { 1962 #ifdef EMLXS_BIG_ENDIAN 1963 uint8_t tmatch; 1964 uint8_t tmask; 1965 uint8_t rctlmatch; 1966 uint8_t rctlmask; 1967 #endif 1968 #ifdef EMLXS_LITTLE_ENDIAN 1969 uint8_t rctlmask; 1970 uint8_t rctlmatch; 1971 uint8_t tmask; 1972 uint8_t tmatch; 1973 #endif 1974 } HBQ_MASK; 1975 1976 #define EMLXS_MAX_HBQ_BUFFERS 4096 1977 1978 typedef struct { 1979 uint32_t HBQ_num_mask; /* number of mask entries in prt array */ 1980 uint32_t HBQ_recvNotify; /* Receive buffer notification */ 1981 uint32_t HBQ_numEntries; /* # of entries in HBQ */ 1982 uint32_t HBQ_headerLen; /* 0 if not profile 4 or 5 */ 1983 uint32_t HBQ_logEntry; /* Set to 1 if this HBQ used for LogEntry */ 1984 uint32_t HBQ_profile; /* Selection profile 0=all, 7=logentry */ 1985 uint32_t HBQ_ringMask; /* Binds HBQ to a ring e.g. ring2=b0100 */ 1986 uint32_t HBQ_id; /* index of this hbq in ring .HBQs[] */ 1987 uint32_t HBQ_PutIdx_next; /* Index to next HBQ slot to use */ 1988 uint32_t HBQ_PutIdx; /* HBQ slot to use */ 1989 uint32_t HBQ_GetIdx; /* Local copy of Get index from Port */ 1990 uint16_t HBQ_PostBufCnt; /* Current number of entries in list */ 1991 MATCHMAP *HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS]; 1992 MATCHMAP HBQ_host_buf; /* HBQ host buffer for HBQEs */ 1993 HBQ_MASK HBQ_Masks[6]; 1994 1995 union { 1996 uint32_t allprofiles[12]; 1997 1998 struct { 1999 #ifdef EMLXS_BIG_ENDIAN 2000 uint32_t seqlenoff:16; 2001 uint32_t maxlen:16; 2002 #endif 2003 #ifdef EMLXS_LITTLE_ENDIAN 2004 uint32_t maxlen:16; 2005 uint32_t seqlenoff:16; 2006 #endif 2007 #ifdef EMLXS_BIG_ENDIAN 2008 uint32_t rsvd1:28; 2009 uint32_t seqlenbcnt:4; 2010 #endif 2011 #ifdef EMLXS_LITTLE_ENDIAN 2012 uint32_t seqlenbcnt:4; 2013 uint32_t rsvd1:28; 2014 #endif 2015 uint32_t rsvd[10]; 2016 } profile2; 2017 2018 struct { 2019 #ifdef EMLXS_BIG_ENDIAN 2020 uint32_t seqlenoff:16; 2021 uint32_t maxlen:16; 2022 #endif 2023 #ifdef EMLXS_LITTLE_ENDIAN 2024 uint32_t maxlen:16; 2025 uint32_t seqlenoff:16; 2026 #endif 2027 #ifdef EMLXS_BIG_ENDIAN 2028 uint32_t cmdcodeoff:28; 2029 uint32_t rsvd1:12; 2030 uint32_t seqlenbcnt:4; 2031 #endif 2032 #ifdef EMLXS_LITTLE_ENDIAN 2033 uint32_t seqlenbcnt:4; 2034 uint32_t rsvd1:12; 2035 uint32_t cmdcodeoff:28; 2036 #endif 2037 uint32_t cmdmatch[8]; 2038 2039 uint32_t rsvd[2]; 2040 } profile3; 2041 2042 struct { 2043 #ifdef EMLXS_BIG_ENDIAN 2044 uint32_t seqlenoff:16; 2045 uint32_t maxlen:16; 2046 #endif 2047 #ifdef EMLXS_LITTLE_ENDIAN 2048 uint32_t maxlen:16; 2049 uint32_t seqlenoff:16; 2050 #endif 2051 #ifdef EMLXS_BIG_ENDIAN 2052 uint32_t cmdcodeoff:28; 2053 uint32_t rsvd1:12; 2054 uint32_t seqlenbcnt:4; 2055 #endif 2056 #ifdef EMLXS_LITTLE_ENDIAN 2057 uint32_t seqlenbcnt:4; 2058 uint32_t rsvd1:12; 2059 uint32_t cmdcodeoff:28; 2060 #endif 2061 uint32_t cmdmatch[8]; 2062 2063 uint32_t rsvd[2]; 2064 } profile5; 2065 2066 } profiles; 2067 2068 } HBQ_INIT_t; 2069 2070 2071 2072 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 2073 2074 2075 typedef struct { 2076 #ifdef EMLXS_BIG_ENDIAN 2077 uint32_t rsvd2:25; 2078 uint32_t acknowledgment:1; 2079 uint32_t version:1; 2080 uint32_t erase_or_prog:1; 2081 uint32_t update_flash:1; 2082 uint32_t update_ram:1; 2083 uint32_t method:1; 2084 uint32_t load_cmplt:1; 2085 #endif 2086 #ifdef EMLXS_LITTLE_ENDIAN 2087 uint32_t load_cmplt:1; 2088 uint32_t method:1; 2089 uint32_t update_ram:1; 2090 uint32_t update_flash:1; 2091 uint32_t erase_or_prog:1; 2092 uint32_t version:1; 2093 uint32_t acknowledgment:1; 2094 uint32_t rsvd2:25; 2095 #endif 2096 2097 #define DL_FROM_BDE 0 /* method */ 2098 #define DL_FROM_SLIM 1 2099 2100 #define PROGRAM_FLASH 0 /* erase_or_prog */ 2101 #define ERASE_FLASH 1 2102 2103 uint32_t dl_to_adr; 2104 uint32_t dl_len; 2105 union { 2106 uint32_t dl_from_slim_offset; 2107 ULP_BDE dl_from_bde; 2108 ULP_BDE64 dl_from_bde64; 2109 PROG_ID prog_id; 2110 } un; 2111 2112 } LOAD_SM_VAR; 2113 2114 2115 /* Structure for MB Command READ_NVPARM (02) */ 2116 2117 typedef struct { 2118 uint32_t rsvd1[3]; /* Read as all one's */ 2119 uint32_t rsvd2; /* Read as all zero's */ 2120 uint32_t portname[2]; /* N_PORT name */ 2121 uint32_t nodename[2]; /* NODE name */ 2122 #ifdef EMLXS_BIG_ENDIAN 2123 uint32_t pref_DID:24; 2124 uint32_t hardAL_PA:8; 2125 #endif 2126 #ifdef EMLXS_LITTLE_ENDIAN 2127 uint32_t hardAL_PA:8; 2128 uint32_t pref_DID:24; 2129 #endif 2130 uint32_t rsvd3[21]; /* Read as all one's */ 2131 } READ_NV_VAR; 2132 2133 2134 /* Structure for MB Command WRITE_NVPARMS (03) */ 2135 2136 typedef struct { 2137 uint32_t rsvd1[3]; /* Must be all one's */ 2138 uint32_t rsvd2; /* Must be all zero's */ 2139 uint32_t portname[2]; /* N_PORT name */ 2140 uint32_t nodename[2]; /* NODE name */ 2141 #ifdef EMLXS_BIG_ENDIAN 2142 uint32_t pref_DID:24; 2143 uint32_t hardAL_PA:8; 2144 #endif 2145 #ifdef EMLXS_LITTLE_ENDIAN 2146 uint32_t hardAL_PA:8; 2147 uint32_t pref_DID:24; 2148 #endif 2149 uint32_t rsvd3[21]; /* Must be all one's */ 2150 } WRITE_NV_VAR; 2151 2152 2153 /* Structure for MB Command RUN_BIU_DIAG (04) */ 2154 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 2155 2156 typedef struct { 2157 uint32_t rsvd1; 2158 union { 2159 struct { 2160 ULP_BDE xmit_bde; 2161 ULP_BDE rcv_bde; 2162 } s1; 2163 struct { 2164 ULP_BDE64 xmit_bde64; 2165 ULP_BDE64 rcv_bde64; 2166 } s2; 2167 } un; 2168 } BIU_DIAG_VAR; 2169 2170 2171 /* Structure for MB Command INIT_LINK (05) */ 2172 2173 typedef struct { 2174 #ifdef EMLXS_BIG_ENDIAN 2175 uint32_t rsvd1:24; 2176 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2177 #endif 2178 #ifdef EMLXS_LITTLE_ENDIAN 2179 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2180 uint32_t rsvd1:24; 2181 #endif 2182 2183 #ifdef EMLXS_BIG_ENDIAN 2184 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2185 uint8_t rsvd2; 2186 uint16_t link_flags; 2187 #endif 2188 #ifdef EMLXS_LITTLE_ENDIAN 2189 uint16_t link_flags; 2190 uint8_t rsvd2; 2191 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2192 #endif 2193 /* link_flags (=1) ENDEC loopback */ 2194 #define FLAGS_LOCAL_LB 0x01 2195 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 2196 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 2197 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 2198 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 2199 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 2200 2201 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 2202 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 2203 #define FLAGS_PREABORT_RETURN 0x4000 /* Bit 14 */ 2204 2205 uint32_t link_speed; /* NEW_FEATURE */ 2206 #define LINK_SPEED_AUTO 0 /* Auto selection */ 2207 #define LINK_SPEED_1G 1 /* 1 Gigabaud */ 2208 #define LINK_SPEED_2G 2 /* 2 Gigabaud */ 2209 2210 } INIT_LINK_VAR; 2211 2212 2213 /* Structure for MB Command DOWN_LINK (06) */ 2214 2215 typedef struct { 2216 uint32_t rsvd1; 2217 } DOWN_LINK_VAR; 2218 2219 2220 /* Structure for MB Command CONFIG_LINK (07) */ 2221 2222 typedef struct { 2223 #ifdef EMLXS_BIG_ENDIAN 2224 uint32_t cr:1; 2225 uint32_t ci:1; 2226 uint32_t cr_delay:6; 2227 uint32_t cr_count:8; 2228 uint32_t rsvd1:8; 2229 uint32_t MaxBBC:8; 2230 #endif 2231 #ifdef EMLXS_LITTLE_ENDIAN 2232 uint32_t MaxBBC:8; 2233 uint32_t rsvd1:8; 2234 uint32_t cr_count:8; 2235 uint32_t cr_delay:6; 2236 uint32_t ci:1; 2237 uint32_t cr:1; 2238 #endif 2239 uint32_t myId; 2240 uint32_t rsvd2; 2241 uint32_t edtov; 2242 uint32_t arbtov; 2243 uint32_t ratov; 2244 uint32_t rttov; 2245 uint32_t altov; 2246 uint32_t crtov; 2247 uint32_t citov; 2248 #ifdef EMLXS_BIG_ENDIAN 2249 uint32_t rrq_enable:1; 2250 uint32_t rrq_immed:1; 2251 uint32_t rsvd4:29; 2252 uint32_t ack0_enable:1; 2253 #endif 2254 #ifdef EMLXS_LITTLE_ENDIAN 2255 uint32_t ack0_enable:1; 2256 uint32_t rsvd4:29; 2257 uint32_t rrq_immed:1; 2258 uint32_t rrq_enable:1; 2259 #endif 2260 } CONFIG_LINK; 2261 2262 2263 /* Structure for MB Command PART_SLIM (08) */ 2264 2265 typedef struct { 2266 #ifdef EMLXS_BIG_ENDIAN 2267 uint32_t unused1:24; 2268 uint32_t numRing:8; 2269 #endif 2270 #ifdef EMLXS_LITTLE_ENDIAN 2271 uint32_t numRing:8; 2272 uint32_t unused1:24; 2273 #endif 2274 emlxs_ring_def_t ringdef[4]; 2275 uint32_t hbainit; 2276 } PART_SLIM_VAR; 2277 2278 2279 /* Structure for MB Command CONFIG_RING (09) */ 2280 2281 typedef struct { 2282 #ifdef EMLXS_BIG_ENDIAN 2283 uint32_t unused2:6; 2284 uint32_t recvSeq:1; 2285 uint32_t recvNotify:1; 2286 uint32_t numMask:8; 2287 uint32_t profile:8; 2288 uint32_t unused1:4; 2289 uint32_t ring:4; 2290 #endif 2291 #ifdef EMLXS_LITTLE_ENDIAN 2292 uint32_t ring:4; 2293 uint32_t unused1:4; 2294 uint32_t profile:8; 2295 uint32_t numMask:8; 2296 uint32_t recvNotify:1; 2297 uint32_t recvSeq:1; 2298 uint32_t unused2:6; 2299 #endif 2300 #ifdef EMLXS_BIG_ENDIAN 2301 uint16_t maxRespXchg; 2302 uint16_t maxOrigXchg; 2303 #endif 2304 #ifdef EMLXS_LITTLE_ENDIAN 2305 uint16_t maxOrigXchg; 2306 uint16_t maxRespXchg; 2307 #endif 2308 RR_REG rrRegs[6]; 2309 } CONFIG_RING_VAR; 2310 2311 2312 /* Structure for MB Command RESET_RING (10) */ 2313 2314 typedef struct { 2315 uint32_t ring_no; 2316 } RESET_RING_VAR; 2317 2318 2319 /* Structure for MB Command READ_CONFIG (11) */ 2320 2321 typedef struct { 2322 #ifdef EMLXS_BIG_ENDIAN 2323 uint32_t cr:1; 2324 uint32_t ci:1; 2325 uint32_t cr_delay:6; 2326 uint32_t cr_count:8; 2327 uint32_t InitBBC:8; 2328 uint32_t MaxBBC:8; 2329 #endif 2330 #ifdef EMLXS_LITTLE_ENDIAN 2331 uint32_t MaxBBC:8; 2332 uint32_t InitBBC:8; 2333 uint32_t cr_count:8; 2334 uint32_t cr_delay:6; 2335 uint32_t ci:1; 2336 uint32_t cr:1; 2337 #endif 2338 #ifdef EMLXS_BIG_ENDIAN 2339 uint32_t topology:8; 2340 uint32_t myDid:24; 2341 #endif 2342 #ifdef EMLXS_LITTLE_ENDIAN 2343 uint32_t myDid:24; 2344 uint32_t topology:8; 2345 #endif 2346 /* Defines for topology (defined previously) */ 2347 #ifdef EMLXS_BIG_ENDIAN 2348 uint32_t AR:1; 2349 uint32_t IR:1; 2350 uint32_t rsvd1:29; 2351 uint32_t ack0:1; 2352 #endif 2353 #ifdef EMLXS_LITTLE_ENDIAN 2354 uint32_t ack0:1; 2355 uint32_t rsvd1:29; 2356 uint32_t IR:1; 2357 uint32_t AR:1; 2358 #endif 2359 uint32_t edtov; 2360 uint32_t arbtov; 2361 uint32_t ratov; 2362 uint32_t rttov; 2363 uint32_t altov; 2364 uint32_t lmt; 2365 2366 #define LMT_1GB_CAPABLE 0x0004 2367 #define LMT_2GB_CAPABLE 0x0008 2368 #define LMT_4GB_CAPABLE 0x0040 2369 #define LMT_8GB_CAPABLE 0x0080 2370 #define LMT_10GB_CAPABLE 0x0100 2371 /* E2E supported on adapters >= 8GB */ 2372 #define LMT_E2E_CAPABLE (LMT_8GB_CAPABLE|LMT_10GB_CAPABLE) 2373 2374 uint32_t rsvd2; 2375 uint32_t rsvd3; 2376 uint32_t max_xri; 2377 uint32_t max_iocb; 2378 uint32_t max_rpi; 2379 uint32_t avail_xri; 2380 uint32_t avail_iocb; 2381 uint32_t avail_rpi; 2382 2383 #ifdef SLI3_SUPPORT 2384 uint32_t max_vpi; 2385 uint32_t max_alpa; 2386 uint32_t rsvd4; 2387 uint32_t avail_vpi; 2388 #else 2389 uint32_t default_rpi; 2390 #endif /* SLI3_SUPPORT */ 2391 2392 } READ_CONFIG_VAR; 2393 2394 2395 /* Structure for MB Command READ_RCONFIG (12) */ 2396 2397 typedef struct { 2398 #ifdef EMLXS_BIG_ENDIAN 2399 uint32_t rsvd2:7; 2400 uint32_t recvNotify:1; 2401 uint32_t numMask:8; 2402 uint32_t profile:8; 2403 uint32_t rsvd1:4; 2404 uint32_t ring:4; 2405 #endif 2406 #ifdef EMLXS_LITTLE_ENDIAN 2407 uint32_t ring:4; 2408 uint32_t rsvd1:4; 2409 uint32_t profile:8; 2410 uint32_t numMask:8; 2411 uint32_t recvNotify:1; 2412 uint32_t rsvd2:7; 2413 #endif 2414 #ifdef EMLXS_BIG_ENDIAN 2415 uint16_t maxResp; 2416 uint16_t maxOrig; 2417 #endif 2418 #ifdef EMLXS_LITTLE_ENDIAN 2419 uint16_t maxOrig; 2420 uint16_t maxResp; 2421 #endif 2422 RR_REG rrRegs[6]; 2423 #ifdef EMLXS_BIG_ENDIAN 2424 uint16_t cmdRingOffset; 2425 uint16_t cmdEntryCnt; 2426 uint16_t rspRingOffset; 2427 uint16_t rspEntryCnt; 2428 uint16_t nextCmdOffset; 2429 uint16_t rsvd3; 2430 uint16_t nextRspOffset; 2431 uint16_t rsvd4; 2432 #endif 2433 #ifdef EMLXS_LITTLE_ENDIAN 2434 uint16_t cmdEntryCnt; 2435 uint16_t cmdRingOffset; 2436 uint16_t rspEntryCnt; 2437 uint16_t rspRingOffset; 2438 uint16_t rsvd3; 2439 uint16_t nextCmdOffset; 2440 uint16_t rsvd4; 2441 uint16_t nextRspOffset; 2442 #endif 2443 } READ_RCONF_VAR; 2444 2445 2446 /* Structure for MB Command READ_SPARM (13) */ 2447 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2448 2449 typedef struct { 2450 uint32_t rsvd1; 2451 uint32_t rsvd2; 2452 union { 2453 ULP_BDE sp; /* This BDE points to SERV_PARM structure */ 2454 ULP_BDE64 sp64; 2455 } un; 2456 } READ_SPARM_VAR; 2457 2458 2459 /* Structure for MB Command READ_STATUS (14) */ 2460 2461 typedef struct { 2462 #ifdef EMLXS_BIG_ENDIAN 2463 uint32_t rsvd1:31; 2464 uint32_t clrCounters:1; 2465 uint16_t activeXriCnt; 2466 uint16_t activeRpiCnt; 2467 #endif 2468 #ifdef EMLXS_LITTLE_ENDIAN 2469 uint32_t clrCounters:1; 2470 uint32_t rsvd1:31; 2471 uint16_t activeRpiCnt; 2472 uint16_t activeXriCnt; 2473 #endif 2474 uint32_t xmitByteCnt; 2475 uint32_t rcvByteCnt; 2476 uint32_t xmitFrameCnt; 2477 uint32_t rcvFrameCnt; 2478 uint32_t xmitSeqCnt; 2479 uint32_t rcvSeqCnt; 2480 uint32_t totalOrigExchanges; 2481 uint32_t totalRespExchanges; 2482 uint32_t rcvPbsyCnt; 2483 uint32_t rcvFbsyCnt; 2484 } READ_STATUS_VAR; 2485 2486 2487 /* Structure for MB Command READ_RPI (15) */ 2488 /* Structure for MB Command READ_RPI64 (0x8F) */ 2489 2490 typedef struct { 2491 #ifdef EMLXS_BIG_ENDIAN 2492 uint16_t nextRpi; 2493 uint16_t reqRpi; 2494 uint32_t rsvd2:8; 2495 uint32_t DID:24; 2496 #endif 2497 #ifdef EMLXS_LITTLE_ENDIAN 2498 uint16_t reqRpi; 2499 uint16_t nextRpi; 2500 uint32_t DID:24; 2501 uint32_t rsvd2:8; 2502 #endif 2503 union { 2504 ULP_BDE sp; 2505 ULP_BDE64 sp64; 2506 } un; 2507 2508 } READ_RPI_VAR; 2509 2510 2511 /* Structure for MB Command READ_XRI (16) */ 2512 2513 typedef struct { 2514 #ifdef EMLXS_BIG_ENDIAN 2515 uint16_t nextXri; 2516 uint16_t reqXri; 2517 uint16_t rsvd1; 2518 uint16_t rpi; 2519 uint32_t rsvd2:8; 2520 uint32_t DID:24; 2521 uint32_t rsvd3:8; 2522 uint32_t SID:24; 2523 uint32_t rsvd4; 2524 uint8_t seqId; 2525 uint8_t rsvd5; 2526 uint16_t seqCount; 2527 uint16_t oxId; 2528 uint16_t rxId; 2529 uint32_t rsvd6:30; 2530 uint32_t si:1; 2531 uint32_t exchOrig:1; 2532 #endif 2533 #ifdef EMLXS_LITTLE_ENDIAN 2534 uint16_t reqXri; 2535 uint16_t nextXri; 2536 uint16_t rpi; 2537 uint16_t rsvd1; 2538 uint32_t DID:24; 2539 uint32_t rsvd2:8; 2540 uint32_t SID:24; 2541 uint32_t rsvd3:8; 2542 uint32_t rsvd4; 2543 uint16_t seqCount; 2544 uint8_t rsvd5; 2545 uint8_t seqId; 2546 uint16_t rxId; 2547 uint16_t oxId; 2548 uint32_t exchOrig:1; 2549 uint32_t si:1; 2550 uint32_t rsvd6:30; 2551 #endif 2552 } READ_XRI_VAR; 2553 2554 2555 /* Structure for MB Command READ_REV (17) */ 2556 2557 typedef struct { 2558 #ifdef EMLXS_BIG_ENDIAN 2559 uint32_t cv:1; 2560 uint32_t rr:1; 2561 uint32_t co:1; 2562 uint32_t rp:1; 2563 uint32_t cv3:1; 2564 uint32_t rf3:1; 2565 uint32_t rsvd1:10; 2566 uint32_t offset:14; 2567 uint32_t rv:2; 2568 #endif 2569 #ifdef EMLXS_LITTLE_ENDIAN 2570 2571 uint32_t rv:2; 2572 uint32_t offset:14; 2573 uint32_t rsvd1:10; 2574 uint32_t rf3:1; 2575 uint32_t cv3:1; 2576 uint32_t rp:1; 2577 uint32_t co:1; 2578 uint32_t rr:1; 2579 uint32_t cv:1; 2580 #endif 2581 uint32_t biuRev; 2582 uint32_t smRev; 2583 union { 2584 uint32_t smFwRev; 2585 struct { 2586 #ifdef EMLXS_BIG_ENDIAN 2587 uint8_t ProgType; 2588 uint8_t ProgId; 2589 uint16_t ProgVer:4; 2590 uint16_t ProgRev:4; 2591 uint16_t ProgFixLvl:2; 2592 uint16_t ProgDistType:2; 2593 uint16_t DistCnt:4; 2594 #endif 2595 #ifdef EMLXS_LITTLE_ENDIAN 2596 uint16_t DistCnt:4; 2597 uint16_t ProgDistType:2; 2598 uint16_t ProgFixLvl:2; 2599 uint16_t ProgRev:4; 2600 uint16_t ProgVer:4; 2601 uint8_t ProgId; 2602 uint8_t ProgType; 2603 #endif 2604 } b; 2605 } un; 2606 uint32_t endecRev; 2607 #ifdef EMLXS_BIG_ENDIAN 2608 uint8_t feaLevelHigh; 2609 uint8_t feaLevelLow; 2610 uint8_t fcphHigh; 2611 uint8_t fcphLow; 2612 #endif 2613 #ifdef EMLXS_LITTLE_ENDIAN 2614 uint8_t fcphLow; 2615 uint8_t fcphHigh; 2616 uint8_t feaLevelLow; 2617 uint8_t feaLevelHigh; 2618 #endif 2619 uint32_t postKernRev; 2620 uint32_t opFwRev; 2621 uint8_t opFwName[16]; 2622 2623 uint32_t sliFwRev1; 2624 uint8_t sliFwName1[16]; 2625 uint32_t sliFwRev2; 2626 uint8_t sliFwName2[16]; 2627 2628 } READ_REV_VAR; 2629 2630 #define rxSeqRev postKernRev 2631 #define txSeqRev opFwRev 2632 2633 /* Structure for MB Command READ_LINK_STAT (18) */ 2634 2635 typedef struct { 2636 uint32_t rsvd1; 2637 uint32_t linkFailureCnt; 2638 uint32_t lossSyncCnt; 2639 2640 uint32_t lossSignalCnt; 2641 uint32_t primSeqErrCnt; 2642 uint32_t invalidXmitWord; 2643 uint32_t crcCnt; 2644 uint32_t primSeqTimeout; 2645 uint32_t elasticOverrun; 2646 uint32_t arbTimeout; 2647 2648 uint32_t rxBufCredit; 2649 uint32_t rxBufCreditCur; 2650 2651 uint32_t txBufCredit; 2652 uint32_t txBufCreditCur; 2653 2654 uint32_t EOFaCnt; 2655 uint32_t EOFdtiCnt; 2656 uint32_t EOFniCnt; 2657 uint32_t SOFfCnt; 2658 2659 } READ_LNK_VAR; 2660 2661 2662 /* Structure for MB Command REG_LOGIN (19) */ 2663 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2664 2665 typedef struct { 2666 #ifdef EMLXS_BIG_ENDIAN 2667 uint16_t rsvd1; 2668 uint16_t rpi; 2669 uint32_t rsvd2:8; 2670 uint32_t did:24; 2671 #endif 2672 #ifdef EMLXS_LITTLE_ENDIAN 2673 uint16_t rpi; 2674 uint16_t rsvd1; 2675 uint32_t did:24; 2676 uint32_t rsvd2:8; 2677 #endif 2678 union { 2679 ULP_BDE sp; 2680 ULP_BDE64 sp64; 2681 } un; 2682 2683 #ifdef SLI3_SUPPORT 2684 #ifdef EMLXS_BIG_ENDIAN 2685 uint16_t rsvd6; 2686 uint16_t vpi; 2687 #endif 2688 #ifdef EMLXS_LITTLE_ENDIAN 2689 uint16_t vpi; 2690 uint16_t rsvd6; 2691 #endif 2692 #endif /* SLI3_SUPPORT */ 2693 2694 } REG_LOGIN_VAR; 2695 2696 /* Word 30 contents for REG_LOGIN */ 2697 typedef union { 2698 struct { 2699 #ifdef EMLXS_BIG_ENDIAN 2700 uint16_t rsvd1:12; 2701 uint16_t class:4; 2702 uint16_t xri; 2703 #endif 2704 #ifdef EMLXS_LITTLE_ENDIAN 2705 uint16_t xri; 2706 uint16_t class:4; 2707 uint16_t rsvd1:12; 2708 #endif 2709 } f; 2710 uint32_t word; 2711 } REG_WD30; 2712 2713 2714 /* Structure for MB Command UNREG_LOGIN (20) */ 2715 2716 typedef struct { 2717 #ifdef EMLXS_BIG_ENDIAN 2718 uint16_t rsvd1; 2719 uint16_t rpi; 2720 #endif 2721 #ifdef EMLXS_LITTLE_ENDIAN 2722 uint16_t rpi; 2723 uint16_t rsvd1; 2724 #endif 2725 2726 #ifdef SLI3_SUPPORT 2727 uint32_t rsvd2; 2728 uint32_t rsvd3; 2729 uint32_t rsvd4; 2730 uint32_t rsvd5; 2731 #ifdef EMLXS_BIG_ENDIAN 2732 uint16_t rsvd6; 2733 uint16_t vpi; 2734 #endif 2735 #ifdef EMLXS_LITTLE_ENDIAN 2736 uint16_t vpi; 2737 uint16_t rsvd6; 2738 #endif 2739 #endif /* SLI3_SUPPORT */ 2740 2741 } UNREG_LOGIN_VAR; 2742 2743 2744 /* Structure for MB Command UNREG_D_ID (0x23) */ 2745 2746 typedef struct { 2747 uint32_t did; 2748 2749 #ifdef SLI3_SUPPORT 2750 uint32_t rsvd2; 2751 uint32_t rsvd3; 2752 uint32_t rsvd4; 2753 uint32_t rsvd5; 2754 #ifdef EMLXS_BIG_ENDIAN 2755 uint16_t rsvd6; 2756 uint16_t vpi; 2757 #endif 2758 #ifdef EMLXS_LITTLE_ENDIAN 2759 uint16_t vpi; 2760 uint16_t rsvd6; 2761 #endif 2762 #endif /* SLI3_SUPPORT */ 2763 2764 } UNREG_D_ID_VAR; 2765 2766 2767 /* Structure for MB Command READ_LA (21) */ 2768 /* Structure for MB Command READ_LA64 (0x95) */ 2769 2770 typedef struct { 2771 uint32_t eventTag; /* Event tag */ 2772 #ifdef EMLXS_BIG_ENDIAN 2773 uint32_t rsvd2:19; 2774 uint32_t fa:1; 2775 uint32_t mm:1; 2776 uint32_t tc:1; 2777 uint32_t pb:1; 2778 uint32_t il:1; 2779 uint32_t attType:8; 2780 #endif 2781 #ifdef EMLXS_LITTLE_ENDIAN 2782 uint32_t attType:8; 2783 uint32_t il:1; 2784 uint32_t pb:1; 2785 uint32_t tc:1; 2786 uint32_t mm:1; 2787 uint32_t fa:1; 2788 uint32_t rsvd2:19; 2789 #endif 2790 #define AT_RESERVED 0x00 /* Reserved - attType */ 2791 #define AT_LINK_UP 0x01 /* Link is up */ 2792 #define AT_LINK_DOWN 0x02 /* Link is down */ 2793 #ifdef EMLXS_BIG_ENDIAN 2794 uint8_t granted_AL_PA; 2795 uint8_t lipAlPs; 2796 uint8_t lipType; 2797 uint8_t topology; 2798 #endif 2799 #ifdef EMLXS_LITTLE_ENDIAN 2800 uint8_t topology; 2801 uint8_t lipType; 2802 uint8_t lipAlPs; 2803 uint8_t granted_AL_PA; 2804 #endif 2805 2806 /* lipType */ 2807 /* An L_PORT initing (F7, AL_PS) - lipType */ 2808 #define LT_PORT_INIT 0x00 2809 2810 /* Err @L_PORT rcv'er (F8, AL_PS) */ 2811 #define LT_PORT_ERR 0x01 2812 2813 /* Lip Reset of some other port */ 2814 #define LT_RESET_APORT 0x02 2815 2816 #define LT_RESET_MYPORT 0x03 /* Lip Reset of my port */ 2817 2818 /* topology */ 2819 /* Topology is pt-pt pt-fabric */ 2820 #define TOPOLOGY_PT_PT 0x01 2821 /* Topology is FC-AL (private) */ 2822 #define TOPOLOGY_LOOP 0x02 2823 2824 union { 2825 /* This BDE points to a 128 byte buffer to */ 2826 ULP_BDE lilpBde; 2827 /* store the LILP AL_PA position map into */ 2828 ULP_BDE64 lilpBde64; 2829 } un; 2830 #ifdef EMLXS_BIG_ENDIAN 2831 uint32_t Dlu:1; 2832 uint32_t Dtf:1; 2833 uint32_t Drsvd2:14; 2834 uint32_t DlnkSpeed:8; 2835 uint32_t DnlPort:4; 2836 uint32_t Dtx:2; 2837 uint32_t Drx:2; 2838 #endif 2839 #ifdef EMLXS_LITTLE_ENDIAN 2840 uint32_t Drx:2; 2841 uint32_t Dtx:2; 2842 uint32_t DnlPort:4; 2843 uint32_t DlnkSpeed:8; 2844 uint32_t Drsvd2:14; 2845 uint32_t Dtf:1; 2846 uint32_t Dlu:1; 2847 #endif 2848 #ifdef EMLXS_BIG_ENDIAN 2849 uint32_t Ulu:1; 2850 uint32_t Utf:1; 2851 uint32_t Ursvd2:14; 2852 uint32_t UlnkSpeed:8; 2853 uint32_t UnlPort:4; 2854 uint32_t Utx:2; 2855 uint32_t Urx:2; 2856 #endif 2857 #ifdef EMLXS_LITTLE_ENDIAN 2858 uint32_t Urx:2; 2859 uint32_t Utx:2; 2860 uint32_t UnlPort:4; 2861 uint32_t UlnkSpeed:8; 2862 uint32_t Ursvd2:14; 2863 uint32_t Utf:1; 2864 uint32_t Ulu:1; 2865 #endif 2866 2867 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 2868 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 2869 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 2870 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 2871 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 2872 2873 } READ_LA_VAR; 2874 2875 2876 /* Structure for MB Command CLEAR_LA (22) */ 2877 2878 typedef struct { 2879 uint32_t eventTag; /* Event tag */ 2880 uint32_t rsvd1; 2881 } CLEAR_LA_VAR; 2882 2883 /* Structure for MB Command DUMP */ 2884 2885 typedef struct { 2886 #ifdef EMLXS_BIG_ENDIAN 2887 uint32_t rsvd:25; 2888 uint32_t ra:1; 2889 uint32_t co:1; 2890 uint32_t cv:1; 2891 uint32_t type:4; 2892 2893 uint32_t entry_index:16; 2894 uint32_t region_id:16; 2895 #endif 2896 #ifdef EMLXS_LITTLE_ENDIAN 2897 uint32_t type:4; 2898 uint32_t cv:1; 2899 uint32_t co:1; 2900 uint32_t ra:1; 2901 uint32_t rsvd:25; 2902 2903 uint32_t region_id:16; 2904 uint32_t entry_index:16; 2905 #endif 2906 uint32_t base_adr; 2907 uint32_t word_cnt; 2908 uint32_t resp_offset; 2909 } DUMP_VAR; 2910 2911 /* 2912 * Dump type 2913 */ 2914 #define DMP_MEM_REG 0x1 2915 #define DMP_NV_PARAMS 0x2 2916 2917 /* 2918 * Dump region ID 2919 */ 2920 #define NODE_CFG_A_REGION_ID 0 2921 #define NODE_CFG_B_REGION_ID 1 2922 #define NODE_CFG_C_REGION_ID 2 2923 #define NODE_CFG_D_REGION_ID 3 2924 #define WAKE_UP_PARMS_REGION_ID 4 2925 #define DEF_PCI_CFG_REGION_ID 5 2926 #define PCI_CFG_1_REGION_ID 6 2927 #define PCI_CFG_2_REGION_ID 7 2928 #define RSVD1_REGION_ID 8 2929 #define RSVD2_REGION_ID 9 2930 #define RSVD3_REGION_ID 10 2931 #define RSVD4_REGION_ID 11 2932 #define RSVD5_REGION_ID 12 2933 #define RSVD6_REGION_ID 13 2934 #define RSVD7_REGION_ID 14 2935 #define DIAG_TRACE_REGION_ID 15 2936 #define WWN_REGION_ID 16 2937 2938 #define DMP_VPD_REGION 0xe 2939 #define DMP_VPD_SIZE 1024 2940 #define DMP_VPD_DUMP_WCOUNT 25 2941 2942 2943 2944 /* Structure for MB Command UPDATE_CFG */ 2945 2946 typedef struct { 2947 #ifdef EMLXS_BIG_ENDIAN 2948 uint32_t rsvd2:16; 2949 uint32_t proc_type:8; 2950 uint32_t rsvd1:1; 2951 uint32_t Abit:1; 2952 uint32_t Obit:1; 2953 uint32_t Vbit:1; 2954 uint32_t req_type:4; 2955 #define INIT_REGION 1 2956 #define UPDATE_DATA 2 2957 #define CLEAN_UP_CFG 3 2958 uint32_t entry_len:16; 2959 uint32_t region_id:16; 2960 #endif 2961 2962 #ifdef EMLXS_LITTLE_ENDIAN 2963 uint32_t req_type:4; 2964 #define INIT_REGION 1 2965 #define UPDATE_DATA 2 2966 #define CLEAN_UP_CFG 3 2967 uint32_t Vbit:1; 2968 uint32_t Obit:1; 2969 uint32_t Abit:1; 2970 uint32_t rsvd1:1; 2971 uint32_t proc_type:8; 2972 uint32_t rsvd2:16; 2973 2974 uint32_t region_id:16; 2975 uint32_t entry_len:16; 2976 #endif 2977 2978 uint32_t rsp_info; 2979 uint32_t byte_len; 2980 uint32_t cfg_data; 2981 2982 } UPDATE_CFG_VAR; 2983 2984 /* Structure for MB Command DEL_LD_ENTRY (29) */ 2985 2986 typedef struct { 2987 #ifdef EMLXS_LITTLE_ENDIAN 2988 uint32_t list_req:2; 2989 uint32_t list_rsp:2; 2990 uint32_t rsvd:28; 2991 #else 2992 uint32_t rsvd:28; 2993 uint32_t list_rsp:2; 2994 uint32_t list_req:2; 2995 #endif 2996 2997 #define FLASH_LOAD_LIST 1 2998 #define RAM_LOAD_LIST 2 2999 #define BOTH_LISTS 3 3000 3001 PROG_ID prog_id; 3002 3003 } DEL_LD_ENTRY_VAR; 3004 3005 /* Structure for MB Command LOAD_AREA (81) */ 3006 typedef struct { 3007 #ifdef EMLXS_LITTLE_ENDIAN 3008 uint32_t load_cmplt:1; 3009 uint32_t method:1; 3010 uint32_t rsvd1:1; 3011 uint32_t update_flash:1; 3012 uint32_t erase_or_prog:1; 3013 uint32_t version:1; 3014 uint32_t rsvd2:2; 3015 uint32_t progress:8; 3016 uint32_t step:8; 3017 uint32_t area_id:8; 3018 #else 3019 uint32_t area_id:8; 3020 uint32_t step:8; 3021 uint32_t progress:8; 3022 uint32_t rsvd2:2; 3023 uint32_t version:1; 3024 uint32_t erase_or_prog:1; 3025 uint32_t update_flash:1; 3026 uint32_t rsvd1:1; 3027 uint32_t method:1; 3028 uint32_t load_cmplt:1; 3029 #endif 3030 uint32_t dl_to_adr; 3031 uint32_t dl_len; 3032 union { 3033 uint32_t dl_from_slim_offset; 3034 ULP_BDE dl_from_bde; 3035 ULP_BDE64 dl_from_bde64; 3036 PROG_ID prog_id; 3037 } un; 3038 } LOAD_AREA_VAR; 3039 3040 /* Structure for MB Command LOAD_EXP_ROM (9C) */ 3041 typedef struct { 3042 #ifdef EMLXS_LITTLE_ENDIAN 3043 uint32_t rsvd1:8; 3044 uint32_t progress:8; 3045 uint32_t step:8; 3046 uint32_t rsvd2:8; 3047 #else 3048 uint32_t rsvd2:8; 3049 uint32_t step:8; 3050 uint32_t progress:8; 3051 uint32_t rsvd1:8; 3052 #endif 3053 uint32_t dl_to_adr; 3054 uint32_t rsvd3; 3055 union { 3056 uint32_t word[2]; 3057 PROG_ID prog_id; 3058 } un; 3059 } LOAD_EXP_ROM_VAR; 3060 3061 3062 /* Structure for MB Command CONFIG_HBQ (7C) */ 3063 3064 typedef struct { 3065 #ifdef EMLXS_BIG_ENDIAN 3066 uint32_t rsvd1:7; 3067 uint32_t recvNotify:1; /* Receive Notification */ 3068 uint32_t numMask:8; /* # Mask Entries */ 3069 uint32_t profile:8; /* Selection Profile */ 3070 uint32_t rsvd2:8; 3071 #endif 3072 #ifdef EMLXS_LITTLE_ENDIAN 3073 uint32_t rsvd2:8; 3074 uint32_t profile:8; /* Selection Profile */ 3075 uint32_t numMask:8; /* # Mask Entries */ 3076 uint32_t recvNotify:1; /* Receive Notification */ 3077 uint32_t rsvd1:7; 3078 #endif 3079 3080 #ifdef EMLXS_BIG_ENDIAN 3081 uint32_t hbqId:16; 3082 uint32_t rsvd3:12; 3083 uint32_t ringMask:4; 3084 #endif 3085 #ifdef EMLXS_LITTLE_ENDIAN 3086 uint32_t ringMask:4; 3087 uint32_t rsvd3:12; 3088 uint32_t hbqId:16; 3089 #endif 3090 3091 #ifdef EMLXS_BIG_ENDIAN 3092 uint32_t numEntries:16; 3093 uint32_t rsvd4:8; 3094 uint32_t headerLen:8; 3095 #endif 3096 #ifdef EMLXS_LITTLE_ENDIAN 3097 uint32_t headerLen:8; 3098 uint32_t rsvd4:8; 3099 uint32_t numEntries:16; 3100 #endif 3101 3102 uint32_t hbqaddrLow; 3103 uint32_t hbqaddrHigh; 3104 3105 #ifdef EMLXS_BIG_ENDIAN 3106 uint32_t rsvd5:31; 3107 uint32_t logEntry:1; 3108 #endif 3109 #ifdef EMLXS_LITTLE_ENDIAN 3110 uint32_t logEntry:1; 3111 uint32_t rsvd5:31; 3112 #endif 3113 3114 uint32_t rsvd6; /* w7 */ 3115 uint32_t rsvd7; /* w8 */ 3116 uint32_t rsvd8; /* w9 */ 3117 3118 HBQ_MASK hbqMasks[6]; 3119 3120 union { 3121 uint32_t allprofiles[12]; 3122 3123 struct { 3124 #ifdef EMLXS_BIG_ENDIAN 3125 uint32_t seqlenoff:16; 3126 uint32_t maxlen:16; 3127 #endif 3128 #ifdef EMLXS_LITTLE_ENDIAN 3129 uint32_t maxlen:16; 3130 uint32_t seqlenoff:16; 3131 #endif 3132 #ifdef EMLXS_BIG_ENDIAN 3133 uint32_t rsvd1:28; 3134 uint32_t seqlenbcnt:4; 3135 #endif 3136 #ifdef EMLXS_LITTLE_ENDIAN 3137 uint32_t seqlenbcnt:4; 3138 uint32_t rsvd1:28; 3139 #endif 3140 uint32_t rsvd[10]; 3141 } profile2; 3142 3143 struct { 3144 #ifdef EMLXS_BIG_ENDIAN 3145 uint32_t seqlenoff:16; 3146 uint32_t maxlen:16; 3147 #endif 3148 #ifdef EMLXS_LITTLE_ENDIAN 3149 uint32_t maxlen:16; 3150 uint32_t seqlenoff:16; 3151 #endif 3152 #ifdef EMLXS_BIG_ENDIAN 3153 uint32_t cmdcodeoff:28; 3154 uint32_t rsvd1:12; 3155 uint32_t seqlenbcnt:4; 3156 #endif 3157 #ifdef EMLXS_LITTLE_ENDIAN 3158 uint32_t seqlenbcnt:4; 3159 uint32_t rsvd1:12; 3160 uint32_t cmdcodeoff:28; 3161 #endif 3162 uint32_t cmdmatch[8]; 3163 3164 uint32_t rsvd[2]; 3165 } profile3; 3166 3167 struct { 3168 #ifdef EMLXS_BIG_ENDIAN 3169 uint32_t seqlenoff:16; 3170 uint32_t maxlen:16; 3171 #endif 3172 #ifdef EMLXS_LITTLE_ENDIAN 3173 uint32_t maxlen:16; 3174 uint32_t seqlenoff:16; 3175 #endif 3176 #ifdef EMLXS_BIG_ENDIAN 3177 uint32_t cmdcodeoff:28; 3178 uint32_t rsvd1:12; 3179 uint32_t seqlenbcnt:4; 3180 #endif 3181 #ifdef EMLXS_LITTLE_ENDIAN 3182 uint32_t seqlenbcnt:4; 3183 uint32_t rsvd1:12; 3184 uint32_t cmdcodeoff:28; 3185 #endif 3186 uint32_t cmdmatch[8]; 3187 3188 uint32_t rsvd[2]; 3189 } profile5; 3190 3191 } profiles; 3192 3193 } CONFIG_HBQ_VAR; 3194 3195 3196 /* Structure for MB Command REG_VPI(0x96) */ 3197 typedef struct { 3198 #ifdef EMLXS_BIG_ENDIAN 3199 uint32_t rsvd1; 3200 uint32_t rsvd2:8; 3201 uint32_t sid:24; 3202 uint32_t rsvd3; 3203 uint32_t rsvd4; 3204 uint32_t rsvd5; 3205 uint16_t rsvd6; 3206 uint16_t vpi; 3207 #endif 3208 #ifdef EMLXS_LITTLE_ENDIAN 3209 uint32_t rsvd1; 3210 uint32_t sid:24; 3211 uint32_t rsvd2:8; 3212 uint32_t rsvd3; 3213 uint32_t rsvd4; 3214 uint32_t rsvd5; 3215 uint16_t vpi; 3216 uint16_t rsvd6; 3217 #endif 3218 } REG_VPI_VAR; 3219 3220 /* Structure for MB Command UNREG_VPI (0x97) */ 3221 typedef struct { 3222 uint32_t rsvd1; 3223 uint32_t rsvd2; 3224 uint32_t rsvd3; 3225 uint32_t rsvd4; 3226 uint32_t rsvd5; 3227 #ifdef EMLXS_BIG_ENDIAN 3228 uint16_t rsvd6; 3229 uint16_t vpi; 3230 #endif 3231 #ifdef EMLXS_LITTLE_ENDIAN 3232 uint16_t vpi; 3233 uint16_t rsvd6; 3234 #endif 3235 3236 } UNREG_VPI_VAR; 3237 3238 3239 typedef struct { 3240 #ifdef EMLXS_BIG_ENDIAN 3241 uint32_t read_log:1; 3242 uint32_t clear_log:1; 3243 uint32_t mbox_rsp:1; 3244 uint32_t resv:28; 3245 #endif 3246 #ifdef EMLXS_LITTLE_ENDIAN 3247 uint32_t resv:28; 3248 uint32_t mbox_rsp:1; 3249 uint32_t clear_log:1; 3250 uint32_t read_log:1; 3251 #endif 3252 3253 uint32_t offset; 3254 3255 union { 3256 ULP_BDE sp; 3257 ULP_BDE64 sp64; 3258 } un; 3259 3260 } READ_EVT_LOG_VAR; 3261 3262 3263 /* Structure for MB Command CONFIG_PORT (0x88) */ 3264 3265 3266 #ifdef SLI3_SUPPORT 3267 3268 typedef struct { 3269 #ifdef EMLXS_BIG_ENDIAN 3270 uint32_t cBE:1; 3271 uint32_t cET:1; 3272 uint32_t cHpcb:1; 3273 uint32_t rMA:1; 3274 uint32_t sli_mode:4; 3275 uint32_t pcbLen:24; /* bit 23:0 of memory based port cfg block */ 3276 #endif 3277 #ifdef EMLXS_LITTLE_ENDIAN 3278 uint32_t pcbLen:24; /* bit 23:0 of memory based port cfg block */ 3279 uint32_t sli_mode:4; 3280 uint32_t rMA:1; 3281 uint32_t cHpcb:1; 3282 uint32_t cET:1; 3283 uint32_t cBE:1; 3284 #endif 3285 3286 uint32_t pcbLow; /* bit 31:0 of memory based port cfg block */ 3287 uint32_t pcbHigh; /* bit 63:32 of memory based port cfg block */ 3288 uint32_t hbainit[5]; 3289 3290 #ifdef EMLXS_BIG_ENDIAN 3291 uint32_t hps:1; /* Host pointers in SLIM */ 3292 uint32_t rsvd:31; 3293 #endif 3294 #ifdef EMLXS_LITTLE_ENDIAN 3295 uint32_t rsvd:31; 3296 uint32_t hps:1; /* Host pointers in SLIM */ 3297 #endif 3298 3299 #ifdef EMLXS_BIG_ENDIAN 3300 uint32_t rsvd1:24; 3301 uint32_t cmv:1; /* Configure Max VPIs */ 3302 uint32_t ccrp:1; /* Config Command Ring Polling */ 3303 uint32_t csah:1; /* Configure Synchronous Abort Handling */ 3304 uint32_t chbs:1; /* Cofigure Host Backing store */ 3305 uint32_t cinb:1; /* Enable Interrupt Notification Block */ 3306 uint32_t cerbm:1; /* Configure Enhanced Receive Buf Mgmt */ 3307 uint32_t cmx:1; /* Configure Max XRIs */ 3308 uint32_t cmr:1; /* Configure Max RPIs */ 3309 #endif 3310 #ifdef EMLXS_LITTLE_ENDIAN 3311 uint32_t cmr:1; /* Configure Max RPIs */ 3312 uint32_t cmx:1; /* Configure Max XRIs */ 3313 uint32_t cerbm:1; /* Configure Enhanced Receive Buf Mgmt */ 3314 uint32_t cinb:1; /* Enable Interrupt Notification Block */ 3315 uint32_t chbs:1; /* Cofigure Host Backing store */ 3316 uint32_t csah:1; /* Configure Synchronous Abort Handling */ 3317 uint32_t ccrp:1; /* Config Command Ring Polling */ 3318 uint32_t cmv:1; /* Configure Max VPIs */ 3319 uint32_t rsvd1:24; /* Reserved */ 3320 #endif 3321 #ifdef EMLXS_BIG_ENDIAN 3322 uint32_t rsvd2:24; /* Reserved */ 3323 uint32_t gmv:1; /* Grant Max VPIs */ 3324 uint32_t gcrp:1; /* Grant Command Ring Polling */ 3325 uint32_t gsah:1; /* Grant Synchronous Abort Handling */ 3326 uint32_t ghbs:1; /* Grant Host Backing Store */ 3327 uint32_t ginb:1; /* Grant Interrupt Notification Block */ 3328 uint32_t gerbm:1; /* Grant ERBM Request */ 3329 uint32_t gmx:1; /* Grant Max XRIs */ 3330 uint32_t gmr:1; /* Grant Max RPIs */ 3331 #endif 3332 #ifdef EMLXS_LITTLE_ENDIAN 3333 uint32_t gmr:1; /* Grant Max RPIs */ 3334 uint32_t gmx:1; /* Grant Max XRIs */ 3335 uint32_t gerbm:1; /* Grant ERBM Request */ 3336 uint32_t ginb:1; /* Grant Interrupt Notification Block */ 3337 uint32_t ghbs:1; /* Grant Host Backing Store */ 3338 uint32_t gsah:1; /* Grant Synchronous Abort Handling */ 3339 uint32_t gcrp:1; /* Grant Command Ring Polling */ 3340 uint32_t gmv:1; /* Grant Max VPIs */ 3341 uint32_t rsvd2:24; /* Reserved */ 3342 #endif 3343 3344 #ifdef EMLXS_BIG_ENDIAN 3345 uint32_t max_rpi:16; /* Max RPIs Port should configure */ 3346 uint32_t max_xri:16; /* Max XRIs Port should configure */ 3347 #endif 3348 #ifdef EMLXS_LITTLE_ENDIAN 3349 uint32_t max_xri:16; /* Max XRIs Port should configure */ 3350 uint32_t max_rpi:16; /* Max RPIs Port should configure */ 3351 #endif 3352 3353 #ifdef EMLXS_BIG_ENDIAN 3354 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */ 3355 uint32_t rsvd3:16; /* Max HBQs Host expect to configure */ 3356 #endif 3357 #ifdef EMLXS_LITTLE_ENDIAN 3358 uint32_t rsvd3:16; /* Max HBQs Host expect to configure */ 3359 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */ 3360 #endif 3361 3362 uint32_t rsvd4; /* Reserved */ 3363 3364 #ifdef EMLXS_BIG_ENDIAN 3365 uint32_t rsvd5:16; /* Reserved */ 3366 uint32_t vpi_max:16; /* Max number of virt N-Ports */ 3367 #endif 3368 #ifdef EMLXS_LITTLE_ENDIAN 3369 uint32_t vpi_max:16; /* Max number of virt N-Ports */ 3370 uint32_t rsvd5:16; /* Reserved */ 3371 #endif 3372 3373 } CONFIG_PORT_VAR; 3374 3375 #else /* !SLI3_SUPPORT */ 3376 3377 typedef struct { 3378 uint32_t pcbLen; 3379 uint32_t pcbLow; /* bit 31:0 of memory based port cfg block */ 3380 uint32_t pcbHigh; /* bit 63:32 of memory based port cfg block */ 3381 uint32_t hbainit; 3382 } CONFIG_PORT_VAR; 3383 3384 #endif /* SLI3_SUPPORT */ 3385 3386 3387 3388 /* SLI-2 Port Control Block */ 3389 3390 /* SLIM POINTER */ 3391 #define SLIMOFF 0x30 /* WORD */ 3392 3393 typedef struct _SLI2_RDSC { 3394 uint32_t cmdEntries; 3395 uint32_t cmdAddrLow; 3396 uint32_t cmdAddrHigh; 3397 3398 uint32_t rspEntries; 3399 uint32_t rspAddrLow; 3400 uint32_t rspAddrHigh; 3401 } SLI2_RDSC; 3402 3403 typedef struct _PCB { 3404 #ifdef EMLXS_BIG_ENDIAN 3405 uint32_t type:8; 3406 #define TYPE_NATIVE_SLI2 0x01; 3407 uint32_t feature:8; 3408 #define FEATURE_INITIAL_SLI2 0x01; 3409 uint32_t rsvd:12; 3410 uint32_t maxRing:4; 3411 #endif 3412 #ifdef EMLXS_LITTLE_ENDIAN 3413 uint32_t maxRing:4; 3414 uint32_t rsvd:12; 3415 uint32_t feature:8; 3416 #define FEATURE_INITIAL_SLI2 0x01; 3417 uint32_t type:8; 3418 #define TYPE_NATIVE_SLI2 0x01; 3419 #endif 3420 3421 uint32_t mailBoxSize; 3422 uint32_t mbAddrLow; 3423 uint32_t mbAddrHigh; 3424 3425 uint32_t hgpAddrLow; 3426 uint32_t hgpAddrHigh; 3427 3428 uint32_t pgpAddrLow; 3429 uint32_t pgpAddrHigh; 3430 SLI2_RDSC rdsc[MAX_RINGS_AVAILABLE]; 3431 } PCB; 3432 3433 /* NEW_FEATURE */ 3434 typedef struct { 3435 #ifdef EMLXS_BIG_ENDIAN 3436 uint32_t rsvd0:27; 3437 uint32_t discardFarp:1; 3438 uint32_t IPEnable:1; 3439 uint32_t nodeName:1; 3440 uint32_t portName:1; 3441 uint32_t filterEnable:1; 3442 #endif 3443 #ifdef EMLXS_LITTLE_ENDIAN 3444 uint32_t filterEnable:1; 3445 uint32_t portName:1; 3446 uint32_t nodeName:1; 3447 uint32_t IPEnable:1; 3448 uint32_t discardFarp:1; 3449 uint32_t rsvd:27; 3450 #endif 3451 NAME_TYPE portname; 3452 NAME_TYPE nodename; 3453 uint32_t rsvd1; 3454 uint32_t rsvd2; 3455 uint32_t rsvd3; 3456 uint32_t IPAddress; 3457 } CONFIG_FARP_VAR; 3458 3459 3460 /* NEW_FEATURE */ 3461 typedef struct { 3462 #ifdef EMLXS_BIG_ENDIAN 3463 uint32_t defaultMessageNumber:16; 3464 uint32_t rsvd1:3; 3465 uint32_t nid:5; 3466 uint32_t rsvd2:5; 3467 uint32_t defaultPresent:1; 3468 uint32_t addAssociations:1; 3469 uint32_t reportAssociations:1; 3470 #endif 3471 #ifdef EMLXS_LITTLE_ENDIAN 3472 uint32_t reportAssociations:1; 3473 uint32_t addAssociations:1; 3474 uint32_t defaultPresent:1; 3475 uint32_t rsvd2:5; 3476 uint32_t nid:5; 3477 uint32_t rsvd1:3; 3478 uint32_t defaultMessageNumber:16; 3479 #endif 3480 uint32_t attConditions; 3481 uint8_t attentionId[16]; 3482 uint16_t messageNumberByHA[32]; 3483 uint16_t messageNumberByID[16]; 3484 uint32_t rsvd3; 3485 } CONFIG_MSI_VAR; 3486 3487 3488 /* NEW_FEATURE */ 3489 typedef struct { 3490 #ifdef EMLXS_BIG_ENDIAN 3491 uint32_t defaultMessageNumber:8; 3492 uint32_t rsvd1:11; 3493 uint32_t nid:5; 3494 uint32_t rsvd2:5; 3495 uint32_t defaultPresent:1; 3496 uint32_t addAssociations:1; 3497 uint32_t reportAssociations:1; 3498 #endif 3499 #ifdef EMLXS_LITTLE_ENDIAN 3500 uint32_t reportAssociations:1; 3501 uint32_t addAssociations:1; 3502 uint32_t defaultPresent:1; 3503 uint32_t rsvd2:5; 3504 uint32_t nid:5; 3505 uint32_t rsvd1:11; 3506 uint32_t defaultMessageNumber:8; 3507 #endif 3508 uint32_t attConditions1; 3509 uint32_t attConditions2; 3510 uint8_t attentionId[16]; 3511 uint8_t messageNumberByHA[64]; 3512 uint8_t messageNumberByID[16]; 3513 uint32_t autoClearByHA1; 3514 uint32_t autoClearByHA2; 3515 uint32_t autoClearByID; 3516 uint32_t resv3; 3517 3518 } CONFIG_MSIX_VAR; 3519 3520 3521 /* Union of all Mailbox Command types */ 3522 3523 typedef union { 3524 uint32_t varWords[31]; 3525 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3526 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3527 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3528 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3529 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3530 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3531 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3532 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3533 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3534 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3535 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3536 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3537 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3538 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3539 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3540 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3541 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3542 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3543 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3544 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3545 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 3546 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3547 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3548 UPDATE_CFG_VAR varUpdateCfg; /* cmd = 0x1b Warm Start UPDATE_CFG */ 3549 DEL_LD_ENTRY_VAR varDelLdEntry; /* cmd = 0x1d (DEL_LD_ENTRY) */ 3550 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3551 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) */ 3552 CONFIG_MSI_VAR varCfgMSI; /* cmd = 0x90 (CONFIG_MSI) */ 3553 CONFIG_MSIX_VAR varCfgMSIX; /* cmd = 0x30 (CONFIG_MSIX) */ 3554 CONFIG_HBQ_VAR varCfgHbq; /* cmd = 0x7C (CONFIG_HBQ) */ 3555 LOAD_AREA_VAR varLdArea; /* cmd = 0x81 (LOAD_AREA) */ 3556 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3557 LOAD_EXP_ROM_VAR varLdExpRom; /* cmd = 0x9C (LOAD_XP_ROM) */ 3558 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3559 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3560 READ_EVT_LOG_VAR varRdEvtLog; /* cmd = 0x38 (READ_EVENT_LOG) */ 3561 3562 } MAILVARIANTS; 3563 3564 #define MAILBOX_CMD_BSIZE 128 3565 #define MAILBOX_CMD_WSIZE 32 3566 3567 3568 /* 3569 * SLI-2 specific structures 3570 */ 3571 3572 typedef struct _SLI1_DESC { 3573 emlxs_rings_t mbxCring[4]; 3574 uint32_t mbxUnused[24]; 3575 } SLI1_DESC; /* 128 bytes */ 3576 3577 typedef struct { 3578 uint32_t cmdPutInx; 3579 uint32_t rspGetInx; 3580 } HGP; 3581 3582 typedef struct { 3583 uint32_t cmdGetInx; 3584 uint32_t rspPutInx; 3585 } PGP; 3586 3587 #ifdef SLI3_SUPPORT 3588 typedef struct _SLI2_DESC { 3589 HGP host[4]; 3590 PGP port[4]; 3591 uint32_t HBQ_PortGetIdx[16]; 3592 } SLI2_DESC; /* 128 bytes */ 3593 #else 3594 typedef struct _SLI2_DESC { 3595 HGP host[4]; /* 8 words */ 3596 uint32_t unused[16]; 3597 PGP port[4]; /* 8 words */ 3598 } SLI2_DESC; /* 128 bytes */ 3599 #endif /* SLI3_SUPPORT */ 3600 3601 typedef union { 3602 SLI1_DESC s1; /* 32 words, 128 bytes */ 3603 SLI2_DESC s2; /* 32 words, 128 bytes */ 3604 } SLI_VAR; 3605 3606 typedef volatile struct { 3607 #ifdef EMLXS_BIG_ENDIAN 3608 uint16_t mbxStatus; 3609 uint8_t mbxCommand; 3610 uint8_t mbxReserved:6; 3611 uint8_t mbxHc:1; 3612 uint8_t mbxOwner:1; /* Low order bit first word */ 3613 #endif 3614 #ifdef EMLXS_LITTLE_ENDIAN 3615 uint8_t mbxOwner:1; /* Low order bit first word */ 3616 uint8_t mbxHc:1; 3617 uint8_t mbxReserved:6; 3618 uint8_t mbxCommand; 3619 uint16_t mbxStatus; 3620 #endif 3621 MAILVARIANTS un; /* 124 bytes */ 3622 SLI_VAR us; /* 128 bytes */ 3623 3624 } MAILBOX; /* 256 bytes */ 3625 3626 /* 3627 * End Structure Definitions for Mailbox Commands 3628 */ 3629 3630 3631 /* 3632 * Begin Structure Definitions for IOCB Commands 3633 */ 3634 3635 typedef struct { 3636 #ifdef EMLXS_BIG_ENDIAN 3637 uint8_t statAction; 3638 uint8_t statRsn; 3639 uint8_t statBaExp; 3640 uint8_t statLocalError; 3641 #endif 3642 #ifdef EMLXS_LITTLE_ENDIAN 3643 uint8_t statLocalError; 3644 uint8_t statBaExp; 3645 uint8_t statRsn; 3646 uint8_t statAction; 3647 #endif 3648 /* statAction FBSY reason codes */ 3649 #define FBSY_RSN_MASK 0xF0 /* Rsn stored in upper nibble */ 3650 #define FBSY_FABRIC_BSY 0x10 /* F_bsy due to Fabric BSY */ 3651 #define FBSY_NPORT_BSY 0x30 /* F_bsy due to N_port BSY */ 3652 3653 /* statAction PBSY action codes */ 3654 #define PBSY_ACTION1 0x01 /* Sequence terminated - retry */ 3655 #define PBSY_ACTION2 0x02 /* Sequence active - retry */ 3656 3657 /* statAction P/FRJT action codes */ 3658 #define RJT_RETRYABLE 0x01 /* Retryable class of error */ 3659 #define RJT_NO_RETRY 0x02 /* Non-Retryable class of error */ 3660 3661 /* statRsn LS_RJT reason codes defined in LS_RJT structure */ 3662 3663 /* statRsn P_BSY reason codes */ 3664 #define PBSY_NPORT_BSY 0x01 /* Physical N_port BSY */ 3665 #define PBSY_RESRCE_BSY 0x03 /* N_port resource BSY */ 3666 #define PBSY_VU_BSY 0xFF /* See VU field for rsn */ 3667 3668 /* statRsn P/F_RJT reason codes */ 3669 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3670 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3671 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3672 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3673 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3674 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3675 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3676 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3677 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3678 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3679 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3680 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3681 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3682 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3683 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3684 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3685 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3686 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3687 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3688 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3689 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3690 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3691 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3692 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3693 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3694 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3695 3696 /* statRsn BA_RJT reason codes */ 3697 #define BARJT_BAD_CMD_CODE 0x01 /* Invalid command code */ 3698 #define BARJT_LOGICAL_ERR 0x03 /* Logical error */ 3699 #define BARJT_LOGICAL_BSY 0x05 /* Logical busy */ 3700 #define BARJT_PROTOCOL_ERR 0x07 /* Protocol error */ 3701 #define BARJT_VU_ERR 0xFF /* Vendor unique error */ 3702 3703 /* LS_RJT reason explanation defined in LS_RJT structure */ 3704 3705 /* BA_RJT reason explanation */ 3706 #define BARJT_EXP_INVALID_ID 0x01 /* Invalid OX_ID/RX_ID */ 3707 #define BARJT_EXP_ABORT_SEQ 0x05 /* Abort SEQ, no more info */ 3708 3709 /* Local Reject errors */ 3710 #define IOERR_SUCCESS 0x00 3711 #define IOERR_MISSING_CONTINUE 0x01 3712 #define IOERR_SEQUENCE_TIMEOUT 0x02 3713 #define IOERR_INTERNAL_ERROR 0x03 3714 #define IOERR_INVALID_RPI 0x04 3715 #define IOERR_NO_XRI 0x05 3716 #define IOERR_ILLEGAL_COMMAND 0x06 3717 #define IOERR_XCHG_DROPPED 0x07 3718 #define IOERR_ILLEGAL_FIELD 0x08 3719 /* RESERVED 0x09 */ 3720 /* RESERVED 0x0A */ 3721 #define IOERR_RCV_BUFFER_WAITING 0x0B 3722 /* RESERVED 0x0C */ 3723 #define IOERR_TX_DMA_FAILED 0x0D 3724 #define IOERR_RX_DMA_FAILED 0x0E 3725 #define IOERR_ILLEGAL_FRAME 0x0F 3726 3727 /* RESERVED 0x10 */ 3728 #define IOERR_NO_RESOURCES 0x11 3729 /* RESERVED 0x12 */ 3730 #define IOERR_ILLEGAL_LENGTH 0x13 3731 #define IOERR_UNSUPPORTED_FEATURE 0x14 3732 #define IOERR_ABORT_IN_PROGRESS 0x15 3733 #define IOERR_ABORT_REQUESTED 0x16 3734 #define IOERR_RCV_BUFFER_TIMEOUT 0x17 3735 #define IOERR_LOOP_OPEN_FAILURE 0x18 3736 #define IOERR_RING_RESET 0x19 3737 #define IOERR_LINK_DOWN 0x1A 3738 #define IOERR_CORRUPTED_DATA 0x1B 3739 #define IOERR_CORRUPTED_RPI 0x1C 3740 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3741 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3742 #define IOERR_DUP_FRAME 0x1F 3743 3744 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3745 #define IOERR_BAD_HOST_ADDRESS 0x21 3746 #define IOERR_RCV_HDRBUF_WAITING 0x22 3747 #define IOERR_MISSING_HDR_BUFFER 0x23 3748 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3749 #define IOERR_ABORTMULT_REQUESTED 0x25 3750 /* RESERVED 0x26 */ 3751 /* RESERVED 0x27 */ 3752 #define IOERR_BUFFER_SHORTAGE 0x28 3753 #define IOERR_XRIBUF_WAITING 0x29 3754 /* RESERVED 0x2A */ 3755 #define IOERR_MISSING_HBQ_ENTRY 0x2B 3756 #define IOERR_ABORT_EXT_REQ 0x2C 3757 #define IOERR_CLOSE_EXT_REQ 0x2D 3758 /* RESERVED 0x2E */ 3759 /* RESERVED 0x2F */ 3760 3761 #define IOERR_XRIBUF_MISSING 0x30 3762 #define IOERR_ASSI_RSP_SUPPRESSED 0x31 3763 /* RESERVED 0x32 - 0x3F */ 3764 3765 #define IOERR_ROFFSET_INVAL 0x40 3766 #define IOERR_ROFFSET_MISSING 0x41 3767 #define IOERR_INSUF_BUFFER 0x42 3768 #define IOERR_MISSING_SI 0x43 3769 #define IOERR_MISSING_ES 0x44 3770 #define IOERR_INCOMP_XFER 0x45 3771 /* RESERVED 0x46 - 0xFF */ 3772 3773 /* Driver defined */ 3774 #define IOERR_ABORT_TIMEOUT 0xF0 3775 3776 } PARM_ERR; 3777 3778 typedef union { 3779 struct { 3780 #ifdef EMLXS_BIG_ENDIAN 3781 uint8_t Rctl; /* R_CTL field */ 3782 uint8_t Type; /* TYPE field */ 3783 uint8_t Dfctl; /* DF_CTL field */ 3784 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3785 #endif 3786 #ifdef EMLXS_LITTLE_ENDIAN 3787 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3788 uint8_t Dfctl; /* DF_CTL field */ 3789 uint8_t Type; /* TYPE field */ 3790 uint8_t Rctl; /* R_CTL field */ 3791 #endif 3792 #define FCP_RTYPE 0x08 /* FCP_TARGET_MODE Type - Rctl */ 3793 3794 #define BC 0x02 /* Broadcast Received - Fctl */ 3795 #define SI 0x04 /* Sequence Initiative */ 3796 #define LA 0x08 /* Ignore Link Attention state */ 3797 #define FSEQ 0x40 /* First Sequence */ 3798 #define LSEQ 0x80 /* Last Sequence */ 3799 } hcsw; 3800 uint32_t reserved; 3801 } WORD5; 3802 3803 3804 /* IOCB Command template for a generic response */ 3805 typedef struct { 3806 uint32_t reserved[4]; 3807 PARM_ERR perr; 3808 } GENERIC_RSP; 3809 3810 3811 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3812 typedef struct { 3813 ULP_BDE xrsqbde[2]; 3814 uint32_t xrsqRo; /* Starting Relative Offset */ 3815 WORD5 w5; /* Header control/status word */ 3816 } XR_SEQ_FIELDS; 3817 3818 /* IOCB Command template for ELS_REQUEST */ 3819 typedef struct { 3820 ULP_BDE elsReq; 3821 ULP_BDE elsRsp; 3822 #ifdef EMLXS_BIG_ENDIAN 3823 uint32_t word4Rsvd:7; 3824 uint32_t fl:1; 3825 uint32_t myID:24; 3826 uint32_t word5Rsvd:8; 3827 uint32_t remoteID:24; 3828 #endif 3829 #ifdef EMLXS_LITTLE_ENDIAN 3830 uint32_t myID:24; 3831 uint32_t fl:1; 3832 uint32_t word4Rsvd:7; 3833 uint32_t remoteID:24; 3834 uint32_t word5Rsvd:8; 3835 #endif 3836 } ELS_REQUEST; 3837 3838 /* IOCB Command template for RCV_ELS_REQ */ 3839 typedef struct { 3840 ULP_BDE elsReq[2]; 3841 uint32_t parmRo; 3842 #ifdef EMLXS_BIG_ENDIAN 3843 uint32_t word5Rsvd:8; 3844 uint32_t remoteID:24; 3845 #endif 3846 #ifdef EMLXS_LITTLE_ENDIAN 3847 uint32_t remoteID:24; 3848 uint32_t word5Rsvd:8; 3849 #endif 3850 } RCV_ELS_REQ; 3851 3852 /* IOCB Command template for ABORT / CLOSE_XRI */ 3853 typedef struct { 3854 uint32_t rsvd[3]; 3855 uint32_t abortType; 3856 #define ABORT_TYPE_ABTX 0x00000000 3857 #define ABORT_TYPE_ABTS 0x00000001 3858 uint32_t parm; 3859 #ifdef EMLXS_BIG_ENDIAN 3860 uint16_t abortContextTag; /* ulpContext from cmd to abort/close */ 3861 uint16_t abortIoTag; /* ulpIoTag from cmd to abort/close */ 3862 #endif 3863 #ifdef EMLXS_LITTLE_ENDIAN 3864 uint16_t abortIoTag; /* ulpIoTag from cmd to abort/close */ 3865 uint16_t abortContextTag; /* ulpContext from cmd to abort/close */ 3866 #endif 3867 } AC_XRI; 3868 3869 /* IOCB Command template for GET_RPI */ 3870 typedef struct { 3871 uint32_t rsvd[4]; 3872 uint32_t parmRo; 3873 #ifdef EMLXS_BIG_ENDIAN 3874 uint32_t word5Rsvd:8; 3875 uint32_t remoteID:24; 3876 #endif 3877 #ifdef EMLXS_LITTLE_ENDIAN 3878 uint32_t remoteID:24; 3879 uint32_t word5Rsvd:8; 3880 #endif 3881 } GET_RPI; 3882 3883 /* IOCB Command template for all FCP Initiator commands */ 3884 typedef struct { 3885 ULP_BDE fcpi_cmnd; /* FCP_CMND payload descriptor */ 3886 ULP_BDE fcpi_rsp; /* Rcv buffer */ 3887 uint32_t fcpi_parm; 3888 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3889 } FCPI_FIELDS; 3890 3891 /* IOCB Command template for all FCP Target commands */ 3892 typedef struct { 3893 ULP_BDE fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3894 uint32_t fcpt_Offset; 3895 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3896 } FCPT_FIELDS; 3897 3898 /* SLI-2 IOCB structure definitions */ 3899 3900 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3901 typedef struct { 3902 ULP_BDL bdl; 3903 uint32_t xrsqRo; /* Starting Relative Offset */ 3904 WORD5 w5; /* Header control/status word */ 3905 } XMT_SEQ_FIELDS64; 3906 3907 3908 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3909 typedef struct { 3910 ULP_BDE64 rcvBde; 3911 uint32_t rsvd1; 3912 uint32_t xrsqRo; /* Starting Relative Offset */ 3913 WORD5 w5; /* Header control/status word */ 3914 } RCV_SEQ_FIELDS64; 3915 3916 /* IOCB Command template for ELS_REQUEST64 */ 3917 typedef struct { 3918 ULP_BDL bdl; 3919 #ifdef EMLXS_BIG_ENDIAN 3920 uint32_t word4Rsvd:7; 3921 uint32_t fl:1; 3922 uint32_t myID:24; 3923 3924 uint32_t word5Rsvd:8; 3925 uint32_t remoteID:24; 3926 #endif 3927 #ifdef EMLXS_LITTLE_ENDIAN 3928 uint32_t myID:24; 3929 uint32_t fl:1; 3930 uint32_t word4Rsvd:7; 3931 3932 uint32_t remoteID:24; 3933 uint32_t word5Rsvd:8; 3934 #endif 3935 } ELS_REQUEST64; 3936 3937 3938 /* IOCB Command template for ASYNC_STATUS */ 3939 typedef struct { 3940 ULP_BDL resv; 3941 uint32_t parameter; 3942 #ifdef EMLXS_BIG_ENDIAN 3943 uint16_t EventCode; 3944 uint16_t SubContext; 3945 #endif 3946 #ifdef EMLXS_LITTLE_ENDIAN 3947 uint16_t SubContext; 3948 uint16_t EventCode; 3949 #endif 3950 } ASYNC_STATUS; 3951 3952 3953 /* IOCB Command template for QUE_RING_LIST64 */ 3954 typedef struct { 3955 ULP_BDL bdl; 3956 uint32_t rsvd1; 3957 uint32_t rsvd2; 3958 } QUE_RING_LIST64; 3959 3960 3961 /* IOCB Command template for GEN_REQUEST64 */ 3962 typedef struct { 3963 ULP_BDL bdl; 3964 uint32_t param; /* Starting Relative Offset */ 3965 WORD5 w5; /* Header control/status word */ 3966 } GEN_REQUEST64; 3967 3968 /* IOCB Command template for RCV_ELS_REQ64 */ 3969 typedef struct { 3970 ULP_BDE64 elsReq; 3971 uint32_t rcvd1; 3972 uint32_t parmRo; 3973 #ifdef EMLXS_BIG_ENDIAN 3974 uint32_t word5Rsvd:8; 3975 uint32_t remoteID:24; 3976 #endif 3977 #ifdef EMLXS_LITTLE_ENDIAN 3978 uint32_t remoteID:24; 3979 uint32_t word5Rsvd:8; 3980 #endif 3981 } RCV_ELS_REQ64; 3982 3983 /* IOCB Command template for all 64 bit FCP Initiator commands */ 3984 typedef struct { 3985 ULP_BDL bdl; 3986 uint32_t fcpi_parm; 3987 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3988 } FCPI_FIELDS64; 3989 3990 /* IOCB Command template for all 64 bit FCP Target commands */ 3991 typedef struct { 3992 ULP_BDL bdl; 3993 uint32_t fcpt_Offset; 3994 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3995 } FCPT_FIELDS64; 3996 3997 /* IOCB Command template for all 64 bit FCP Target commands */ 3998 typedef struct { 3999 uint32_t rsp_length; 4000 uint32_t rsvd1; 4001 uint32_t rsvd2; 4002 uint32_t iotag32; 4003 uint32_t status; 4004 #ifdef EMLXS_BIG_ENDIAN 4005 uint32_t rsvd:30; 4006 uint32_t lnk:1; 4007 #endif /* EMLXS_BIG_ENDIAN */ 4008 4009 #ifdef EMLXS_LITTLE_ENDIAN 4010 uint32_t lnk:1; 4011 uint32_t rsvd:30; 4012 #endif /* EMLXS_LITTLE_ENDIAN */ 4013 4014 } AUTO_TRSP; 4015 4016 4017 typedef struct { 4018 uint32_t io_tag64_low; /* Word 8 */ 4019 uint32_t io_tag64_high; /* Word 9 */ 4020 #ifdef EMLXS_BIG_ENDIAN 4021 uint32_t cs_ctl:8; /* Word 10, bit 31:24 */ 4022 uint32_t cs_en:1; /* Word 10, bit 23 */ 4023 uint32_t rsv:15; /* Word 10, bit 22:8 */ 4024 uint32_t ebde_count:8; /* Word 10, bit 7:0 */ 4025 #endif 4026 #ifdef EMLXS_LITTLE_ENDIAN 4027 uint32_t ebde_count:8; /* Word 10, bit 7:0 */ 4028 uint32_t rsv:15; /* Word 10, bit 22:8 */ 4029 uint32_t cs_en:1; /* Word 10, bit 23 */ 4030 uint32_t cs_ctl:8; /* Word 10, bit 31:24 */ 4031 #endif 4032 uint32_t rsplen; /* Word 11 */ 4033 ULP_BDE64 ebde1; /* Word 12:14 */ 4034 ULP_BDE64 ebde2; /* Word 15:17 */ 4035 ULP_BDE64 ebde3; /* Word 18:20 */ 4036 ULP_BDE64 ebde4; /* Word 21:23 */ 4037 ULP_BDE64 ebde5; /* Word 24:26 */ 4038 ULP_BDE64 ebde6; /* Word 27:29 */ 4039 4040 } GENERIC_EXT_IOCB; 4041 4042 /* 4043 * IOCB Command Extension template for CMD_RCV_ELS64_CX (0xB7) 4044 * or CMD_RCV_SEQ64_CX (0xB5) 4045 */ 4046 4047 typedef struct { 4048 uint32_t hdr3; /* word 8 */ 4049 #ifdef EMLXS_BIG_ENDIAN 4050 uint16_t vpi; /* word 9 */ 4051 uint16_t buddy_xri; 4052 4053 uint32_t ccp:8; /* word 10 */ 4054 uint32_t ccpe:1; 4055 uint32_t rsvd:23; 4056 #endif 4057 #ifdef EMLXS_LITTLE_ENDIAN 4058 uint16_t buddy_xri; /* word 9 */ 4059 uint16_t vpi; 4060 4061 uint32_t rsvd:23; /* word 10 */ 4062 uint32_t ccpe:1; 4063 uint32_t ccp:8; 4064 #endif 4065 uint32_t seq_len; /* received sequence length */ 4066 ULP_BDL bde2; /* total 4 words */ 4067 4068 } RCV_SEQ_ELS_64_SLI3_EXT; 4069 4070 4071 4072 typedef volatile struct emlxs_iocb { /* IOCB structure */ 4073 union { 4074 GENERIC_RSP grsp; /* Generic response */ 4075 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 4076 ULP_BDE cont[3]; /* up to 3 continuation bdes */ 4077 ELS_REQUEST elsreq; /* ELS_REQUEST template */ 4078 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 4079 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 4080 GET_RPI getrpi; /* GET_RPI template */ 4081 FCPI_FIELDS fcpi; /* FCP Initiator template */ 4082 FCPT_FIELDS fcpt; /* FCP target template */ 4083 4084 /* SLI-2 structures */ 4085 4086 ULP_BDE64 cont64[2]; /* up to 2 64 bit cont bde_64s */ 4087 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 4088 QUE_RING_LIST64 qringlist64; /* QUE RING LIST64 template */ 4089 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 4090 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 4091 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 4092 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 4093 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 4094 AUTO_TRSP atrsp; /* FCP 64 bit target template */ 4095 4096 RCV_SEQ_FIELDS64 rcvseq64; 4097 ASYNC_STATUS astat; 4098 4099 uint32_t ulpWord[6]; /* generic 6 'words' */ 4100 } un; 4101 union { 4102 struct { 4103 #ifdef EMLXS_BIG_ENDIAN 4104 uint16_t ulpContext; /* High order bits word6 */ 4105 uint16_t ulpIoTag; /* Low order bits word6 */ 4106 #endif 4107 #ifdef EMLXS_LITTLE_ENDIAN 4108 uint16_t ulpIoTag; /* Low order bits word6 */ 4109 uint16_t ulpContext; /* High order bits word6 */ 4110 #endif 4111 } t1; 4112 struct { 4113 #ifdef EMLXS_BIG_ENDIAN 4114 uint16_t ulpContext; /* High order bits word6 */ 4115 uint16_t ulpIoTag1:2; /* Low order bits word6 */ 4116 uint16_t ulpIoTag0:14; /* Low order bits word6 */ 4117 #endif 4118 #ifdef EMLXS_LITTLE_ENDIAN 4119 uint16_t ulpIoTag0:14; /* Low order bits word6 */ 4120 uint16_t ulpIoTag1:2; /* Low order bits word6 */ 4121 uint16_t ulpContext; /* High order bits word6 */ 4122 #endif 4123 } t2; 4124 } un1; 4125 #define ulpContext un1.t1.ulpContext 4126 #define ulpIoTag un1.t1.ulpIoTag 4127 #define ulpIoTag0 un1.t2.ulpIoTag0 4128 #define ulpDelayXmit un1.t2.ulpIoTag1 4129 4130 #define IOCB_DELAYXMIT_MSK 0x3000 4131 4132 4133 union { 4134 struct { 4135 #ifdef EMLXS_BIG_ENDIAN 4136 uint32_t ulpRsvdByte:8; 4137 uint32_t ulpXS:1; 4138 uint32_t ulpFCP2Rcvy:1; 4139 uint32_t ulpPU:2; 4140 uint32_t ulpIr:1; 4141 uint32_t ulpClass:3; 4142 uint32_t ulpCommand:8; 4143 uint32_t ulpStatus:4; 4144 uint32_t ulpBdeCount:2; 4145 uint32_t ulpLe:1; 4146 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4147 #endif 4148 #ifdef EMLXS_LITTLE_ENDIAN 4149 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4150 uint32_t ulpLe:1; 4151 uint32_t ulpBdeCount:2; 4152 uint32_t ulpStatus:4; 4153 uint32_t ulpCommand:8; 4154 uint32_t ulpClass:3; 4155 uint32_t ulpIr:1; 4156 uint32_t ulpPU:2; 4157 uint32_t ulpFCP2Rcvy:1; 4158 uint32_t ulpXS:1; 4159 uint32_t ulpRsvdByte:8; 4160 #endif 4161 } t1; 4162 4163 struct { 4164 #ifdef EMLXS_BIG_ENDIAN 4165 uint32_t ulpRsvdByte:8; 4166 uint32_t ulpCT:2; 4167 uint32_t ulpPU:2; 4168 uint32_t ulpIr:1; 4169 uint32_t ulpClass:3; 4170 uint32_t ulpCommand:8; 4171 uint32_t ulpStatus:4; 4172 uint32_t ulpBdeCount:2; 4173 uint32_t ulpLe:1; 4174 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4175 #endif 4176 #ifdef EMLXS_LITTLE_ENDIAN 4177 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4178 uint32_t ulpLe:1; 4179 uint32_t ulpBdeCount:2; 4180 uint32_t ulpStatus:4; 4181 uint32_t ulpCommand:8; 4182 uint32_t ulpClass:3; 4183 uint32_t ulpIr:1; 4184 uint32_t ulpPU:2; 4185 uint32_t ulpCT:2; 4186 uint32_t ulpRsvdByte:8; 4187 #endif 4188 } t2; 4189 4190 } un2; 4191 4192 #define ulpCT un2.t2.ulpCT 4193 #define ulpRsvdByte un2.t1.ulpRsvdByte 4194 #define ulpXS un2.t1.ulpXS 4195 #define ulpFCP2Rcvy un2.t1.ulpFCP2Rcvy 4196 #define ulpPU un2.t1.ulpPU 4197 #define ulpIr un2.t1.ulpIr 4198 #define ulpClass un2.t1.ulpClass 4199 #define ulpCommand un2.t1.ulpCommand 4200 #define ulpStatus un2.t1.ulpStatus 4201 #define ulpBdeCount un2.t1.ulpBdeCount 4202 #define ulpLe un2.t1.ulpLe 4203 #define ulpOwner un2.t1.ulpOwner 4204 /* 32 bytes at this point */ 4205 4206 #ifdef SLI3_SUPPORT 4207 union { 4208 GENERIC_EXT_IOCB ext_iocb; 4209 RCV_SEQ_ELS_64_SLI3_EXT ext_rcv; 4210 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 4211 } unsli3; 4212 /* 128 bytes at this point */ 4213 #endif /* SLI3_SUPPORT */ 4214 4215 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds - ulpRsvByte */ 4216 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 4217 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 4218 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 4219 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 4220 #define CLASS1 0 /* Class 1 */ 4221 #define CLASS2 1 /* Class 2 */ 4222 #define CLASS3 2 /* Class 3 */ 4223 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 4224 4225 #define IOSTAT_SUCCESS 0x0 /* ulpStatus */ 4226 #define IOSTAT_FCP_RSP_ERROR 0x1 4227 #define IOSTAT_REMOTE_STOP 0x2 4228 #define IOSTAT_LOCAL_REJECT 0x3 4229 #define IOSTAT_NPORT_RJT 0x4 4230 #define IOSTAT_FABRIC_RJT 0x5 4231 #define IOSTAT_NPORT_BSY 0x6 4232 #define IOSTAT_FABRIC_BSY 0x7 4233 #define IOSTAT_INTERMED_RSP 0x8 4234 #define IOSTAT_LS_RJT 0x9 4235 #define IOSTAT_RESERVED_A 0xA 4236 #define IOSTAT_CMD_REJECT 0xB 4237 #define IOSTAT_FCP_TGT_LENCHK 0xC 4238 #define IOSTAT_NEED_BUF_ENTRY 0xD 4239 #define IOSTAT_RESERVED_E 0xE 4240 #define IOSTAT_ILLEGAL_FRAME_RCVD 0xF 4241 4242 /* Special error codes */ 4243 #define IOSTAT_DATA_OVERRUN 0x10 /* Added for resid handling */ 4244 #define IOSTAT_DATA_UNDERRUN 0x11 /* Added for resid handling */ 4245 4246 } emlxs_iocb_t; 4247 typedef emlxs_iocb_t IOCB; 4248 4249 4250 typedef struct emlxs_iocbq { 4251 emlxs_iocb_t iocb; 4252 struct emlxs_iocbq *next; 4253 4254 uint8_t *bp; /* ptr to data buffer structure */ 4255 void *port; /* Board info pointer */ 4256 void *ring; /* Ring pointer */ 4257 void *node; /* Node pointer */ 4258 void *sbp; /* Pkt pointer */ 4259 uint32_t flag; 4260 4261 #define IOCB_POOL_ALLOCATED 0x00000001 4262 #define IOCB_PRIORITY 0x00000002 4263 #define IOCB_SPECIAL 0x00000004 4264 4265 } emlxs_iocbq_t; 4266 typedef emlxs_iocbq_t IOCBQ; 4267 4268 4269 typedef struct emlxs_mbq { 4270 volatile uint32_t mbox[MAILBOX_CMD_WSIZE]; 4271 struct emlxs_mbq *next; 4272 4273 /* Defferred handling pointers */ 4274 uint8_t *bp; /* ptr to data buffer structure */ 4275 uint8_t *sbp; /* ptr to emlxs_buf_t structure */ 4276 uint8_t *ubp; /* ptr to fc_unsol_buf_t structure */ 4277 uint8_t *iocbq; /* ptr to IOCBQ structure */ 4278 uint32_t flag; 4279 4280 #define MBQ_POOL_ALLOCATED 0x00000001 4281 #define MBQ_PASSTHRU 0x00000002 4282 #define MBQ_COMPLETED 0x00010000 /* Used for MBX_SLEEP */ 4283 #define MBQ_INIT_MASK 0x0000ffff 4284 4285 #ifdef MBOX_EXT_SUPPORT 4286 uint8_t *extbuf; /* ptr to mailbox extension buffer */ 4287 uint32_t extsize; /* size of mailbox extension buffer */ 4288 #endif /* MBOX_EXT_SUPPORT */ 4289 4290 } emlxs_mbq_t; 4291 typedef emlxs_mbq_t MAILBOXQ; 4292 4293 4294 /* We currently do not support IOCBs in SLI1 mode */ 4295 typedef struct { 4296 MAILBOX mbx; 4297 #ifdef MBOX_EXT_SUPPORT 4298 uint8_t mbxExt[MBOX_EXTENSION_SIZE]; 4299 #endif /* MBOX_EXT_SUPPORT */ 4300 uint8_t pad[(SLI_SLIM1_SIZE-(sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))]; 4301 } SLIM1; 4302 4303 4304 typedef struct { 4305 MAILBOX mbx; 4306 #ifdef MBOX_EXT_SUPPORT 4307 uint8_t mbxExt[MBOX_EXTENSION_SIZE]; 4308 #endif /* MBOX_EXT_SUPPORT */ 4309 PCB pcb; 4310 uint8_t IOCBs[SLI_IOCB_MAX_SIZE]; 4311 } SLIM2; 4312 4313 4314 4315 /* 4316 * This file defines the Header File for the FDMI HBA Management Service 4317 */ 4318 4319 /* 4320 * FDMI HBA MAnagement Operations Command Codes 4321 */ 4322 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 4323 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 4324 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 4325 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 4326 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 4327 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 4328 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 4329 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 4330 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 4331 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 4332 4333 /* 4334 * Management Service Subtypes 4335 */ 4336 #define SLI_CT_FDMI_Subtypes 0x10 4337 4338 4339 /* 4340 * HBA Management Service Reject Code 4341 */ 4342 #define REJECT_CODE 0x9 /* Unable to perform command request */ 4343 4344 /* 4345 * HBA Management Service Reject Reason Code 4346 * Please refer to the Reason Codes above 4347 */ 4348 4349 /* 4350 * HBA Attribute Types 4351 */ 4352 #define NODE_NAME 0x1 4353 #define MANUFACTURER 0x2 4354 #define SERIAL_NUMBER 0x3 4355 #define MODEL 0x4 4356 #define MODEL_DESCRIPTION 0x5 4357 #define HARDWARE_VERSION 0x6 4358 #define DRIVER_VERSION 0x7 4359 #define OPTION_ROM_VERSION 0x8 4360 #define FIRMWARE_VERSION 0x9 4361 #define VENDOR_SPECIFIC 0xa 4362 #define DRV_NAME 0xb 4363 #define OS_NAME_VERSION 0xc 4364 #define MAX_CT_PAYLOAD_LEN 0xd 4365 4366 /* 4367 * Port Attrubute Types 4368 */ 4369 #define SUPPORTED_FC4_TYPES 0x1 4370 #define SUPPORTED_SPEED 0x2 4371 #define PORT_SPEED 0x3 4372 #define MAX_FRAME_SIZE 0x4 4373 #define OS_DEVICE_NAME 0x5 4374 4375 union AttributesDef { 4376 /* Structure is in Big Endian format */ 4377 struct { 4378 uint32_t AttrType:16; 4379 uint32_t AttrLen:16; 4380 } bits; 4381 uint32_t word; 4382 }; 4383 4384 /* 4385 * HBA Attribute Entry (8 - 260 bytes) 4386 */ 4387 typedef struct { 4388 union AttributesDef ad; 4389 union { 4390 uint32_t VendorSpecific; 4391 uint32_t SupportSpeed; 4392 uint32_t PortSpeed; 4393 uint32_t MaxFrameSize; 4394 uint32_t MaxCTPayloadLen; 4395 uint8_t SupportFC4Types[32]; 4396 uint8_t OsDeviceName[256]; 4397 uint8_t Manufacturer[64]; 4398 uint8_t SerialNumber[64]; 4399 uint8_t Model[256]; 4400 uint8_t ModelDescription[256]; 4401 uint8_t HardwareVersion[256]; 4402 uint8_t DriverVersion[256]; 4403 uint8_t OptionROMVersion[256]; 4404 uint8_t FirmwareVersion[256]; 4405 uint8_t DriverName[256]; 4406 NAME_TYPE NodeName; 4407 } un; 4408 } ATTRIBUTE_ENTRY, *PATTRIBUTE_ENTRY; 4409 4410 4411 /* 4412 * HBA Attribute Block 4413 */ 4414 typedef struct { 4415 uint32_t EntryCnt; /* Number of HBA attribute entries */ 4416 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 4417 } ATTRIBUTE_BLOCK, *PATTRIBUTE_BLOCK; 4418 4419 4420 /* 4421 * Port Entry 4422 */ 4423 typedef struct { 4424 NAME_TYPE PortName; 4425 } PORT_ENTRY, *PPORT_ENTRY; 4426 4427 /* 4428 * HBA Identifier 4429 */ 4430 typedef struct { 4431 NAME_TYPE PortName; 4432 } HBA_IDENTIFIER, *PHBA_IDENTIFIER; 4433 4434 /* 4435 * Registered Port List Format 4436 */ 4437 typedef struct { 4438 uint32_t EntryCnt; 4439 PORT_ENTRY pe; /* Variable-length array */ 4440 } REG_PORT_LIST, *PREG_PORT_LIST; 4441 4442 /* 4443 * Register HBA(RHBA) 4444 */ 4445 typedef struct { 4446 HBA_IDENTIFIER hi; 4447 REG_PORT_LIST rpl; /* variable-length array */ 4448 /* ATTRIBUTE_BLOCK ab; */ 4449 } REG_HBA, *PREG_HBA; 4450 4451 /* 4452 * Register HBA Attributes (RHAT) 4453 */ 4454 typedef struct { 4455 NAME_TYPE HBA_PortName; 4456 ATTRIBUTE_BLOCK ab; 4457 } REG_HBA_ATTRIBUTE, *PREG_HBA_ATTRIBUTE; 4458 4459 /* 4460 * Register Port Attributes (RPA) 4461 */ 4462 typedef struct { 4463 NAME_TYPE HBA_PortName; 4464 NAME_TYPE PortName; 4465 ATTRIBUTE_BLOCK ab; 4466 } REG_PORT_ATTRIBUTE, *PREG_PORT_ATTRIBUTE; 4467 4468 /* 4469 * Get Registered HBA List (GRHL) Accept Payload Format 4470 */ 4471 typedef struct { 4472 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 4473 NAME_TYPE HBA_PortName; /* Variable-length array */ 4474 } GRHL_ACC_PAYLOAD, *PGRHL_ACC_PAYLOAD; 4475 4476 /* 4477 * Get Registered Port List (GRPL) Accept Payload Format 4478 */ 4479 typedef struct { 4480 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 4481 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 4482 } GRPL_ACC_PAYLOAD, *PGRPL_ACC_PAYLOAD; 4483 4484 /* 4485 * Get Port Attributes (GPAT) Accept Payload Format 4486 */ 4487 4488 typedef struct { 4489 ATTRIBUTE_BLOCK pab; 4490 } GPAT_ACC_PAYLOAD, *PGPAT_ACC_PAYLOAD; 4491 4492 /* 4493 * Use for Firmware DownLoad 4494 */ 4495 4496 /* ------------------------ download.h ------------------------------ */ 4497 4498 #define REDUCED_SRAM_CFG 0x7FFFC /* 9802DC */ 4499 #define FULL_SRAM_CFG 0x13FFFC /* 9802 */ 4500 4501 #define SLI_FW_TYPE_SHIFT(x) ((x << 20)) 4502 #define SLI_FW_ADAPTER_TYPE_MASK 0x00f00000 4503 #define SLI_FW_TYPE_6000 SLI_FW_TYPE_SHIFT(0) 4504 #define SLI_FW_TYPE_7000 SLI_FW_TYPE_SHIFT(1) 4505 #define SLI_FW_TYPE_8000 SLI_FW_TYPE_SHIFT(2) 4506 #define SLI_FW_TYPE_850 SLI_FW_TYPE_SHIFT(3) 4507 #define SLI_FW_TYPE_9000 SLI_FW_TYPE_SHIFT(4) 4508 #define SLI_FW_TYPE_950 SLI_FW_TYPE_SHIFT(5) 4509 #define SLI_FW_TYPE_9802 SLI_FW_TYPE_SHIFT(6) /* [022702] */ 4510 #define SLI_FW_TYPE_982 SLI_FW_TYPE_SHIFT(7) 4511 #define SLI_FW_TYPE_10000 SLI_FW_TYPE_SHIFT(8) 4512 #define SLI_FW_TYPE_1050 SLI_FW_TYPE_SHIFT(9) 4513 #define SLI_FW_TYPE_X1000 SLI_FW_TYPE_SHIFT(0xa) 4514 #define SLI_FW_TYPE_101 SLI_FW_TYPE_SHIFT(0xb) /* LP101 */ 4515 4516 4517 enum emlxs_prog_type { 4518 TEST_PROGRAM, /* 0 */ 4519 UTIL_PROGRAM, /* 1 */ 4520 FUNC_FIRMWARE, /* 2 */ 4521 BOOT_BIOS, /* 3 */ 4522 CONFIG_DATA, /* 4 */ 4523 SEQUENCER_CODE, /* 5 */ 4524 SLI1_OVERLAY, /* 6 */ 4525 SLI2_OVERLAY, /* 7 */ 4526 GASKET, /* 8 */ 4527 HARDWARE_IMAGE, /* 9 */ 4528 SBUS_FCODE, /* A */ 4529 SLI3_OVERLAY, /* B */ 4530 RESERVED_C, 4531 RESERVED_D, 4532 SLI4_OVERLAY, /* E */ 4533 KERNEL_CODE, /* F */ 4534 MAX_PROG_TYPES 4535 4536 } emlxs_prog_type_t; 4537 4538 4539 typedef struct emlxs_fw_file { 4540 uint32_t version; 4541 uint32_t revcomp; 4542 char label[16]; 4543 uint32_t offset; 4544 4545 } emlxs_fw_file_t; 4546 4547 typedef struct emlxs_fw_image { 4548 emlxs_fw_file_t awc; 4549 emlxs_fw_file_t bwc; 4550 emlxs_fw_file_t dwc; 4551 emlxs_fw_file_t prog[MAX_PROG_TYPES]; 4552 4553 } emlxs_fw_image_t; 4554 4555 4556 4557 4558 #define NOP_IMAGE_TYPE 0xe1a00000 4559 4560 #define FLASH_BASE_ADR 0x01400000 4561 #define DL_FROM_SLIM_OFFSET MBOX_EXTENSION_OFFSET 4562 4563 #ifdef MBOX_EXT_SUPPORT 4564 #define DL_SLIM_SEG_BYTE_COUNT MBOX_EXTENSION_SIZE 4565 #else 4566 #define DL_SLIM_SEG_BYTE_COUNT 128 4567 #endif /* MBOX_EXT_SUPPORT */ 4568 4569 #define SLI_CKSUM_LENGTH 4 4570 #define SLI_CKSUM_SEED 0x55555555 4571 #define SLI_CKSUM_ERR 0x1982abcd 4572 4573 #define AIF_NOOP 0xe1a00000 4574 #define AIF_BLAL 0xeb000000 4575 #define OS_EXIT 0xef000011 4576 #define OS_GETENV 0xef000010 4577 #define AIF_IMAGEBASE 0x00008000 4578 #define AIF_BLZINIT 0xeb00000c 4579 #define DEBUG_TASK 0xef041d41 4580 #define AIF_DBG_SRC 2 4581 #define AIF_DBG_LL 1 4582 #define AIF_DATABASAT 0x100 4583 4584 #define JEDEC_ID_ADDRESS 0x0080001c 4585 #define MAX_RBUS_SRAM_SIZE_ADR 0x788 4586 #define MAX_IBUS_SRAM_SIZE_ADR 0x78c 4587 #define FULL_RBUS_SRAM_CFG 0x7fffc 4588 #define FULL_IBUS_SRAM_CFG 0x187fffc 4589 #define REDUCED_RBUS_SRAM_CFG 0x5fffc 4590 #define REDUCED_IBUS_SRAM_CFG 0x183fffc 4591 #define FULL_SRAM_CFG_PROG_ID 1 4592 #define REDUCED_SRAM_CFG_PROG_ID 2 4593 #define OTHER_SRAM_CFG_PROG_ID 3 4594 4595 #define NO_FLASH_MEM_AVAIL 0xf1 4596 4597 #define PROG_TYPE_MASK 0xff000000 4598 #define PROG_TYPE_SHIFT 24 4599 4600 #define FLASH_LOAD_LIST_ADR 0x79c 4601 #define RAM_LOAD_ENTRY_SIZE 9 4602 #define FLASH_LOAD_ENTRY_SIZE 6 4603 #define RAM_LOAD_ENTRY_TYPE 0 4604 #define FLASH_LOAD_ENTRY_TYPE 1 4605 4606 #define CFG_DATA_NO_REGION -3 4607 4608 #define SLI_IMAGE_START 0x20080 4609 #define SLI_VERSION_LOC 0x270 4610 4611 /* def for new 2MB Flash (Pegasus ...) */ 4612 #define MBX_LOAD_AREA 0x81 4613 #define MBX_LOAD_EXP_ROM 0x9C 4614 4615 #define FILE_TYPE_AWC 0xE1A01001 4616 #define FILE_TYPE_DWC 0xE1A02002 4617 #define FILE_TYPE_BWC 0xE1A03003 4618 4619 #define AREA_ID_MASK 0xFFFFFF0F 4620 #define AREA_ID_AWC 0x00000001 4621 #define AREA_ID_DWC 0x00000002 4622 #define AREA_ID_BWC 0x00000003 4623 4624 #define CMD_START_ERASE 1 4625 #define CMD_CONTINUE_ERASE 2 4626 #define CMD_DOWNLOAD 3 4627 #define CMD_END_DOWNLOAD 4 4628 4629 #define RSP_ERASE_STARTED 1 4630 #define RSP_ERASE_COMPLETE 2 4631 #define RSP_DOWNLOAD_MORE 3 4632 #define RSP_DOWNLOAD_DONE 4 4633 4634 #define EROM_CMD_FIND_IMAGE 8 4635 #define EROM_CMD_CONTINUE_ERASE 9 4636 #define EROM_CMD_COPY 10 4637 4638 #define EROM_RSP_ERASE_STARTED 8 4639 #define EROM_RSP_ERASE_COMPLETE 9 4640 #define EROM_RSP_COPY_MORE 10 4641 #define EROM_RSP_COPY_DONE 11 4642 4643 #define ALLext 1 4644 #define DWCext 2 4645 #define BWCext 3 4646 4647 #define NO_ALL 0 4648 #define ALL_WITHOUT_BWC 1 4649 #define ALL_WITH_BWC 2 4650 4651 #define KERNEL_START_ADDRESS 0x000000 4652 #define DOWNLOAD_START_ADDRESS 0x040000 4653 #define EXP_ROM_START_ADDRESS 0x180000 4654 #define SCRATCH_START_ADDRESS 0x1C0000 4655 #define CONFIG_START_ADDRESS 0x1E0000 4656 4657 4658 typedef struct SliAifHdr { 4659 uint32_t CompressBr; 4660 uint32_t RelocBr; 4661 uint32_t ZinitBr; 4662 uint32_t EntryBr; 4663 uint32_t Area_ID; 4664 uint32_t RoSize; 4665 uint32_t RwSize; 4666 uint32_t DbgSize; 4667 uint32_t ZinitSize; 4668 uint32_t DbgType; 4669 uint32_t ImageBase; 4670 uint32_t Area_Size; 4671 uint32_t AddressMode; 4672 uint32_t DataBase; 4673 uint32_t AVersion; 4674 uint32_t Spare2; 4675 uint32_t DebugSwi; 4676 uint32_t ZinitCode[15]; 4677 } AIF_HDR, *PAIF_HDR; 4678 4679 typedef struct ImageHdr { 4680 uint32_t BlockSize; 4681 PROG_ID Id; 4682 uint32_t Flags; 4683 uint32_t EntryAdr; 4684 uint32_t InitAdr; 4685 uint32_t ExitAdr; 4686 uint32_t ImageBase; 4687 uint32_t ImageSize; 4688 uint32_t ZinitSize; 4689 uint32_t RelocSize; 4690 uint32_t HdrCks; 4691 } IMAGE_HDR, *PIMAGE_HDR; 4692 4693 4694 4695 typedef struct { 4696 PROG_ID prog_id; 4697 #ifdef EMLXS_BIG_ENDIAN 4698 uint32_t pci_cfg_rsvd:27; 4699 uint32_t use_hdw_def:1; 4700 uint32_t pci_cfg_sel:3; 4701 uint32_t pci_cfg_lookup_sel:1; 4702 #endif 4703 #ifdef EMLXS_LITTLE_ENDIAN 4704 uint32_t pci_cfg_lookup_sel:1; 4705 uint32_t pci_cfg_sel:3; 4706 uint32_t use_hdw_def:1; 4707 uint32_t pci_cfg_rsvd:27; 4708 #endif 4709 union { 4710 PROG_ID boot_bios_id; 4711 uint32_t boot_bios_wd[2]; 4712 } u0; 4713 PROG_ID sli1_prog_id; 4714 PROG_ID sli2_prog_id; 4715 PROG_ID sli3_prog_id; 4716 PROG_ID sli4_prog_id; 4717 union { 4718 PROG_ID EROM_prog_id; 4719 uint32_t EROM_prog_wd[2]; 4720 } u1; 4721 } WAKE_UP_PARMS, *PWAKE_UP_PARMS; 4722 4723 4724 #define PROG_DESCR_STR_LEN 24 4725 #define MAX_LOAD_ENTRY 10 4726 4727 typedef struct { 4728 uint32_t next; 4729 uint32_t prev; 4730 uint32_t start_adr; 4731 uint32_t len; 4732 union { 4733 PROG_ID id; 4734 uint32_t wd[2]; 4735 } un; 4736 uint8_t prog_descr[PROG_DESCR_STR_LEN]; 4737 } LOAD_ENTRY; 4738 4739 typedef struct { 4740 uint32_t head; 4741 uint32_t tail; 4742 uint32_t entry_cnt; 4743 LOAD_ENTRY load_entry[MAX_LOAD_ENTRY]; 4744 } LOAD_LIST; 4745 4746 4747 4748 #define SLI_HW_REVISION_CHECK(x, y) ((x & 0xf0) == y) 4749 #define SLI_FCODE_REVISION_CHECK(x, y) (x == y) 4750 4751 4752 /* Define the adapters */ 4753 #include <emlxs_adapters.h> 4754 4755 #ifdef __cplusplus 4756 } 4757 #endif 4758 4759 #endif /* _EMLXS_HW_H */ 4760