1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Emulex. All rights reserved. 24 * Use is subject to License terms. 25 */ 26 27 28 #ifndef _EMLXS_DFCLIB_H 29 #define _EMLXS_DFCLIB_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define MAX_DFC_EVENTS 16 36 #define MAX_EMLXS_BRDS 128 37 #define MAX_CFG_PARAM 64 38 #define MAX_NODES 4096 39 40 41 #ifndef MAX_VPORTS 42 #ifdef NPIV_SUPPORT 43 #define MAX_VPORTS 256 44 #else 45 #define MAX_VPORTS 1 46 #endif /* NPIV_SUPPORT */ 47 #endif /* MAX_VPORTS */ 48 49 #ifdef EMLXS_SPARC /* BIG ENDIAN */ 50 #define EMLXS_BIG_ENDIAN 51 #else /* LITTLE ENDIAN */ 52 #define EMLXS_LITTLE_ENDIAN 53 #endif 54 55 56 typedef struct brdinfo { 57 uint32_t a_mem_hi; /* memory identifier for adapter access */ 58 uint32_t a_mem_low; /* memory identifier for adapter access */ 59 uint32_t a_flash_hi; /* memory identifier for adapter access */ 60 uint32_t a_flash_low; /* memory identifier for adapter access */ 61 uint32_t a_ctlreg_hi; /* memory identifier for adapter access */ 62 uint32_t a_ctlreg_low; /* memory identifier for adapter access */ 63 uint32_t a_intrlvl; /* interrupt level for adapter */ 64 uint32_t a_pci; /* PCI identifier (device / vendor id) */ 65 uint32_t a_busid; /* identifier of PCI bus adapter is on */ 66 uint32_t a_devid; /* identifier of PCI device number */ 67 uint8_t a_rsvd1; /* reserved for future use */ 68 uint8_t a_rsvd2; /* reserved for future use */ 69 uint8_t a_siglvl; /* signal handler used by library */ 70 uint8_t a_ddi; /* identifier device driver instance number */ 71 uint32_t a_onmask; /* mask of ONDI primatives supported */ 72 uint32_t a_offmask; /* mask of OFFDI primatives supported */ 73 uint8_t a_drvrid[16]; /* driver version */ 74 uint8_t a_fwname[32]; /* firmware version */ 75 76 } brdinfo_t; 77 78 79 typedef struct dfc_brdinfo { 80 uint32_t a_mem_hi; /* memory identifier for adapter access */ 81 uint32_t a_mem_low; /* memory identifier for adapter access */ 82 uint32_t a_flash_hi; /* memory identifier for adapter access */ 83 uint32_t a_flash_low; /* memory identifier for adapter access */ 84 uint32_t a_ctlreg_hi; /* memory identifier for adapter access */ 85 uint32_t a_ctlreg_low; /* memory identifier for adapter access */ 86 uint32_t a_intrlvl; /* interrupt level for adapter */ 87 uint32_t a_pci; /* PCI identifier (device / vendor id) */ 88 uint32_t a_busid; /* identifier of PCI bus adapter is on */ 89 uint32_t a_devid; /* identifier of PCI device number */ 90 uint8_t a_rsvd; /* reserved for word alignment */ 91 uint8_t a_siglvl; /* signal handler used by library */ 92 uint16_t a_ddi; /* identifier device driver instance number */ 93 uint32_t a_onmask; /* mask of ONDI primatives supported */ 94 uint32_t a_offmask; /* mask of OFFDI primatives supported */ 95 uint8_t a_drvrid[16]; /* driver version */ 96 uint8_t a_fwname[32]; /* firmware version */ 97 uint8_t a_wwpn[8]; /* worldwide portname */ 98 99 } dfc_brdinfo_t; 100 101 102 #define putPaddrLow(addr) ((uint32_t)((uint64_t)(addr) & 0xffffffff)) 103 #define putPaddrHigh(addr) ((uint32_t)((uint64_t)(addr) >> 32)) 104 #define getPaddr(high, low) ((uint64_t)(((uint64_t)(high) << 32) | \ 105 ((uint64_t)(low) & 0xffffffff))) 106 107 typedef struct ulp_bde { 108 uint32_t bdeAddress; 109 110 #ifdef EMLXS_BIG_ENDIAN 111 uint32_t bdeReserved:4; 112 uint32_t bdeAddrHigh:4; 113 uint32_t bdeSize:24; 114 #endif 115 #ifdef EMLXS_LITTLE_ENDIAN 116 uint32_t bdeSize:24; 117 uint32_t bdeAddrHigh:4; 118 uint32_t bdeReserved:4; 119 #endif 120 } ulp_bde_t; 121 122 typedef struct ulp_bde64 { 123 union { 124 uint32_t w; 125 struct { 126 #ifdef EMLXS_BIG_ENDIAN 127 uint32_t bdeFlags:8; 128 uint32_t bdeSize:24; 129 #endif 130 #ifdef EMLXS_LITTLE_ENDIAN 131 uint32_t bdeSize:24; 132 uint32_t bdeFlags:8; 133 #endif 134 135 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 136 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 137 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 138 #define BUFF_USE_RCV 0x08 /* """",1=rcv buffer, 0=xmit */ 139 /* buffer */ 140 #define BUFF_TYPE_32BIT 0x10 /* """",1=32 bit addr 0=64 bit */ 141 /* addr */ 142 #define BUFF_TYPE_SPECIA 0x20 /* Not Implemented with LP6000 */ 143 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 144 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 145 } f; 146 } tus; 147 148 uint32_t addrLow; 149 uint32_t addrHigh; 150 151 } ulp_bde64_t; 152 153 typedef struct read_sparm_var { 154 uint32_t rsvd1; 155 uint32_t rsvd2; 156 union { 157 ulp_bde_t sp; 158 ulp_bde64_t sp64; 159 } un; 160 161 } read_sparm_var_t; 162 163 typedef struct read_rev_var { 164 #ifdef EMLXS_BIG_ENDIAN 165 uint32_t cv:1; 166 uint32_t rr:1; 167 uint32_t rsvd1:29; 168 uint32_t rv:1; 169 #endif 170 #ifdef EMLXS_LITTLE_ENDIAN 171 uint32_t rv:1; 172 uint32_t rsvd1:29; 173 uint32_t rr:1; 174 uint32_t cv:1; 175 #endif 176 uint32_t biuRev; 177 uint32_t smRev; 178 union { 179 uint32_t smFwRev; 180 struct { 181 #ifdef EMLXS_BIG_ENDIAN 182 uint8_t ProgType; 183 uint8_t ProgId; 184 uint16_t ProgVer:4; 185 uint16_t ProgRev:4; 186 uint16_t ProgFixLvl:2; 187 uint16_t ProgDistType:2; 188 uint16_t DistCnt:4; 189 #endif 190 #ifdef EMLXS_LITTLE_ENDIAN 191 uint16_t DistCnt:4; 192 uint16_t ProgDistType:2; 193 uint16_t ProgFixLvl:2; 194 uint16_t ProgRev:4; 195 uint16_t ProgVer:4; 196 uint8_t ProgId; 197 uint8_t ProgType; 198 #endif 199 } b; 200 } un; 201 uint32_t endecRev; 202 203 #ifdef EMLXS_BIG_ENDIAN 204 uint8_t feaLevelHigh; 205 uint8_t feaLevelLow; 206 uint8_t fcphHigh; 207 uint8_t fcphLow; 208 #endif 209 #ifdef EMLXS_LITTLE_ENDIAN 210 uint8_t fcphLow; 211 uint8_t fcphHigh; 212 uint8_t feaLevelLow; 213 uint8_t feaLevelHigh; 214 #endif 215 uint32_t postKernRev; 216 uint32_t opFwRev; 217 uint8_t opFwName[16]; 218 uint32_t sli1FwRev; 219 uint8_t sli1FwName[16]; 220 uint32_t sli2FwRev; 221 uint8_t sli2FwName[16]; 222 223 } read_rev_var_t; 224 225 226 typedef struct dump_var { 227 #ifdef EMLXS_BIG_ENDIAN 228 uint32_t rsvd:25; 229 uint32_t ra:1; 230 uint32_t co:1; 231 uint32_t cv:1; 232 uint32_t type:4; 233 234 uint32_t entry_index:16; 235 uint32_t region_id:16; 236 #endif 237 #ifdef EMLXS_LITTLE_ENDIAN 238 uint32_t type:4; 239 uint32_t cv:1; 240 uint32_t co:1; 241 uint32_t ra:1; 242 uint32_t rsvd:25; 243 244 uint32_t region_id:16; 245 uint32_t entry_index:16; 246 #endif 247 uint32_t base_adr; 248 uint32_t word_cnt; 249 uint32_t resp_offset; 250 251 } dump_var_t; 252 253 254 typedef struct read_cfg_var { 255 #ifdef EMLXS_BIG_ENDIAN 256 uint32_t cr:1; 257 uint32_t ci:1; 258 uint32_t cr_delay:6; 259 uint32_t cr_count:8; 260 uint32_t InitBBC:8; 261 uint32_t MaxBBC:8; 262 #endif 263 #ifdef EMLXS_LITTLE_ENDIAN 264 uint32_t MaxBBC:8; 265 uint32_t InitBBC:8; 266 uint32_t cr_count:8; 267 uint32_t cr_delay:6; 268 uint32_t ci:1; 269 uint32_t cr:1; 270 #endif 271 #ifdef EMLXS_BIG_ENDIAN 272 uint32_t topology:8; 273 uint32_t myDid:24; 274 #endif 275 #ifdef EMLXS_LITTLE_ENDIAN 276 uint32_t myDid:24; 277 uint32_t topology:8; 278 #endif 279 /* Defines for topology (defined previously) */ 280 #ifdef EMLXS_BIG_ENDIAN 281 uint32_t AR:1; 282 uint32_t IR:1; 283 uint32_t rsvd1:29; 284 uint32_t ack0:1; 285 #endif 286 #ifdef EMLXS_LITTLE_ENDIAN 287 uint32_t ack0:1; 288 uint32_t rsvd1:29; 289 uint32_t IR:1; 290 uint32_t AR:1; 291 #endif 292 uint32_t edtov; 293 uint32_t arbtov; 294 uint32_t ratov; 295 uint32_t rttov; 296 uint32_t altov; 297 uint32_t lmt; 298 299 #define LMT_1GB_CAPABLE 0x0004 300 #define LMT_2GB_CAPABLE 0x0008 301 #define LMT_4GB_CAPABLE 0x0040 302 #define LMT_8GB_CAPABLE 0x0080 303 #define LMT_10GB_CAPABLE 0x0100 304 305 uint32_t rsvd2; 306 uint32_t rsvd3; 307 uint32_t max_xri; 308 uint32_t max_iocb; 309 uint32_t max_rpi; 310 uint32_t avail_xri; 311 uint32_t avail_iocb; 312 uint32_t avail_rpi; 313 uint32_t default_rpi; 314 315 } read_cfg_var_t; 316 317 318 typedef struct read_log_var { 319 #ifdef EMLXS_BIG_ENDIAN 320 uint32_t type:8; 321 uint32_t byte_count:8; 322 uint32_t write:1; 323 uint32_t resv:3; 324 uint32_t offset:12; 325 #endif 326 #ifdef EMLXS_LITTLE_ENDIAN 327 uint32_t offset:12; 328 uint32_t resv:3; 329 uint32_t write:1; 330 uint32_t byte_count:8; 331 uint32_t type:8; 332 #endif 333 334 uint32_t data; 335 } read_log_var_t; 336 337 338 typedef struct log_status_var { 339 340 #ifdef EMLXS_BIG_ENDIAN 341 uint16_t split_log_next; 342 uint16_t log_next; 343 344 uint32_t size; 345 346 uint32_t format:8; 347 uint32_t resv2:22; 348 uint32_t log_level:1; 349 uint32_t split_log:1; 350 #endif 351 #ifdef EMLXS_LITTLE_ENDIAN 352 uint16_t log_next; 353 uint16_t split_log_next; 354 355 uint32_t size; 356 357 uint32_t split_log:1; 358 uint32_t log_level:1; 359 uint32_t resv2:22; 360 uint32_t format:8; 361 #endif 362 363 uint32_t offset; 364 365 } log_status_var_t; 366 367 368 typedef struct read_evt_log_var { 369 #ifdef EMLXS_BIG_ENDIAN 370 uint32_t read_log:1; 371 uint32_t clear_log:1; 372 uint32_t mbox_rsp:1; 373 uint32_t resv:28; 374 #endif 375 #ifdef EMLXS_LITTLE_ENDIAN 376 uint32_t resv:28; 377 uint32_t mbox_rsp:1; 378 uint32_t clear_log:1; 379 uint32_t read_log:1; 380 #endif 381 382 uint32_t offset; 383 384 union { 385 ulp_bde_t sp; 386 ulp_bde64_t sp64; 387 } un; 388 389 } read_evt_log_var_t; 390 391 392 typedef struct dfc_mailbox { 393 #ifdef EMLXS_BIG_ENDIAN 394 uint16_t mbxStatus; 395 uint8_t mbxCommand; 396 uint8_t mbxReserved:6; 397 uint8_t mbxHc:1; 398 uint8_t mbxOwner:1; /* Low order bit first word */ 399 #endif 400 #ifdef EMLXS_LITTLE_ENDIAN 401 uint8_t mbxOwner:1; /* Low order bit first word */ 402 uint8_t mbxHc:1; 403 uint8_t mbxReserved:6; 404 uint8_t mbxCommand; 405 uint16_t mbxStatus; 406 #endif 407 408 union { 409 uint32_t varWords[31]; 410 read_sparm_var_t varRdSparm; 411 read_rev_var_t varRdRev; 412 read_cfg_var_t varRdCfg; 413 dump_var_t varDmp; 414 read_log_var_t varRdLog; 415 log_status_var_t varLogStat; 416 read_evt_log_var_t varRdEvtLog; 417 418 } un; 419 420 } dfc_mailbox_t; 421 422 423 typedef struct dfc_ioinfo { 424 uint32_t a_mboxCmd; /* mailbox commands issued */ 425 uint32_t a_mboxCmpl; /* mailbox commands completed */ 426 uint32_t a_mboxErr; /* mailbox commands completed, error status */ 427 uint32_t a_iocbCmd; /* iocb command ring issued */ 428 uint32_t a_iocbRsp; /* iocb rsp ring received */ 429 uint32_t a_adapterIntr; /* adapter interrupt events */ 430 uint32_t a_fcpCmd; /* FCP commands issued */ 431 uint32_t a_fcpCmpl; /* FCP command completions received */ 432 uint32_t a_fcpErr; /* FCP command completions errors */ 433 uint32_t a_seqXmit; /* IP xmit sequences sent */ 434 uint32_t a_seqRcv; /* IP sequences received */ 435 uint32_t a_bcastXmit; /* cnt of successful xmit bcast cmds issued */ 436 uint32_t a_bcastRcv; /* cnt of receive bcast cmds received */ 437 uint32_t a_elsXmit; /* cnt of successful ELS req cmds issued */ 438 uint32_t a_elsRcv; /* cnt of ELS request commands received */ 439 uint32_t a_RSCNRcv; /* cnt of RSCN commands received */ 440 uint32_t a_seqXmitErr; /* cnt of unsuccessful xmit bcast cmds issued */ 441 uint32_t a_elsXmitErr; /* cnt of unsuccessful ELS req cmds issued */ 442 uint32_t a_elsBufPost; /* cnt of ELS buffers posted to adapter */ 443 uint32_t a_ipBufPost; /* cnt of IP buffers posted to adapter */ 444 uint32_t a_cnt1; /* generic counter */ 445 uint32_t a_cnt2; /* generic counter */ 446 uint32_t a_cnt3; /* generic counter */ 447 uint32_t a_cnt4; /* generic counter */ 448 449 450 } dfc_ioinfo_t; 451 452 453 typedef struct dfc_linkinfo { 454 uint32_t a_linkEventTag; 455 uint32_t a_linkUp; 456 uint32_t a_linkDown; 457 uint32_t a_linkMulti; 458 uint32_t a_DID; 459 uint8_t a_topology; 460 uint8_t a_linkState; 461 uint8_t a_alpa; 462 uint8_t a_alpaCnt; 463 uint8_t a_alpaMap[128]; 464 uint8_t a_wwpName[8]; 465 uint8_t a_wwnName[8]; 466 467 } dfc_linkinfo_t; 468 469 /* values for a_topology */ 470 #define LNK_LOOP 0x1 471 #define LNK_PUBLIC_LOOP 0x2 472 #define LNK_FABRIC 0x3 473 #define LNK_PT2PT 0x4 474 #define LNK_MENLO_MAINTENANCE 0x5 475 476 /* values for a_linkState */ 477 #define LNK_DOWN 0x1 478 #define LNK_UP 0x2 479 #define LNK_FLOGI 0x3 480 #define LNK_DISCOVERY 0x4 481 #define LNK_REDISCOVERY 0x5 482 #define LNK_READY 0x6 483 484 485 typedef struct dfc_traceinfo { 486 uint8_t a_event; 487 uint8_t a_cmd; 488 uint16_t a_status; 489 uint32_t a_information; 490 491 } dfc_traceinfo_t; 492 493 494 typedef struct dfc_cfgparam { 495 char a_string[32]; 496 uint32_t a_low; 497 uint32_t a_hi; 498 uint32_t a_default; 499 uint32_t a_current; 500 uint16_t a_flag; 501 #define CFG_EXPORT 0x1 /* Export this parameter to the end */ 502 /* user */ 503 #define CFG_IGNORE 0x2 /* Ignore this parameter */ 504 505 uint16_t a_changestate; 506 #define CFG_REBOOT 0x0 /* Changes effective after system */ 507 /* reboot */ 508 #define CFG_DYMANIC 0x1 /* Changes effective immediately */ 509 #define CFG_RESTART 0x2 /* Changes effective after adapter */ 510 /* restart */ 511 512 513 char a_help[80]; 514 515 } dfc_cfgparam_t; 516 517 518 519 typedef struct dfc_nodeinfo { 520 uint16_t a_flag; 521 uint16_t a_state; 522 uint32_t a_did; 523 uint8_t a_wwpn[8]; 524 uint8_t a_wwnn[8]; 525 uint32_t a_targetid; 526 527 } dfc_nodeinfo_t; 528 529 /* Defines for a_state */ 530 #define NODE_UNUSED 0 /* unused NL_PORT entry */ 531 #define NODE_LIMBO 0x1 /* entry to hang around for wwpn/sid */ 532 #define NODE_LOGOUT 0x2 /* NL_PORT not logged in entry cached */ 533 #define NODE_PLOGI 0x3 /* PLOGI was sent to NL_PORT */ 534 #define NODE_LOGIN 0x4 /* NL_PORT is logged in / REG_LOGINed */ 535 #define NODE_PRLI 0x5 /* PRLI was sent to NL_PORT */ 536 #define NODE_ALLOC 0x6 /* NL_PORT ready to start adapter I/O */ 537 #define NODE_SEED 0x7 /* seed scsi id bind in table */ 538 539 /* Defines for a_flag */ 540 #define NODE_RPI_XRI 0x1 /* creating xri for entry */ 541 #define NODE_REQ_SND 0x2 /* sent ELS request for this entry */ 542 #define NODE_ADDR_AUTH 0x4 /* Authenticating addr for this entry */ 543 #define NODE_RM_ENTRY 0x8 /* Remove this entry */ 544 #define NODE_FARP_SND 0x10 /* sent FARP request for this entry */ 545 #define NODE_FABRIC 0x20 /* this entry represents the Fabric */ 546 #define NODE_FCP_TARGET 0x40 /* this entry is an FCP target */ 547 #define NODE_IP_NODE 0x80 /* this entry is an IP node */ 548 #define NODE_DISC_START 0x100 /* start discovery on this entry */ 549 #define NODE_SEED_WWPN 0x200 /* Entry scsi id is seeded for WWPN */ 550 #define NODE_SEED_WWNN 0x400 /* Entry scsi id is seeded for WWNN */ 551 #define NODE_SEED_DID 0x800 /* Entry scsi id is seeded for DID */ 552 #define NODE_SEED_MASK 0xe00 /* mask for seeded flags */ 553 #define NODE_AUTOMAP 0x1000 /* This entry was automap'ed */ 554 #define NODE_NS_REMOVED 0x2000 /* This entry removed from NameServer */ 555 556 557 typedef struct dfc_vpd { 558 uint32_t version; 559 #define DFC_VPD_VERSION 1 560 561 char ModelDescription[256]; /* VPD field V1 */ 562 char Model[80]; /* VPD field V2 */ 563 char ProgramType[256]; /* VPD field V3 */ 564 char PortNum[20]; /* VPD field V4 */ 565 566 } dfc_vpd_t; 567 568 typedef struct dfc_destid { 569 uint32_t idType; /* 0 - wwpn, 1 - d_id */ 570 uint32_t d_id; 571 uint8_t wwpn[8]; 572 573 } dfc_destid_t; 574 575 576 typedef struct dfc_loopback { 577 uint32_t bufSize; 578 uint8_t *XmitBuffer; 579 uint8_t *RcvBuffer; 580 581 } dfc_loopback_t; 582 583 584 typedef struct dfc_drvinfo { 585 uint8_t drvInfoVer; /* Version of this structure */ 586 #define DFC_DRVINFO_VERSION2 0x02 587 #define DFC_DRVINFO_VERSION3 0x03 /* NPIV */ 588 #define DFC_DRVINFO_VERSION4 0x04 /* DHCHAP */ 589 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION2 590 591 #ifdef NPIV_SUPPORT 592 #undef DFC_DRVINFO_VERSION 593 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION3 594 #endif /* NPIV_SUPPORT */ 595 596 #ifdef DHCHAP_SUPPORT 597 #undef DFC_DRVINFO_VERSION 598 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION4 599 #endif /* DHCHAP_SUPPORT */ 600 601 uint8_t drvType; 602 #define DFC_DRVINFO_SOLARIS 0x11 /* Solaris */ 603 #define DFC_DRVINFO_LEADVILLE 0x14 /* Solaris ULP */ 604 605 uint16_t reserved; 606 uint8_t rmLevel; /* Remote Management (HBAnyware) Support */ 607 /* Level */ 608 #define DFC_DRVINFO_RMLEVEL 0x02 /* HBAnyware v2.3 */ 609 610 uint8_t mpLevel; /* MultiPulse support Level */ 611 uint8_t hbaapiLevel; /* HBAAPI support level */ 612 #define DFC_DRVINFO_HBAAPI 0x01 /* HBAAPI v1.0 */ 613 614 uint8_t reserved1; 615 char drvVer[16]; /* Driver Version string */ 616 char drvName[8]; /* Driver Name */ 617 char ftrDrvVer[16]; /* Filter/IOCtl Driver Version string */ 618 char ftrDrvName[8]; /* Filter/IOCtl Driver Name */ 619 char ipDrvVer[16]; /* IP Driver/component Version string */ 620 char ipDrvName[8]; /* IP Driver/component Name */ 621 uint32_t d_id; 622 uint8_t wwpn[8]; 623 uint8_t wwnn[8]; 624 uint8_t hostname[32]; /* IP node hostname from uname -n */ 625 626 #if (DFC_DRVINFO_VERSION >= DFC_DRVINFO_VERSION3) 627 uint32_t NPIVsupport; 628 #define DFC_DRVINFO_NPIV_DRV 0x00000001 629 #define DFC_DRVINFO_NPIV_MODS 0x00000002 630 #define DFC_DRVINFO_NPIV_PARMS 0x00000004 631 #define DFC_DRVINFO_NPIV_FW 0x00000008 632 633 #endif /* >= DFC_DRVINFO_VERSION3 */ 634 635 #if (DFC_DRVINFO_VERSION >= DFC_DRVINFO_VERSION4) 636 uint32_t sliMode; 637 uint64_t featureList; 638 #define DFC_DRVINFO_FEATURE_DIAG 0x00000001 639 #define DFC_DRVINFO_FEATURE_MAPPING 0x00000002 640 #define DFC_DRVINFO_FEATURE_DHCHAP 0x00000004 641 #define DFC_DRVINFO_FEATURE_IKE 0x00000008 642 #define DFC_DRVINFO_FEATURE_NPIV 0x00000010 643 #define DFC_DRVINFO_FEATURE_RESET_WWN 0x00000020 644 #define DFC_DRVINFO_FEATURE_VOLATILE_WWN 0x00000040 645 #define DFC_DRVINFO_FEATURE_E2E_AUTH 0x00000080 646 647 #endif /* >= DFC_DRVINFO_VERSION4 */ 648 649 } dfc_drvinfo_t; 650 651 652 653 typedef struct dfc_regevent { 654 uint32_t ppid; 655 uint32_t cpid; 656 657 uint32_t event; 658 uint32_t type; 659 uint32_t outsz; 660 void *ctx; 661 void (*func) (); 662 663 uint32_t cindex; /* Set only by child */ 664 uint32_t state; /* Set only by child */ 665 666 /* state */ 667 #define CHILD_UNKNOWN 0 668 #define CHILD_UNBORN 1 669 #define CHILD_ALIVE 2 670 #define CHILD_REGISTERED 3 671 #define CHILD_ASLEEP 4 672 #define CHILD_AWAKE 5 673 #define CHILD_DIED 6 674 675 uint32_t pindex; /* Set only by parent */ 676 uint32_t flags; /* Set only by parent */ 677 678 /* flags */ 679 #define EVENT_REGISTERED 0x01 680 #define EVENT_SERVICE_ACTIVE 0x02 681 682 683 } dfc_regevent_t; 684 685 686 /* Defines for RegisterForEvent mask */ 687 #define FC_REG_LINK_EVENT 0x01 /* Register for link up / down events */ 688 #define FC_REG_RSCN_EVENT 0x02 /* Register for RSCN events */ 689 #define FC_REG_CT_EVENT 0x04 /* Register for CT request events */ 690 #define FC_REG_MULTIPULSE_EVENT 0x08 /* Register for MultiPulse events */ 691 #define FC_REG_DUMP_EVENT 0x10 /* Register for Diagnostic Dump */ 692 /* events */ 693 #define FC_REG_TEMP_EVENT 0x20 /* Register for Temperature events */ 694 #define FC_REG_FCOE_EVENT 0x80000000 /* (Unofficial) Register for */ 695 /* FCOE events */ 696 697 #define MAX_RSCN_PAYLOAD 1024 698 #define MAX_CT_PAYLOAD (1024*320) 699 700 /* Temperature event types */ 701 #define DFC_TEMP_CRITICAL 1 702 #define DFC_TEMP_WARNING 2 703 #define DFC_TEMP_SAFE 3 704 705 /* bits in a_onmask */ 706 #define ONDI_MBOX 0x1 /* allows non-destructive mailbox commands */ 707 #define ONDI_IOINFO 0x2 /* supports retrieval of I/O info */ 708 #define ONDI_LNKINFO 0x4 /* supports retrieval of link info */ 709 #define ONDI_NODEINFO 0x8 /* supports retrieval of node info */ 710 #define ONDI_TRACEINFO 0x10 /* supports retrieval of trace info */ 711 #define ONDI_SETTRACE 0x20 /* supports configuration of trace info */ 712 #define ONDI_SLI1 0x40 /* hardware supports SLI-1 interface */ 713 #define ONDI_SLI2 0x80 /* hardware supports SLI-2 interface */ 714 #define ONDI_BIG_ENDIAN 0x100 /* DDI interface is BIG Endian */ 715 #define ONDI_LTL_ENDIAN 0x200 /* DDI interface is LITTLE Endian */ 716 #define ONDI_RMEM 0x400 /* allows reading of adapter shared memory */ 717 #define ONDI_RFLASH 0x800 /* allows reading of adapter flash */ 718 #define ONDI_RPCI 0x1000 /* allows reading of adapter pci registers */ 719 #define ONDI_RCTLREG 0x2000 /* allows reading of adapter cntrol registers */ 720 #define ONDI_CFGPARAM 0x4000 /* supports get/set configuration parameters */ 721 #define ONDI_CT 0x8000 /* supports passthru CT interface */ 722 #define ONDI_HBAAPI 0x10000 /* supports HBA API interface */ 723 #define ONDI_SBUS 0x20000 /* supports SBUS adapter interface */ 724 725 /* bits in a_offmask */ 726 #define OFFDI_MBOX 0x1 /* allows all mailbox commands */ 727 #define OFFDI_RMEM 0x2 /* allows reading of adapter shared memory */ 728 #define OFFDI_WMEM 0x4 /* allows writing of adapter shared memory */ 729 #define OFFDI_RFLASH 0x8 /* allows reading of adapter flash */ 730 #define OFFDI_WFLASH 0x10 /* allows writing of adapter flash */ 731 #define OFFDI_RPCI 0x20 /* allows reading of adapter pci registers */ 732 #define OFFDI_WPCI 0x40 /* allows writing of adapter pci registers */ 733 #define OFFDI_RCTLREG 0x80 /* allows reading of adapter cntrol registers */ 734 #define OFFDI_WCTLREG 0x100 /* allows writing of adapter cntrol registers */ 735 #define OFFDI_OFFLINE 0x80000000 /* if set, adapter is in offline */ 736 /* state */ 737 738 739 #define DDI_SHOW 0x0 740 #define DDI_ONDI 0x1 741 #define DDI_OFFDI 0x2 742 #define DDI_WARMDI 0x3 743 #define DDI_DIAGDI 0x4 744 745 /* mbxStatus */ 746 #define DFC_MBX_SUCCESS 0x00 747 #define DFC_MBXERR_NUM_RINGS 0x01 748 #define DFC_MBXERR_NUM_IOCBS 0x02 749 #define DFC_MBXERR_IOCBS_EXCEEDED 0x03 750 #define DFC_MBXERR_BAD_RING_NUMBER 0x04 751 #define DFC_MBXERR_MASK_ENTRIES_RANGE 0x05 752 #define DFC_MBXERR_MASKS_EXCEEDED 0x06 753 #define DFC_MBXERR_BAD_PROFILE 0x07 754 #define DFC_MBXERR_BAD_DEF_CLASS 0x08 755 #define DFC_MBXERR_BAD_MAX_RESPONDER 0x09 756 #define DFC_MBXERR_BAD_MAX_ORIGINATOR 0x0A 757 #define DFC_MBXERR_RPI_REGISTERED 0x0B 758 #define DFC_MBXERR_RPI_FULL 0x0C 759 #define DFC_MBXERR_NO_RESOURCES 0x0D 760 #define DFC_MBXERR_BAD_RCV_LENGTH 0x0E 761 #define DFC_MBXERR_DMA_ERROR 0x0F 762 #define DFC_MBXERR_ERROR 0x10 763 764 #define DFC_MBXERR_OVERTEMP_ERROR 0xFA 765 #define DFC_MBXERR_HARDWARE_ERROR 0xFB 766 #define DFC_MBXERR_DRVR_ERROR 0xFC 767 #define DFC_MBXERR_BUSY 0xFD 768 #define DFC_MBXERR_TIMEOUT 0xFE 769 #define DFC_MBX_NOT_FINISHED 0xFF 770 771 772 773 /* Error codes for library calls */ 774 #define DFC_ERR_GENERAL_ERROR 0x1 775 776 #define DFC_ERR_MBOX_ERROR 0x2 777 #define DFC_ERR_LINK_DOWN 0x2 778 #define DFC_ERR_INCORRECT_VER 0x2 779 #define DFC_ERR_INVALID_ID 0x2 780 #define DFC_ERR_TIMEOUT 0x2 781 #define DFC_ERR_NOT_SUPPORTED 0x2 782 #define DFC_ERR_NPIV_ACTIVE 0x2 783 784 #define DFC_ERR_NO_RPI 0x3 785 #define DFC_ERR_BUFFER_OVERFLOW 0x3 786 #define DFC_ERR_INVALID_LOOPBACK_TYPE 0x3 787 #define DFC_ERR_OVERTEMP 0x3 788 789 #define DFC_ERR_LOOPBACK_BUSY 0x4 790 #define DFC_ERR_INVALID_RESET_TYPE 0x4 791 #define DFC_ERR_MENLO_LINKDOWN 0x4 792 793 #define DFC_ERR_SEQ_TIMEOUT 0x5 794 795 #define DFC_ERR_NO_XMIT 0x6 796 #define DFC_ERR_INVALID_NUMBER 0x6 797 798 #define DFC_ERR_RESET_RECV 0x7 799 800 801 802 803 /* type definitions for GetBindList function */ 804 typedef enum dfc_bindtype { 805 BIND_NONE, 806 BIND_WWNN, 807 BIND_WWPN, 808 BIND_DID, 809 BIND_ALPA 810 811 } dfc_bindtype_t; 812 813 814 typedef struct dfc_bind_entry { 815 dfc_bindtype_t bind_type; 816 uint32_t scsi_id; 817 uint32_t did; 818 uint8_t wwnn[8]; 819 uint8_t wwpn[8]; 820 uint32_t flags; 821 822 /* Bind Entry flags */ 823 #define DFC_BIND_AUTOMAP 0x1 /* Node is automapped */ 824 #define DFC_BIND_BINDLIST 0x2 /* entry in bind list not mapped */ 825 #define DFC_BIND_MAPPED 0x4 /* Node is mapped to a scsiid */ 826 #define DFC_BIND_UNMAPPED 0x8 /* Node is unmapped */ 827 #define DFC_BIND_NODEVTMO 0x10 /* NODEVTMO flag of the node */ 828 #define DFC_BIND_NOSCSIID 0x20 /* No scsi id is assigned yet */ 829 #define DFC_BIND_RPTLUNST 0x40 /* Node is in report lun cmpl state */ 830 831 } dfc_bind_entry_t; 832 833 typedef struct dfc_bind_list { 834 uint32_t NumberOfEntries; 835 dfc_bind_entry_t entry[1]; /* Variable length array */ 836 } dfc_bind_list_t; 837 838 839 840 /* Defines for error codes -OLD- */ 841 #define FC_ERROR_BUFFER_OVERFLOW 0xff 842 #define FC_ERROR_RESPONSE_TIMEOUT 0xfe 843 #define FC_ERROR_LINK_UNAVAILABLE 0xfd 844 #define FC_ERROR_INSUFFICIENT_RESOURCES 0xfc 845 #define FC_ERROR_EXISTING_REGISTRATION 0xfb 846 #define FC_ERROR_INVALID_TAG 0xfa 847 #define FC_ERROR_INVALID_WWN 0xf9 848 #define FC_ERROR_CREATEVENT_FAILED 0xf8 849 850 851 852 typedef union dfc_ct_rev { 853 /* Structure is in Big Endian format */ 854 struct { 855 uint32_t Revision:8; 856 uint32_t InId:24; 857 } bits; 858 uint32_t word; 859 860 } dfc_ct_rev_t; 861 862 typedef union dfc_ct_resp { 863 /* Structure is in Big Endian format */ 864 struct { 865 uint32_t CmdRsp:16; 866 uint32_t Size:16; 867 } bits; 868 uint32_t word; 869 870 } dfc_ct_resp_t; 871 872 typedef struct dfc_ct_request { 873 /* Structure is in Big Endian format */ 874 dfc_ct_rev_t RevisionId; 875 uint8_t FsType; 876 uint8_t FsSubType; 877 uint8_t Options; 878 uint8_t Rsrvd1; 879 dfc_ct_resp_t CommandResponse; 880 uint8_t Rsrvd2; 881 uint8_t ReasonCode; 882 uint8_t Explanation; 883 uint8_t VendorUnique; 884 885 } dfc_ct_request_t; 886 887 888 #define FC_FSTYPE_ALL 0xffff /* match on all fsTypes */ 889 890 /* Emulex Vendor-Unique CT Request Command Codes */ 891 #define CT_OP_GSAT 0x0101 /* Get Server Attributes */ 892 #define CT_OP_GHAT 0x0102 /* Get HBA Attributes */ 893 #define CT_OP_GPAT 0x0103 /* Get Port Attributes */ 894 #define CT_OP_GDAT 0x0104 /* Get Driver Attributes */ 895 #define CT_OP_GPST 0x0105 /* Get Port Statistics */ 896 /* 0x0106 reserved */ 897 #define CT_OP_GDP 0x0107 /* Get Driver Parameters */ 898 #define CT_OP_GDPG 0x0108 /* Get Driver Parameters Global */ 899 #define CT_OP_GEPS 0x0109 /* Get Extended Port Statistics */ 900 #define CT_OP_GLAT 0x010A /* Get Lun Attributes */ 901 902 #define CT_OP_SSAT 0x0111 /* Set Server Attributes */ 903 #define CT_OP_SHAT 0x0112 /* Set HBA Attributes */ 904 #define CT_OP_SPAT 0x0113 /* Set Port Attributes */ 905 #define CT_OP_SDAT 0x0114 /* Set Driver Attributes */ 906 /* 0x0115 reserved */ 907 /* 0x0116 reserved */ 908 #define CT_OP_SDP 0x0117 /* Set Driver Parameter */ 909 #define CT_OP_SBBS 0x0118 /* Set Boot Bios State */ 910 911 #define CT_OP_RPST 0x0121 /* Reset Port Statistics */ 912 #define CT_OP_VFW 0x0122 /* Verify Firmware */ 913 #define CT_OP_DFW 0x0123 /* Download Firmware */ 914 #define CT_OP_RES 0x0124 /* Reset HBA */ 915 #define CT_OP_RHD 0x0125 /* Run HBA Diagnostic */ 916 #define CT_OP_UFW 0x0126 /* Upgrade Firmware */ 917 #define CT_OP_RDP 0x0127 /* Reset Driver Parameters */ 918 #define CT_OP_GHDR 0x0128 /* Get HBA Diagnotic Results */ 919 #define CT_OP_CHD 0x0129 /* Cancel HBA Diagnostic */ 920 921 /* 0x0131 reserved */ 922 /* 0x0132 reserved */ 923 #define CT_OP_SSR 0x0133 /* Send Software Resource */ 924 925 #define CT_OP_RSAT 0x0141 /* ReadSA Table */ 926 #define CT_OP_WSAT 0x0142 /* Write SA Table */ 927 #define CT_OP_RSAH 0x0143 /* ReadSA Table Header */ 928 #define CT_OP_WSAH 0x0144 /* Write SA Table Header */ 929 #define CT_OP_RACT 0x0145 /* ReadAccess Control Table */ 930 #define CT_OP_WACT 0x0146 /* Write Access Control Table */ 931 #define CT_OP_RKT 0x0147 /* ReadKey Table Table */ 932 #define CT_OP_WKT 0x0148 /* Write Key Table Table */ 933 #define CT_OP_SSC 0x0149 /* Cause SA Table */ 934 /* re-read;sync */ 935 936 #define CT_OP_QHBA 0x0151 /* Query HBA */ 937 #define CT_OP_GST 0x0152 /* Get Status */ 938 939 #define CT_OP_GFTM 0x0161 /* Get FCP Target Mapping */ 940 #define CT_OP_SRL 0x0162 /* SCSI Report Luns */ 941 #define CT_OP_SI 0x0163 /* SCSI Inquiry */ 942 #define CT_OP_SRC 0x0164 /* SCSI Read Capacity */ 943 944 #define CT_OP_GPB 0x0171 /* Get FCP Persistent Binding */ 945 #define CT_OP_SPB 0x0172 /* Set FCP Persistent Binding */ 946 #define CT_OP_RPB 0x0173 /* Remove FCP Persistent Binding */ 947 #define CT_OP_RAPB 0x0174 /* Remove All FCP Persistent Bindings */ 948 #define CT_OP_GBC 0x0175 /* Get Binding Capability */ 949 #define CT_OP_GBS 0x0176 /* Get Binding Support */ 950 #define CT_OP_SBS 0x0177 /* Set Binding Support */ 951 #define CT_OP_GANI 0x0178 /* Get All Nodes Info */ 952 #define CT_OP_GRV 0x0179 /* Get Range Value for Bus#, Target#, */ 953 /* Lun# */ 954 #define CT_OP_GAPBS 0x017A /* Get AutoPB service state */ 955 /* (AutoPilotManager) */ 956 #define CT_OP_APBC 0x017B /* Configure AutoPB service */ 957 /* (AutoPilotManager) */ 958 959 #define CT_OP_GDT 0x0180 /* Get Driver Type */ 960 #define CT_OP_GDLMI 0x0181 /* Get Drive Letter Mapping */ 961 /* Information [GDLM] */ 962 #define CT_OP_GANA 0x0182 /* Get All Node Addresses */ 963 #define CT_OP_GDLV 0x0183 /* Get Driver Library Version */ 964 #define CT_OP_GWUP 0x0184 /* Get Adapter Wakeup Parameters */ 965 #define CT_OP_GLM 0x0185 /* Get Adapter Loopmap */ 966 #define CT_OP_GABS 0x0186 /* Get Adapter Beacon State */ 967 #define CT_OP_SABS 0x0187 /* Set Adapter Beacon State */ 968 #define CT_OP_RPR 0x0188 /* Read Adapter PCI Registers */ 969 970 971 #ifdef NPIV_SUPPORT 972 973 /* NPIV return codes */ 974 #define DFC_NPIV_SUCCESS 0 975 #define DFC_NPIV_GENERAL_ERROR 1 976 #define DFC_NPIV_NOT_SUPPORTED 2 977 #define DFC_NPIV_NO_RESOURCES 3 978 #define DFC_NPIV_INVALID_HANDLE 3 979 #define DFC_NPIV_ILLEGAL_WWPN 4 980 #define DFC_NPIV_TOO_MANY_VPORTS 4 981 #define DFC_NPIV_ILLEGAL_WWN 5 982 #define DFC_NPIV_BUSY 5 983 #define DFC_NPIV_INVALID_WWN 6 984 #define DFC_NPIV_LINK_DOWN 7 985 #define DFC_NPIV_MORE_DATA 7 986 #define DFC_NPIV_FABRIC_NOT_SUPPORTED 8 987 #define DFC_NPIV_FABRIC_OUT_OF_RESOURCE 9 988 #define DFC_NPIV_INVALID_ACCESS_KEY 10 989 #define DFC_NPIV_INVALID_HANDLE_AT_CREATE 11 990 #define DFC_NPIV_UNSUPPORTED_OPTION 12 991 992 typedef struct dfc_vport_QoS { 993 uint32_t resv; 994 995 } dfc_vport_QoS_t; 996 997 998 /* VPORT type */ 999 #define VPORT_TYPE_PHYSICAL 0 1000 #define VPORT_TYPE_VIRTUAL 1 1001 1002 /* VPORT States */ 1003 #define VPORT_STATE_UNKNOWN 0 1004 #define VPORT_STATE_LINKDOWN 1 1005 #define VPORT_STATE_INIT 2 1006 #define VPORT_STATE_NO_FABRIC_SUPPORT 3 1007 #define VPORT_STATE_NO_FABRIC_RESOURCE 4 1008 #define VPORT_STATE_FABRIC_LOGOUT 5 1009 #define VPORT_STATE_FABRIC_REJECT_WWN 6 1010 #define VPORT_STATE_FABRIC_LOGIN_FAIL 7 1011 #define VPORT_STATE_ACTIVE 8 1012 #define VPORT_STATE_AUTH_FAILED 9 1013 1014 /* VPORT Options */ 1015 #define VPORT_OPT_AUTORETRY 0x00000001 1016 #define VPORT_OPT_AUTOWWN 0x00000002 1017 #define VPORT_OPT_ACTIVATE 0x00000004 1018 1019 #define VPORT_OPT_SAVE_CREATE_ONLY 0x00000000 1020 #define VPORT_OPT_SAVE_CREATE_UPDATE 0x00000010 1021 #define VPORT_OPT_SAVE_UPDATE_ONLY 0x00000018 1022 #define VPORT_OPT_SAVE_MASK 0x00000018 1023 1024 #define VPORT_OPT_RESTRICT 0x00000020 1025 #define VPORT_OPT_UNRESTRICT 0x00000040 1026 #define VPORT_OPT_RESTRICT_MASK 0x00000060 1027 1028 #define VPORT_OPT_FAILOVER 0x00000080 1029 1030 /* Check list bit-mapped value */ 1031 #define CL_NPIV_PARM_ENABLE 0x00000001 1032 #define CL_SLI3_ENABLE 0x00000002 1033 #define CL_HBA_SUPPORT_NPIV 0x00000004 1034 #define CL_HBA_HAS_RESOURCES 0x00000008 1035 #define CL_HBA_LINKUP 0x00000010 1036 #define CL_P2P_TOPOLOGY 0x00000020 1037 #define CL_FABRIC_SUPPORTS_NPIV 0x00000040 1038 #define CL_FABRIC_HAS_RESOURCES 0x00000080 1039 #define CL_NPIV_READY 0x000000FF 1040 1041 1042 1043 1044 #define DFC_VPORT_ATTR_VERSION 2 1045 typedef struct dfc_vport_attrs { 1046 uint8_t version; /* 2 = version of this structure, for */ 1047 /* compatibility check */ 1048 uint8_t reserved1[3]; 1049 1050 uint8_t wwpn[8]; /* virtual port WWPN */ 1051 uint8_t wwnn[8]; /* virtual port WWNN */ 1052 char name[256]; /* name to be register with the fabric */ 1053 1054 uint32_t options; 1055 1056 uint32_t portFcId; /* D-ID; set when the N-port is created */ 1057 /* successfully */ 1058 1059 uint8_t state; /* VPORT state */ 1060 uint8_t restrictLogin; 1061 uint8_t reserved2[2]; 1062 uint64_t buf; /* Used for VPI */ 1063 1064 uint8_t fabric_wwn[8]; /* Fabric WWN (WWNN) */ 1065 uint32_t checklist; 1066 uint8_t accessKey[32]; 1067 1068 } dfc_vport_attrs_t; 1069 1070 1071 typedef struct dfc_vport_entry { 1072 uint8_t wwpn[8]; /* wwpn of the virtual port */ 1073 uint8_t wwnn[8]; /* wwnn of the virtual port */ 1074 uint32_t PortFcId; /* FC port ID assigned to this virtual port */ 1075 1076 } dfc_vport_entry_t; 1077 1078 1079 typedef struct dfc_vport_entry_list { 1080 uint32_t NumberOfEntries; 1081 dfc_vport_entry_t entry[MAX_VPORTS]; 1082 1083 } dfc_vport_entry_list_t; 1084 1085 1086 typedef struct dfc_vport_nodeinfo_entry { 1087 uint32_t bind_type; 1088 #define VPORT_NODE_BINDDID 0x0000 1089 #define VPORT_NODE_BINDWWNN 0x0001 1090 #define VPORT_NODE_BINDWWPN 0x0002 1091 #define VPORT_NODE_AUTOMAP 0x0004 1092 #define VPORT_NODE_UNMASK_ALL_LUN 0x0008 1093 #define VPORT_NODE_DISABLE_LUN_AUTOMAP 0x0010 1094 #define VPORT_NODE_ALPA 0x0020 1095 1096 HBA_SCSIID scsiId; 1097 HBA_FCPID fcpId; 1098 1099 uint32_t nodeState; 1100 #define VPORT_NODESTATE_EXIST 0x0001 1101 #define VPORT_NODESTATE_READY 0x0002 1102 #define VPORT_NODESTATE_LINKDOWN 0x0004 1103 #define VPORT_NODESTATE_UNMAPPED 0x0008 1104 #define VPORT_NODESTATE_BOUND 0x0010 1105 1106 1107 uint32_t reserved; 1108 1109 } dfc_vport_nodeinfo_entry_t; 1110 1111 typedef struct dfc_vport_get_nodeinfo { 1112 uint32_t NumberOfEntries; /* number of nodes */ 1113 1114 /* start of the dfc_vport_nodeinfo_entry_t array */ 1115 dfc_vport_nodeinfo_entry_t entry[MAX_NODES]; 1116 1117 } dfc_vport_get_nodeinfo_t; 1118 1119 1120 typedef struct dfc_vport_resource { 1121 uint32_t vpi_max; 1122 uint32_t vpi_inuse; 1123 uint32_t rpi_max; 1124 uint32_t rpi_inuse; 1125 1126 } dfc_vport_resource_t; 1127 1128 1129 typedef struct dfc_vlinkinfo { 1130 uint32_t api_versions; 1131 1132 uint8_t linktype; 1133 uint8_t state; 1134 uint8_t fail_reason; 1135 uint8_t prev_fail_reason; 1136 #define VPORT_FAIL_UNKNOWN 0 1137 #define VPORT_FAIL_LINKDOWN 1 1138 #define VPORT_FAIL_FAB_UNSUPPORTED 2 1139 #define VPORT_FAIL_FAB_NORESOURCES 3 1140 #define VPORT_FAIL_FAB_LOGOUT 4 1141 #define VPORT_FAIL_HBA_NORESOURCES 5 1142 1143 uint8_t wwnn[8]; 1144 uint8_t wwpn[8]; 1145 1146 void *vlink; 1147 1148 uint32_t vpi_max; 1149 uint32_t vpi_inuse; 1150 uint32_t rpi_max; 1151 uint32_t rpi_inuse; 1152 1153 } dfc_vlinkinfo_t; 1154 1155 #endif /* NPIV_SUPPORT */ 1156 1157 1158 #ifdef DHCHAP_SUPPORT 1159 1160 /* DHCHAP return code */ 1161 #define DFC_AUTH_STATUS_NOT_CONFIGURED 0x8001 1162 #define DFC_AUTH_STATUS_AUTH_FAILED_NO_SA_FOUND 0x8002 1163 #define DFC_AUTH_STATUS_AUTH_INIT_OK_AUTH_FAILED 0x8003 1164 #define DFC_AUTH_STATUS_COMPARE_FAILED 0x8004 1165 #define DFC_AUTH_STATUS_WWN_NOT_FOUND 0x8005 1166 #define DFC_AUTH_STATUS_PASSWORD_INVALID 0x8006 1167 #define DFC_AUTH_STATUS_INVALID_ENTITY 0x8007 1168 #define DFC_AUTH_STATUS_ENTITY_NOT_ACTIVE 0x8008 1169 #define DFC_AUTH_STATUS_INVALID_OPERATION 0x8009 1170 #define DFC_AUTH_STATUS_OUT_OF_RESOURCES 0x800a 1171 #define DFC_AUTH_STATUS_AUTHENTICATION_GOINGON 0x800b 1172 #define DFC_AUTH_STATUS_INVALID_BOARD_NO 0x800c 1173 #define DFC_AUTH_STATUS_IO_ERROR 0x800d 1174 #define DFC_AUTH_STATUS_CREATE_STORKEY_ERROR 0x800e 1175 #define DFC_AUTH_STATUS_CREATE_PARMKEY_ERROR 0x800f 1176 #define DFC_AUTH_STATUS_CREATE_AUTHKEY_ERROR 0x8010 1177 #define DFC_AUTH_STATUS_CREATE_BORDKEY_ERROR 0x8020 1178 #define DFC_AUTH_STATUS_DRVTYPE_NOT_SUPPORTED 0x8030 1179 #define DFC_AUTH_STATUS_AUTHENTICATION_NOT_SUPPORTED 0x8031 1180 #define DFC_AUTH_STATUS_GENERAL_ERROR 0x8032 1181 #define DFC_AUTH_STATUS_CONFIG_NOT_FOUND 0x8034 1182 #define DFC_AUTH_STATUS_NOT_PRIVILEGE_USER 0x8040 1183 1184 1185 typedef struct dfc_fcsp_config { 1186 HBA_WWN lwwpn; 1187 HBA_WWN rwwpn; 1188 1189 uint16_t auth_tov; /* seconds */ 1190 #define DFC_AUTH_TOV_MIN 20 1191 #define DFC_AUTH_TOV_MAX 1000 1192 #define DFC_AUTH_TOV_DEFAULT 45 1193 1194 uint8_t auth_mode; 1195 #define DFC_AUTH_MODE_DISABLED 1 1196 #define DFC_AUTH_MODE_ACTIVE 2 1197 #define DFC_AUTH_MODE_PASSIVE 3 1198 #define DFC_AUTH_MODE_DEFAULT DFC_AUTH_MODE_DISABLED 1199 1200 uint8_t auth_bidir:1; 1201 #define DFC_AUTH_BIDIR_DISABLED 0 1202 #define DFC_AUTH_BIDIR_ENABLED 1 1203 #define DFC_AUTH_BIDIR_DEFAULT DFC_AUTH_BIDIR_DISABLED 1204 uint8_t reserved:7; 1205 1206 uint8_t type_priority[4]; 1207 #define DFC_AUTH_TYPE_DHCHAP 1 /* Only one supported */ 1208 #define DFC_AUTH_TYPE_FCAP 2 1209 #define DFC_AUTH_TYPE_FCPAP 3 1210 #define DFC_AUTH_TYPE_KERBEROS 4 1211 #define DFC_AUTH_TYPE_MAX 4 1212 #define DFC_AUTH_TYPE_DEFAULT0 DFC_AUTH_TYPE_DHCHAP 1213 #define DFC_AUTH_TYPE_DEFAULT1 0 1214 #define DFC_AUTH_TYPE_DEFAULT2 0 1215 #define DFC_AUTH_TYPE_DEFAULT3 0 1216 1217 uint8_t hash_priority[4]; 1218 #define DFC_AUTH_HASH_MD5 1 1219 #define DFC_AUTH_HASH_SHA1 2 1220 #define DFC_AUTH_HASH_MAX 2 1221 #define DFC_AUTH_HASH_DEFAULT0 DFC_AUTH_HASH_MD5 1222 #define DFC_AUTH_HASH_DEFAULT1 DFC_AUTH_HASH_SHA1 1223 #define DFC_AUTH_HASH_DEFAULT2 0 1224 #define DFC_AUTH_HASH_DEFAULT3 0 1225 1226 uint8_t group_priority[8]; 1227 #define DFC_AUTH_GROUP_NULL 1 1228 #define DFC_AUTH_GROUP_1024 2 1229 #define DFC_AUTH_GROUP_1280 3 1230 #define DFC_AUTH_GROUP_1536 4 1231 #define DFC_AUTH_GROUP_2048 5 1232 #define DFC_AUTH_GROUP_MAX 5 1233 1234 #define DFC_AUTH_GROUP_DEFAULT0 DFC_AUTH_GROUP_NULL 1235 #define DFC_AUTH_GROUP_DEFAULT1 DFC_AUTH_GROUP_1024 1236 #define DFC_AUTH_GROUP_DEFAULT2 DFC_AUTH_GROUP_1280 1237 #define DFC_AUTH_GROUP_DEFAULT3 DFC_AUTH_GROUP_1536 1238 #define DFC_AUTH_GROUP_DEFAULT4 DFC_AUTH_GROUP_2048 1239 #define DFC_AUTH_GROUP_DEFAULT5 0 1240 #define DFC_AUTH_GROUP_DEFAULT6 0 1241 #define DFC_AUTH_GROUP_DEFAULT7 0 1242 1243 uint32_t reauth_tov; /* minutes */ 1244 #define DFC_REAUTH_TOV_MIN 0 1245 #define DFC_REAUTH_TOV_MAX 7200 1246 #define DFC_REAUTH_TOV_DEFAULT 1440 1247 1248 } dfc_fcsp_config_t; 1249 1250 1251 typedef struct dfc_password { 1252 uint16_t length; 1253 #define DFC_PASSWORD_LENGTH_MIN 8 1254 #define DFC_PASSWORD_LENGTH_MAX 128 1255 1256 uint16_t type; 1257 #define DFC_PASSWORD_TYPE_ASCII 1 1258 #define DFC_PASSWORD_TYPE_BINARY 2 1259 #define DFC_PASSWORD_TYPE_IGNORE 3 1260 1261 uint8_t password[DFC_PASSWORD_LENGTH_MAX]; 1262 1263 } dfc_password_t; 1264 1265 typedef struct dfc_auth_password { 1266 HBA_WWN lwwpn; 1267 HBA_WWN rwwpn; 1268 1269 dfc_password_t lpw; 1270 dfc_password_t rpw; 1271 1272 dfc_password_t lpw_new; 1273 dfc_password_t rpw_new; 1274 1275 } dfc_auth_password_t; 1276 1277 1278 typedef struct dfc_auth_cfglist { 1279 uint32_t cnt; 1280 HBA_WWN rwwpn[1]; 1281 1282 } dfc_auth_cfglist_t; 1283 1284 1285 typedef struct dfc_auth_status { 1286 HBA_WWN lwwpn; 1287 HBA_WWN rwwpn; 1288 1289 uint8_t auth_state; 1290 #define DFC_AUTH_STATE_OFF 1 1291 #define DFC_AUTH_STATE_INP 2 1292 #define DFC_AUTH_STATE_ON 3 1293 #define DFC_AUTH_STATE_FAILED 4 1294 1295 uint8_t auth_failReason; 1296 #define DFC_AUTH_FAIL_GENERIC 1 1297 #define DFC_AUTH_FAIL_ELS_TMO 2 1298 #define DFC_AUTH_FAIL_XACT_TMO 3 1299 #define DFC_AUTH_FAIL_LS_RJT 4 1300 #define DFC_AUTH_FAIL_BSY_LS_RJT 5 1301 #define DFC_AUTH_FAIL_REJECTED 6 1302 1303 uint8_t type_priority; 1304 uint8_t group_priority; 1305 1306 uint8_t hash_priority; 1307 uint8_t localAuth:1; 1308 uint8_t remoteAuth:1; 1309 uint8_t pad:6; 1310 uint16_t reserved0; 1311 1312 uint32_t time_from_last_auth; /* seconds */ 1313 uint32_t time_until_next_auth; /* seconds */ 1314 1315 uint32_t reserved1; 1316 uint32_t reserved2; 1317 1318 } dfc_auth_status_t; 1319 1320 #endif /* DHCHAP_SUPPORT */ 1321 1322 /* 1323 * Start of FCP specific structures 1324 */ 1325 1326 #ifndef MAX_FCP_SNS 1327 typedef struct emlxs_fcp_rsp { 1328 uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 1329 uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 1330 1331 uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 1332 uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 1333 uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 1334 #define RSP_LEN_VALID 0x01 /* bit 0 */ 1335 #define SNS_LEN_VALID 0x02 /* bit 1 */ 1336 #define RESID_OVER 0x04 /* bit 2 */ 1337 #define RESID_UNDER 0x08 /* bit 3 */ 1338 uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 1339 #define SCSI_STAT_GOOD 0x00 1340 #define SCSI_STAT_CHECK_COND 0x02 1341 #define SCSI_STAT_COND_MET 0x04 1342 #define SCSI_STAT_BUSY 0x08 1343 #define SCSI_STAT_INTERMED 0x10 1344 #define SCSI_STAT_INTERMED_CM 0x14 1345 #define SCSI_STAT_RES_CNFLCT 0x18 1346 #define SCSI_STAT_CMD_TERM 0x22 1347 #define SCSI_STAT_QUE_FULL 0x28 1348 #define SCSI_STAT_ACA_ACTIVE 0x30 1349 #define SCSI_STAT_TASK_ABORT 0x40 1350 1351 uint32_t rspResId; /* Residual xfer if RESID_xxxx set in */ 1352 /* fcpStatus2 */ 1353 /* Received in Big Endian format */ 1354 uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 1355 /* Received in Big Endian format */ 1356 uint32_t rspRspLen; /* Length of FCP response data in fcpRspInfo */ 1357 /* Received in Big Endian format */ 1358 1359 uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 1360 uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 1361 uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 1362 uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 1363 1364 #define RSP_NO_FAILURE 0x00 1365 #define RSP_DATA_BURST_ERR 0x01 1366 #define RSP_CMD_FIELD_ERR 0x02 1367 #define RSP_RO_MISMATCH_ERR 0x03 1368 #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 1369 #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 1370 1371 uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 1372 1373 /* 1374 * Define maximum size of SCSI Sense buffer. Seagate never issues 1375 * more than 18 bytes of Sense data 1376 */ 1377 #define MAX_FCP_SNS 128 1378 uint8_t rspSnsInfo[MAX_FCP_SNS]; 1379 1380 } emlxs_fcp_rsp; 1381 typedef emlxs_fcp_rsp FCP_RSP; 1382 #endif /* MAX_FCP_SNS */ 1383 1384 1385 #ifndef FC_LUN_SHIFT 1386 typedef struct emlxs_fcp_cmd { 1387 uint32_t fcpLunMsl; /* most significant lun word (32 bits) */ 1388 uint32_t fcpLunLsl; /* least significant lun word (32 bits) */ 1389 1390 /* 1391 * # of bits to shift lun id to end up in right payload word, little 1392 * endian = 8, big = 16. 1393 */ 1394 #ifdef EMLXS_LITTLE_ENDIAN 1395 #define FC_LUN_SHIFT 8 1396 #define FC_ADDR_MODE_SHIFT 0 1397 #endif 1398 #ifdef EMLXS_BIG_ENDIAN 1399 #define FC_LUN_SHIFT 16 1400 #define FC_ADDR_MODE_SHIFT 24 1401 #endif 1402 1403 uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 1404 uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 1405 #define SIMPLE_Q 0x00 1406 #define HEAD_OF_Q 0x01 1407 #define ORDERED_Q 0x02 1408 #define ACA_Q 0x04 1409 #define UNTAGGED 0x05 1410 uint8_t fcpCntl2; /* FCP_CTL byte 2 task management codes */ 1411 #define ABORT_TASK_SET 0x02 /* Bit 1 */ 1412 #define CLEAR_TASK_SET 0x04 /* bit 2 */ 1413 #define LUN_RESET 0x10 /* bit 4 */ 1414 #define TARGET_RESET 0x20 /* bit 5 */ 1415 #define CLEAR_ACA 0x40 /* bit 6 */ 1416 #define TERMINATE_TASK 0x80 /* bit 7 */ 1417 uint8_t fcpCntl3; 1418 #define WRITE_DATA 0x01 /* Bit 0 */ 1419 #define READ_DATA 0x02 /* Bit 1 */ 1420 1421 uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 1422 uint32_t fcpDl; /* Total transfer length */ 1423 1424 } emlxs_fcp_cmd_t; 1425 typedef emlxs_fcp_cmd_t FCP_CMND; 1426 #endif /* FC_LUN_SHIFT */ 1427 1428 1429 /* 1430 * Used by libdfc (SendScsiCmd, SendFcpCmd, DFC_SendScsiCmdV2, DFC_SendFcpCmdV2 1431 * and emlxs_dfc_send_scsi_fcp functions 1432 */ 1433 typedef struct dfc_send_scsi_fcp_cmd_info { 1434 HBA_WWN src_wwn; 1435 HBA_WWN dst_wwn; 1436 uint32_t cnt1; 1437 uint32_t cnt2; 1438 uint32_t ver; 1439 1440 } dfc_send_scsi_fcp_cmd_info_t; 1441 #define SCSI_RSP_CNT(x) x.cnt1 1442 #define SCSI_SNS_CNT(x) x.cnt2 1443 #define FC_DATA_CNT(x) x.cnt1 1444 #define FC_RSP_CNT(x) x.cnt2 1445 #define DFC_SEND_SCSI_FCP_V1 1 1446 #define DFC_SEND_SCSI_FCP_V2 2 1447 1448 #ifdef __cplusplus 1449 } 1450 #endif 1451 1452 #endif /* _EMLXS_DFCLIB_H */ 1453