1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2019, Joyent, Inc. 24 * Copyright 2022 Oxide Computer Company 25 */ 26 27 #ifndef _SYS_AUXV_386_H 28 #define _SYS_AUXV_386_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * Flags used in AT_SUN_HWCAP elements to describe various userland 36 * instruction set extensions available on different processors. 37 * The basic assumption is that of the i386 ABI; that is, i386 plus i387 38 * floating point. 39 * 40 * Note that if a given bit is set; the implication is that the kernel 41 * provides all the underlying architectural support for the correct 42 * functioning of the extended instruction(s). 43 */ 44 #define AV_386_FPU 0x00001 /* x87-style floating point */ 45 #define AV_386_TSC 0x00002 /* rdtsc insn */ 46 #define AV_386_CX8 0x00004 /* cmpxchg8b insn */ 47 #define AV_386_SEP 0x00008 /* sysenter and sysexit */ 48 #define AV_386_AMD_SYSC 0x00010 /* AMD's syscall and sysret */ 49 #define AV_386_CMOV 0x00020 /* conditional move insns */ 50 #define AV_386_MMX 0x00040 /* MMX insns */ 51 #define AV_386_AMD_MMX 0x00080 /* AMD's MMX insns */ 52 #define AV_386_AMD_3DNow 0x00100 /* AMD's 3Dnow! insns */ 53 #define AV_386_AMD_3DNowx 0x00200 /* AMD's 3Dnow! extended insns */ 54 #define AV_386_FXSR 0x00400 /* fxsave and fxrstor */ 55 #define AV_386_SSE 0x00800 /* SSE insns and regs */ 56 #define AV_386_SSE2 0x01000 /* SSE2 insns and regs */ 57 /* 0x02000 withdrawn - do not assign */ 58 #define AV_386_SSE3 0x04000 /* SSE3 insns and regs */ 59 /* 0x08000 withdrawn - do not assign */ 60 #define AV_386_CX16 0x10000 /* cmpxchg16b insn */ 61 #define AV_386_AHF 0x20000 /* lahf/sahf insns */ 62 #define AV_386_TSCP 0x40000 /* rdtscp instruction */ 63 #define AV_386_AMD_SSE4A 0x80000 /* AMD's SSE4A insns */ 64 #define AV_386_POPCNT 0x100000 /* POPCNT insn */ 65 #define AV_386_AMD_LZCNT 0x200000 /* AMD's LZCNT insn */ 66 #define AV_386_SSSE3 0x400000 /* Intel SSSE3 insns */ 67 #define AV_386_SSE4_1 0x800000 /* Intel SSE4.1 insns */ 68 #define AV_386_SSE4_2 0x1000000 /* Intel SSE4.2 insns */ 69 #define AV_386_MOVBE 0x2000000 /* Intel MOVBE insns */ 70 #define AV_386_AES 0x4000000 /* Intel AES insns */ 71 #define AV_386_PCLMULQDQ 0x8000000 /* Intel PCLMULQDQ insn */ 72 #define AV_386_XSAVE 0x10000000 /* Intel XSAVE/XRSTOR insns */ 73 #define AV_386_AVX 0x20000000 /* Intel AVX insns */ 74 #define AV_386_VMX 0x40000000 /* Intel VMX support */ 75 #define AV_386_AMD_SVM 0x80000000 /* AMD SVM support */ 76 77 #define FMT_AV_386 \ 78 "\020" \ 79 "\040svm\037vmx\036avx\035xsave" \ 80 "\034pclmulqdq\033aes" \ 81 "\032movbe\031sse4.2" \ 82 "\030sse4.1\027ssse3\026amd_lzcnt\025popcnt" \ 83 "\024amd_sse4a\023tscp\022ahf\021cx16" \ 84 "\017sse3\015sse2\014sse\013fxsr\012amd3dx\011amd3d" \ 85 "\010amdmmx\07mmx\06cmov\05amdsysc\04sep\03cx8\02tsc\01fpu" 86 87 /* 88 * Flags used in AT_SUN_HWCAP2 elements 89 */ 90 #define AV_386_2_F16C 0x00000001 /* F16C half percision extensions */ 91 #define AV_386_2_RDRAND 0x00000002 /* RDRAND insn */ 92 #define AV_386_2_BMI1 0x00000004 /* BMI1 insns */ 93 #define AV_386_2_BMI2 0x00000008 /* BMI2 insns */ 94 #define AV_386_2_FMA 0x00000010 /* FMA insns */ 95 #define AV_386_2_AVX2 0x00000020 /* AVX2 insns */ 96 #define AV_386_2_ADX 0x00000040 /* ADX insns */ 97 #define AV_386_2_RDSEED 0x00000080 /* RDSEED insn */ 98 #define AV_386_2_AVX512F 0x00000100 /* AVX512 foundation insns */ 99 #define AV_386_2_AVX512DQ 0x00000200 /* AVX512DQ insns */ 100 #define AV_386_2_AVX512IFMA 0x00000400 /* AVX512IFMA insns */ 101 #define AV_386_2_AVX512PF 0x00000800 /* AVX512PF insns */ 102 #define AV_386_2_AVX512ER 0x00001000 /* AVX512ER insns */ 103 #define AV_386_2_AVX512CD 0x00002000 /* AVX512CD insns */ 104 #define AV_386_2_AVX512BW 0x00004000 /* AVX512BW insns */ 105 #define AV_386_2_AVX512VL 0x00008000 /* AVX512VL insns */ 106 #define AV_386_2_AVX512VBMI 0x00010000 /* AVX512VBMI insns */ 107 #define AV_386_2_AVX512VPOPCDQ 0x00020000 /* AVX512VPOPCNTDQ insns */ 108 #define AV_386_2_AVX512_4NNIW 0x00040000 /* AVX512 4NNIW insns */ 109 #define AV_386_2_AVX512_4FMAPS 0x00080000 /* AVX512 4FMAPS insns */ 110 #define AV_386_2_SHA 0x00100000 /* SHA insns */ 111 #define AV_386_2_FSGSBASE 0x00200000 /* FSBASE/GSBASE */ 112 #define AV_386_2_CLFLUSHOPT 0x00400000 /* CLFLUSHOPT instr */ 113 #define AV_386_2_CLWB 0x00800000 /* CLWB insn */ 114 #define AV_386_2_MONITORX 0x01000000 /* MONITORX insns */ 115 #define AV_386_2_CLZERO 0x02000000 /* CLZERO */ 116 #define AV_386_2_AVX512_VNNI 0x04000000 /* AVX512_VNNI */ 117 #define AV_386_2_VPCLMULQDQ 0x08000000 /* VPCLMULQDQ */ 118 #define AV_386_2_VAES 0x10000000 /* VAES */ 119 #define AV_386_2_GFNI 0x20000000 /* GFNI */ 120 #define AV_386_2_AVX512_VP2INT 0x40000000 /* AVX512 VP2INTERESECT */ 121 #define AV_386_2_AVX512_BITALG 0x80000000 /* AVX512 BITALG */ 122 123 #define FMT_AV_386_2 \ 124 "\040avx512_vbmi2\037avx512_vp2intersect" \ 125 "\036gfni\035vaes\034vpclmulqdq\033avx512_vnni" \ 126 "\032clzero\031monitorx\030clwb\027clflushopt\026fsgsbase" \ 127 "\025sha\024avx512_4fmaps\023avx512_4nniw\022avx512vpopcntdq" \ 128 "\021avx512vbmi\020avx512vl\017avx512bw\016avx512cd" \ 129 "\015avx512er\014avx512pf\013avx512ifma\012avx512dq\011avx512f" \ 130 "\010rdseed\07adx\06avx2\05fma\04bmi2\03bmi1\02rdrand\01f16c" 131 132 /* 133 * Flags used in AT_SUN_HWCAP3 elements 134 */ 135 #define AV_386_3_AVX512_VBMI2 0x00000001 /* AVX512_VBMI2 */ 136 #define AV_386_3_AVX512_BF16 0x00000002 /* AVX512_BF16 */ 137 138 #define FMT_AV_386_3 \ 139 "\02avx512_bf16\01avx512_vbmi2" 140 141 /* 142 * Flags used in AT_SUN_FPTYPE on x86. 143 * 144 * We don't currently support xsavec in illumos. However, when we do, then we 145 * should add this to the type list and extend our primary consumer (rtld) to 146 * use it. xsaveopt is not in this list because it is not appropriate for the 147 * stack based storage. 148 */ 149 #define AT_386_FPINFO_NONE 0 150 #define AT_386_FPINFO_FXSAVE 1 151 #define AT_386_FPINFO_XSAVE 2 152 #define AT_386_FPINFO_XSAVE_AMD 3 153 154 #ifdef __cplusplus 155 } 156 #endif 157 158 #endif /* !_SYS_AUXV_386_H */ 159