1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_1394_S1394_H 28 #define _SYS_1394_S1394_H 29 30 /* 31 * s1394.h 32 * Contains all of the structures used (internally) by the 1394 33 * Software Framework 34 */ 35 36 #include <sys/types.h> 37 #include <sys/dditypes.h> 38 #include <sys/ddi.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/callb.h> 42 #include <sys/note.h> 43 44 #include <sys/1394/s1394_impl.h> 45 #include <sys/1394/t1394.h> 46 #include <sys/1394/h1394.h> 47 #include <sys/1394/cmd1394.h> 48 #include <sys/1394/ieee1212.h> 49 #include <sys/1394/ieee1394.h> 50 51 #ifdef __cplusplus 52 extern "C" { 53 #endif 54 55 /* SelfID buffer size */ 56 #define S1394_SELFID_BUF_SIZE 8192 57 58 /* Maximum number of allocated commands per target */ 59 #define MAX_NUMBER_ALLOC_CMDS 256 60 61 /* Maximum number of lock retries */ 62 #define MAX_NUMBER_OF_LOCK_RETRIES 256 63 64 #define S1394_INITIAL_STATES 2 65 66 /* Invalid entry in the Speed Map */ 67 #define SPEED_MAP_INVALID 0xFF 68 69 /* Invalid node num */ 70 #define S1394_INVALID_NODE_NUM 0x3F 71 72 /* Node state */ 73 #define S1394_NODE_OFFLINE 1 74 #define S1394_NODE_ONLINE 2 75 76 /* Where are commands inserted onto the pending Q? */ 77 #define S1394_PENDING_Q_FRONT 1 78 #define S1394_PENDING_Q_REAR 2 79 80 /* Number of self-initiated bus resets until HAL fails */ 81 #define NUM_BR_FAIL 5 82 83 /* Reasons for Self-Initiated Bus Reset */ 84 #define NON_CRITICAL 0 85 #define CRITICAL 1 86 87 /* Bus Mgr (IRM) defines */ 88 #define ROOT_HOLDOFF (1 << 0) 89 #define GAP_COUNT (1 << 1) 90 91 /* Root Node has no parents */ 92 #define NO_PARENT -1 93 94 /* Maximum number of Hops between Nodes on the Bus */ 95 #define MAX_HOPS 23 96 97 /* Invalid lo and hi addresses used in s1394_init_addr_space() */ 98 #define ADDR_LO_INVALID 0x0000000000000001 99 #define ADDR_HI_INVALID 0x0000000000000000 100 101 /* Time to delay after CYCLE_TOO_LONG before enabling cycle master */ 102 #define CYCLE_MASTER_TIMER 1000 /* 1 second */ 103 104 /* Size of directory stack used during config rom scan */ 105 #define S1394_DIR_STACK_SIZE 16 106 107 /* 108 * P1394a (Draft 2.x) proposes to disallow a 109 * Config ROM "generation" to be repeated within 110 * a 60 second window. 111 * Because of that, this value should not be set 112 * to any value smaller than 5 seconds without 113 * another method in place to ensure that this 114 * "generation" reuse can not happen. 115 */ 116 117 /* 118 * Time delay (in ms) from Config ROM update to 119 * software-initiated bus reset. 120 */ 121 #define CONFIG_ROM_UPDATE_DELAY 5000 /* 5 seconds */ 122 123 #define S1394_ROOT_TEXT_LEAF_SZ 36 124 #define S1394_ROOT_TEXT_LEAF_QUAD_SZ 9 125 #define S1394_ROOT_TEXT_KEY 0x81 126 127 #define S1394_NODE_UNIQUE_ID_SZ 12 128 #define S1394_NODE_UNIQUE_ID_QUAD_SZ 3 129 #define S1394_NODE_UNIQUE_ID_KEY 0x8D 130 131 #define S1394_UNIT_DIR_SZ 56 132 #define S1394_UNIT_DIR_QUAD_SZ 14 133 #define S1394_UNIT_DIR_KEY 0xD1 134 135 /* The Organizationally Unique Identifier for Sun Microsystems, Inc. */ 136 #define S1394_SUNW_OUI 0x080020 137 138 /* Number of retries in reading the Config ROM */ 139 #define CFGROM_READ_RETRIES 5 140 141 /* Delay time between reads of the Config ROM */ 142 #define CFGROM_READ_DELAY 20000 /* 20ms */ 143 144 /* Error message for serious HBA hardware shutdowns */ 145 #define HALT_ERROR_MESSAGE "%s%d: Unexpected Error: Shutting down HBA -" \ 146 " Hardware disabled until next reboot" 147 148 /* Command Transaction Type */ 149 #define S1394_CMD_READ 0 150 #define S1394_CMD_WRITE 1 151 #define S1394_CMD_LOCK 2 152 153 /* Channel allocations */ 154 #define S1394_CHANNEL_ALLOC_HI 1 155 #define S1394_CHANNEL_ALLOC_LO 0 156 157 /* Maximum number of bus resets allowed in isoch rsrc alloc */ 158 #define S1394_ISOCH_ALLOC_RETRIES 5 159 160 #define ADDR_RESERVED 1 161 162 /* Flags used by the used tree (red-black tree) */ 163 #define BLACK 0 164 #define RED 1 165 #define LEFT 0 166 #define RIGHT 1 167 168 /* Isoch Bandwidth Allocation Units conversion */ 169 #define ISOCH_SPEED_FACTOR_S100 16 170 #define ISOCH_SPEED_FACTOR_S200 8 171 #define ISOCH_SPEED_FACTOR_S400 4 172 173 /* s1394_hal_state_t */ 174 typedef enum { 175 S1394_HAL_INIT, 176 S1394_HAL_RESET, 177 S1394_HAL_NORMAL, 178 S1394_HAL_DREQ, 179 S1394_HAL_SHUTDOWN 180 } s1394_hal_state_t; 181 182 /* s1394_isoch_cec_type_t */ 183 typedef enum { 184 S1394_SINGLE = 1, 185 S1394_PEER_TO_PEER = 2 186 } s1394_isoch_cec_type_t; 187 188 /* s1394_isoch_cec_state_t */ 189 typedef enum { 190 ISOCH_CEC_FREE = (1 << 0), 191 ISOCH_CEC_JOIN = (1 << 1), 192 ISOCH_CEC_LEAVE = (1 << 2), 193 ISOCH_CEC_SETUP = (1 << 3), 194 ISOCH_CEC_TEARDOWN = (1 << 4), 195 ISOCH_CEC_START = (1 << 5), 196 ISOCH_CEC_STOP = (1 << 6) 197 } s1394_isoch_cec_state_t; 198 199 /* s1394_status_t */ 200 typedef enum { 201 S1394_NOSTATUS = (1 << 0), 202 S1394_LOCK_FAILED = (1 << 1), 203 S1394_CMD_ALLOC_FAILED = (1 << 2), 204 S1394_XFER_FAILED = (1 << 3), 205 S1394_UNKNOWN = (1 << 4), 206 S1394_CMD_INFLIGHT = (1 << 5) 207 } s1394_status_t; 208 209 /* s1394_free_cfgrom_t */ 210 typedef enum { 211 S1394_FREE_CFGROM_BOTH, 212 S1394_FREE_CFGROM_NEW, 213 S1394_FREE_CFGROM_OLD 214 } s1394_free_cfgrom_t; 215 216 typedef struct s1394_node_s s1394_node_t; 217 typedef struct s1394_target_s s1394_target_t; 218 typedef struct s1394_hal_s s1394_hal_t; 219 typedef struct s1394_addr_space_blk_s s1394_addr_space_blk_t; 220 typedef struct s1394_config_rom_s s1394_config_rom_t; 221 typedef struct s1394_kstat_s s1394_kstat_t; 222 typedef struct s1394_isoch_cec_s s1394_isoch_cec_t; 223 typedef struct s1394_isoch_cec_member_s s1394_isoch_cec_member_t; 224 225 /* cfgrom_dir_t */ 226 typedef struct { 227 ushort_t dir_start; 228 ushort_t dir_size; 229 ushort_t dir_next_quad; 230 } cfgrom_dir_t; 231 232 /* s1394_selfid_pkt_t */ 233 typedef struct s1394_selfid_pkt_s { 234 uint32_t spkt_data; 235 uint32_t spkt_inverse; 236 } s1394_selfid_pkt_t; 237 238 /* s1394_node_t */ 239 struct s1394_node_s { 240 s1394_selfid_pkt_t *selfid_packet; 241 s1394_node_t *phy_port[IEEE1394_MAX_NUM_PORTS]; 242 s1394_node_t *old_node; 243 s1394_node_t *cur_node; 244 s1394_target_t *target_list; 245 ushort_t cfgrom_size; /* in quads */ 246 ushort_t cfgrom_valid_size; /* in quads */ 247 uchar_t link_active; 248 uchar_t node_num; 249 uchar_t max_1st; 250 uchar_t max_2nd; 251 uchar_t last_port_checked; 252 uchar_t parent_port; 253 uchar_t is_a_leaf; 254 /* All fields above can be zero'd while initing the topology tree */ 255 uint32_t *cfgrom; 256 #define node_guid_hi cfgrom[3] 257 #define node_guid_lo cfgrom[4] 258 #define node_root_dir cfgrom[5] 259 uint_t node_state; 260 uint_t cfgrom_state; 261 uint_t bus_enum_flags; 262 /* fields dir_stack through expected_dir_quad constitute dir stack */ 263 cfgrom_dir_t dir_stack[S1394_DIR_STACK_SIZE]; 264 ushort_t cur_dir_start; 265 ushort_t cur_dir_size; 266 char dir_stack_top; 267 uchar_t expected_type; 268 uchar_t expected_dir_quad; 269 ushort_t cfgrom_quad_to_read; 270 ushort_t cfgrom_quad_read_cnt; /* if rdg blk */ 271 uchar_t rescan_cnt; 272 uchar_t cfgrom_read_fails; 273 uchar_t cfgrom_read_delay; /* in ms */ 274 }; 275 276 /* defines used during enumeration */ 277 #define NODE_DIR_SIZE(data) ((data) & 0xff) 278 #define NODE_DIR_START(data) (((data) >> 8) & 0xff) 279 #define NODE_DIR_QUAD(data) (((data) >> 16) & 0xff) 280 281 /* defines for link_active */ 282 #define SET_LINK_ACTIVE(n) ((n)->link_active = 1) 283 #define CLEAR_LINK_ACTIVE(n) ((n)->link_active = 0) 284 #define LINK_ACTIVE(n) \ 285 (((n)->link_active == 0) ? B_FALSE : B_TRUE) 286 /* defines for state */ 287 #define S1394_NODE_CONSUMING_PWR 0x00000001 288 #define S1394_NODE_ACTIVE 0x00000010 289 #define S1394_NODE_BUS_PWR_CONSUMER(n) \ 290 ((IEEE1394_SELFID_POWER((n)->selfid_packet) > 0x3) ? B_TRUE : B_FALSE) 291 292 /* defines for cfgrom_state */ 293 #define S1394_CFGROM_NEW_ALLOC 0x00000001 /* fresh alloc */ 294 #define S1394_CFGROM_BIB_READ 0x00000002 /* bus info blocks read */ 295 #define S1394_CFGROM_ALL_READ 0x00000004 /* read all of it */ 296 #define S1394_CFGROM_BLK_READ_OK 0x00000008 /* can be read in blocks */ 297 #define S1394_CFGROM_GEN_CHANGED 0x00000010 /* config rom gen changed */ 298 #define S1394_CFGROM_PARSED 0x00000020 /* rom enumerated */ 299 #define S1394_CFGROM_DIR_STACK_OFF 0x00000040 /* dir stack turned off */ 300 #define S1394_CFGROM_SIZE_IS_CRCSIZE 0x00000080 /* crc size == cfgrom size */ 301 302 #define S1394_CFGROM_READ_MASK (S1394_CFGROM_BIB_READ | S1394_CFGROM_ALL_READ) 303 304 #define S1394_VALID_MASK \ 305 (S1394_CFGROM_READ_MASK | S1394_CFGROM_BLK_READ_OK | \ 306 S1394_CFGROM_GEN_CHANGED | S1394_CFGROM_PARSED) 307 308 #define CLEAR_CFGROM_STATE(n) ((n)->cfgrom_state &= ~S1394_VALID_MASK) 309 #define CFGROM_VALID(n) \ 310 ((((n)->cfgrom_state & S1394_CFGROM_READ_MASK) != 0 && (n)->cfgrom != \ 311 NULL) ? B_TRUE : B_FALSE) 312 313 /* macros for cfgrom_state */ 314 #define SET_CFGROM_NEW_ALLOC(n) ((n)->cfgrom_state |= S1394_CFGROM_NEW_ALLOC) 315 #define CLEAR_CFGROM_NEW_ALLOC(n) ((n)->cfgrom_state &= ~S1394_CFGROM_NEW_ALLOC) 316 #define CFGROM_NEW_ALLOC(n) \ 317 (((n)->cfgrom_state & S1394_CFGROM_NEW_ALLOC) != 0 ? B_TRUE : B_FALSE) 318 319 #define SET_CFGROM_BIB_READ(n) ((n)->cfgrom_state |= S1394_CFGROM_BIB_READ) 320 #define CLEAR_CFGROM_BIB_READ(n) ((n)->cfgrom_state &= ~S1394_CFGROM_BIB_READ) 321 #define CFGROM_BIB_READ(n) \ 322 (((n)->cfgrom_state & S1394_CFGROM_BIB_READ) != 0 ? B_TRUE : B_FALSE) 323 324 #define SET_CFGROM_ALL_READ(n) ((n)->cfgrom_state |= S1394_CFGROM_ALL_READ) 325 #define CLEAR_CFGROM_ALL_READ(n) ((n)->cfgrom_state &= \ 326 ~S1394_CFGROM_ALL_READ) 327 #define CFGROM_ALL_READ(n) \ 328 (((n)->cfgrom_state & S1394_CFGROM_ALL_READ) != 0 ? B_TRUE : B_FALSE) 329 330 #define SET_CFGROM_BLK_READ_OK(n) \ 331 ((n)->cfgrom_state |= S1394_CFGROM_BLK_READ_OK) 332 #define CLEAR_CFGROM_BLK_READ_OK(n) \ 333 ((n)->cfgrom_state &= ~S1394_CFGROM_BLK_READ_OK) 334 #define CFGROM_BLK_READ_OK(n) \ 335 (((n)->cfgrom_state & S1394_CFGROM_BLK_READ_OK) != 0 : B_TRUE : B_FALSE) 336 337 #define SET_CFGROM_GEN_CHANGED(n) \ 338 ((n)->cfgrom_state |= S1394_CFGROM_GEN_CHANGED) 339 #define CLEAR_CFGROM_GEN_CHANGED(n) \ 340 ((n)->cfgrom_state &= ~S1394_CFGROM_GEN_CHANGED) 341 #define CFGROM_GEN_CHANGED(n) \ 342 (((n)->cfgrom_state & S1394_CFGROM_GEN_CHANGED) != 0 ? B_TRUE : B_FALSE) 343 344 #define SET_CFGROM_PARSED(n) ((n)->cfgrom_state |= S1394_CFGROM_PARSED) 345 #define CLEAR_CFGROM_PARSED(n) ((n)->cfgrom_state &= ~S1394_CFGROM_PARSED) 346 #define CFGROM_PARSED(n) \ 347 (((n)->cfgrom_state & S1394_CFGROM_PARSED) != 0 ? B_TRUE : B_FALSE) 348 349 #define SET_CFGROM_DIR_STACK_OFF(n) \ 350 ((n)->cfgrom_state |= S1394_CFGROM_DIR_STACK_OFF) 351 #define CLEAR_CFGROM_DIR_STACK_OFF(n) \ 352 ((n)->cfgrom_state &= ~S1394_CFGROM_DIR_STACK_OFF) 353 #define CFGROM_DIR_STACK_OFF(n) \ 354 (((n)->cfgrom_state & S1394_CFGROM_DIR_STACK_OFF) != 0 ? B_TRUE : \ 355 B_FALSE) 356 357 #define SET_CFGROM_SIZE_IS_CRCSIZE(n) \ 358 ((n)->cfgrom_state |= S1394_CFGROM_SIZE_IS_CRCSIZE) 359 #define CLEAR_CFGROM_SIZE_IS_CRCSIZE(n) \ 360 ((n)->cfgrom_state &= ~S1394_CFGROM_SIZE_IS_CRCSIZE) 361 #define CFGROM_SIZE_IS_CRCSIZE(n) \ 362 (((n)->cfgrom_state & S1394_CFGROM_SIZE_IS_CRCSIZE) != 0 ? B_TRUE : \ 363 B_FALSE) 364 365 /* defines for bus_enum_flags */ 366 #define S1394_NODE_VISITED 0x00000001 367 #define S1394_NODE_MATCHED 0x00000010 368 369 /* macros that set/clear bus_enum_flags */ 370 #define SET_NODE_VISITED(n) ((n)->bus_enum_flags |= S1394_NODE_VISITED) 371 #define CLEAR_NODE_VISITED(n) ((n)->bus_enum_flags &= ~S1394_NODE_VISITED) 372 #define NODE_VISITED(n) \ 373 (((n)->bus_enum_flags & S1394_NODE_VISITED) != 0 ? B_TRUE : B_FALSE) 374 375 #define SET_NODE_MATCHED(n) ((n)->bus_enum_flags |= S1394_NODE_MATCHED) 376 #define CLEAR_NODE_MATCHED(n) ((n)->bus_enum_flags &= ~S1394_NODE_MATCHED) 377 #define NODE_MATCHED(n) \ 378 (((n)->bus_enum_flags & S1394_NODE_MATCHED) != 0 ? B_TRUE : B_FALSE) 379 380 #define SET_NODE_IDENTIFIED(n) ((n)->bus_enum_flags |= S1394_NODE_IDENTIFIED) 381 #define CLEAR_NODE_IDENTIFIED(n) ((n)->bus_enum_flags &= ~S1394_NODE_IDENTIFIED) 382 #define NODE_IDENTIFIED(n) \ 383 (((n)->bus_enum_flags & S1394_NODE_IDENTIFIED) != 0 ? B_TRUE : B_FALSE) 384 385 /* 386 * s1394_fa_type_t - FA types, used as index into target_fa and hal_fa 387 */ 388 typedef enum { 389 S1394_FA_TYPE_FCP_CTL, /* FCP controller */ 390 S1394_FA_TYPE_FCP_TGT, /* FCP target */ 391 S1394_FA_TYPE_CMP_OMPR, /* CMP oMPR */ 392 S1394_FA_TYPE_CMP_IMPR, /* CMP iMPR */ 393 S1394_FA_NTYPES, /* should remain the last field */ 394 S1394_FA_TYPE_CMP = S1394_FA_TYPE_CMP_OMPR /* common CMP type */ 395 } s1394_fa_type_t; 396 397 398 /* 399 * s1394_fa_descr_t - FA type descriptor 400 */ 401 typedef struct s1394_fa_descr_s { 402 uint64_t fd_addr; /* address space */ 403 size_t fd_size; /* address space size */ 404 t1394_addr_enable_t fd_enable; /* access types */ 405 t1394_addr_evts_t fd_evts; /* event callbacks */ 406 uint64_t fd_conv_base; /* address conversion base */ 407 } s1394_fa_descr_t; 408 409 /* 410 * s1394_fcp_target_t - per-target data required for FCP support 411 */ 412 typedef struct s1394_fcp_target_s { 413 t1394_fcp_evts_t fc_evts; 414 } s1394_fcp_target_t; 415 416 /* 417 * s1394_cmp_target_t - per-target data required for CMP support 418 */ 419 typedef struct s1394_cmp_target_s { 420 t1394_cmp_evts_t cm_evts; 421 } s1394_cmp_target_t; 422 423 /* 424 * s1394_fa_target_t - per-target data required for fixed address support 425 */ 426 typedef struct s1394_fa_target_s { 427 s1394_target_t *fat_next; /* next in the list */ 428 /* type-specific data */ 429 union { 430 s1394_fcp_target_t fcp; 431 s1394_cmp_target_t cmp; 432 } fat_u; 433 } s1394_fa_target_t; 434 435 /* s1394_target_t - fields protected by the HAL's target_list_rwlock */ 436 struct s1394_target_s { 437 int target_version; 438 439 dev_info_t *target_dip; 440 441 /* Pointers to the node and HAL on which the target exists */ 442 s1394_node_t *on_node; 443 s1394_hal_t *on_hal; 444 445 s1394_target_t *target_next; 446 s1394_target_t *target_prev; 447 448 /* target_list is a copy of target_list pointer in the node */ 449 s1394_target_t *target_list; 450 s1394_target_t *target_sibling; 451 452 uint_t unit_dir; 453 454 /* The max_payload sizes - max and current conditions */ 455 uint_t dev_max_payload; 456 uint_t current_max_payload; 457 458 /* Number of asynch command target has allocated */ 459 uint_t target_num_cmds; 460 461 /* 462 * Are physical AR requests allowed from this target's node? 463 * This field keeps track of the number of allocated blocks 464 * of physical memory the target has. 465 */ 466 uint_t physical_arreq_enabled; 467 468 uint_t target_state; 469 470 /* FCP controller and target */ 471 s1394_fa_target_t target_fa[S1394_FA_NTYPES]; 472 }; 473 #define S1394_TARG_HP_NODE 0x00000001 /* on a hp node */ 474 #define S1394_TARG_GONE 0x00000002 /* unplugged */ 475 #define S1394_TARG_USING_BUS_PWR 0x00000004 /* consuming pwr now */ 476 #define S1394_TARG_BUS_PWR_CONSUMER 0x00000008 /* power consumer */ 477 #define S1394_TARG_ACTIVE 0x00000010 /* active */ 478 479 /* 480 * s1394_fa_hal_t - per-hal data required for fixed address support 481 */ 482 typedef struct s1394_fa_hal_s { 483 /* 484 * each hal keeps a list of registered fixed address clients 485 */ 486 s1394_target_t *fal_head; 487 s1394_target_t *fal_tail; 488 uint_t fal_gen; /* list generation */ 489 490 s1394_fa_descr_t *fal_descr; /* type descriptor */ 491 s1394_addr_space_blk_t *fal_addr_blk; /* address space block */ 492 } s1394_fa_hal_t; 493 494 /* 495 * s1394_cmp_hal_t - per-hal data required for fixed address support 496 */ 497 typedef struct s1394_cmp_hal_s { 498 /* oMPR */ 499 krwlock_t cmp_ompr_rwlock; 500 uint32_t cmp_ompr_val; 501 /* iMPR */ 502 krwlock_t cmp_impr_rwlock; 503 uint32_t cmp_impr_val; 504 } s1394_cmp_hal_t; 505 506 /* s1394_hal_t */ 507 struct s1394_hal_s { 508 s1394_hal_t *hal_next; 509 s1394_hal_t *hal_prev; 510 511 /* Target list */ 512 s1394_target_t *target_head; 513 s1394_target_t *target_tail; 514 krwlock_t target_list_rwlock; 515 516 /* halinfo structure given at attach time */ 517 h1394_halinfo_t halinfo; 518 519 boolean_t hal_was_suspended; 520 521 /* Bus reset thread */ 522 kthread_t *br_thread; 523 kmutex_t br_thread_mutex; 524 kcondvar_t br_thread_cv; 525 uint_t br_thread_ev_type; 526 uint32_t br_cfgrom_read_gen; 527 kmutex_t br_cmplq_mutex; 528 kcondvar_t br_cmplq_cv; 529 cmd1394_cmd_t *br_cmplq_head; 530 cmd1394_cmd_t *br_cmplq_tail; 531 532 s1394_hal_state_t hal_state; 533 534 /* kstats - kernel statistics for the Services Layer */ 535 s1394_kstat_t *hal_kstats; 536 kstat_t *hal_ksp; 537 538 /* CSR STATE register bits (DREQ and ABDICATE) */ 539 uint_t disable_requests_bit; 540 uint_t abdicate_bus_mgr_bit; 541 542 boolean_t initiated_bus_reset; 543 int initiated_br_reason; 544 uint32_t num_bus_reset_till_fail; 545 546 /* IRM and Bus Manager */ 547 int IRM_node; 548 kmutex_t bus_mgr_node_mutex; 549 kcondvar_t bus_mgr_node_cv; 550 int bus_mgr_node; 551 boolean_t incumbent_bus_mgr; 552 timeout_id_t bus_mgr_timeout_id; 553 timeout_id_t bus_mgr_query_timeout_id; 554 555 /* 1394 Bus stats */ 556 int gap_count; 557 int optimum_gap_count; 558 uint8_t slowest_node_speed; 559 560 /* Local Config ROM */ 561 kmutex_t local_config_rom_mutex; 562 uint32_t *local_config_rom; 563 uint32_t *temp_config_rom_buf; 564 s1394_config_rom_t *root_directory; 565 uint_t free_space; 566 uint_t config_rom_update_amount; 567 boolean_t config_rom_timer_set; 568 timeout_id_t config_rom_timer; 569 570 /* Cycle Master - CYCLE_TOO_LONG timer */ 571 kmutex_t cm_timer_mutex; 572 boolean_t cm_timer_set; 573 timeout_id_t cm_timer; 574 575 /* Incoming (AR) request and 1394 address space */ 576 kmutex_t addr_space_free_mutex; 577 s1394_addr_space_blk_t *addr_space_free_list; 578 kmutex_t addr_space_used_mutex; 579 s1394_addr_space_blk_t *addr_space_used_tree; 580 uint64_t physical_addr_lo; 581 uint64_t physical_addr_hi; 582 uint64_t csr_addr_lo; 583 uint64_t csr_addr_hi; 584 uint64_t normal_addr_lo; 585 uint64_t normal_addr_hi; 586 uint64_t posted_write_addr_lo; 587 uint64_t posted_write_addr_hi; 588 589 /* Outgoing (AT) request queues */ 590 kmutex_t outstanding_q_mutex; 591 cmd1394_cmd_t *outstanding_q_head; 592 cmd1394_cmd_t *outstanding_q_tail; 593 kmutex_t pending_q_mutex; 594 cmd1394_cmd_t *pending_q_head; 595 cmd1394_cmd_t *pending_q_tail; 596 597 /* SelfID buffers */ 598 void *selfid_buf0; 599 void *selfid_buf1; 600 int current_buffer; 601 s1394_selfid_pkt_t *selfid_ptrs[IEEE1394_MAX_NODES]; 602 603 /* Topology trees and local bus stats */ 604 kmutex_t topology_tree_mutex; 605 uint32_t cfgroms_being_read; 606 s1394_node_t *topology_tree; 607 s1394_node_t *old_tree; 608 uint32_t generation_count; 609 ushort_t number_of_nodes; 610 ushort_t node_id; 611 boolean_t topology_tree_valid; 612 boolean_t topology_tree_processed; 613 uint32_t old_generation_count; 614 ushort_t old_number_of_nodes; 615 ushort_t old_node_id; 616 s1394_node_t current_tree[IEEE1394_MAX_NODES]; 617 s1394_node_t last_valid_tree[IEEE1394_MAX_NODES]; 618 boolean_t old_tree_valid; 619 620 /* TOPOLOGY_MAP backing store buffer */ 621 uint32_t *CSR_topology_map; 622 623 /* Speed Map */ 624 uint8_t speed_map[IEEE1394_MAX_NODES][IEEE1394_MAX_NODES]; 625 626 /* Stack, Queue, and Node Number list */ 627 void *hal_stack[IEEE1394_MAX_NODES]; 628 int hal_stack_depth; 629 void *hal_queue[IEEE1394_MAX_NODES]; 630 int hal_queue_front; 631 int hal_queue_back; 632 int hal_node_number_list[IEEE1394_MAX_NODES]; 633 int hal_node_number_list_size; 634 635 /* Isoch CEC list */ 636 kmutex_t isoch_cec_list_mutex; 637 s1394_isoch_cec_t *isoch_cec_list_head; 638 s1394_isoch_cec_t *isoch_cec_list_tail; 639 640 struct kmem_cache *hal_kmem_cachep; 641 642 ndi_event_hdl_t hal_ndi_event_hdl; 643 644 callb_cpr_t hal_cprinfo; 645 646 /* FCP controllers and targets */ 647 s1394_fa_hal_t hal_fa[S1394_FA_NTYPES]; 648 649 /* CMP support */ 650 s1394_cmp_hal_t hal_cmp; 651 }; 652 653 _NOTE(SCHEME_PROTECTS_DATA("No lock needed to start/stop timer", \ 654 s1394_hal_s::cm_timer)) 655 656 /* defines for br_thread_ev_type */ 657 #define BR_THR_CFGROM_SCAN 0x00000001 /* start reading */ 658 #define BR_THR_GO_AWAY 0x00000002 /* clean & exit */ 659 660 /* 661 * FCP command and response address space 662 */ 663 #define IEC61883_FCP_BASE_ADDR 0xFFFFF0000B00 664 #define IEC61883_FCP_CMD_ADDR IEC61883_FCP_BASE_ADDR 665 #define IEC61883_FCP_CMD_SIZE 0x200 666 #define IEC61883_FCP_RESP_ADDR (IEC61883_FCP_CMD_ADDR + IEC61883_FCP_CMD_SIZE) 667 #define IEC61883_FCP_RESP_SIZE 0x200 668 #define IEC61883_FCP_END_ADDR (IEC61883_FCP_RESP_ADDR + IEC61883_FCP_RESP_SIZE) 669 670 /* CMP master plugs */ 671 #define IEC61883_CMP_OMPR_ADDR 0xFFFFF0000900 672 #define IEC61883_CMP_IMPR_ADDR 0xFFFFF0000980 673 #define IEC61883_CMP_OMPR_INIT_VAL 0xBFFFFF00 674 #define IEC61883_CMP_IMPR_INIT_VAL 0x80FFFF00 675 #define IEC61883_CMP_OMPR_LOCK_MASK 0x3FFFFF00 676 #define IEC61883_CMP_IMPR_LOCK_MASK 0x00FFFF00 677 678 /* s1394_addr_space_blk_t */ 679 struct s1394_addr_space_blk_s { 680 /* Pointers and coloring for Red-Black tree */ 681 s1394_addr_space_blk_t *asb_parent; 682 s1394_addr_space_blk_t *asb_left; 683 s1394_addr_space_blk_t *asb_right; 684 uint32_t asb_color; 685 boolean_t free_kmem_bufp; 686 687 /* Addr Blk info - callbacks, permissions, backing store, etc. */ 688 uint64_t addr_lo; 689 uint64_t addr_hi; 690 uint32_t addr_reserved; 691 t1394_addr_enable_t addr_enable; 692 t1394_addr_type_t addr_type; 693 t1394_addr_evts_t addr_events; 694 caddr_t kmem_bufp; 695 void *addr_arg; 696 }; 697 698 /* s1394_config_rom_t */ 699 struct s1394_config_rom_s { 700 boolean_t cfgrom_used; 701 uint32_t cfgrom_addr_lo; 702 uint32_t cfgrom_addr_hi; 703 704 uint_t root_dir_offset; 705 706 s1394_config_rom_t *cfgrom_next; 707 s1394_config_rom_t *cfgrom_prev; 708 }; 709 710 /* s1394_kstat_t */ 711 struct s1394_kstat_s { 712 /* Asynch Receive (AR) requests */ 713 uint_t arreq_quad_rd; 714 uint_t arreq_blk_rd; 715 uint_t arreq_quad_wr; 716 uint_t arreq_blk_wr; 717 uint_t arreq_lock32; 718 uint_t arreq_lock64; 719 720 uint_t arreq_blk_rd_size; 721 uint_t arreq_blk_wr_size; 722 723 uint_t arreq_posted_write_error; 724 725 /* Failure responses to AR requests (sent) */ 726 uint_t arresp_quad_rd_fail; 727 uint_t arresp_blk_rd_fail; 728 uint_t arresp_quad_wr_fail; 729 uint_t arresp_blk_wr_fail; 730 uint_t arresp_lock32_fail; 731 uint_t arresp_lock64_fail; 732 733 /* Asynch Transmit (AT) requests */ 734 uint_t atreq_quad_rd; 735 uint_t atreq_blk_rd; 736 uint_t atreq_quad_wr; 737 uint_t atreq_blk_wr; 738 uint_t atreq_lock32; 739 uint_t atreq_lock64; 740 741 uint_t atreq_blk_rd_size; 742 uint_t atreq_blk_wr_size; 743 744 /* Failure responses to AT requests (received) */ 745 uint_t atresp_quad_rd_fail; 746 uint_t atresp_blk_rd_fail; 747 uint_t atresp_quad_wr_fail; 748 uint_t atresp_blk_wr_fail; 749 uint_t atresp_lock32_fail; 750 uint_t atresp_lock64_fail; 751 752 753 /* Allocate & free requests */ 754 uint_t cmd_alloc; 755 uint_t cmd_alloc_fail; 756 uint_t cmd_free; 757 uint_t addr_phys_alloc; 758 uint_t addr_posted_alloc; 759 uint_t addr_normal_alloc; 760 uint_t addr_csr_alloc; 761 uint_t addr_alloc_fail; 762 uint_t addr_space_free; 763 764 /* Bus reset and miscellaneous */ 765 uint_t bus_reset; 766 uint_t selfid_complete; 767 uint_t selfid_buffer_error; 768 uint_t pending_q_insert; 769 uint64_t guid; 770 }; 771 772 _NOTE(SCHEME_PROTECTS_DATA("Statistics", \ 773 s1394_kstat_s::{arreq_blk_rd arreq_blk_wr arreq_quad_rd arreq_quad_wr \ 774 cmd_free selfid_buffer_error arreq_posted_write_error})) 775 776 /* s1394_isoch_cec_t */ 777 struct s1394_isoch_cec_s { 778 s1394_isoch_cec_t *cec_next; 779 s1394_isoch_cec_t *cec_prev; 780 781 kmutex_t isoch_cec_mutex; 782 783 /* Isoch CEC member list */ 784 s1394_isoch_cec_type_t cec_type; 785 s1394_isoch_cec_member_t *cec_member_list_head; 786 s1394_isoch_cec_member_t *cec_member_list_tail; 787 s1394_isoch_cec_member_t *cec_member_talker; 788 789 /* Properties given in t1394_alloc_isoch_cec() */ 790 t1394_isoch_cec_props_t cec_alloc_props; 791 792 /* Current state of Isoch CEC */ 793 uint_t filter_min_speed; 794 uint_t filter_max_speed; 795 uint_t filter_current_speed; 796 uint64_t filter_channel_mask; 797 uint_t bandwidth; 798 t1394_cec_options_t cec_options; 799 s1394_isoch_cec_state_t state_transitions; 800 boolean_t in_callbacks; 801 boolean_t in_fail_callbacks; 802 kcondvar_t in_callbacks_cv; 803 boolean_t cec_want_wakeup; 804 805 boolean_t realloc_valid; 806 boolean_t realloc_failed; 807 t1394_isoch_rsrc_error_t realloc_fail_reason; 808 uint_t realloc_chnl_num; 809 uint_t realloc_bandwidth; 810 uint_t realloc_speed; 811 }; 812 #define CEC_IN_ANY_CALLBACKS(cec) (((cec)->in_callbacks == B_TRUE) || \ 813 ((cec)->in_fail_callbacks == B_TRUE)) 814 815 #define CEC_TRANSITION_LEGAL(cec, tran) ((cec)->state_transitions & (tran)) 816 #define CEC_SET_LEGAL(cec, tran) ((cec)->state_transitions |= (tran)) 817 #define CEC_SET_ILLEGAL(cec, tran) ((cec)->state_transitions &= ~(tran)) 818 819 820 /* s1394_isoch_cec_member_t */ 821 struct s1394_isoch_cec_member_s { 822 s1394_isoch_cec_member_t *cec_mem_next; 823 s1394_isoch_cec_member_t *cec_mem_prev; 824 825 /* Events for Isoch CEC member - given in t1394_join_isoch_cec() */ 826 t1394_isoch_cec_evts_t isoch_cec_evts; 827 opaque_t isoch_cec_evts_arg; 828 uint64_t req_channel_mask; 829 uint_t req_max_speed; 830 t1394_jii_options_t cec_mem_options; 831 s1394_target_t *cec_mem_target; 832 }; 833 834 /* cmd1394_fa_cmd_priv_t - per-command data for fixed address support */ 835 typedef struct s1394_fa_cmd_priv_s { 836 s1394_fa_type_t type; 837 void (*completion_callback)(); 838 opaque_t callback_arg; 839 } s1394_fa_cmd_priv_t; 840 841 /* s1394_cmd_priv_t */ 842 typedef struct s1394_cmd_priv_s { 843 /* Services Layer private structure for asynch commands */ 844 cmd1394_cmd_t *cmd_priv_next; 845 cmd1394_cmd_t *cmd_priv_prev; 846 847 uint32_t cmd_priv_xfer_type; 848 s1394_target_t *sent_by_target; 849 s1394_hal_t *sent_on_hal; 850 851 int lock_req_step; 852 int temp_num_retries; 853 854 size_t data_remaining; 855 856 kmutex_t blocking_mutex; 857 kcondvar_t blocking_cv; 858 boolean_t blocking_flag; 859 860 boolean_t cmd_in_use; 861 boolean_t posted_write; 862 boolean_t arreq_valid_addr; 863 864 /* 865 * Commands can be extended to support additional functionality. 866 * The only extension at this time is FA (currently used only for FCP). 867 * The downside here is that every command should carry FA overhead 868 * even if the target doesn't use FA. However, alternative approaches 869 * would require separate allocation of FA overhead per command, which 870 * complicates the code and fragments the memory -- seems not worth it 871 * given that FA overhead is just a few bytes and there's a limit of 872 * 256 commands per target. 873 */ 874 int cmd_ext_type; 875 union { 876 s1394_fa_cmd_priv_t fa; 877 } cmd_ext; 878 879 h1394_cmd_priv_t hal_cmd_private; 880 } s1394_cmd_priv_t; 881 #define S1394_GET_CMD_PRIV(cmd) \ 882 ((s1394_cmd_priv_t *)((uchar_t *)(cmd) + sizeof (cmd1394_cmd_t))) 883 884 /* command extension types */ 885 enum { 886 S1394_CMD_EXT_FA = 1 887 }; 888 #define S1394_GET_FA_CMD_PRIV(cmd) (&(S1394_GET_CMD_PRIV(cmd)->cmd_ext.fa)) 889 890 #define S1394_IS_CMD_FCP(s_priv) \ 891 ((s_priv->cmd_ext.fa.type == S1394_FA_TYPE_FCP_CTL) || \ 892 (s_priv->cmd_ext.fa.type == S1394_FA_TYPE_FCP_TGT)) 893 894 _NOTE(SCHEME_PROTECTS_DATA("Unique per command", \ 895 s1394_cmd_priv_s::cmd_priv_xfer_type)) 896 897 898 /* s1394_state_t */ 899 typedef struct s1394_state_s { 900 /* HAL list */ 901 kmutex_t hal_list_mutex; 902 s1394_hal_t *hal_head; 903 s1394_hal_t *hal_tail; 904 } s1394_state_t; 905 906 /* Service Layer Global State Pointer */ 907 extern s1394_state_t *s1394_statep; 908 909 910 /* 1394 Services Layer Internals - 1394 Address Space Routines */ 911 int s1394_request_addr_blk(s1394_hal_t *hal, t1394_alloc_addr_t *addr_allocp); 912 913 int s1394_claim_addr_blk(s1394_hal_t *hal, t1394_alloc_addr_t *addr_allocp); 914 915 int s1394_free_addr_blk(s1394_hal_t *hal, s1394_addr_space_blk_t *blk); 916 917 int s1394_reserve_addr_blk(s1394_hal_t *hal, t1394_alloc_addr_t *addr_allocp); 918 919 int s1394_init_addr_space(s1394_hal_t *hal); 920 921 void s1394_destroy_addr_space(s1394_hal_t *hal); 922 923 void s1394_free_list_insert(s1394_hal_t *hal, s1394_addr_space_blk_t *new_blk); 924 925 s1394_addr_space_blk_t *s1394_used_tree_search(s1394_hal_t *hal, 926 uint64_t addr); 927 928 s1394_addr_space_blk_t *s1394_used_tree_delete(s1394_hal_t *hal, 929 s1394_addr_space_blk_t *z); 930 931 boolean_t s1394_is_posted_write(s1394_hal_t *hal, uint64_t addr); 932 933 boolean_t s1394_is_physical_addr(s1394_hal_t *hal, uint64_t addr); 934 935 boolean_t s1394_is_csr_addr(s1394_hal_t *hal, uint64_t addr); 936 937 boolean_t s1394_is_normal_addr(s1394_hal_t *hal, uint64_t addr); 938 939 /* 1394 Services Layer Internals - Asynchronous Communications Routines */ 940 int s1394_alloc_cmd(s1394_hal_t *hal, uint_t flags, cmd1394_cmd_t **cmdp); 941 942 int s1394_free_cmd(s1394_hal_t *hal, cmd1394_cmd_t **cmdp); 943 944 int s1394_xfer_asynch_command(s1394_hal_t *hal, cmd1394_cmd_t *cmd, int *err); 945 946 int s1394_setup_asynch_command(s1394_hal_t *hal, s1394_target_t *target, 947 cmd1394_cmd_t *cmd, uint32_t xfer_type, int *err); 948 949 void s1394_insert_q_asynch_cmd(s1394_hal_t *hal, cmd1394_cmd_t *cmd); 950 951 void s1394_remove_q_asynch_cmd(s1394_hal_t *hal, cmd1394_cmd_t *cmd); 952 953 void s1394_atreq_cmd_complete(s1394_hal_t *hal, cmd1394_cmd_t *req, 954 int status); 955 956 void s1394_atresp_cmd_complete(s1394_hal_t *hal, cmd1394_cmd_t *resp, 957 int status); 958 959 int s1394_send_response(s1394_hal_t *hal, cmd1394_cmd_t *resp); 960 961 int s1394_compare_swap(s1394_hal_t *hal, s1394_target_t *target, 962 cmd1394_cmd_t *cmd); 963 964 int s1394_split_lock_req(s1394_hal_t *hal, s1394_target_t *target, 965 cmd1394_cmd_t *cmd); 966 967 void s1394_pending_q_insert(s1394_hal_t *hal, cmd1394_cmd_t *cmd, uint_t flags); 968 969 void s1394_resend_pending_cmds(s1394_hal_t *hal); 970 971 /* 1394 Services Layer Internals - Bus Reset Routines */ 972 int s1394_parse_selfid_buffer(s1394_hal_t *hal, void *selfid_buf_addr, 973 uint32_t selfid_size); 974 975 void s1394_sort_selfids(s1394_hal_t *hal); 976 977 void s1394_init_topology_tree(s1394_hal_t *hal, boolean_t copied, 978 ushort_t number_of_nodes); 979 980 int s1394_topology_tree_build(s1394_hal_t *hal); 981 982 void s1394_topology_tree_mark_all_unvisited(s1394_hal_t *hal); 983 984 void s1394_old_tree_mark_all_unvisited(s1394_hal_t *hal); 985 986 void s1394_old_tree_mark_all_unmatched(s1394_hal_t *hal); 987 988 void s1394_copy_old_tree(s1394_hal_t *hal); 989 990 void s1394_match_tree_nodes(s1394_hal_t *hal); 991 992 int s1394_topology_tree_calculate_diameter(s1394_hal_t *hal); 993 994 int s1394_gap_count_optimize(int diameter); 995 996 int s1394_get_current_gap_count(s1394_hal_t *hal); 997 998 void s1394_speed_map_fill(s1394_hal_t *hal); 999 1000 uint8_t s1394_speed_map_get(s1394_hal_t *hal, uint32_t from_node, 1001 uint32_t to_node); 1002 1003 void s1394_update_speed_map_link_speeds(s1394_hal_t *hal); 1004 1005 int s1394_get_isoch_rsrc_mgr(s1394_hal_t *hal); 1006 1007 void s1394_physical_arreq_setup_all(s1394_hal_t *hal); 1008 1009 void s1394_physical_arreq_set_one(s1394_target_t *target); 1010 1011 void s1394_physical_arreq_clear_one(s1394_target_t *target); 1012 1013 s1394_node_t *s1394_topology_tree_get_root_node(s1394_hal_t *hal); 1014 1015 /* 1394 Services Layer Internals - CSR and Config ROM Routines */ 1016 int s1394_setup_CSR_space(s1394_hal_t *hal); 1017 1018 void s1394_CSR_topology_map_update(s1394_hal_t *hal); 1019 1020 void s1394_CSR_topology_map_disable(s1394_hal_t *hal); 1021 1022 int s1394_init_local_config_rom(s1394_hal_t *hal); 1023 1024 void s1394_destroy_local_config_rom(s1394_hal_t *hal); 1025 1026 int s1394_add_config_rom_entry(s1394_hal_t *hal, uint8_t key, 1027 uint32_t *buffer, uint_t size, void **handle, int *status); 1028 1029 int s1394_remove_config_rom_entry(s1394_hal_t *hal, void **handle, 1030 int *status); 1031 1032 void s1394_update_config_rom_callback(void *arg); 1033 1034 /* In s1394_dev_disc.c */ 1035 void s1394_br_thread(s1394_hal_t *hal); 1036 1037 void s1394_free_cfgrom(s1394_hal_t *hal, s1394_node_t *node, 1038 s1394_free_cfgrom_t options); 1039 1040 void s1394_copy_cfgrom(s1394_node_t *to, s1394_node_t *from); 1041 1042 int s1394_read_rest_of_cfgrom(s1394_hal_t *hal, s1394_node_t *node, 1043 s1394_status_t *status); 1044 1045 void s1394_cfgrom_parse_unit_dir(uint32_t *unit_dir, uint32_t *addr_hi, 1046 uint32_t *addr_lo, uint32_t *size_hi, uint32_t *size_lo); 1047 1048 boolean_t s1394_valid_cfgrom(s1394_hal_t *hal, s1394_node_t *node); 1049 1050 boolean_t s1394_valid_dir(s1394_hal_t *hal, s1394_node_t *node, uint32_t key, 1051 uint32_t *dir); 1052 1053 void s1394_get_maxpayload(s1394_target_t *target, uint_t *dev_max_payload, 1054 uint_t *current_max_payload); 1055 1056 int s1394_lock_tree(s1394_hal_t *hal); 1057 1058 void s1394_unlock_tree(s1394_hal_t *hal); 1059 1060 /* 1394 Services Layer Driver - Hotplug Routines */ 1061 dev_info_t *s1394_devi_find(dev_info_t *pdip, char *name, char *caddr); 1062 1063 int s1394_update_devinfo_tree(s1394_hal_t *hal, s1394_node_t *node); 1064 1065 int s1394_offline_node(s1394_hal_t *hal, s1394_node_t *node); 1066 1067 int s1394_process_topology_tree(s1394_hal_t *hal, int *wait_for_cbs, 1068 uint_t *wait_gen); 1069 1070 int s1394_process_old_tree(s1394_hal_t *hal); 1071 1072 void s1394_add_target_to_node(s1394_target_t *target); 1073 1074 void s1394_remove_target_from_node(s1394_target_t *target); 1075 1076 /* fixed address support */ 1077 int s1394_fa_claim_addr(s1394_hal_t *hal, s1394_fa_type_t type, 1078 s1394_fa_descr_t *descr); 1079 1080 void s1394_fa_free_addr(s1394_hal_t *hal, s1394_fa_type_t type); 1081 1082 void s1394_fa_list_add(s1394_hal_t *hal, s1394_target_t *target, 1083 s1394_fa_type_t type); 1084 1085 int s1394_fa_list_remove(s1394_hal_t *hal, s1394_target_t *target, 1086 s1394_fa_type_t type); 1087 1088 boolean_t s1394_fa_list_is_empty(s1394_hal_t *hal, s1394_fa_type_t type); 1089 1090 uint_t s1394_fa_list_gen(s1394_hal_t *hal, s1394_fa_type_t type); 1091 1092 void s1394_fa_init_cmd(s1394_cmd_priv_t *s_priv, s1394_fa_type_t type); 1093 1094 void s1394_fa_convert_cmd(s1394_hal_t *hal, cmd1394_cmd_t *cmd); 1095 1096 void s1394_fa_restore_cmd(s1394_hal_t *hal, cmd1394_cmd_t *cmd); 1097 1098 void s1394_fa_check_restore_cmd(s1394_hal_t *hal, cmd1394_cmd_t *cmd); 1099 1100 /* FCP */ 1101 int s1394_fcp_hal_init(s1394_hal_t *hal); 1102 1103 int s1394_fcp_register_ctl(s1394_target_t *target, t1394_fcp_evts_t *evts); 1104 1105 int s1394_fcp_register_tgt(s1394_target_t *target, t1394_fcp_evts_t *evts); 1106 1107 int s1394_fcp_unregister_ctl(s1394_target_t *target); 1108 1109 int s1394_fcp_unregister_tgt(s1394_target_t *target); 1110 1111 int s1394_fcp_write_check_cmd(cmd1394_cmd_t *cmd); 1112 1113 /* CMP */ 1114 int s1394_cmp_register(s1394_target_t *target, t1394_cmp_evts_t *evts); 1115 1116 int s1394_cmp_unregister(s1394_target_t *target); 1117 1118 int s1394_cmp_read(s1394_target_t *target, t1394_cmp_reg_t reg, uint32_t *valp); 1119 1120 int s1394_cmp_cas(s1394_target_t *target, t1394_cmp_reg_t reg, uint32_t arg_val, 1121 uint32_t new_val, uint32_t *old_valp); 1122 1123 /* 1394 Services Layer Internals - Isochronous Communication Routines */ 1124 void s1394_isoch_rsrc_realloc(s1394_hal_t *hal); 1125 1126 void s1394_isoch_rsrc_realloc_notify(s1394_hal_t *hal); 1127 1128 int s1394_channel_alloc(s1394_hal_t *hal, uint32_t channel_mask, 1129 uint_t generation, uint_t flags, uint32_t *old_channels, int *result); 1130 1131 int s1394_channel_free(s1394_hal_t *hal, uint32_t channel_mask, 1132 uint_t generation, uint_t flags, uint32_t *old_channels, int *result); 1133 1134 int s1394_bandwidth_alloc(s1394_hal_t *hal, uint32_t bw_alloc_units, 1135 uint_t generation, int *result); 1136 1137 uint_t s1394_compute_bw_alloc_units(s1394_hal_t *hal, uint_t bandwidth, 1138 uint_t speed); 1139 1140 int s1394_bandwidth_free(s1394_hal_t *hal, uint32_t bw_alloc_units, 1141 uint_t generation, int *result); 1142 1143 void s1394_isoch_cec_list_insert(s1394_hal_t *hal, s1394_isoch_cec_t *cec); 1144 1145 void s1394_isoch_cec_list_remove(s1394_hal_t *hal, s1394_isoch_cec_t *cec); 1146 1147 void s1394_isoch_cec_member_list_insert(s1394_hal_t *hal, 1148 s1394_isoch_cec_t *cec, s1394_isoch_cec_member_t *member); 1149 1150 void s1394_isoch_cec_member_list_remove(s1394_hal_t *hal, 1151 s1394_isoch_cec_t *cec, s1394_isoch_cec_member_t *member); 1152 1153 /* 1394 Services Layer Internals - Miscellaneous Routines */ 1154 void s1394_cleanup_for_detach(s1394_hal_t *hal, uint_t cleanup_level); 1155 1156 void s1394_hal_shutdown(s1394_hal_t *hal, boolean_t disable_hal); 1157 1158 void s1394_initiate_hal_reset(s1394_hal_t *hal, int reason); 1159 1160 boolean_t s1394_on_br_thread(s1394_hal_t *hal); 1161 1162 void s1394_destroy_br_thread(s1394_hal_t *hal); 1163 1164 void s1394_tickle_bus_reset_thread(s1394_hal_t *hal); 1165 1166 void s1394_block_on_asynch_cmd(cmd1394_cmd_t *cmd); 1167 1168 int s1394_HAL_asynch_error(s1394_hal_t *hal, cmd1394_cmd_t *cmd, 1169 s1394_hal_state_t state); 1170 1171 boolean_t s1394_mblk_too_small(cmd1394_cmd_t *cmd); 1172 1173 boolean_t s1394_address_rollover(cmd1394_cmd_t *cmd); 1174 1175 uint_t s1394_stoi(char *p, int len, int base); 1176 1177 uint_t s1394_CRC16(uint_t *d, uint_t crc_length); 1178 1179 uint_t s1394_CRC16_old(uint_t *d, uint_t crc_length); 1180 1181 int s1394_ioctl(s1394_hal_t *hal, int cmd, intptr_t arg, int mode, 1182 cred_t *cred_p, int *rval_p); 1183 1184 void s1394_check_pwr_mgmt(s1394_hal_t *hal, s1394_target_t *target, 1185 boolean_t add); 1186 1187 int s1394_kstat_init(s1394_hal_t *hal); 1188 1189 int s1394_kstat_delete(s1394_hal_t *hal); 1190 1191 int s1394_kstat_update(kstat_t *ksp, int rw); 1192 1193 void s1394_addr_alloc_kstat(s1394_hal_t *hal, uint64_t addr); 1194 1195 void s1394_print_node_info(s1394_hal_t *hal); 1196 1197 s1394_hal_t *s1394_dip_to_hal(dev_info_t *dip); 1198 1199 s1394_target_t *s1394_target_from_dip(s1394_hal_t *hal, dev_info_t *tdip); 1200 s1394_target_t *s1394_target_from_dip_locked(s1394_hal_t *hal, 1201 dev_info_t *tdip); 1202 1203 void s1394_destroy_timers(s1394_hal_t *hal); 1204 1205 void s1394_cycle_too_long_callback(void *arg); 1206 1207 #ifdef __cplusplus 1208 } 1209 #endif 1210 1211 #endif /* _SYS_1394_S1394_H */ 1212