1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 1999-2002 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_1394_H1394_H 28 #define _SYS_1394_H1394_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * h1394.h 34 * Contains the structure and error codes used to communicate 35 * between the HAL and the rest of the 1394 Software Framework 36 */ 37 38 #include <sys/types.h> 39 #include <sys/modctl.h> 40 #include <sys/ddi.h> 41 #include <sys/sunddi.h> 42 #include <sys/note.h> 43 44 #include <sys/1394/cmd1394.h> 45 #include <sys/1394/id1394.h> 46 47 #ifdef __cplusplus 48 extern "C" { 49 #endif 50 51 #define H1394_CLEANUP_LEVEL7 7 52 #define H1394_CLEANUP_LEVEL6 6 53 #define H1394_CLEANUP_LEVEL5 5 54 #define H1394_CLEANUP_LEVEL4 4 55 #define H1394_CLEANUP_LEVEL3 3 56 #define H1394_CLEANUP_LEVEL2 2 57 #define H1394_CLEANUP_LEVEL1 1 58 #define H1394_CLEANUP_LEVEL0 0 59 60 /* h1394_phy_t */ 61 typedef enum { 62 H1394_PHY_1995 = 0, 63 H1394_PHY_1394A = 1 64 } h1394_phy_t; 65 66 /* h1394_error_t */ 67 typedef enum { 68 H1394_LOCK_RESP_ERR = 1, 69 H1394_POSTED_WR_ERR = 2, 70 H1394_SELF_INITIATED_SHUTDOWN = 3, 71 H1394_CYCLE_TOO_LONG = 4 72 } h1394_error_t; 73 74 /* 75 * h1394_posted_wr_err_t 76 * The upper 16 bits contain the source id (bus/node) of the source node, 77 * the lower 48 bits contain the address that the error occured at. 78 */ 79 typedef struct h1394_posted_wr_err_s { 80 uint64_t addr; 81 } h1394_posted_wr_err_t; 82 83 /* 84 * h1394_node_pwr_flags_t 85 * Node power flags info 86 */ 87 typedef enum { 88 H1394_NODE_PWR_FLAGS_NONE = (1 << 1), 89 H1394_BUS_PWRD_NODES_ONE_MORE = (1 << 2), 90 H1394_BUS_PWRD_NODES_ONE_LESS = (1 << 3), 91 H1394_ACTIVE_NODES_ONE_MORE = (1 << 4), 92 H1394_ACTIVE_NODES_ONE_LESS = (1 << 5) 93 } h1394_node_pwr_flags_t; 94 95 /* 96 * h1394_addr_type_t 97 * h1394_addr_map.addr_type 98 */ 99 typedef enum { 100 H1394_ADDR_POSTED_WRITE = 0, 101 H1394_ADDR_NORMAL = 1, 102 H1394_ADDR_CSR = 2, 103 H1394_ADDR_PHYSICAL = 3, 104 H1394_ADDR_RESERVED = 4 105 } h1394_addr_type_t; 106 107 /* h1394_mblk_t */ 108 typedef struct h1394_mblk_s { 109 mblk_t *curr_mblk; 110 unsigned char *curr_offset; 111 uint_t length; 112 mblk_t *next_mblk; 113 unsigned char *next_offset; 114 } h1394_mblk_t; 115 116 /* h1394_cmd_priv_t */ 117 typedef struct h1394_cmd_priv_s { 118 uint_t speed; 119 uint_t ack_tstamp; 120 uint_t recv_tstamp; 121 uint_t bus_generation; 122 h1394_mblk_t mblk; 123 void *hal_overhead; 124 } h1394_cmd_priv_t; 125 126 _NOTE(SCHEME_PROTECTS_DATA("Used by a single thread", h1394_cmd_priv_s \ 127 h1394_mblk_s::next_mblk h1394_mblk_s::next_offset)) 128 129 /* h1394_evts_t */ 130 typedef struct h1394_evts_s { 131 uint_t hal_version; 132 uint_t reserved; 133 void (*shutdown)(void *hal_private); 134 int (*send_phy_configuration_packet)(void *hal_private, 135 cmd1394_cmd_t *phy_pkt, h1394_cmd_priv_t *cmd_private, 136 int *result); 137 int (*read)(void *hal_private, cmd1394_cmd_t *req, 138 h1394_cmd_priv_t *cmd_private, int *result); 139 int (*read_response)(void *hal_private, cmd1394_cmd_t *resp, 140 h1394_cmd_priv_t *cmd_private, int *result); 141 int (*write)(void *hal_private, cmd1394_cmd_t *req, 142 h1394_cmd_priv_t *cmd_private, int *result); 143 int (*write_response)(void *hal_private, cmd1394_cmd_t *resp, 144 h1394_cmd_priv_t *cmd_private, int *result); 145 void (*response_complete)(void *hal_private, cmd1394_cmd_t *resp, 146 h1394_cmd_priv_t *cmd_private); 147 int (*lock)(void *hal_private, cmd1394_cmd_t *req, 148 h1394_cmd_priv_t *cmd_private, int *result); 149 int (*lock_response)(void *hal_private, cmd1394_cmd_t *resp, 150 h1394_cmd_priv_t *cmd_private, int *result); 151 int (*alloc_isoch_dma)(void *hal_private, 152 id1394_isoch_dmainfo_t *idi, void **hal_idma_handle, 153 int *result); 154 void (*free_isoch_dma)(void *hal_private, 155 void *hal_isoch_dma_handle); 156 int (*start_isoch_dma)(void *hal_private, 157 void *hal_isoch_dma_handle, 158 id1394_isoch_dma_ctrlinfo_t *idma_ctrlinfo, uint_t flags, 159 int *result); 160 void (*stop_isoch_dma)(void *hal_private, void *hal_isoch_dma_handle, 161 int *result); 162 int (*update_isoch_dma)(void *hal_private, 163 void *hal_isoch_dma_handle, 164 id1394_isoch_dma_updateinfo_t *idma_updateinfo, 165 uint_t flags, int *result); 166 int (*update_config_rom)(void *hal_private, void *local_buf, 167 uint_t quadlet_count); 168 int (*bus_reset)(void *hal_private); 169 int (*short_bus_reset)(void *hal_private); 170 int (*set_contender_bit)(void *hal_private); 171 int (*set_root_holdoff_bit)(void *hal_private); 172 int (*set_gap_count)(void *hal_private, uint_t gap_count); 173 int (*csr_read)(void *hal_private, uint_t offset, uint32_t *data); 174 int (*csr_write)(void *hal_private, uint_t offset, uint32_t data); 175 int (*csr_cswap32)(void *hal_private, uint_t generation, 176 uint_t offset, uint32_t compare, uint32_t swap, 177 uint32_t *old); 178 int (*physical_arreq_enable_set)(void *hal_private, uint64_t mask, 179 uint_t generation); 180 int (*physical_arreq_enable_clr)(void *hal_private, uint64_t mask, 181 uint_t generation); 182 void (*node_power_state_change)(void *hal_private, 183 h1394_node_pwr_flags_t nodeflags); 184 } h1394_evts_t; 185 /* Version value for h1394_evts_t */ 186 #define H1394_EVTS_V1 1 187 188 #define HAL_CALL(hal) (hal)->halinfo.hal_events 189 190 /* Result field returned by read/write/lock requests */ 191 #define H1394_STATUS_NO_ERROR 0 192 #define H1394_STATUS_INVALID_BUSGEN 1 193 #define H1394_STATUS_EMPTY_TLABEL 2 194 #define H1394_STATUS_NOMORE_SPACE 3 195 #define H1394_STATUS_INTERNAL_ERROR 4 196 197 /* h1394_addr_map_t */ 198 typedef struct h1394_addr_map_s { 199 uint64_t address; 200 uint64_t length; 201 h1394_addr_type_t addr_type; 202 } h1394_addr_map_t; 203 204 /* h1394_halinfo_t */ 205 typedef struct h1394_halinfo_s { 206 void *hal_private; 207 dev_info_t *dip; 208 h1394_evts_t hal_events; 209 ddi_iblock_cookie_t hw_interrupt; 210 211 /* Buffer attributes */ 212 ddi_device_acc_attr_t acc_attr; 213 ddi_dma_attr_t dma_attr; 214 215 /* Type of PHY on HAL */ 216 h1394_phy_t phy; 217 218 uint_t hal_overhead; /* in bytes */ 219 uint32_t bus_capabilities; 220 uint64_t guid; 221 uint32_t node_capabilities; 222 223 /* 224 * The maximum value generation can have before 225 * it rolls over (inclusive) 226 */ 227 uint_t max_generation; 228 229 /* Description of the 1394 Address Space */ 230 h1394_addr_map_t *addr_map; 231 uint_t addr_map_num_entries; 232 233 /* Description of the reserved spaces */ 234 h1394_addr_map_t *resv_map; 235 uint_t resv_map_num_entries; 236 } h1394_halinfo_t; 237 238 239 /* Calls to Services layer during HAL driver _init() and _fini() */ 240 int h1394_init(struct modlinkage *modlp); 241 void h1394_fini(struct modlinkage *modlp); 242 243 244 /* Calls to Services layer during HAL driver attach/detach */ 245 int h1394_attach(h1394_halinfo_t *halinfo, ddi_attach_cmd_t cmd, 246 void **sl_private); 247 248 int h1394_detach(void **sl_private, ddi_detach_cmd_t cmd); 249 250 251 /* Calls to Services layer during HW interrupt processing */ 252 void h1394_cmd_is_complete(void *sl_private, cmd1394_cmd_t *command_id, 253 uint32_t cmd_type, int status); 254 /* Command types (passed to h1394_command_is_complete) */ 255 #define H1394_AT_REQ 0 256 #define H1394_AT_RESP 1 257 /* Command statuses (passed to h1394_command_is_complete) */ 258 #define H1394_CMD_SUCCESS 0x00 /* ack_complete */ 259 #define H1394_CMD_ETIMEOUT 0x01 /* evt_missing_ack */ 260 #define H1394_CMD_EBUSRESET 0x02 /* evt_flushed */ 261 #define H1394_CMD_EDEVICE_BUSY 0x03 /* ack_busy_? */ 262 #define H1394_CMD_EDATA_ERROR 0x04 /* ack_data_error */ 263 #define H1394_CMD_ETYPE_ERROR 0x05 /* ack_type_error */ 264 #define H1394_CMD_EADDR_ERROR 0x06 /* resp_address_error */ 265 #define H1394_CMD_ERSRC_CONFLICT 0x07 /* resp_conflict_error */ 266 #define H1394_CMD_EDEVICE_POWERUP 0x08 /* ack_tardy */ 267 #define H1394_CMD_EDEVICE_ERROR 0x09 /* device error */ 268 #define H1394_CMD_EUNKNOWN_ERROR 0x0A /* unknown error type */ 269 270 void h1394_bus_reset(void *sl_private, void **selfid_buf_addr); 271 272 void h1394_self_ids(void *sl_private, void *selfid_buf_addr, 273 uint32_t selfid_size, uint32_t node_id, uint32_t generation_count); 274 275 void h1394_write_request(void *sl_private, cmd1394_cmd_t *req); 276 277 void h1394_read_request(void *sl_private, cmd1394_cmd_t *req); 278 279 void h1394_lock_request(void *sl_private, cmd1394_cmd_t *req); 280 281 int h1394_alloc_cmd(void *sl_private, uint_t flags, cmd1394_cmd_t **cmdp, 282 h1394_cmd_priv_t **hal_priv_ptr); 283 /* Flags for h1394_alloc_cmd() */ 284 #define H1394_ALLOC_CMD_SLEEP 0x00000000 /* can sleep allocating */ 285 #define H1394_ALLOC_CMD_NOSLEEP 0x00000001 /* don't sleep allocating */ 286 287 int h1394_free_cmd(void *sl_private, cmd1394_cmd_t **cmdp); 288 int h1394_ioctl(void *sl_private, int cmd, intptr_t arg, int mode, 289 cred_t *cred_p, int *rval_p); 290 291 void h1394_phy_packet(void *sl_private, uint32_t *packet_data, 292 uint_t quadlet_count, uint_t timestamp); 293 294 void h1394_error_detected(void *sl_private, h1394_error_t type, void *arg); 295 296 #ifdef __cplusplus 297 } 298 #endif 299 300 #endif /* _SYS_1394_H1394_H */ 301