1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_1394_ADAPTERS_HCI1394_OHCI_H 27 #define _SYS_1394_ADAPTERS_HCI1394_OHCI_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 /* 32 * hci1394_ohci.h 33 * Provides access macros and routines to the OpenHCI HW. 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include <sys/ddi.h> 41 #include <sys/modctl.h> 42 #include <sys/sunddi.h> 43 #include <sys/types.h> 44 #include <sys/note.h> 45 46 #include <sys/1394/adapters/hci1394_def.h> 47 #include <sys/1394/adapters/hci1394_buf.h> 48 49 50 #define OHCI_MAX_SELFID_SIZE 2048 51 #define OHCI_BUSGEN_MAX 0xFF 52 53 54 /* Misc */ 55 #define OHCI_REG_SET 1 /* ddi_regs_map_setup */ 56 #define OHCI_CHIP_RESET_TIME_IN_uSEC ((clock_t)100) /* 100uS */ 57 #define OHCI_BUS_RESET_TIME_IN_uSEC ((clock_t)100000) /* 100mS */ 58 #define OHCI_MAX_COOKIE 16 59 #define OHCI_uS_PER_BUS_CYCLE 125 60 #define OHCI_nS_PER_BUS_CYCLE 125000 61 #define OHCI_BUS_CYCLE_TO_uS(cycles) (cycles * OHCI_uS_PER_BUS_CYCLE) 62 #define OHCI_BUS_CYCLE_TO_nS(cycles) (cycles * OHCI_nS_PER_BUS_CYCLE) 63 #define OHCI_CYCLE_SEC_SHIFT 13 64 #define OHCI_CYCLE_SEC_MASK 0xE000 65 #define OHCI_CYCLE_CNT_MASK 0x1FFF 66 #define OHCI_MAX_CYCLE_CNT 8000 67 #define OHCI_TIMESTAMP_MASK 0xFFFF 68 #define OHCI_REG_ADDR_MASK 0x7FC 69 70 /* OpenHCI Global Swap location in PCI space */ 71 #define OHCI_PCI_HCI_CONTROL_REG ((off_t)0x40) 72 #define OHCI_PCI_GLOBAL_SWAP 0x00000001 73 74 75 /* PHY Register #1 */ 76 #define OHCI_PHY_RHB 0x80 77 #define OHCI_PHY_IBR 0x40 78 #define OHCI_PHY_MAX_GAP 0x3F 79 80 /* PHY Register #4 */ 81 #define OHCI_PHY_EXTND_MASK 0xE0 82 #define OHCI_PHY_EXTND 0xE0 83 84 /* PHY Register #4 */ 85 #define OHCI_PHY_CNTDR 0x40 86 87 /* PHY Register #5 */ 88 #define OHCI_PHY_ISBR 0x40 89 #define OHCI_PHY_LOOP_ERR 0x20 90 #define OHCI_PHY_PWRFAIL_ERR 0x10 91 #define OHCI_PHY_TIMEOUT_ERR 0x08 92 #define OHCI_PHY_PORTEVT_ERR 0x04 93 #define OHCI_PHY_ENBL_ACCEL 0x02 94 #define OHCI_PHY_ENBL_MULTI 0x01 95 96 /* OpenHCI Event Codes. Refer to OHCI 1.0 section 3.1.1 */ 97 #define OHCI_EVT_NO_STATUS 0x0 98 #define OHCI_EVT_LONG_PACKET 0x2 99 #define OHCI_EVT_MISSING_ACK 0x3 100 #define OHCI_EVT_UNDERRUN 0x4 101 #define OHCI_EVT_OVERRUN 0x5 102 #define OHCI_EVT_DESCRIPTOR_READ 0x6 103 #define OHCI_EVT_DATA_READ 0x7 104 #define OHCI_EVT_DATA_WRITE 0x8 105 #define OHCI_EVT_BUS_RESET 0x9 106 #define OHCI_EVT_TIMEOUT 0xA 107 #define OHCI_EVT_TCODE_ERR 0xB 108 #define OHCI_EVT_UNKNOWN 0xE 109 #define OHCI_EVT_FLUSHED 0xF 110 #define OHCI_ACK_COMPLETE 0x11 111 #define OHCI_ACK_PENDING 0x12 112 #define OHCI_ACK_BUSY_X 0x14 113 #define OHCI_ACK_BUSY_A 0x15 114 #define OHCI_ACK_BUSY_B 0x16 115 #define OHCI_ACK_TARDY 0x1B 116 #define OHCI_ACK_CONFLICT_ERROR 0x1C 117 #define OHCI_ACK_DATA_ERROR 0x1D 118 #define OHCI_ACK_TYPE_ERROR 0x1E 119 #define OHCI_ACK_ADDRESS_ERROR 0x1F 120 121 #define OHCI_REG_NODEID_ROOT 0x40000000 122 #define OHCI_REG_BUSOPTIONS_CMC 0x40000000 123 124 /* hci_regs_s.ir_ctxt_regs.ctxt_match */ 125 #define OHCI_MTC_TAG3_MASK 0x80000000 126 #define OHCI_MTC_TAG3_SHIFT 31 127 #define OHCI_MTC_TAG2_MASK 0x40000000 128 #define OHCI_MTC_TAG2_SHIFT 30 129 #define OHCI_MTC_TAG1_MASK 0x20000000 130 #define OHCI_MTC_TAG1_SHIFT 29 131 #define OHCI_MTC_TAG0_MASK 0x10000000 132 #define OHCI_MTC_TAG0_SHIFT 28 133 #define OHCI_MTC_MATCH_MASK 0x07FFF000 134 #define OHCI_MTC_MATCH_SHIFT 12 135 #define OHCI_MTC_SYNC_MASK 0x00000F00 136 #define OHCI_MTC_SYNC_SHIFT 8 137 #define OHCI_MTC_TAG1SY_MASK 0x00000040 138 #define OHCI_MTC_TAG1SY_SHIFT 6 139 #define OHCI_MTC_CHAN_MASK 0x0000003F 140 #define OHCI_MTC_CHAN_SHIFT 0 141 142 /* hci_regs_s.self_id_buflo - See OpenHCI 1.00 section 11.1 */ 143 #define OHCI_SLF_BUF_LO 0xFFFFF800 144 145 /* hci_regs_s.self_id_count - See OpenHCI 1.00 section 11.2 */ 146 #define OHCI_SLFC_ERROR 0x80000000 147 #define OHCI_SLFC_GEN_MASK 0x00FF0000 148 #define OHCI_SLFC_GEN_SHIFT 16 149 #define OHCI_SLFC_NUM_QUADS_MASK 0x00001FFC 150 151 152 /* 153 * hci_regs_s.int_event_* and hci_regs_s.int_mask_* 154 * See OpenHCI 1.00 section 6 155 */ 156 #define OHCI_INTR_REQ_TX_CMPLT 0x00000001 157 #define OHCI_INTR_RESP_TX_CMPLT 0x00000002 158 #define OHCI_INTR_ARRQ 0x00000004 159 #define OHCI_INTR_ARRS 0x00000008 160 #define OHCI_INTR_RQPKT 0x00000010 161 #define OHCI_INTR_RSPKT 0x00000020 162 #define OHCI_INTR_ISOCH_TX 0x00000040 /* RO */ 163 #define OHCI_INTR_ISOCH_RX 0x00000080 /* RO */ 164 #define OHCI_INTR_POST_WR_ERR 0x00000100 165 #define OHCI_INTR_LOCK_RESP_ERR 0x00000200 166 #define OHCI_INTR_SELFID_CMPLT 0x00010000 167 #define OHCI_INTR_BUS_RESET 0x00020000 168 #define OHCI_INTR_PHY 0x00080000 169 #define OHCI_INTR_CYC_SYNCH 0x00100000 170 #define OHCI_INTR_CYC_64_SECS 0x00200000 171 #define OHCI_INTR_CYC_LOST 0x00400000 172 #define OHCI_INTR_CYC_INCONSISTENT 0x00800000 173 #define OHCI_INTR_UNRECOVERABLE_ERR 0x01000000 174 #define OHCI_INTR_CYC_TOO_LONG 0x02000000 175 #define OHCI_INTR_PHY_REG_RCVD 0x04000000 176 #define OHCI_INTR_VENDOR_SPECIFIC 0x40000000 177 #define OHCI_INTR_MASTER_INTR_ENBL 0x80000000 /* int_mask_* only */ 178 179 /* hci_regs_s.fairness_ctrl - See OpenHCI 1.00 section 5.8 */ 180 #define OHCI_FAIR_PRI_REQ 0x000000FF 181 182 /* hci_regs_s.link_ctrl_set/clr - See OpenHCI 1.00 section 5.9 */ 183 #define OHCI_LC_CYC_SRC 0x00400000 184 #define OHCI_LC_CYC_MAST 0x00200000 185 #define OHCI_LC_CTIME_ENBL 0x00100000 186 #define OHCI_LC_RCV_PHY 0x00000400 187 #define OHCI_LC_RCV_SELF 0x00000200 188 #define OHCI_LC_CYC_SYNC 0x00000010 189 190 /* Defines for registers in HCI register space */ 191 /* Note: bits are read/write unless otherwise noted (RO-read only) */ 192 193 /* hci_regs_s.version - See OpenHCI 1.00 section 5.2 */ 194 #define OHCI_VER_GUID_ROM 0x01000000 195 #define OHCI_VER_VERSION_MASK 0x00FF0000 196 #define OHCI_VER_VERSION_SHIFT 16 197 #define OHCI_VER_REVISION_MASK 0x000000FF 198 #define OHCI_VERSION(version) \ 199 ((version & OHCI_VER_VERSION_MASK) >> OHCI_VER_VERSION_SHIFT) 200 #define OHCI_REVISION(revision) \ 201 (revision & OHCI_VER_REVISION_MASK) 202 203 /* hci_regs_s.guid_rom - See OpenHCI 1.00 section 5.3 */ 204 #define OHCI_GROM_ADDR_RESET 0x80000000 /* 1-initiate reset */ 205 #define OHCI_GROM_RD_START 0x02000000 /* 1-start byte read */ 206 #define OHCI_GROM_RD_DATA 0x00FF0000 /* RO */ 207 208 /* hci_regs_s.at_retries - See OpenHCI 1.00 section 5.4 */ 209 #define OHCI_RET_SECLIM_MASK 0xE0000000 /* dual-phase retry */ 210 #define OHCI_RET_SECLIM_SHIFT 29 211 #define OHCI_RET_CYCLLIM_MASK 0xFFFF0000 /* dual-phase retry */ 212 #define OHCI_RET_CYCLLIM_SHIFT 16 213 #define OHCI_RET_MAX_PHYS_RESP_MASK 0x00000F00 /* physical resp rtry */ 214 #define OHCI_RET_MAX_PHYS_RESP_SHIFT 8 215 #define OHCI_RET_MAX_ATRESP_MASK 0x000000F0 /* AT response retry */ 216 #define OHCI_RET_MAX_ATRESP_SHIFT 4 217 #define OHCI_RET_MAX_ATREQ_MASK 0x0000000F /* AT request retry */ 218 #define OHCI_RET_MAX_ATREQ_SHIFT 0 219 220 /* hci_regs_s.csr_ctrl - See OpenHCI 1.00 section 5.5.1 */ 221 #define OHCI_CSR_DONE 0x80000000 /* RO 1-cmp_swap complete */ 222 #define OHCI_CSR_SELECT 0x00000003 223 224 #define OHCI_CSR_SEL_BUS_MGR_ID 0 /* bus manager ID register */ 225 #define OHCI_CSR_SEL_BANDWIDTH_AVAIL 1 /* bandwidth available reg */ 226 #define OHCI_CSR_SEL_CHANS_AVAIL_HI 2 /* channels_available_hi reg */ 227 #define OHCI_CSR_SEL_CHANS_AVAIL_LO 3 /* channels_available_lo reg */ 228 229 /* hci_regs_s.config_rom_hdr - See OpenHCI 1.00 section 5.5.6 */ 230 #define OHCI_CROM_INFO_LEN 0xFF000000 231 #define OHCI_CROM_CRC_LEN 0x00FF0000 232 #define OHCI_CROM_ROM_CRC_VAL 0x0000FFFF 233 234 /* hci_regs_s.bus_options - See OpenHCI 1.00 section 5.5.4 */ 235 #define OHCI_BOPT_IRMC 0x80000000 /* Isoch resrce mgr capable */ 236 #define OHCI_BOPT_CMC 0x40000000 /* cycle master capable */ 237 #define OHCI_BOPT_ISC 0x20000000 /* isochronous data capable */ 238 #define OHCI_BOPT_BMC 0x10000000 /* bus manager capable */ 239 #define OHCI_BOPT_PMC 0x80000000 /* power manager capable */ 240 #define OHCI_BOPT_CYC_CLK_ACC 0x00FF0000 241 #define OHCI_BOPT_MAX_REC 0x0000F000 242 #define OHCI_BOPT_GEN 0x000000C0 243 #define OHCI_BOPT_LINK_SPD 0x00000007 244 245 /* hci_regs_s.guid_hi - See OpenHCI 1.00 section 5.5.5 */ 246 #define OHCI_GUID_NODE_VENDOR_ID 0xFFFFFF00 247 #define OHCI_GUID_CHIP_ID_HI 0x000000FF 248 249 /* hci_regs_s.config_rom_maplo - See OpenHCI 1.00 section 5.5.6 */ 250 #define OHCI_CMAP_ADDR 0xFFFFFF00 /* 1k aligned */ 251 252 /* hci_regs_s.posted_write_addrhi - See OpenHCI 1.00 section 13.2.8.1 */ 253 #define OHCI_POST_SOURCE_ID 0xFFFF0000 254 #define OHCI_POST_OFFSET_HI 0x0000FFFF 255 256 /* hci_regs_s.vendor_id - See OpenHCI 1.00 section 5.2 */ 257 #define OHCI_VEND_ID 0x00FFFFFF 258 #define OHCI_VEND_UNIQUE 0xFF000000 259 260 /* hci_regs_s.hc_ctrl_set/clr - See OpenHCI 1.00 section 5.7 */ 261 #define OHCI_HC_NO_BSWAP 0x40000000 /* 1-big endian,0-little end */ 262 #define OHCI_HC_PROG_PHY_ENBL 0x00800000 /* 1-prog phy capabilities */ 263 #define OHCI_HC_APHY_ENBL 0x00040000 /* 1-Aphy enhancements enbld */ 264 #define OHCI_HC_LPS 0x00080000 /* 1-link pwr on, 0-off */ 265 #define OHCI_HC_POSTWR_ENBL 0x00040000 /* 1-enabled, 0-disabled */ 266 #define OHCI_HC_LINK_ENBL 0x00020000 /* 1-enabled, 0-disabled */ 267 #define OHCI_HC_SOFT_RESET 0x00010000 /* 1-reset in prog, 0-done */ 268 269 /* hci_regs_s.node_id - See OpenHCI 1.00 section 5.10 */ 270 #define OHCI_NDID_IDVALID 0x80000000 271 #define OHCI_NDID_ROOT_MASK 0x40000000 272 #define OHCI_NDID_ROOT_SHIFT 30 273 #define OHCI_NDID_CPS_MASK 0x08000000 274 #define OHCI_NDID_CPS_SHIFT 27 275 #define OHCI_NDID_BUSNUM_MASK 0x0000FFC0 276 #define OHCI_NDID_BUSNUM_SHIFT 6 277 #define OHCI_NDID_NODENUM_MASK 0x0000003F 278 #define OHCI_NDID_NODENUM_SHIFT 0 279 280 /* hci_regs_s.phy_ctrl - See OpenHCI 1.00 section 5.11, 1394-1994 J.4.1 */ 281 #define OHCI_PHYC_RDDONE 0x80000000 282 #define OHCI_PHYC_RDREG 0x00008000 283 #define OHCI_PHYC_WRREG 0x00004000 284 #define OHCI_PHYC_RDADDR_MASK 0x0F000000 285 #define OHCI_PHYC_RDADDR_SHIFT 24 286 #define OHCI_PHYC_RDDATA_MASK 0x00FF0000 287 #define OHCI_PHYC_RDDATA_SHIFT 16 288 #define OHCI_PHYC_REGADDR_MASK 0x00000F00 289 #define OHCI_PHYC_REGADDR_SHIFT 8 290 #define OHCI_PHYC_WRDATA_MASK 0x000000FF 291 #define OHCI_PHYC_WRDATA_SHIFT 0 292 293 /* hci_regs_s.context_ctrl -- several contexts */ 294 #define OHCI_CC_RUN_MASK 0x00008000 295 #define OHCI_CC_RUN_SHIFT 15 296 #define OHCI_CC_WAKE_MASK 0x00001000 297 #define OHCI_CC_WAKE_SHIFT 12 298 #define OHCI_CC_DEAD_MASK 0x00000800 299 #define OHCI_CC_DEAD_SHIFT 11 300 #define OHCI_CC_ACTIVE_MASK 0x00000400 301 #define OHCI_CC_ACTIVE_SHIFT 10 302 303 #define OHCI_CC_SPD_MASK 0x000000E0 304 #define OHCI_CC_SPD_SHIFT 5 305 #define OHCI_CC_EVT_MASK 0x0000001F 306 #define OHCI_CC_EVT_SHIFT 0 307 308 /* hci_regs context_ctrl for IR */ 309 #define OHCI_IRCTL_BFILL_MASK 0x80000000 310 #define OHCI_IRCTL_BFILL_SHIFT 31 311 #define OHCI_IRCTL_IHDR_MASK 0x40000000 312 #define OHCI_IRCTL_IHDR_SHIFT 30 313 #define OHCI_IRCTL_MTC_ENBL_MASK 0x20000000 314 #define OHCI_IRCTL_MTC_ENBL_SHIFT 29 315 #define OHCI_IRCTL_MULTI_MASK 0x10000000 316 #define OHCI_IRCTL_MULTI_SHIFT 28 317 318 /* hci_regs context_ctrl for IT */ 319 #define OHCI_ITCTL_MTC_ENBL_MASK 0x80000000 320 #define OHCI_ITCTL_MTC_ENBL_SHIFT 31 321 #define OHCI_ITCTL_MATCH_MASK 0x7FFF0000 322 #define OHCI_ITCTL_MATCH_SHIFT 16 323 324 325 #define HCI1394_IS_ARRESP(tcode) \ 326 ((tcode == IEEE1394_TCODE_WRITE_RESP) || \ 327 (tcode == IEEE1394_TCODE_READ_QUADLET_RESP) || \ 328 (tcode == IEEE1394_TCODE_READ_BLOCK_RESP) || \ 329 (tcode == IEEE1394_TCODE_LOCK_RESP)) 330 331 #define HCI1394_IS_ARREQ(tcode) \ 332 ((tcode == IEEE1394_TCODE_READ_QUADLET) || \ 333 (tcode == IEEE1394_TCODE_WRITE_QUADLET) || \ 334 (tcode == IEEE1394_TCODE_READ_BLOCK) || \ 335 (tcode == IEEE1394_TCODE_WRITE_BLOCK) || \ 336 (tcode == IEEE1394_TCODE_LOCK) || \ 337 (tcode == IEEE1394_TCODE_PHY)) 338 339 #define HCI1394_IRCTXT_CTRL_SET(HCIP, I, BFFILL, IHDR, MATCHENBL, MULTI, RUN, \ 340 WAKE) (ddi_put32((HCIP)->ohci->ohci_reg_handle, \ 341 &(HCIP)->ohci->ohci_regs->ir[(I)].ctxt_ctrl_set, \ 342 0 | (((BFFILL) << OHCI_IRCTL_BFILL_SHIFT) & OHCI_IRCTL_BFILL_MASK) | \ 343 (((IHDR) << OHCI_IRCTL_IHDR_SHIFT) & OHCI_IRCTL_IHDR_MASK) | \ 344 (((MATCHENBL) << OHCI_IRCTL_MTC_ENBL_SHIFT) & \ 345 OHCI_IRCTL_MTC_ENBL_MASK) | \ 346 (((MULTI) << OHCI_IRCTL_MULTI_SHIFT) & OHCI_IRCTL_MULTI_MASK) | \ 347 (((RUN) << OHCI_CC_RUN_SHIFT) & OHCI_CC_RUN_MASK) | \ 348 (((WAKE) << OHCI_CC_WAKE_SHIFT) & OHCI_CC_WAKE_MASK))) 349 350 #define HCI1394_IRCTXT_CTRL_CLR(HCIP, I, BFFILL, IHDR, MATCHENBL, MULTI, RUN) \ 351 (ddi_put32((HCIP)->ohci->ohci_reg_handle, \ 352 &(HCIP)->ohci->ohci_regs->ir[(I)].ctxt_ctrl_clr, \ 353 0 | (((BFFILL) << OHCI_IRCTL_BFILL_SHIFT) & OHCI_IRCTL_BFILL_MASK) | \ 354 (((IHDR) << OHCI_IRCTL_IHDR_SHIFT) & OHCI_IRCTL_IHDR_MASK) | \ 355 (((MATCHENBL) << OHCI_IRCTL_MTC_ENBL_SHIFT) & \ 356 OHCI_IRCTL_MTC_ENBL_MASK) | \ 357 (((MULTI) << OHCI_IRCTL_MULTI_SHIFT) & OHCI_IRCTL_MULTI_MASK) | \ 358 (((RUN) << OHCI_CC_RUN_SHIFT) & OHCI_CC_RUN_MASK))) 359 360 #define HCI1394_ITCTXT_CTRL_SET(HCIP, I, MATCHENBL, MATCH, RUN, WAKE) \ 361 (ddi_put32((HCIP)->ohci->ohci_reg_handle, \ 362 &(HCIP)->ohci->ohci_regs->it[(I)].ctxt_ctrl_set, 0 | \ 363 (((MATCHENBL) << OHCI_ITCTL_MTC_ENBL_SHIFT) & \ 364 OHCI_ITCTL_MTC_ENBL_MASK) | \ 365 (((MATCH) << OHCI_ITCTL_MATCH_SHIFT) & OHCI_ITCTL_MATCH_MASK) | \ 366 (((RUN) << OHCI_CC_RUN_SHIFT) & OHCI_CC_RUN_MASK) | \ 367 (((WAKE) << OHCI_CC_WAKE_SHIFT) & OHCI_CC_WAKE_MASK))) 368 369 #define HCI1394_ITCTXT_CTRL_CLR(HCIP, I, MATCHENBL, MATCH, RUN) \ 370 (ddi_put32((HCIP)->ohci->ohci_reg_handle, \ 371 &(HCIP)->ohci->ohci_regs->it[(I)].ctxt_ctrl_clr, 0 | \ 372 (((MATCHENBL) << OHCI_ITCTL_MTC_ENBL_SHIFT) & \ 373 OHCI_ITCTL_MTC_ENBL_MASK) | \ 374 (((MATCH) << OHCI_ITCTL_MATCH_SHIFT) & OHCI_ITCTL_MATCH_MASK) | \ 375 (((RUN) << OHCI_CC_RUN_SHIFT) & OHCI_CC_RUN_MASK))) 376 377 378 #define HCI1394_IRCTXT_MATCH_WRITE(HCIP, I, TAG3, TAG2, TAG1, TAG0, MATCH, \ 379 SYNC, TAG1SYNC, CHAN) (ddi_put32((HCIP)->ohci->ohci_reg_handle, \ 380 &(HCIP)->ohci->ohci_regs->ir[(I)].ctxt_match, 0 | \ 381 (((TAG3) << OHCI_MTC_TAG3_SHIFT) & OHCI_MTC_TAG3_MASK) | \ 382 (((TAG2) << OHCI_MTC_TAG2_SHIFT) & OHCI_MTC_TAG2_MASK) | \ 383 (((TAG1) << OHCI_MTC_TAG1_SHIFT) & OHCI_MTC_TAG1_MASK) | \ 384 (((TAG0) << OHCI_MTC_TAG0_SHIFT) & OHCI_MTC_TAG0_MASK) | \ 385 (((MATCH) << OHCI_MTC_MATCH_SHIFT) & OHCI_MTC_MATCH_MASK) | \ 386 (((SYNC) << OHCI_MTC_SYNC_SHIFT) & OHCI_MTC_SYNC_MASK) | \ 387 (((TAG1SYNC) << OHCI_MTC_TAG1SY_SHIFT) & OHCI_MTC_TAG1SY_MASK) | \ 388 (((CHAN) << OHCI_MTC_CHAN_SHIFT) & OHCI_MTC_CHAN_MASK))) 389 390 #define HCI1394_ISOCH_CTXT_ACTIVE(SOFTSTATEP, CTXTP) \ 391 (ddi_get32((SOFTSTATEP)->ohci->ohci_reg_handle, \ 392 &(CTXTP)->ctxt_regsp->ctxt_ctrl_set) & OHCI_CC_ACTIVE_MASK) 393 394 #define HCI1394_ISOCH_CTXT_RUN(SOFTSTATEP, CTXTP) \ 395 (ddi_get32((SOFTSTATEP)->ohci->ohci_reg_handle, \ 396 &(CTXTP)->ctxt_regsp->ctxt_ctrl_set) & OHCI_CC_RUN_MASK) 397 398 #define HCI1394_ISOCH_CTXT_CMD_PTR(SOFTSTATEP, CTXTP) \ 399 (ddi_get32((SOFTSTATEP)->ohci->ohci_reg_handle, \ 400 &(CTXTP)->ctxt_regsp->cmd_ptrlo)) 401 402 /* 403 * 1394 OpenHCI 1.0 general context register layout 404 * All contexts except for Isoch Receive have the following layout 405 * See the OpenHCI v1.0 specification for register definitions. 406 */ 407 typedef struct hci1394_ctxt_regs_s { 408 uint32_t ctxt_ctrl_set; 409 uint32_t ctxt_ctrl_clr; 410 uint32_t reserved; 411 uint32_t cmd_ptrlo; 412 } hci1394_ctxt_regs_t; 413 414 /* 415 * 1394 OpenHCI 1.0 Isochronous Receive context register layout 416 * See the OpenHCI v1.0 specification for register definitions. 417 */ 418 typedef struct hci1394_ir_ctxt_regs_s { 419 uint32_t ctxt_ctrl_set; 420 uint32_t ctxt_ctrl_clr; 421 uint32_t reserved0; 422 uint32_t cmd_ptrlo; 423 uint32_t ctxt_match; 424 uint32_t reserved1[3]; 425 } hci1394_ir_ctxt_regs_t; 426 427 /* 428 * 1394 OpenHCI 1.0 registers 429 * See the OpenHCI v1.0 specification for register definitions. 430 */ 431 typedef struct hci1394_regs_s { 432 uint32_t version; 433 uint32_t guid_rom; 434 uint32_t at_retries; 435 uint32_t csr_data; 436 uint32_t csr_compare_data; 437 uint32_t csr_ctrl; 438 uint32_t config_rom_hdr; 439 uint32_t bus_id; 440 uint32_t bus_options; 441 uint32_t guid_hi; 442 uint32_t guid_lo; 443 uint32_t reserved01; 444 uint32_t reserved02; 445 uint32_t config_rom_maplo; 446 uint32_t posted_write_addrlo; 447 uint32_t posted_write_addrhi; 448 uint32_t vendor_id; 449 uint32_t reserved03[3]; 450 uint32_t hc_ctrl_set; 451 uint32_t hc_ctrl_clr; 452 uint32_t reserved06[2]; 453 uint32_t reserved08; 454 uint32_t self_id_buflo; 455 uint32_t self_id_count; 456 uint32_t reserved09; 457 uint32_t ir_multi_maskhi_set; 458 uint32_t ir_multi_maskhi_clr; 459 uint32_t ir_multi_masklo_set; 460 uint32_t ir_multi_masklo_clr; 461 uint32_t intr_event_set; 462 uint32_t intr_event_clr; 463 uint32_t intr_mask_set; 464 uint32_t intr_mask_clr; 465 uint32_t it_intr_event_set; 466 uint32_t it_intr_event_clr; 467 uint32_t it_intr_mask_set; 468 uint32_t it_intr_mask_clr; 469 uint32_t ir_intr_event_set; 470 uint32_t ir_intr_event_clr; 471 uint32_t ir_intr_mask_set; 472 uint32_t ir_intr_mask_clr; 473 uint32_t reserved10[11]; 474 uint32_t fairness_ctrl; 475 uint32_t link_ctrl_set; 476 uint32_t link_ctrl_clr; 477 uint32_t node_id; 478 uint32_t phy_ctrl; 479 uint32_t isoch_cycle_timer; 480 uint32_t reserved21[3]; 481 uint32_t ar_req_filterhi_set; 482 uint32_t ar_req_filterhi_clr; 483 uint32_t ar_req_filterlo_set; 484 uint32_t ar_req_filterlo_clr; 485 uint32_t phys_req_filterhi_set; 486 uint32_t phys_req_filterhi_clr; 487 uint32_t phys_req_filterlo_set; 488 uint32_t phys_req_filterlo_clr; 489 uint32_t phys_upper_bound; 490 uint32_t reserved24[23]; 491 hci1394_ctxt_regs_t at_req; 492 uint32_t reserved47[4]; 493 hci1394_ctxt_regs_t at_resp; 494 uint32_t reserved51[4]; 495 hci1394_ctxt_regs_t ar_req; 496 uint32_t reserved55[4]; 497 hci1394_ctxt_regs_t ar_resp; 498 uint32_t reserved59[4]; 499 hci1394_ctxt_regs_t it[HCI1394_MAX_ISOCH_CONTEXTS]; 500 hci1394_ir_ctxt_regs_t ir[HCI1394_MAX_ISOCH_CONTEXTS]; 501 } hci1394_regs_t; 502 503 504 /* private structure to keep track of OpenHCI */ 505 typedef struct hci1394_ohci_s { 506 /* config ROM and selfid buffers */ 507 hci1394_buf_handle_t ohci_cfgrom_handle; 508 hci1394_buf_handle_t ohci_selfid_handle; 509 510 /* 511 * Phy register #1 cached settings. These are only used for 1394-1995 512 * phy's. When setting the root holdoff bit and gap count in 1394, 513 * you send out a PHY configuration packet. The 1995 PHY's will 514 * not look at the PHY packet if we sent it out which means we have 515 * to write directly to PHY register 1. This creates some ugly race 516 * conditions. Since we will be following up these settings with a bus 517 * reset shortly, we "cache" them until we generate the bus reset. This 518 * solution is not perfect, but it is the best of a bad thing. 519 */ 520 boolean_t ohci_set_root_holdoff; 521 boolean_t ohci_set_gap_count; 522 uint_t ohci_gap_count; 523 524 /* 525 * The bus time is kept using the cycle timer and then counting the 526 * rollovers via the cycle 64 seconds interrupt. (NOTE: every 2 527 * interrupts is one rollover) We do not wish to be interrupting 528 * the CPU if there is nothing plugged into the bus (since bus time 529 * really isn't used for anything yet (maybe when bridges come out?)). 530 * We will start with the interrupt disabled, if the bus master writes 531 * to the CSR bus time register, we will enable the interrupt. These 532 * fields keep track of the rollover and whether or not the interrupt 533 * is enabled. 534 */ 535 volatile uint_t ohci_bustime_count; 536 boolean_t ohci_bustime_enabled; 537 538 /* whether we have a 1394-1995 or 1394A phy */ 539 h1394_phy_t ohci_phy; 540 541 /* General Driver Info */ 542 hci1394_drvinfo_t *ohci_drvinfo; 543 544 /* 545 * self id buffer and config rom info. These are towards bottom of the 546 * structure to make debugging easier. 547 */ 548 hci1394_buf_info_t ohci_selfid; 549 hci1394_buf_info_t ohci_cfgrom; 550 551 /* OpenHCI registers */ 552 ddi_acc_handle_t ohci_reg_handle; 553 hci1394_regs_t *ohci_regs; 554 555 /* 556 * This mutex is used to protect "atomic" operations to the OpenHCI 557 * hardware. This includes reads and writes to the PHY, cswap 558 * operations to the HW implemented CSR registers, and any read/modify/ 559 * write operations such as updating atreq retries. 560 */ 561 kmutex_t ohci_mutex; 562 563 hci1394_state_t *soft_state; 564 } hci1394_ohci_t; 565 566 _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", \ 567 hci1394_ohci_s::ohci_bustime_count \ 568 hci1394_ohci_s::ohci_bustime_enabled \ 569 hci1394_ohci_s::ohci_gap_count \ 570 hci1394_ohci_s::ohci_set_gap_count \ 571 hci1394_ohci_s::ohci_set_root_holdoff)) 572 573 /* handle passed back from init() and used for rest of functions */ 574 typedef hci1394_ohci_t *hci1394_ohci_handle_t; 575 576 577 int hci1394_ohci_init(hci1394_state_t *soft_state, hci1394_drvinfo_t *drvinfo, 578 hci1394_ohci_handle_t *ohci_hdl); 579 void hci1394_ohci_fini(hci1394_ohci_handle_t *ohci_hdl); 580 581 void hci1394_ohci_reg_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 582 uint32_t *data); 583 void hci1394_ohci_reg_write(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 584 uint32_t data); 585 int hci1394_ohci_phy_init(hci1394_ohci_handle_t ohci_hdl); 586 int hci1394_ohci_phy_set(hci1394_ohci_handle_t ohci_hdl, uint_t regAddr, 587 uint_t bits); 588 int hci1394_ohci_phy_clr(hci1394_ohci_handle_t ohci_hdl, uint_t regAddr, 589 uint_t bits); 590 int hci1394_ohci_phy_read(hci1394_ohci_handle_t ohci_hdl, uint_t regAddr, 591 uint_t *rdData); 592 int hci1394_ohci_phy_write(hci1394_ohci_handle_t ohci_hdl, uint_t regAddr, 593 uint_t wrData); 594 int hci1394_ohci_phy_info(hci1394_ohci_handle_t ohci_hdl, uint32_t *info); 595 void hci1394_ohci_intr_master_enable(hci1394_ohci_handle_t ohci_hdl); 596 void hci1394_ohci_intr_master_disable(hci1394_ohci_handle_t ohci_hdl); 597 uint32_t hci1394_ohci_intr_asserted(hci1394_ohci_handle_t ohci_hdl); 598 void hci1394_ohci_intr_enable(hci1394_ohci_handle_t ohci_hdl, 599 uint32_t intr_mask); 600 void hci1394_ohci_intr_disable(hci1394_ohci_handle_t ohci_hdl, 601 uint32_t intr_mask); 602 void hci1394_ohci_intr_clear(hci1394_ohci_handle_t ohci_hdl, 603 uint32_t intr_mask); 604 uint32_t hci1394_ohci_it_intr_asserted(hci1394_ohci_handle_t ohci_hdl); 605 void hci1394_ohci_it_intr_enable(hci1394_ohci_handle_t ohci_hdl, 606 uint32_t intr_mask); 607 void hci1394_ohci_it_intr_disable(hci1394_ohci_handle_t ohci_hdl, 608 uint32_t intr_mask); 609 void hci1394_ohci_it_intr_clear(hci1394_ohci_handle_t ohci_hdl, 610 uint32_t intr_mask); 611 int hci1394_ohci_it_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl); 612 void hci1394_ohci_it_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl, 613 uint_t context_number, uint32_t io_addr); 614 uint32_t hci1394_ohci_ir_intr_asserted(hci1394_ohci_handle_t ohci_hdl); 615 void hci1394_ohci_ir_intr_enable(hci1394_ohci_handle_t ohci_hdl, 616 uint32_t intr_mask); 617 void hci1394_ohci_ir_intr_disable(hci1394_ohci_handle_t ohci_hdl, 618 uint32_t intr_mask); 619 void hci1394_ohci_ir_intr_clear(hci1394_ohci_handle_t ohci_hdl, 620 uint32_t intr_mask); 621 int hci1394_ohci_ir_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl); 622 void hci1394_ohci_ir_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl, 623 uint_t context_number, uint32_t io_addr); 624 void hci1394_ohci_link_enable(hci1394_ohci_handle_t ohci_hdl); 625 void hci1394_ohci_link_disable(hci1394_ohci_handle_t ohci_hdl); 626 uint_t hci1394_ohci_current_busgen(hci1394_ohci_handle_t ohci_hdl); 627 int hci1394_ohci_soft_reset(hci1394_ohci_handle_t ohci_hdl); 628 int hci1394_ohci_startup(hci1394_ohci_handle_t ohci_hdl); 629 uint64_t hci1394_ohci_guid(hci1394_ohci_handle_t ohci_hdl); 630 int hci1394_ohci_csr_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 631 uint32_t *data); 632 int hci1394_ohci_csr_cswap(hci1394_ohci_handle_t ohci_hdl, uint_t generation, 633 uint_t offset, uint32_t compare, uint32_t swap, uint32_t *old); 634 int hci1394_ohci_bus_reset(hci1394_ohci_handle_t ohci_hdl); 635 int hci1394_ohci_bus_reset_nroot(hci1394_ohci_handle_t ohci_hdl); 636 int hci1394_ohci_bus_reset_short(hci1394_ohci_handle_t ohci_hdl); 637 void hci1394_ohci_postwr_addr(hci1394_ohci_handle_t ohci_hdl, uint64_t *addr); 638 int hci1394_ohci_contender_enable(hci1394_ohci_handle_t ohci_hdl); 639 int hci1394_ohci_root_holdoff_enable(hci1394_ohci_handle_t ohci_hdl); 640 int hci1394_ohci_gap_count_set(hci1394_ohci_handle_t ohci_hdl, 641 uint_t gap_count); 642 int hci1394_ohci_phy_filter_set(hci1394_ohci_handle_t ohci_hdl, 643 uint64_t mask, uint_t generation); 644 int hci1394_ohci_phy_filter_clr(hci1394_ohci_handle_t ohci_hdl, 645 uint64_t mask, uint_t generation); 646 void hci1394_ohci_cfgrom_update(hci1394_ohci_handle_t ohci_hdl, 647 void *local_buf, uint_t quadlet_count); 648 void hci1394_ohci_selfid_enable(hci1394_ohci_handle_t ohci_hdl); 649 void hci1394_ohci_selfid_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 650 uint32_t *data); 651 void hci1394_ohci_selfid_info(hci1394_ohci_handle_t ohci_hdl, uint_t *busgen, 652 uint_t *size, boolean_t *error); 653 boolean_t hci1394_ohci_selfid_buf_current(hci1394_ohci_handle_t ohci_hdl); 654 void hci1394_ohci_selfid_sync(hci1394_ohci_handle_t ohci_hdl); 655 void hci1394_ohci_nodeid_set(hci1394_ohci_handle_t ohci_hdl, uint_t nodeid); 656 void hci1394_ohci_nodeid_get(hci1394_ohci_handle_t ohci_hdl, uint_t *nodeid); 657 void hci1394_ohci_nodeid_info(hci1394_ohci_handle_t ohci_hdl, 658 uint_t *nodeid, boolean_t *error); 659 void hci1394_ohci_cycletime_get(hci1394_ohci_handle_t ohci_hdl, 660 uint32_t *cycle_time); 661 void hci1394_ohci_cycletime_set(hci1394_ohci_handle_t ohci_hdl, 662 uint32_t cycle_time); 663 void hci1394_ohci_bustime_get(hci1394_ohci_handle_t ohci_hdl, 664 uint32_t *bus_time); 665 void hci1394_ohci_bustime_set(hci1394_ohci_handle_t ohci_hdl, 666 uint32_t bus_time); 667 void hci1394_ohci_atreq_retries_get(hci1394_ohci_handle_t ohci_hdl, 668 uint_t *atreq_retries); 669 void hci1394_ohci_atreq_retries_set(hci1394_ohci_handle_t ohci_hdl, 670 uint_t atreq_retries); 671 void hci1394_ohci_isr_cycle64seconds(hci1394_ohci_handle_t ohci_hdl); 672 void hci1394_ohci_isr_phy(hci1394_ohci_handle_t ohci_hdl); 673 boolean_t hci1394_ohci_root_check(hci1394_ohci_handle_t ohci_hdl); 674 boolean_t hci1394_ohci_cmc_check(hci1394_ohci_handle_t ohci_hdl); 675 void hci1394_ohci_cycle_master_enable(hci1394_ohci_handle_t ohci_hdl); 676 void hci1394_ohci_cycle_master_disable(hci1394_ohci_handle_t ohci_hdl); 677 int hci1394_ohci_resume(hci1394_ohci_handle_t ohci_hdl); 678 void hci1394_ohci_bus_capabilities(hci1394_ohci_handle_t ohci_hdl, 679 uint32_t *bus_capabilities); 680 boolean_t hci1394_ohci_at_active(hci1394_ohci_handle_t ohci_hdl); 681 void hci1394_ohci_atreq_start(hci1394_ohci_handle_t ohci_hdl, 682 uint32_t cmdptr); 683 void hci1394_ohci_atreq_wake(hci1394_ohci_handle_t ohci_hdl); 684 void hci1394_ohci_atreq_stop(hci1394_ohci_handle_t ohci_hdl); 685 void hci1394_ohci_arresp_start(hci1394_ohci_handle_t ohci_hdl, 686 uint32_t cmdptr); 687 void hci1394_ohci_arresp_wake(hci1394_ohci_handle_t ohci_hdl); 688 void hci1394_ohci_arresp_stop(hci1394_ohci_handle_t ohci_hdl); 689 void hci1394_ohci_arreq_start(hci1394_ohci_handle_t ohci_hdl, 690 uint32_t cmdptr); 691 void hci1394_ohci_arreq_wake(hci1394_ohci_handle_t ohci_hdl); 692 void hci1394_ohci_arreq_stop(hci1394_ohci_handle_t ohci_hdl); 693 void hci1394_ohci_atresp_start(hci1394_ohci_handle_t ohci_hdl, 694 uint32_t cmdptr); 695 void hci1394_ohci_atresp_wake(hci1394_ohci_handle_t ohci_hdl); 696 void hci1394_ohci_atresp_stop(hci1394_ohci_handle_t ohci_hdl); 697 698 699 #ifdef __cplusplus 700 } 701 #endif 702 703 #endif /* _SYS_1394_ADAPTERS_HCI1394_OHCI_H */ 704