1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_1394_ADAPTERS_HCI1394_ISOCH_H 28 #define _SYS_1394_ADAPTERS_HCI1394_ISOCH_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * hci1394_isoch.h 34 * Function declarations for front-end functions for hci1394 isochronous 35 * support. Also all isochronous related soft_state structures and defs. 36 */ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <sys/note.h> 43 #include <sys/1394/adapters/hci1394_def.h> 44 45 46 /* handle passed back from init() and used for rest of functions */ 47 typedef struct hci1394_isoch_s *hci1394_isoch_handle_t; 48 49 /* 50 * Isochronous structures and defs used in the hci1394 soft state. 51 * (see hci1394_state.h). 52 */ 53 54 /* 55 * control structure for allocated isochronous dma descriptor memory. 56 * when attempting to bind memory, if ddi_addr_bind_handle indicates multiple 57 * cookies, each cookie will be tracked within a separate copy of this 58 * structure. Only the last cookie's idma_desc_mem structure will contain 59 * a valid mem_handle and mem, to be used when freeing all the memory. 60 * 61 * 'used' specifies the number of bytes used for descriptors in this cookie. 62 * 'offset' is this cookie's offset relative to the beginning of the buffer. 63 */ 64 typedef struct hci1394_idma_desc_mem_s { 65 struct hci1394_idma_desc_mem_s *dma_nextp; 66 hci1394_buf_handle_t mem_handle; 67 hci1394_buf_info_t mem; 68 uint32_t used; 69 uint32_t offset; 70 } hci1394_idma_desc_mem_t; 71 72 _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_idma_desc_mem_s)) 73 74 /* structure to track one isochronous context */ 75 /* XXX if IR Multichan mode support is added, this must be modified */ 76 typedef struct hci1394_iso_ctxt_s { 77 int ctxt_index; /* 0-31 -- which context this is */ 78 int ctxt_io_mode; /* xmit, recv pkt or buf, hdrs, multi */ 79 uint32_t ctxt_flags; /* general context info */ 80 volatile uint32_t intr_flags; /* flags while context is running */ 81 kmutex_t intrprocmutex; /* interrupt/update coordination */ 82 kcondvar_t intr_cv; /* interrupt completion cv */ 83 uint16_t isospd; /* speed of packets for context */ 84 uint16_t isochan; /* isochronous channel for contxt */ 85 86 hci1394_ctxt_regs_t *ctxt_regsp; /* ctxt regs within hci1394_regs_t */ 87 88 void *xcs_firstp; /* first alloc xfer_ctl_t struct */ 89 hci1394_idma_desc_mem_t *dma_firstp; /* 1st alloc dma descriptor mem */ 90 uint32_t dma_mem_execp; /* exec start(bound mem w/Z bits) */ 91 uint32_t reserved; 92 93 ixl1394_command_t *ixl_firstp; /* 1st ixl cmmand in linked list */ 94 ixl1394_command_t *ixl_execp; /* currently executing ixl cmmand */ 95 uint_t ixl_exec_depth; /* curr exec ixl cmd xfer_ctl idx */ 96 97 uint_t max_dma_skips; /* max skips allowed before xmit */ 98 /* recovery required (16 => 2ms) */ 99 uint_t max_noadv_intrs; /* max intrs with no dma descriptor */ 100 /* block advances (8) */ 101 uint_t rem_noadv_intrs; /* remaining intrs allowed with no */ 102 /* dma advances (i.e. no status set) */ 103 104 uint16_t dma_last_time; /* last completd desc blk tmestmp */ 105 106 uint16_t default_tag; /* default tag value */ 107 uint16_t default_sync; /* default sync value */ 108 uint16_t default_skipmode; /* default skip mode */ 109 110 ixl1394_command_t *default_skiplabelp; /* set if needed */ 111 ixl1394_command_t *default_skipxferp; /* xfercmd for default skiplabl */ 112 113 void *global_callback_arg; /* provided to IXLcallbacks */ 114 opaque_t idma_evt_arg; /* provided to "stopped" callback */ 115 116 /* target callback if dma stops */ 117 void (*isoch_dma_stopped)(struct isoch_dma_handle *idma_hdl, 118 opaque_t idma_evt_arg, id1394_isoch_dma_stopped_t idma_stop_args); 119 120 } hci1394_iso_ctxt_t; 121 122 _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_iso_ctxt_s)) 123 124 /* 125 * defs for hci1394_iso_ctxt_t.ctxt_io_mode. 126 * overall io characteristics of the contexts, initialized during isoch init 127 * and never changed. 128 */ 129 /* 130 * defs for hci1394_iso_ctxt_t.ctxt_flags 131 * These flags are protected by the context list mutex in the isoch handle 132 * (see hci1394_isoch.c for mutex definition) 133 */ 134 #define HCI1394_ISO_CTXT_INUSE 0x00000001 /* context is in use */ 135 #define HCI1394_ISO_CTXT_RUNNING 0x00000002 /* context is running */ 136 #define HCI1394_ISO_CTXT_RECV 0x00000004 /* isoch receive context */ 137 #define HCI1394_ISO_CTXT_CMDREG 0x00000008 /* dev has readable dma cmdptr */ 138 #define HCI1394_ISO_CTXT_BFFILL 0x00000010 /* on=BufFill off=Pkt IR only */ 139 #define HCI1394_ISO_CTXT_RHDRS 0x00000020 /* recv packet hdrs into mem */ 140 #define HCI1394_ISO_CTXT_MULTI 0x00000040 /* in multichan mode - IR only */ 141 142 /* 143 * defs for hci1394_iso_ctxt_t.intr_flags 144 * These flags are protected by the per-context mutex "intrprocmutex" 145 */ 146 #define HCI1394_ISO_CTXT_STOP 0x00000010 /* context stopped */ 147 #define HCI1394_ISO_CTXT_INTRSET 0x00000020 /* intr flagged, not processed */ 148 #define HCI1394_ISO_CTXT_ININTR 0x00000040 /* in intrproc, not due to int */ 149 #define HCI1394_ISO_CTXT_INUPDATE 0x00000080 /* in intrproc, not due to int */ 150 #define HCI1394_ISO_CTXT_INCALL 0x00000100 /* intrproc is doing callback */ 151 152 /* 153 * structure used to do accounting for interrupt usage. Specifically, 154 * used to determine when CYCLE_LOST or CYCLE_INCONSISTENT storms 155 * should cause us to disable those interrupts. 156 */ 157 typedef struct hci1394_intr_thresh_s { 158 hrtime_t last_intr_time; 159 hrtime_t delta_t_thresh; 160 int delta_t_counter; 161 int counter_thresh; 162 } hci1394_intr_thresh_t; 163 164 /* defs for the hci1394_intr_thresh_t struct */ 165 #define HCI1394_CYC_LOST_DELTA 400000; /* 400ms */ 166 #define HCI1394_CYC_LOST_COUNT 25; 167 #define HCI1394_CYC_INCON_DELTA 400000; /* 400ms */ 168 #define HCI1394_CYC_INCON_COUNT 25; 169 170 /* 171 * Structure used for tracking all transmit and receive isochronous contexts 172 * Also contains the information necessary for tracking CYCLE_LOST and 173 * CYCLE_INCONSISTENT interrupt usage. 174 * The ctxt_list mutex protects the in-use status of the contexts while 175 * searching for a free isoch context to use in hci1394_alloc_isoch_dma(), 176 * during interrupt processing, and during free_isoch_dma processing. 177 * An openHCI 1.0 hardware implementation may support up to 32 separate DMA 178 * engines each for transmit and receive, referred to as "contexts". 179 * The number of supported contexts is determined during ohci board 180 * initialization, and can be different for transmit vs. receive. 181 */ 182 typedef struct hci1394_isoch_s { 183 hci1394_intr_thresh_t cycle_lost_thresh; 184 hci1394_intr_thresh_t cycle_incon_thresh; 185 int isoch_dma_alloc_cnt; 186 int unused; 187 int ctxt_xmit_count; 188 int ctxt_recv_count; 189 hci1394_iso_ctxt_t ctxt_xmit[HCI1394_MAX_ISOCH_CONTEXTS]; 190 hci1394_iso_ctxt_t ctxt_recv[HCI1394_MAX_ISOCH_CONTEXTS]; 191 kmutex_t ctxt_list_mutex; 192 } hci1394_isoch_t; 193 194 195 void hci1394_isoch_init(hci1394_drvinfo_t *drvinfo, hci1394_ohci_handle_t ohci, 196 hci1394_isoch_handle_t *isoch_hdl); 197 void hci1394_isoch_fini(hci1394_isoch_handle_t *isoch_hdl); 198 void hci1394_isoch_cycle_inconsistent(hci1394_state_t *soft_statep); 199 void hci1394_isoch_cycle_lost(hci1394_state_t *soft_statep); 200 int hci1394_isoch_resume(hci1394_state_t *soft_statep); 201 void hci1394_isoch_error_ints_enable(hci1394_state_t *soft_statep); 202 203 int hci1394_isoch_recv_count_get(hci1394_isoch_handle_t isoch_hdl); 204 hci1394_iso_ctxt_t *hci1394_isoch_recv_ctxt_get(hci1394_isoch_handle_t 205 isoch_hdl, int num); 206 int hci1394_isoch_xmit_count_get(hci1394_isoch_handle_t isoch_hdl); 207 hci1394_iso_ctxt_t *hci1394_isoch_xmit_ctxt_get(hci1394_isoch_handle_t 208 isoch_hdl, int num); 209 210 211 int hci1394_alloc_isoch_dma(void *hal_private, id1394_isoch_dmainfo_t *idi, 212 void **hal_idma_handle, int *resultp); 213 void hci1394_free_isoch_dma(void *hal_private, void *hal_isoch_dma_handle); 214 int hci1394_start_isoch_dma(void *hal_private, void *hal_isoch_dma_handle, 215 id1394_isoch_dma_ctrlinfo_t *idma_ctrlinfo, uint_t flags, int *resultp); 216 int hci1394_update_isoch_dma(void *hal_private, void *hal_isoch_dma_handle, 217 id1394_isoch_dma_updateinfo_t *idma_updateinfop, uint_t flags, 218 int *resultp); 219 void hci1394_stop_isoch_dma(void *hal_private, void *hal_isoch_dma_handle, 220 int *resultp); 221 void hci1394_do_stop(hci1394_state_t *soft_statep, hci1394_iso_ctxt_t *ctxtp, 222 boolean_t do_callback, id1394_isoch_dma_stopped_t stop_args); 223 224 #ifdef __cplusplus 225 } 226 #endif 227 228 #endif /* _SYS_1394_ADAPTERS_HCI1394_ISOCH_H */ 229