1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _SYS_1394_ADAPTERS_HCI1394_IOCTL_H 28 #define _SYS_1394_ADAPTERS_HCI1394_IOCTL_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * hci1394_ioctl.h 34 * Test ioctl's to support test/debug of the 1394 HW. hci1394_ioctl_enum_t is 35 * passed in cmd and a pointer to the appropriate structure (i.e. 36 * hci1394_ioctl_wrreg_t) is passed in arg. 37 */ 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 44 /* 45 * write_reg - write OpenHCI register 46 * read_reg - read OpenHCI register 47 * write_vreg - write OpenHCI Vendor Specific register 48 * read_vreg - read OpenHCI Vendor Specific register 49 * reset_bus - reset the 1394 bus 50 * selfid_cnt - return the number of times we saw the selfid complete 51 * interrupt signifying a bus reset has completed. This does not 52 * have to match the bus generation and probably won't. 53 * busgen_cnt - return the current bus generation 54 * read_selfid - read selfid buffer 55 * write_phy - write PHY register 56 * read_phy - read PHY register 57 * hba_info - HBA vendor information 58 */ 59 #define HCI11394_IOCTL ('f' << 8) 60 typedef enum { 61 HCI1394_IOCTL_WRITE_REG = HCI11394_IOCTL | 0x00, 62 HCI1394_IOCTL_READ_REG = HCI11394_IOCTL | 0x01, 63 HCI1394_IOCTL_WRITE_VREG = HCI11394_IOCTL | 0x02, 64 HCI1394_IOCTL_READ_VREG = HCI11394_IOCTL | 0x03, 65 HCI1394_IOCTL_RESET_BUS = HCI11394_IOCTL | 0x04, 66 HCI1394_IOCTL_SELFID_CNT = HCI11394_IOCTL | 0x05, 67 HCI1394_IOCTL_BUSGEN_CNT = HCI11394_IOCTL | 0x06, 68 HCI1394_IOCTL_READ_SELFID = HCI11394_IOCTL | 0x07, 69 HCI1394_IOCTL_WRITE_PHY = HCI11394_IOCTL | 0x08, 70 HCI1394_IOCTL_READ_PHY = HCI11394_IOCTL | 0x09, 71 HCI1394_IOCTL_HBA_INFO = HCI11394_IOCTL | 0x0A 72 } hci1394_ioctl_enum_t; 73 74 75 /* 76 * HCI1394_IOCTL_WRITE_REG 77 * Write OHCI register. addr is an offset into the OpenHCI register map. 78 * (i.e. addr = 0 would write to the Version Register). addr must be 32-bit 79 * aligned (i.e. 0, 4, 8, C, 10). data is the 32-bit word to write into the 80 * OpenHCI register. 81 * 82 * NOTE: Writing OpenHCI registers can cause the hardware and/or SW to 83 * misbehave. Extreme care should be used when using this call. 84 */ 85 typedef struct hci1394_ioctl_wrreg_s { 86 uint_t addr; 87 uint32_t data; 88 } hci1394_ioctl_wrreg_t; 89 90 91 /* 92 * HCI1394_IOCTL_READ_REG 93 * Read OHCI register. addr is an offset into the OpenHCI register map. 94 * (i.e. addr = 0 would write to the Version Register). addr must be 32-bit 95 * aligned (i.e. 0, 4, 8, C, 10). When the ioctl returns successfully, data 96 * will contain the 32-bit word read from the OHCI register. 97 */ 98 typedef struct hci1394_ioctl_rdreg_s { 99 uint_t addr; 100 uint32_t data; 101 } hci1394_ioctl_rdreg_t; 102 103 104 /* 105 * HCI1394_IOCTL_WRITE_VREG 106 * Write Vendor Specific OHCI register. addr is an offset into the Vendor 107 * Specific OpenHCI register map. (i.e. addr = 0 would write to the first 108 * Vendor Specific register. addr must be 32-bit aligned (i.e. 0, 4, 8, C, 109 * 10). data is the 32-bit word to write into the Vendor Specific OpenHCI 110 * register. regset defines which vendor specific register set to write to. 111 * There will usually be one vendor specific register set so this will 112 * usually be set to 0. 113 * 114 * NOTE: Writing Vendor Specific OpenHCI registers can cause the hardware 115 * and/or SW to misbehave. Extreme care should be used when using this 116 * call. 117 */ 118 typedef struct hci1394_ioctl_wrvreg_s { 119 uint_t regset; 120 uint_t addr; 121 uint32_t data; 122 } hci1394_ioctl_wrvreg_t; 123 124 125 /* 126 * HCI1394_IOCTL_READ_VREG 127 * Read Vendor specific OHCI register. addr is an offset into the Vendor 128 * Specific OpenHCI register space. (i.e. addr = 0 is the first Vendor 129 * Specific register). addr must be 32-bit aligned (i.e. 0, 4, 8, C, 10). 130 * When the ioctl returns successfully, data will contain the 32-bit word 131 * read from the Vendor Specific OHCI register. regset defines which vendor 132 * specific register set to read from. There will usually be one vendor 133 * specific register set so this will usually be set to 0. 134 */ 135 typedef struct hci1394_ioctl_rdvreg_s { 136 uint_t regset; 137 uint_t addr; 138 uint32_t data; 139 } hci1394_ioctl_rdvreg_t; 140 141 142 /* HCI1394_IOCTL_RESET_BUS has no parameters */ 143 144 145 /* 146 * HCI1394_IOCTL_SELFID_CNT 147 * When the ioctl returns successfully, count will contain the number of 148 * times the nexus driver has seen and responded to a selfid_complete 149 * interrupt. This interrupt signifies that the bus reset has completed 150 * and the hardware based bus enumeration has completed. This number will 151 * most likely not be the same as the bus generation. Everytime this 152 * increments, the bus generation count should increment by at least one. 153 * 154 * NOTE: The current implementation of the nexus driver uses a uint_t for 155 * selfid_cnt. 156 */ 157 typedef struct hci1394_ioctl_selfid_cnt_s { 158 uint_t count; 159 } hci1394_ioctl_selfid_cnt_t; 160 161 162 /* 163 * HCI1394_IOCTL_BUSGEN_CNT 164 * When the ioctl returns successfully, count will contain the current 1394 165 * bus generation count. 166 * 167 * NOTE: The current implementation of the nexus driver uses the OpenHCI 168 * generation count which is an 8 bit value. Therefore, this count will 169 * wrap over at 0xFF. 170 */ 171 typedef struct hci1394_ioctl_busgen_cnt_s { 172 uint_t count; 173 } hci1394_ioctl_busgen_cnt_t; 174 175 176 /* 177 * HCI1394_IOCTL_READ_SELFID 178 * Copies the contents of the selfid buffer into a buffer pointed to by buf. 179 * Count is the number of 32-bit words to copy into buf. The maximum size 180 * of the selfid buffer is 1024 32-bit words. The very first word is the 181 * OpenHCI selfid header. 182 */ 183 typedef struct hci1394_ioctl_read_selfid_s { 184 uint32_t *buf; 185 uint_t count; 186 } hci1394_ioctl_read_selfid_t; 187 188 189 /* 190 * HCI1394_IOCTL_WRPHY 191 * Write PHY register. addr is an offset into the phy register space. 192 * (i.e. addr = 0 is the first phy register). addr is byte aligned 193 * (i.e. 0, 1, 2, 3, 4). data should contain the 8-bit value to write to the 194 * PHY register. The data should be stored as follows <0x000000dd> where dd 195 * is the byte written. 196 * 197 * NOTE: Phy register 0 cannot be read or written. 198 * 199 * NOTE: Writing PHY registers can cause the hardware and/or SW to misbehave. 200 * Extreme care should be used when using this call. 201 */ 202 typedef struct hci1394_ioctl_wrphy_s { 203 uint_t addr; 204 uint_t data; 205 } hci1394_ioctl_wrphy_t; 206 207 208 /* 209 * HCI1394_IOCTL_RDPHY 210 * Read PHY register. addr is an offset into the phy register space. 211 * (i.e. addr = 0 is the first phy register). addr is byte aligned 212 * (i.e. 0, 1, 2, 3, 4). When the ioctl returns successfully, data will 213 * contain the 8-bit data read from the PHY register. The data will be stored 214 * as follows <0x000000dd> where dd is the byte read. 215 * 216 * NOTE: Phy register 0 cannot be read or written. 217 */ 218 typedef struct hci1394_ioctl_rdphy_s { 219 uint_t addr; 220 uint_t data; 221 } hci1394_ioctl_rdphy_t; 222 223 224 /* 225 * HCI1394_IOCTL_HBA_INFO 226 * HBA Vendor Information 227 * 228 * Vendor Specific Info 229 * pci_vendor_id - VendorID from PCI config space (0x0-0x1) 230 * pci_device_id - DeviceID from PCI config space (0x2-0x3) 231 * pci_revision_id - RevisionID from PCI config space (0x8) 232 * ohci_version - 1394 OpenHCI Version Register (0x0) 233 * ohci_vendor_id - 1394 OpenHCI Vendor ID Register (0x40) 234 * ohci_vregset_cnt - Number of vendor specific register maps that have been 235 * mapped by the driver. The driver will only map in 236 * vendor specific registers for adapters it knows about. 237 */ 238 typedef struct hci1394_ioctl_hbainfo_s { 239 uint_t pci_vendor_id; 240 uint_t pci_device_id; 241 uint_t pci_revision_id; 242 uint32_t ohci_version; 243 uint32_t ohci_vendor_id; 244 uint_t ohci_vregset_cnt; 245 } hci1394_ioctl_hbainfo_t; 246 247 248 #ifdef __cplusplus 249 } 250 #endif 251 252 #endif /* _SYS_1394_ADAPTERS_HCI1394_IOCTL_H */ 253