1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _SYS_1394_ADAPTERS_HCI1394_IOCTL_H 28 #define _SYS_1394_ADAPTERS_HCI1394_IOCTL_H 29 30 /* 31 * hci1394_ioctl.h 32 * Test ioctl's to support test/debug of the 1394 HW. hci1394_ioctl_enum_t is 33 * passed in cmd and a pointer to the appropriate structure (i.e. 34 * hci1394_ioctl_wrreg_t) is passed in arg. 35 */ 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 42 /* 43 * write_reg - write OpenHCI register 44 * read_reg - read OpenHCI register 45 * write_vreg - write OpenHCI Vendor Specific register 46 * read_vreg - read OpenHCI Vendor Specific register 47 * reset_bus - reset the 1394 bus 48 * selfid_cnt - return the number of times we saw the selfid complete 49 * interrupt signifying a bus reset has completed. This does not 50 * have to match the bus generation and probably won't. 51 * busgen_cnt - return the current bus generation 52 * read_selfid - read selfid buffer 53 * write_phy - write PHY register 54 * read_phy - read PHY register 55 * hba_info - HBA vendor information 56 */ 57 #define HCI11394_IOCTL ('f' << 8) 58 typedef enum { 59 HCI1394_IOCTL_WRITE_REG = HCI11394_IOCTL | 0x00, 60 HCI1394_IOCTL_READ_REG = HCI11394_IOCTL | 0x01, 61 HCI1394_IOCTL_WRITE_VREG = HCI11394_IOCTL | 0x02, 62 HCI1394_IOCTL_READ_VREG = HCI11394_IOCTL | 0x03, 63 HCI1394_IOCTL_RESET_BUS = HCI11394_IOCTL | 0x04, 64 HCI1394_IOCTL_SELFID_CNT = HCI11394_IOCTL | 0x05, 65 HCI1394_IOCTL_BUSGEN_CNT = HCI11394_IOCTL | 0x06, 66 HCI1394_IOCTL_READ_SELFID = HCI11394_IOCTL | 0x07, 67 HCI1394_IOCTL_WRITE_PHY = HCI11394_IOCTL | 0x08, 68 HCI1394_IOCTL_READ_PHY = HCI11394_IOCTL | 0x09, 69 HCI1394_IOCTL_HBA_INFO = HCI11394_IOCTL | 0x0A 70 } hci1394_ioctl_enum_t; 71 72 73 /* 74 * HCI1394_IOCTL_WRITE_REG 75 * Write OHCI register. addr is an offset into the OpenHCI register map. 76 * (i.e. addr = 0 would write to the Version Register). addr must be 32-bit 77 * aligned (i.e. 0, 4, 8, C, 10). data is the 32-bit word to write into the 78 * OpenHCI register. 79 * 80 * NOTE: Writing OpenHCI registers can cause the hardware and/or SW to 81 * misbehave. Extreme care should be used when using this call. 82 */ 83 typedef struct hci1394_ioctl_wrreg_s { 84 uint_t addr; 85 uint32_t data; 86 } hci1394_ioctl_wrreg_t; 87 88 89 /* 90 * HCI1394_IOCTL_READ_REG 91 * Read OHCI register. addr is an offset into the OpenHCI register map. 92 * (i.e. addr = 0 would write to the Version Register). addr must be 32-bit 93 * aligned (i.e. 0, 4, 8, C, 10). When the ioctl returns successfully, data 94 * will contain the 32-bit word read from the OHCI register. 95 */ 96 typedef struct hci1394_ioctl_rdreg_s { 97 uint_t addr; 98 uint32_t data; 99 } hci1394_ioctl_rdreg_t; 100 101 102 /* 103 * HCI1394_IOCTL_WRITE_VREG 104 * Write Vendor Specific OHCI register. addr is an offset into the Vendor 105 * Specific OpenHCI register map. (i.e. addr = 0 would write to the first 106 * Vendor Specific register. addr must be 32-bit aligned (i.e. 0, 4, 8, C, 107 * 10). data is the 32-bit word to write into the Vendor Specific OpenHCI 108 * register. regset defines which vendor specific register set to write to. 109 * There will usually be one vendor specific register set so this will 110 * usually be set to 0. 111 * 112 * NOTE: Writing Vendor Specific OpenHCI registers can cause the hardware 113 * and/or SW to misbehave. Extreme care should be used when using this 114 * call. 115 */ 116 typedef struct hci1394_ioctl_wrvreg_s { 117 uint_t regset; 118 uint_t addr; 119 uint32_t data; 120 } hci1394_ioctl_wrvreg_t; 121 122 123 /* 124 * HCI1394_IOCTL_READ_VREG 125 * Read Vendor specific OHCI register. addr is an offset into the Vendor 126 * Specific OpenHCI register space. (i.e. addr = 0 is the first Vendor 127 * Specific register). addr must be 32-bit aligned (i.e. 0, 4, 8, C, 10). 128 * When the ioctl returns successfully, data will contain the 32-bit word 129 * read from the Vendor Specific OHCI register. regset defines which vendor 130 * specific register set to read from. There will usually be one vendor 131 * specific register set so this will usually be set to 0. 132 */ 133 typedef struct hci1394_ioctl_rdvreg_s { 134 uint_t regset; 135 uint_t addr; 136 uint32_t data; 137 } hci1394_ioctl_rdvreg_t; 138 139 140 /* HCI1394_IOCTL_RESET_BUS has no parameters */ 141 142 143 /* 144 * HCI1394_IOCTL_SELFID_CNT 145 * When the ioctl returns successfully, count will contain the number of 146 * times the nexus driver has seen and responded to a selfid_complete 147 * interrupt. This interrupt signifies that the bus reset has completed 148 * and the hardware based bus enumeration has completed. This number will 149 * most likely not be the same as the bus generation. Everytime this 150 * increments, the bus generation count should increment by at least one. 151 * 152 * NOTE: The current implementation of the nexus driver uses a uint_t for 153 * selfid_cnt. 154 */ 155 typedef struct hci1394_ioctl_selfid_cnt_s { 156 uint_t count; 157 } hci1394_ioctl_selfid_cnt_t; 158 159 160 /* 161 * HCI1394_IOCTL_BUSGEN_CNT 162 * When the ioctl returns successfully, count will contain the current 1394 163 * bus generation count. 164 * 165 * NOTE: The current implementation of the nexus driver uses the OpenHCI 166 * generation count which is an 8 bit value. Therefore, this count will 167 * wrap over at 0xFF. 168 */ 169 typedef struct hci1394_ioctl_busgen_cnt_s { 170 uint_t count; 171 } hci1394_ioctl_busgen_cnt_t; 172 173 174 /* 175 * HCI1394_IOCTL_READ_SELFID 176 * Copies the contents of the selfid buffer into a buffer pointed to by buf. 177 * Count is the number of 32-bit words to copy into buf. The maximum size 178 * of the selfid buffer is 1024 32-bit words. The very first word is the 179 * OpenHCI selfid header. 180 */ 181 typedef struct hci1394_ioctl_read_selfid_s { 182 uint32_t *buf; 183 uint_t count; 184 } hci1394_ioctl_read_selfid_t; 185 186 187 /* 188 * HCI1394_IOCTL_WRPHY 189 * Write PHY register. addr is an offset into the phy register space. 190 * (i.e. addr = 0 is the first phy register). addr is byte aligned 191 * (i.e. 0, 1, 2, 3, 4). data should contain the 8-bit value to write to the 192 * PHY register. The data should be stored as follows <0x000000dd> where dd 193 * is the byte written. 194 * 195 * NOTE: Phy register 0 cannot be read or written. 196 * 197 * NOTE: Writing PHY registers can cause the hardware and/or SW to misbehave. 198 * Extreme care should be used when using this call. 199 */ 200 typedef struct hci1394_ioctl_wrphy_s { 201 uint_t addr; 202 uint_t data; 203 } hci1394_ioctl_wrphy_t; 204 205 206 /* 207 * HCI1394_IOCTL_RDPHY 208 * Read PHY register. addr is an offset into the phy register space. 209 * (i.e. addr = 0 is the first phy register). addr is byte aligned 210 * (i.e. 0, 1, 2, 3, 4). When the ioctl returns successfully, data will 211 * contain the 8-bit data read from the PHY register. The data will be stored 212 * as follows <0x000000dd> where dd is the byte read. 213 * 214 * NOTE: Phy register 0 cannot be read or written. 215 */ 216 typedef struct hci1394_ioctl_rdphy_s { 217 uint_t addr; 218 uint_t data; 219 } hci1394_ioctl_rdphy_t; 220 221 222 /* 223 * HCI1394_IOCTL_HBA_INFO 224 * HBA Vendor Information 225 * 226 * Vendor Specific Info 227 * pci_vendor_id - VendorID from PCI config space (0x0-0x1) 228 * pci_device_id - DeviceID from PCI config space (0x2-0x3) 229 * pci_revision_id - RevisionID from PCI config space (0x8) 230 * ohci_version - 1394 OpenHCI Version Register (0x0) 231 * ohci_vendor_id - 1394 OpenHCI Vendor ID Register (0x40) 232 * ohci_vregset_cnt - Number of vendor specific register maps that have been 233 * mapped by the driver. The driver will only map in 234 * vendor specific registers for adapters it knows about. 235 */ 236 typedef struct hci1394_ioctl_hbainfo_s { 237 uint_t pci_vendor_id; 238 uint_t pci_device_id; 239 uint_t pci_revision_id; 240 uint32_t ohci_version; 241 uint32_t ohci_vendor_id; 242 uint_t ohci_vregset_cnt; 243 } hci1394_ioctl_hbainfo_t; 244 245 246 #ifdef __cplusplus 247 } 248 #endif 249 250 #endif /* _SYS_1394_ADAPTERS_HCI1394_IOCTL_H */ 251