1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/sunndi.h> 31 #include <sys/sysmacros.h> 32 #include <sys/pci.h> 33 #include <sys/pcie.h> 34 #include <sys/pci_impl.h> 35 #include <sys/epm.h> 36 37 int 38 pci_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 39 { 40 caddr_t cfgaddr; 41 ddi_device_acc_attr_t attr; 42 43 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 44 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 45 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 46 47 /* Check for fault management capabilities */ 48 if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(dip))) { 49 attr.devacc_attr_version = DDI_DEVICE_ATTR_V1; 50 attr.devacc_attr_access = DDI_FLAGERR_ACC; 51 } 52 53 return (ddi_regs_map_setup(dip, 0, &cfgaddr, 0, 0, &attr, handle)); 54 } 55 56 void 57 pci_config_teardown(ddi_acc_handle_t *handle) 58 { 59 ddi_regs_map_free(handle); 60 } 61 62 uint8_t 63 pci_config_get8(ddi_acc_handle_t handle, off_t offset) 64 { 65 caddr_t cfgaddr; 66 ddi_acc_hdl_t *hp; 67 68 hp = impl_acc_hdl_get(handle); 69 cfgaddr = hp->ah_addr + offset; 70 return (ddi_get8(handle, (uint8_t *)cfgaddr)); 71 } 72 73 uint16_t 74 pci_config_get16(ddi_acc_handle_t handle, off_t offset) 75 { 76 caddr_t cfgaddr; 77 ddi_acc_hdl_t *hp; 78 79 hp = impl_acc_hdl_get(handle); 80 cfgaddr = hp->ah_addr + offset; 81 return (ddi_get16(handle, (uint16_t *)cfgaddr)); 82 } 83 84 uint32_t 85 pci_config_get32(ddi_acc_handle_t handle, off_t offset) 86 { 87 caddr_t cfgaddr; 88 ddi_acc_hdl_t *hp; 89 90 hp = impl_acc_hdl_get(handle); 91 cfgaddr = hp->ah_addr + offset; 92 return (ddi_get32(handle, (uint32_t *)cfgaddr)); 93 } 94 95 uint64_t 96 pci_config_get64(ddi_acc_handle_t handle, off_t offset) 97 { 98 caddr_t cfgaddr; 99 ddi_acc_hdl_t *hp; 100 101 hp = impl_acc_hdl_get(handle); 102 cfgaddr = hp->ah_addr + offset; 103 return (ddi_get64(handle, (uint64_t *)cfgaddr)); 104 } 105 106 void 107 pci_config_put8(ddi_acc_handle_t handle, off_t offset, uint8_t value) 108 { 109 caddr_t cfgaddr; 110 ddi_acc_hdl_t *hp; 111 112 hp = impl_acc_hdl_get(handle); 113 cfgaddr = hp->ah_addr + offset; 114 ddi_put8(handle, (uint8_t *)cfgaddr, value); 115 } 116 117 void 118 pci_config_put16(ddi_acc_handle_t handle, off_t offset, uint16_t value) 119 { 120 caddr_t cfgaddr; 121 ddi_acc_hdl_t *hp; 122 123 hp = impl_acc_hdl_get(handle); 124 cfgaddr = hp->ah_addr + offset; 125 ddi_put16(handle, (uint16_t *)cfgaddr, value); 126 } 127 128 void 129 pci_config_put32(ddi_acc_handle_t handle, off_t offset, uint32_t value) 130 { 131 caddr_t cfgaddr; 132 ddi_acc_hdl_t *hp; 133 134 hp = impl_acc_hdl_get(handle); 135 cfgaddr = hp->ah_addr + offset; 136 ddi_put32(handle, (uint32_t *)cfgaddr, value); 137 } 138 139 void 140 pci_config_put64(ddi_acc_handle_t handle, off_t offset, uint64_t value) 141 { 142 caddr_t cfgaddr; 143 ddi_acc_hdl_t *hp; 144 145 hp = impl_acc_hdl_get(handle); 146 cfgaddr = hp->ah_addr + offset; 147 ddi_put64(handle, (uint64_t *)cfgaddr, value); 148 } 149 150 /* 151 * We need to separate the old interfaces from the new ones and leave them 152 * in here for a while. Previous versions of the OS defined the new interfaces 153 * to the old interfaces. This way we can fix things up so that we can 154 * eventually remove these interfaces. 155 * e.g. A 3rd party module/driver using pci_config_get8 and built against S10 156 * or earlier will actually have a reference to pci_config_getb in the binary. 157 */ 158 #ifdef _ILP32 159 uint8_t 160 pci_config_getb(ddi_acc_handle_t handle, off_t offset) 161 { 162 caddr_t cfgaddr; 163 ddi_acc_hdl_t *hp; 164 165 hp = impl_acc_hdl_get(handle); 166 cfgaddr = hp->ah_addr + offset; 167 return (ddi_get8(handle, (uint8_t *)cfgaddr)); 168 } 169 170 uint16_t 171 pci_config_getw(ddi_acc_handle_t handle, off_t offset) 172 { 173 caddr_t cfgaddr; 174 ddi_acc_hdl_t *hp; 175 176 hp = impl_acc_hdl_get(handle); 177 cfgaddr = hp->ah_addr + offset; 178 return (ddi_get16(handle, (uint16_t *)cfgaddr)); 179 } 180 181 uint32_t 182 pci_config_getl(ddi_acc_handle_t handle, off_t offset) 183 { 184 caddr_t cfgaddr; 185 ddi_acc_hdl_t *hp; 186 187 hp = impl_acc_hdl_get(handle); 188 cfgaddr = hp->ah_addr + offset; 189 return (ddi_get32(handle, (uint32_t *)cfgaddr)); 190 } 191 192 uint64_t 193 pci_config_getll(ddi_acc_handle_t handle, off_t offset) 194 { 195 caddr_t cfgaddr; 196 ddi_acc_hdl_t *hp; 197 198 hp = impl_acc_hdl_get(handle); 199 cfgaddr = hp->ah_addr + offset; 200 return (ddi_get64(handle, (uint64_t *)cfgaddr)); 201 } 202 203 void 204 pci_config_putb(ddi_acc_handle_t handle, off_t offset, uint8_t value) 205 { 206 caddr_t cfgaddr; 207 ddi_acc_hdl_t *hp; 208 209 hp = impl_acc_hdl_get(handle); 210 cfgaddr = hp->ah_addr + offset; 211 ddi_put8(handle, (uint8_t *)cfgaddr, value); 212 } 213 214 void 215 pci_config_putw(ddi_acc_handle_t handle, off_t offset, uint16_t value) 216 { 217 caddr_t cfgaddr; 218 ddi_acc_hdl_t *hp; 219 220 hp = impl_acc_hdl_get(handle); 221 cfgaddr = hp->ah_addr + offset; 222 ddi_put16(handle, (uint16_t *)cfgaddr, value); 223 } 224 225 void 226 pci_config_putl(ddi_acc_handle_t handle, off_t offset, uint32_t value) 227 { 228 caddr_t cfgaddr; 229 ddi_acc_hdl_t *hp; 230 231 hp = impl_acc_hdl_get(handle); 232 cfgaddr = hp->ah_addr + offset; 233 ddi_put32(handle, (uint32_t *)cfgaddr, value); 234 } 235 236 void 237 pci_config_putll(ddi_acc_handle_t handle, off_t offset, uint64_t value) 238 { 239 caddr_t cfgaddr; 240 ddi_acc_hdl_t *hp; 241 242 hp = impl_acc_hdl_get(handle); 243 cfgaddr = hp->ah_addr + offset; 244 ddi_put64(handle, (uint64_t *)cfgaddr, value); 245 } 246 #endif /* _ILP32 */ 247 248 /*ARGSUSED*/ 249 int 250 pci_report_pmcap(dev_info_t *dip, int cap, void *arg) 251 { 252 return (DDI_SUCCESS); 253 } 254 255 /* 256 * Note about saving and restoring config space. 257 * PCI devices have only upto 256 bytes of config space while PCI Express 258 * devices can have upto 4k config space. In case of PCI Express device, 259 * we save all 4k config space and restore it even if it doesn't make use 260 * of all 4k. But some devices don't respond to reads to non-existent 261 * registers within the config space. To avoid any panics, we use ddi_peek 262 * to do the reads. A bit mask is used to indicate which words of the 263 * config space are accessible. While restoring the config space, only those 264 * readable words are restored. We do all this in 32 bit size words. 265 */ 266 #define INDEX_SHIFT 3 267 #define BITMASK 0x7 268 269 static uint32_t pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 270 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp); 271 static void pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 272 pci_cap_save_desc_t *cap_descp, uint32_t elements); 273 static uint32_t pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 274 uint32_t *regbuf, uint32_t nwords); 275 static uint32_t pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 276 uint32_t *regbuf, uint32_t notused); 277 static uint32_t pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 278 uint32_t *regbuf, uint32_t notused); 279 static uint32_t pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 280 uint32_t *regbuf, uint32_t notused); 281 static void pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 282 uint32_t *regbuf, uint32_t nwords); 283 static uint32_t cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf, 284 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace); 285 static void pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf, 286 uint16_t pmcap_offset); 287 288 /* 289 * Table below specifies the number of registers to be saved for each PCI 290 * capability. pci_generic_save saves the number of words specified in the 291 * table. Any special considerations will be taken care by the capability 292 * specific save function e.g. use pci_msi_save to save registers associated 293 * with MSI capability. PCI_UNKNOWN_SIZE indicates that number of registers 294 * to be saved is variable and will be determined by the specific save function. 295 * Currently we save/restore all the registers associated with the capability 296 * including read only registers. Regsiters are saved and restored in 32 bit 297 * size words. 298 */ 299 static pci_cap_entry_t pci_cap_table[] = { 300 {PCI_CAP_ID_PM, PCI_PMCAP_NDWORDS, pci_generic_save}, 301 {PCI_CAP_ID_AGP, PCI_AGP_NDWORDS, pci_generic_save}, 302 {PCI_CAP_ID_SLOT_ID, PCI_SLOTID_NDWORDS, pci_generic_save}, 303 {PCI_CAP_ID_MSI_X, PCI_MSIX_NDWORDS, pci_generic_save}, 304 {PCI_CAP_ID_MSI, PCI_CAP_SZUNKNOWN, pci_msi_save}, 305 {PCI_CAP_ID_PCIX, PCI_CAP_SZUNKNOWN, pci_pcix_save}, 306 {PCI_CAP_ID_PCI_E, PCI_CAP_SZUNKNOWN, pci_pcie_save}, 307 /* 308 * {PCI_CAP_ID_cPCI_CRC, 0, NULL}, 309 * {PCI_CAP_ID_VPD, 0, NULL}, 310 * {PCI_CAP_ID_cPCI_HS, 0, NULL}, 311 * {PCI_CAP_ID_PCI_HOTPLUG, 0, NULL}, 312 * {PCI_CAP_ID_AGP_8X, 0, NULL}, 313 * {PCI_CAP_ID_SECURE_DEV, 0, NULL}, 314 */ 315 {PCI_CAP_NEXT_PTR_NULL, 0, NULL} 316 }; 317 318 /* 319 * Save the configuration registers for cdip as a property 320 * so that it persists after detach/uninitchild. 321 */ 322 int 323 pci_save_config_regs(dev_info_t *dip) 324 { 325 peekpoke_ctlops_t cautacc_ctlops_arg; 326 ddi_acc_handle_t confhdl; 327 pci_config_header_state_t *chsp; 328 pci_cap_save_desc_t *pci_cap_descp; 329 int ret; 330 uint32_t i, ncaps, nwords; 331 uint32_t *regbuf, *p; 332 uint8_t *maskbuf; 333 size_t maskbufsz, regbufsz, capbufsz; 334 ddi_acc_hdl_t *hp; 335 off_t offset = 0; 336 uint8_t cap_ptr, cap_id; 337 int pcie = 0; 338 uint16_t status; 339 340 PMD(PMD_SX, ("pci_save_config_regs %s:%d\n", ddi_driver_name(dip), 341 ddi_get_instance(dip))) 342 343 if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) { 344 cmn_err(CE_WARN, "%s%d can't get config handle", 345 ddi_driver_name(dip), ddi_get_instance(dip)); 346 347 return (DDI_FAILURE); 348 } 349 350 /* 351 * Determine if it implements capabilities 352 */ 353 status = pci_config_get16(confhdl, PCI_CONF_STAT); 354 if (!(status & 0x10)) { 355 goto no_cap; 356 } 357 /* 358 * Determine if it is a pci express device. If it is, save entire 359 * 4k config space treating it as a array of 32 bit integers. 360 * If it is not, do it in a usual PCI way. 361 */ 362 cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR); 363 /* 364 * Walk the capabilities searching for pci express capability 365 */ 366 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 367 cap_id = pci_config_get8(confhdl, 368 cap_ptr + PCI_CAP_ID); 369 if (cap_id == PCI_CAP_ID_PCI_E) { 370 pcie = 1; 371 break; 372 } 373 cap_ptr = pci_config_get8(confhdl, 374 cap_ptr + PCI_CAP_NEXT_PTR); 375 } 376 no_cap: 377 if (pcie) { 378 /* PCI express device. Can have data in all 4k space */ 379 regbuf = (uint32_t *)kmem_zalloc((size_t)PCIE_CONF_HDR_SIZE, 380 KM_SLEEP); 381 p = regbuf; 382 /* 383 * Allocate space for mask. 384 * mask size is 128 bytes (4096 / 4 / 8 ) 385 */ 386 maskbufsz = (size_t)((PCIE_CONF_HDR_SIZE/ sizeof (uint32_t)) >> 387 INDEX_SHIFT); 388 maskbuf = (uint8_t *)kmem_zalloc(maskbufsz, KM_SLEEP); 389 hp = impl_acc_hdl_get(confhdl); 390 cautacc_ctlops_arg.size = sizeof (uint32_t); 391 cautacc_ctlops_arg.handle = confhdl; 392 cautacc_ctlops_arg.repcount = 1; 393 cautacc_ctlops_arg.flags = 0; 394 for (i = 0; i < (PCIE_CONF_HDR_SIZE / sizeof (uint32_t)); i++) { 395 cautacc_ctlops_arg.dev_addr = (uintptr_t)(hp->ah_addr + 396 offset); 397 cautacc_ctlops_arg.host_addr = (uintptr_t)p; 398 ret = ddi_ctlops(dip, dip, DDI_CTLOPS_PEEK, 399 &cautacc_ctlops_arg, NULL); 400 if (ret == DDI_SUCCESS) { 401 /* it is readable register. set the bit */ 402 maskbuf[i >> INDEX_SHIFT] |= 403 (uint8_t)(1 << (i & BITMASK)); 404 } 405 p++; 406 offset += sizeof (uint32_t); 407 } 408 409 if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 410 SAVED_CONFIG_REGS_MASK, (uchar_t *)maskbuf, 411 maskbufsz)) != DDI_PROP_SUCCESS) { 412 cmn_err(CE_WARN, "couldn't create %s property while" 413 "saving config space for %s@%d\n", 414 SAVED_CONFIG_REGS_MASK, ddi_driver_name(dip), 415 ddi_get_instance(dip)); 416 } else if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, 417 dip, SAVED_CONFIG_REGS, (uchar_t *)regbuf, 418 (size_t)PCIE_CONF_HDR_SIZE)) != DDI_PROP_SUCCESS) { 419 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 420 SAVED_CONFIG_REGS_MASK); 421 cmn_err(CE_WARN, "%s%d can't update prop %s", 422 ddi_driver_name(dip), ddi_get_instance(dip), 423 SAVED_CONFIG_REGS); 424 } 425 426 kmem_free(maskbuf, (size_t)maskbufsz); 427 kmem_free(regbuf, (size_t)PCIE_CONF_HDR_SIZE); 428 } else { 429 regbuf = (uint32_t *)kmem_zalloc((size_t)PCI_CONF_HDR_SIZE, 430 KM_SLEEP); 431 chsp = (pci_config_header_state_t *)regbuf; 432 433 chsp->chs_command = pci_config_get16(confhdl, PCI_CONF_COMM); 434 chsp->chs_header_type = pci_config_get8(confhdl, 435 PCI_CONF_HEADER); 436 if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) == 437 PCI_HEADER_ONE) 438 chsp->chs_bridge_control = 439 pci_config_get16(confhdl, PCI_BCNF_BCNTRL); 440 chsp->chs_cache_line_size = pci_config_get8(confhdl, 441 PCI_CONF_CACHE_LINESZ); 442 chsp->chs_latency_timer = pci_config_get8(confhdl, 443 PCI_CONF_LATENCY_TIMER); 444 if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) == 445 PCI_HEADER_ONE) { 446 chsp->chs_sec_latency_timer = 447 pci_config_get8(confhdl, PCI_BCNF_LATENCY_TIMER); 448 } 449 450 chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0); 451 chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1); 452 chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2); 453 chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3); 454 chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4); 455 chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5); 456 457 /* 458 * Allocate maximum space required for capability descriptions. 459 * The maximum number of capabilties saved is the number of 460 * capabilities listed in the pci_cap_table. 461 */ 462 ncaps = (sizeof (pci_cap_table) / sizeof (pci_cap_entry_t)); 463 capbufsz = ncaps * sizeof (pci_cap_save_desc_t); 464 pci_cap_descp = (pci_cap_save_desc_t *)kmem_zalloc( 465 capbufsz, KM_SLEEP); 466 p = (uint32_t *)((caddr_t)regbuf + 467 sizeof (pci_config_header_state_t)); 468 nwords = pci_save_caps(confhdl, p, pci_cap_descp, &ncaps); 469 regbufsz = sizeof (pci_config_header_state_t) + 470 nwords * sizeof (uint32_t); 471 472 if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 473 SAVED_CONFIG_REGS, (uchar_t *)regbuf, regbufsz)) != 474 DDI_PROP_SUCCESS) { 475 cmn_err(CE_WARN, "%s%d can't update prop %s", 476 ddi_driver_name(dip), ddi_get_instance(dip), 477 SAVED_CONFIG_REGS); 478 } else if (ncaps) { 479 ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 480 SAVED_CONFIG_REGS_CAPINFO, (uchar_t *)pci_cap_descp, 481 ncaps * sizeof (pci_cap_save_desc_t)); 482 if (ret != DDI_PROP_SUCCESS) 483 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 484 SAVED_CONFIG_REGS); 485 } 486 kmem_free(regbuf, (size_t)PCI_CONF_HDR_SIZE); 487 kmem_free(pci_cap_descp, capbufsz); 488 } 489 pci_config_teardown(&confhdl); 490 491 if (ret != DDI_PROP_SUCCESS) 492 return (DDI_FAILURE); 493 494 return (DDI_SUCCESS); 495 } 496 497 /* 498 * Saves registers associated with PCI capabilities. 499 * Returns number of 32 bit words saved. 500 * Number of capabilities saved is returned in ncapsp. 501 */ 502 static uint32_t 503 pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 504 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp) 505 { 506 return (cap_walk_and_save(confhdl, regbuf, cap_descp, ncapsp, 0)); 507 } 508 509 static uint32_t 510 cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf, 511 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace) 512 { 513 pci_cap_entry_t *pci_cap_entp; 514 uint16_t cap_id, offset, status; 515 uint32_t words_saved = 0, nwords = 0; 516 uint16_t cap_ptr = PCI_CAP_NEXT_PTR_NULL; 517 518 *ncapsp = 0; 519 520 /* 521 * Determine if it implements capabilities 522 */ 523 status = pci_config_get16(confhdl, PCI_CONF_STAT); 524 if (!(status & 0x10)) { 525 return (words_saved); 526 } 527 528 if (!xspace) 529 cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR); 530 /* 531 * Walk the capabilities 532 */ 533 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 534 cap_id = CAP_ID(confhdl, cap_ptr, xspace); 535 /* Search for this cap id in our table */ 536 if (!xspace) 537 pci_cap_entp = pci_cap_table; 538 while (pci_cap_entp->cap_id != PCI_CAP_NEXT_PTR_NULL && 539 pci_cap_entp->cap_id != cap_id) 540 pci_cap_entp++; 541 542 offset = cap_ptr; 543 cap_ptr = NEXT_CAP(confhdl, cap_ptr, xspace); 544 /* 545 * If this cap id is not found in the table, there is nothing 546 * to save. 547 */ 548 if (pci_cap_entp->cap_id == PCI_CAP_NEXT_PTR_NULL) 549 continue; 550 if (pci_cap_entp->cap_save_func) { 551 if ((nwords = pci_cap_entp->cap_save_func(confhdl, 552 offset, regbuf, pci_cap_entp->cap_ndwords))) { 553 cap_descp->cap_nregs = nwords; 554 cap_descp->cap_offset = offset; 555 cap_descp->cap_id = cap_id; 556 regbuf += nwords; 557 cap_descp++; 558 words_saved += nwords; 559 (*ncapsp)++; 560 } 561 } 562 563 } 564 return (words_saved); 565 } 566 567 static void 568 pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 569 uint32_t *regbuf, uint32_t nwords) 570 { 571 int i; 572 573 for (i = 0; i < nwords; i++) { 574 *regbuf = pci_config_get32(confhdl, cap_ptr); 575 regbuf++; 576 cap_ptr += 4; 577 } 578 } 579 580 static uint32_t 581 pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 582 uint32_t nwords) 583 { 584 pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 585 return (nwords); 586 } 587 588 /*ARGSUSED*/ 589 static uint32_t 590 pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 591 uint32_t notused) 592 { 593 uint32_t nwords = PCI_MSI_MIN_WORDS; 594 uint16_t msi_ctrl; 595 596 /* Figure out how many registers to be saved */ 597 msi_ctrl = pci_config_get16(confhdl, cap_ptr + PCI_MSI_CTRL); 598 /* If 64 bit address capable add one word */ 599 if (msi_ctrl & PCI_MSI_64BIT_MASK) 600 nwords++; 601 /* If per vector masking capable, add two more words */ 602 if (msi_ctrl & PCI_MSI_PVM_MASK) 603 nwords += 2; 604 pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 605 606 return (nwords); 607 } 608 609 /*ARGSUSED*/ 610 static uint32_t 611 pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 612 uint32_t notused) 613 { 614 uint32_t nwords = PCI_PCIX_MIN_WORDS; 615 uint16_t pcix_command; 616 617 /* Figure out how many registers to be saved */ 618 pcix_command = pci_config_get16(confhdl, cap_ptr + PCI_PCIX_COMMAND); 619 /* If it is version 1 or version 2, add 4 words */ 620 if (((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_1) || 621 ((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_2)) 622 nwords += 4; 623 pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 624 625 return (nwords); 626 } 627 628 /*ARGSUSED*/ 629 static uint32_t 630 pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 631 uint32_t notused) 632 { 633 return (0); 634 } 635 636 static void 637 pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf, 638 uint16_t pmcap_offset) 639 { 640 uint16_t pmcsr; 641 uint16_t pmcsr_offset = pmcap_offset + PCI_PMCSR; 642 uint32_t *saved_pmcsrp = (uint32_t *)((caddr_t)regbuf + PCI_PMCSR); 643 644 /* 645 * Copy the power state bits from the PMCSR to our saved copy. 646 * This is to make sure that we don't change the D state when 647 * we restore config space of the device. 648 */ 649 pmcsr = pci_config_get16(confhdl, pmcsr_offset); 650 (*saved_pmcsrp) &= ~PCI_PMCSR_STATE_MASK; 651 (*saved_pmcsrp) |= (pmcsr & PCI_PMCSR_STATE_MASK); 652 } 653 654 static void 655 pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 656 pci_cap_save_desc_t *cap_descp, uint32_t elements) 657 { 658 int i, j; 659 uint16_t offset; 660 661 for (i = 0; i < (elements / sizeof (pci_cap_save_desc_t)); i++) { 662 offset = cap_descp->cap_offset; 663 if (cap_descp->cap_id == PCI_CAP_ID_PM) 664 pci_pmcap_check(confhdl, regbuf, offset); 665 for (j = 0; j < cap_descp->cap_nregs; j++) { 666 pci_config_put32(confhdl, offset, *regbuf); 667 regbuf++; 668 offset += 4; 669 } 670 cap_descp++; 671 } 672 } 673 674 /* 675 * Restore config_regs from a single devinfo node. 676 */ 677 int 678 pci_restore_config_regs(dev_info_t *dip) 679 { 680 ddi_acc_handle_t confhdl; 681 pci_config_header_state_t *chs_p; 682 pci_cap_save_desc_t *cap_descp; 683 uint32_t elements, i; 684 uint8_t *maskbuf; 685 uint32_t *regbuf, *p; 686 off_t offset = 0; 687 688 if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) { 689 cmn_err(CE_WARN, "%s%d can't get config handle", 690 ddi_driver_name(dip), ddi_get_instance(dip)); 691 return (DDI_FAILURE); 692 } 693 694 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 695 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS_MASK, 696 (uchar_t **)&maskbuf, &elements) == DDI_PROP_SUCCESS) { 697 698 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 699 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS, 700 (uchar_t **)®buf, &elements) != DDI_PROP_SUCCESS) { 701 goto restoreconfig_err; 702 } 703 ASSERT(elements == PCIE_CONF_HDR_SIZE); 704 /* pcie device and has 4k config space saved */ 705 p = regbuf; 706 for (i = 0; i < PCIE_CONF_HDR_SIZE / sizeof (uint32_t); i++) { 707 /* If the word is readable then restore it */ 708 if (maskbuf[i >> INDEX_SHIFT] & 709 (uint8_t)(1 << (i & BITMASK))) 710 pci_config_put32(confhdl, offset, *p); 711 p++; 712 offset += sizeof (uint32_t); 713 } 714 ddi_prop_free(regbuf); 715 ddi_prop_free(maskbuf); 716 if (ndi_prop_remove(DDI_DEV_T_NONE, dip, 717 SAVED_CONFIG_REGS_MASK) != DDI_PROP_SUCCESS) { 718 cmn_err(CE_WARN, "%s%d can't remove prop %s", 719 ddi_driver_name(dip), ddi_get_instance(dip), 720 SAVED_CONFIG_REGS_MASK); 721 } 722 } else { 723 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 724 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS, 725 (uchar_t **)®buf, &elements) != DDI_PROP_SUCCESS) { 726 727 pci_config_teardown(&confhdl); 728 return (DDI_SUCCESS); 729 } 730 731 chs_p = (pci_config_header_state_t *)regbuf; 732 pci_config_put16(confhdl, PCI_CONF_COMM, 733 chs_p->chs_command); 734 if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) == 735 PCI_HEADER_ONE) { 736 pci_config_put16(confhdl, PCI_BCNF_BCNTRL, 737 chs_p->chs_bridge_control); 738 } 739 pci_config_put8(confhdl, PCI_CONF_CACHE_LINESZ, 740 chs_p->chs_cache_line_size); 741 pci_config_put8(confhdl, PCI_CONF_LATENCY_TIMER, 742 chs_p->chs_latency_timer); 743 if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) == 744 PCI_HEADER_ONE) 745 pci_config_put8(confhdl, PCI_BCNF_LATENCY_TIMER, 746 chs_p->chs_sec_latency_timer); 747 748 pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0); 749 pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1); 750 pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2); 751 pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3); 752 pci_config_put32(confhdl, PCI_CONF_BASE4, chs_p->chs_base4); 753 pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5); 754 755 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 756 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 757 SAVED_CONFIG_REGS_CAPINFO, 758 (uchar_t **)&cap_descp, &elements) == DDI_PROP_SUCCESS) { 759 /* 760 * PCI capability related regsiters are saved. 761 * Restore them based on the description. 762 */ 763 p = (uint32_t *)((caddr_t)regbuf + 764 sizeof (pci_config_header_state_t)); 765 pci_restore_caps(confhdl, p, cap_descp, elements); 766 ddi_prop_free(cap_descp); 767 } 768 769 ddi_prop_free(regbuf); 770 } 771 772 /* 773 * Make sure registers are flushed 774 */ 775 (void) pci_config_get32(confhdl, PCI_CONF_BASE5); 776 777 778 if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS) != 779 DDI_PROP_SUCCESS) { 780 cmn_err(CE_WARN, "%s%d can't remove prop %s", 781 ddi_driver_name(dip), ddi_get_instance(dip), 782 SAVED_CONFIG_REGS); 783 } 784 785 pci_config_teardown(&confhdl); 786 787 return (DDI_SUCCESS); 788 789 restoreconfig_err: 790 ddi_prop_free(maskbuf); 791 if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS_MASK) != 792 DDI_PROP_SUCCESS) { 793 cmn_err(CE_WARN, "%s%d can't remove prop %s", 794 ddi_driver_name(dip), ddi_get_instance(dip), 795 SAVED_CONFIG_REGS_MASK); 796 } 797 pci_config_teardown(&confhdl); 798 return (DDI_FAILURE); 799 } 800 801 /*ARGSUSED*/ 802 static int 803 pci_lookup_pmcap(dev_info_t *dip, ddi_acc_handle_t conf_hdl, 804 uint16_t *pmcap_offsetp) 805 { 806 uint8_t cap_ptr; 807 uint8_t cap_id; 808 uint8_t header_type; 809 uint16_t status; 810 811 header_type = pci_config_get8(conf_hdl, PCI_CONF_HEADER); 812 header_type &= PCI_HEADER_TYPE_M; 813 814 /* we don't deal with bridges, etc here */ 815 if (header_type != PCI_HEADER_ZERO) { 816 return (DDI_FAILURE); 817 } 818 819 status = pci_config_get16(conf_hdl, PCI_CONF_STAT); 820 if ((status & PCI_STAT_CAP) == 0) { 821 return (DDI_FAILURE); 822 } 823 824 cap_ptr = pci_config_get8(conf_hdl, PCI_CONF_CAP_PTR); 825 826 /* 827 * Walk the capabilities searching for a PM entry. 828 */ 829 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 830 cap_id = pci_config_get8(conf_hdl, cap_ptr + PCI_CAP_ID); 831 if (cap_id == PCI_CAP_ID_PM) { 832 break; 833 } 834 cap_ptr = pci_config_get8(conf_hdl, 835 cap_ptr + PCI_CAP_NEXT_PTR); 836 } 837 838 if (cap_ptr == PCI_CAP_NEXT_PTR_NULL) { 839 return (DDI_FAILURE); 840 } 841 *pmcap_offsetp = cap_ptr; 842 return (DDI_SUCCESS); 843 } 844 845 /* 846 * Do common pci-specific suspend actions: 847 * - enable wakeup if appropriate for the device 848 * - put device in lowest D-state that supports wakeup, or D3 if none 849 * - turn off bus mastering in control register 850 * For lack of per-dip storage (parent private date is pretty busy) 851 * we use properties to store the necessary context 852 * To avoid grotting through pci config space on every suspend, 853 * we leave the prop in existence after resume, cause we know that 854 * the detach framework code will dispose of it for us. 855 */ 856 857 typedef struct pci_pm_context { 858 int ppc_flags; 859 uint16_t ppc_cap_offset; /* offset in config space to pm cap */ 860 uint16_t ppc_pmcsr; /* need this too */ 861 uint16_t ppc_suspend_level; 862 } pci_pm_context_t; 863 864 #define SAVED_PM_CONTEXT "pci-pm-context" 865 866 /* values for ppc_flags */ 867 #define PPCF_NOPMCAP 1 868 869 /* 870 * Handle pci-specific suspend processing 871 * PM CSR and PCI CMD are saved by pci_save_config_regs(). 872 * If device can wake up system via PME, enable it to do so 873 * Set device power level to lowest that can generate PME, or D3 if none can 874 * Turn off bus master enable in pci command register 875 */ 876 #if defined(__x86) 877 extern int acpi_ddi_setwake(dev_info_t *dip, int level); 878 #endif 879 880 int 881 pci_post_suspend(dev_info_t *dip) 882 { 883 pci_pm_context_t *p; 884 uint16_t pmcap, pmcsr, pcicmd; 885 uint_t length; 886 int ret; 887 int fromprop = 1; /* source of memory *p */ 888 ddi_acc_handle_t hdl; 889 890 PMD(PMD_SX, ("pci_post_suspend %s:%d\n", 891 ddi_driver_name(dip), ddi_get_instance(dip))) 892 893 if (pci_save_config_regs(dip) != DDI_SUCCESS) { 894 return (DDI_FAILURE); 895 } 896 897 if (pci_config_setup(dip, &hdl) != DDI_SUCCESS) { 898 return (DDI_FAILURE); 899 } 900 901 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 902 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 903 SAVED_PM_CONTEXT, (uchar_t **)&p, &length) != DDI_PROP_SUCCESS) { 904 p = (pci_pm_context_t *)kmem_zalloc(sizeof (*p), KM_SLEEP); 905 fromprop = 0; 906 if (pci_lookup_pmcap(dip, hdl, 907 &p->ppc_cap_offset) != DDI_SUCCESS) { 908 p->ppc_flags |= PPCF_NOPMCAP; 909 ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 910 SAVED_PM_CONTEXT, (uchar_t *)p, 911 sizeof (pci_pm_context_t)); 912 if (ret != DDI_PROP_SUCCESS) { 913 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 914 SAVED_PM_CONTEXT); 915 ret = DDI_FAILURE; 916 } else { 917 ret = DDI_SUCCESS; 918 } 919 kmem_free(p, sizeof (*p)); 920 pci_config_teardown(&hdl); 921 return (DDI_SUCCESS); 922 } 923 /* 924 * Upon suspend, set the power level to the lowest that can 925 * wake the system. If none can, then set to lowest. 926 * XXX later we will need to check policy to see if this 927 * XXX device has had wakeup disabled 928 */ 929 pmcap = pci_config_get16(hdl, p->ppc_cap_offset + PCI_PMCAP); 930 if ((pmcap & PCI_PMCAP_D3COLD_PME) != 0) 931 p->ppc_suspend_level = 932 (PCI_PMCSR_PME_EN | PCI_PMCSR_D3HOT); 933 else if ((pmcap & (PCI_PMCAP_D3HOT_PME | PCI_PMCAP_D2_PME)) != 934 0) 935 p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D2; 936 else if ((pmcap & PCI_PMCAP_D1_PME) != 0) 937 p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D1; 938 else if ((pmcap & PCI_PMCAP_D0_PME) != 0) 939 p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D0; 940 else 941 p->ppc_suspend_level = PCI_PMCSR_D3HOT; 942 943 /* 944 * we defer updating the property to catch the saved 945 * register values as well 946 */ 947 } 948 /* If we set this in kmem_zalloc'd memory, we already returned above */ 949 if ((p->ppc_flags & PPCF_NOPMCAP) != 0) { 950 ddi_prop_free(p); 951 pci_config_teardown(&hdl); 952 return (DDI_SUCCESS); 953 } 954 955 956 /* 957 * Turn off (Bus) Master Enable, since acpica will be turning off 958 * bus master aribitration 959 */ 960 pcicmd = pci_config_get16(hdl, PCI_CONF_COMM); 961 pcicmd &= ~PCI_COMM_ME; 962 pci_config_put16(hdl, PCI_CONF_COMM, pcicmd); 963 964 /* 965 * set pm csr 966 */ 967 pmcsr = pci_config_get16(hdl, p->ppc_cap_offset + PCI_PMCSR); 968 p->ppc_pmcsr = pmcsr; 969 pmcsr &= (PCI_PMCSR_STATE_MASK); 970 pmcsr |= (PCI_PMCSR_PME_STAT | p->ppc_suspend_level); 971 pci_config_put16(hdl, p->ppc_cap_offset + PCI_PMCSR, pmcsr); 972 973 #if defined(__x86) 974 /* 975 * Arrange for platform wakeup enabling 976 */ 977 if ((p->ppc_suspend_level & PCI_PMCSR_PME_EN) != 0) { 978 int retval; 979 980 retval = acpi_ddi_setwake(dip, 3); /* XXX 3 for now */ 981 if (retval) { 982 PMD(PMD_SX, ("pci_post_suspend, setwake %s@%s rets " 983 "%x\n", PM_NAME(dip), PM_ADDR(dip), retval)); 984 } 985 } 986 #endif 987 988 /* 989 * Push out saved register values 990 */ 991 ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, SAVED_PM_CONTEXT, 992 (uchar_t *)p, sizeof (pci_pm_context_t)); 993 if (ret == DDI_PROP_SUCCESS) { 994 if (fromprop) 995 ddi_prop_free(p); 996 else 997 kmem_free(p, sizeof (*p)); 998 pci_config_teardown(&hdl); 999 return (DDI_SUCCESS); 1000 } 1001 /* Failed; put things back the way we found them */ 1002 (void) pci_restore_config_regs(dip); 1003 if (fromprop) 1004 ddi_prop_free(p); 1005 else 1006 kmem_free(p, sizeof (*p)); 1007 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_PM_CONTEXT); 1008 pci_config_teardown(&hdl); 1009 return (DDI_FAILURE); 1010 } 1011 1012 /* 1013 * The inverse of pci_post_suspend; handle pci-specific resume processing 1014 * First, turn device back on, then restore config space. 1015 */ 1016 1017 int 1018 pci_pre_resume(dev_info_t *dip) 1019 { 1020 ddi_acc_handle_t hdl; 1021 pci_pm_context_t *p; 1022 /* E_FUNC_SET_NOT_USED */ 1023 uint16_t pmcap, pmcsr; 1024 int flags; 1025 uint_t length; 1026 clock_t drv_usectohz(clock_t microsecs); 1027 #if defined(__x86) 1028 uint16_t suspend_level; 1029 #endif 1030 1031 PMD(PMD_SX, ("pci_pre_resume %s:%d\n", ddi_driver_name(dip), 1032 ddi_get_instance(dip))) 1033 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 1034 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 1035 SAVED_PM_CONTEXT, (uchar_t **)&p, &length) != DDI_PROP_SUCCESS) { 1036 return (DDI_FAILURE); 1037 } 1038 flags = p->ppc_flags; 1039 pmcap = p->ppc_cap_offset; 1040 pmcsr = p->ppc_pmcsr; 1041 #if defined(__x86) 1042 suspend_level = p->ppc_suspend_level; 1043 #endif 1044 ddi_prop_free(p); 1045 if ((flags & PPCF_NOPMCAP) != 0) 1046 goto done; 1047 #if defined(__x86) 1048 /* 1049 * Turn platform wake enable back off 1050 */ 1051 if ((suspend_level & PCI_PMCSR_PME_EN) != 0) { 1052 int retval; 1053 1054 retval = acpi_ddi_setwake(dip, 0); /* 0 for now */ 1055 if (retval) { 1056 PMD(PMD_SX, ("pci_pre_resume, setwake %s@%s rets " 1057 "%x\n", PM_NAME(dip), PM_ADDR(dip), retval)); 1058 } 1059 } 1060 #endif 1061 if (pci_config_setup(dip, &hdl) != DDI_SUCCESS) { 1062 return (DDI_FAILURE); 1063 } 1064 pci_config_put16(hdl, pmcap + PCI_PMCSR, pmcsr); 1065 delay(drv_usectohz(10000)); /* PCI PM spec D3->D0 (10ms) */ 1066 pci_config_teardown(&hdl); 1067 done: 1068 (void) pci_restore_config_regs(dip); /* fudges D-state! */ 1069 return (DDI_SUCCESS); 1070 } 1071