1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/sunndi.h> 31 #include <sys/sysmacros.h> 32 #include <sys/pci.h> 33 #include <sys/pcie.h> 34 #include <sys/pci_impl.h> 35 #include <sys/epm.h> 36 37 int 38 pci_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 39 { 40 caddr_t cfgaddr; 41 ddi_device_acc_attr_t attr; 42 43 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 44 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 45 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 46 47 /* Check for fault management capabilities */ 48 if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(dip))) { 49 attr.devacc_attr_version = DDI_DEVICE_ATTR_V1; 50 attr.devacc_attr_access = DDI_FLAGERR_ACC; 51 } 52 53 return (ddi_regs_map_setup(dip, 0, &cfgaddr, 0, 0, &attr, handle)); 54 } 55 56 void 57 pci_config_teardown(ddi_acc_handle_t *handle) 58 { 59 ddi_regs_map_free(handle); 60 } 61 62 uint8_t 63 pci_config_get8(ddi_acc_handle_t handle, off_t offset) 64 { 65 caddr_t cfgaddr; 66 ddi_acc_hdl_t *hp; 67 68 hp = impl_acc_hdl_get(handle); 69 cfgaddr = hp->ah_addr + offset; 70 return (ddi_get8(handle, (uint8_t *)cfgaddr)); 71 } 72 73 uint16_t 74 pci_config_get16(ddi_acc_handle_t handle, off_t offset) 75 { 76 caddr_t cfgaddr; 77 ddi_acc_hdl_t *hp; 78 79 hp = impl_acc_hdl_get(handle); 80 cfgaddr = hp->ah_addr + offset; 81 return (ddi_get16(handle, (uint16_t *)cfgaddr)); 82 } 83 84 uint32_t 85 pci_config_get32(ddi_acc_handle_t handle, off_t offset) 86 { 87 caddr_t cfgaddr; 88 ddi_acc_hdl_t *hp; 89 90 hp = impl_acc_hdl_get(handle); 91 cfgaddr = hp->ah_addr + offset; 92 return (ddi_get32(handle, (uint32_t *)cfgaddr)); 93 } 94 95 uint64_t 96 pci_config_get64(ddi_acc_handle_t handle, off_t offset) 97 { 98 caddr_t cfgaddr; 99 ddi_acc_hdl_t *hp; 100 101 hp = impl_acc_hdl_get(handle); 102 cfgaddr = hp->ah_addr + offset; 103 return (ddi_get64(handle, (uint64_t *)cfgaddr)); 104 } 105 106 void 107 pci_config_put8(ddi_acc_handle_t handle, off_t offset, uint8_t value) 108 { 109 caddr_t cfgaddr; 110 ddi_acc_hdl_t *hp; 111 112 hp = impl_acc_hdl_get(handle); 113 cfgaddr = hp->ah_addr + offset; 114 ddi_put8(handle, (uint8_t *)cfgaddr, value); 115 } 116 117 void 118 pci_config_put16(ddi_acc_handle_t handle, off_t offset, uint16_t value) 119 { 120 caddr_t cfgaddr; 121 ddi_acc_hdl_t *hp; 122 123 hp = impl_acc_hdl_get(handle); 124 cfgaddr = hp->ah_addr + offset; 125 ddi_put16(handle, (uint16_t *)cfgaddr, value); 126 } 127 128 void 129 pci_config_put32(ddi_acc_handle_t handle, off_t offset, uint32_t value) 130 { 131 caddr_t cfgaddr; 132 ddi_acc_hdl_t *hp; 133 134 hp = impl_acc_hdl_get(handle); 135 cfgaddr = hp->ah_addr + offset; 136 ddi_put32(handle, (uint32_t *)cfgaddr, value); 137 } 138 139 void 140 pci_config_put64(ddi_acc_handle_t handle, off_t offset, uint64_t value) 141 { 142 caddr_t cfgaddr; 143 ddi_acc_hdl_t *hp; 144 145 hp = impl_acc_hdl_get(handle); 146 cfgaddr = hp->ah_addr + offset; 147 ddi_put64(handle, (uint64_t *)cfgaddr, value); 148 } 149 150 /* 151 * We need to separate the old interfaces from the new ones and leave them 152 * in here for a while. Previous versions of the OS defined the new interfaces 153 * to the old interfaces. This way we can fix things up so that we can 154 * eventually remove these interfaces. 155 * e.g. A 3rd party module/driver using pci_config_get8 and built against S10 156 * or earlier will actually have a reference to pci_config_getb in the binary. 157 */ 158 #ifdef _ILP32 159 uint8_t 160 pci_config_getb(ddi_acc_handle_t handle, off_t offset) 161 { 162 caddr_t cfgaddr; 163 ddi_acc_hdl_t *hp; 164 165 hp = impl_acc_hdl_get(handle); 166 cfgaddr = hp->ah_addr + offset; 167 return (ddi_get8(handle, (uint8_t *)cfgaddr)); 168 } 169 170 uint16_t 171 pci_config_getw(ddi_acc_handle_t handle, off_t offset) 172 { 173 caddr_t cfgaddr; 174 ddi_acc_hdl_t *hp; 175 176 hp = impl_acc_hdl_get(handle); 177 cfgaddr = hp->ah_addr + offset; 178 return (ddi_get16(handle, (uint16_t *)cfgaddr)); 179 } 180 181 uint32_t 182 pci_config_getl(ddi_acc_handle_t handle, off_t offset) 183 { 184 caddr_t cfgaddr; 185 ddi_acc_hdl_t *hp; 186 187 hp = impl_acc_hdl_get(handle); 188 cfgaddr = hp->ah_addr + offset; 189 return (ddi_get32(handle, (uint32_t *)cfgaddr)); 190 } 191 192 uint64_t 193 pci_config_getll(ddi_acc_handle_t handle, off_t offset) 194 { 195 caddr_t cfgaddr; 196 ddi_acc_hdl_t *hp; 197 198 hp = impl_acc_hdl_get(handle); 199 cfgaddr = hp->ah_addr + offset; 200 return (ddi_get64(handle, (uint64_t *)cfgaddr)); 201 } 202 203 void 204 pci_config_putb(ddi_acc_handle_t handle, off_t offset, uint8_t value) 205 { 206 caddr_t cfgaddr; 207 ddi_acc_hdl_t *hp; 208 209 hp = impl_acc_hdl_get(handle); 210 cfgaddr = hp->ah_addr + offset; 211 ddi_put8(handle, (uint8_t *)cfgaddr, value); 212 } 213 214 void 215 pci_config_putw(ddi_acc_handle_t handle, off_t offset, uint16_t value) 216 { 217 caddr_t cfgaddr; 218 ddi_acc_hdl_t *hp; 219 220 hp = impl_acc_hdl_get(handle); 221 cfgaddr = hp->ah_addr + offset; 222 ddi_put16(handle, (uint16_t *)cfgaddr, value); 223 } 224 225 void 226 pci_config_putl(ddi_acc_handle_t handle, off_t offset, uint32_t value) 227 { 228 caddr_t cfgaddr; 229 ddi_acc_hdl_t *hp; 230 231 hp = impl_acc_hdl_get(handle); 232 cfgaddr = hp->ah_addr + offset; 233 ddi_put32(handle, (uint32_t *)cfgaddr, value); 234 } 235 236 void 237 pci_config_putll(ddi_acc_handle_t handle, off_t offset, uint64_t value) 238 { 239 caddr_t cfgaddr; 240 ddi_acc_hdl_t *hp; 241 242 hp = impl_acc_hdl_get(handle); 243 cfgaddr = hp->ah_addr + offset; 244 ddi_put64(handle, (uint64_t *)cfgaddr, value); 245 } 246 #endif /* _ILP32 */ 247 248 /*ARGSUSED*/ 249 int 250 pci_report_pmcap(dev_info_t *dip, int cap, void *arg) 251 { 252 return (DDI_SUCCESS); 253 } 254 255 /* 256 * Note about saving and restoring config space. 257 * PCI devices have only upto 256 bytes of config space while PCI Express 258 * devices can have upto 4k config space. In case of PCI Express device, 259 * we save all 4k config space and restore it even if it doesn't make use 260 * of all 4k. But some devices don't respond to reads to non-existent 261 * registers within the config space. To avoid any panics, we use ddi_peek 262 * to do the reads. A bit mask is used to indicate which words of the 263 * config space are accessible. While restoring the config space, only those 264 * readable words are restored. We do all this in 32 bit size words. 265 */ 266 #define INDEX_SHIFT 3 267 #define BITMASK 0x7 268 269 static uint32_t pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 270 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp); 271 static void pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 272 pci_cap_save_desc_t *cap_descp, uint32_t elements); 273 static uint32_t pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 274 uint32_t *regbuf, uint32_t nwords); 275 static uint32_t pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 276 uint32_t *regbuf, uint32_t notused); 277 static uint32_t pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 278 uint32_t *regbuf, uint32_t notused); 279 static uint32_t pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 280 uint32_t *regbuf, uint32_t notused); 281 static void pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 282 uint32_t *regbuf, uint32_t nwords); 283 static uint32_t cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf, 284 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace); 285 static void pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf, 286 uint16_t pmcap_offset); 287 288 /* 289 * Table below specifies the number of registers to be saved for each PCI 290 * capability. pci_generic_save saves the number of words specified in the 291 * table. Any special considerations will be taken care by the capability 292 * specific save function e.g. use pci_msi_save to save registers associated 293 * with MSI capability. PCI_UNKNOWN_SIZE indicates that number of registers 294 * to be saved is variable and will be determined by the specific save function. 295 * Currently we save/restore all the registers associated with the capability 296 * including read only registers. Regsiters are saved and restored in 32 bit 297 * size words. 298 */ 299 static pci_cap_entry_t pci_cap_table[] = { 300 {PCI_CAP_ID_PM, PCI_PMCAP_NDWORDS, pci_generic_save}, 301 {PCI_CAP_ID_AGP, PCI_AGP_NDWORDS, pci_generic_save}, 302 {PCI_CAP_ID_SLOT_ID, PCI_SLOTID_NDWORDS, pci_generic_save}, 303 {PCI_CAP_ID_MSI_X, PCI_MSIX_NDWORDS, pci_generic_save}, 304 {PCI_CAP_ID_MSI, PCI_CAP_SZUNKNOWN, pci_msi_save}, 305 {PCI_CAP_ID_PCIX, PCI_CAP_SZUNKNOWN, pci_pcix_save}, 306 {PCI_CAP_ID_PCI_E, PCI_CAP_SZUNKNOWN, pci_pcie_save}, 307 /* 308 * {PCI_CAP_ID_cPCI_CRC, 0, NULL}, 309 * {PCI_CAP_ID_VPD, 0, NULL}, 310 * {PCI_CAP_ID_cPCI_HS, 0, NULL}, 311 * {PCI_CAP_ID_PCI_HOTPLUG, 0, NULL}, 312 * {PCI_CAP_ID_AGP_8X, 0, NULL}, 313 * {PCI_CAP_ID_SECURE_DEV, 0, NULL}, 314 */ 315 {PCI_CAP_NEXT_PTR_NULL, 0, NULL} 316 }; 317 318 /* 319 * Save the configuration registers for cdip as a property 320 * so that it persists after detach/uninitchild. 321 */ 322 int 323 pci_save_config_regs(dev_info_t *dip) 324 { 325 ddi_acc_handle_t confhdl; 326 pci_config_header_state_t *chsp; 327 pci_cap_save_desc_t *pci_cap_descp; 328 int ret; 329 uint32_t i, ncaps, nwords; 330 uint32_t *regbuf, *p; 331 uint8_t *maskbuf; 332 size_t maskbufsz, regbufsz, capbufsz; 333 ddi_acc_hdl_t *hp; 334 off_t offset = 0; 335 uint8_t cap_ptr, cap_id; 336 int pcie = 0; 337 PMD(PMD_SX, ("pci_save_config_regs %s:%d\n", ddi_driver_name(dip), 338 ddi_get_instance(dip))) 339 340 if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) { 341 cmn_err(CE_WARN, "%s%d can't get config handle", 342 ddi_driver_name(dip), ddi_get_instance(dip)); 343 344 return (DDI_FAILURE); 345 } 346 /* 347 * Determine if it is a pci express device. If it is, save entire 348 * 4k config space treating it as a array of 32 bit integers. 349 * If it is not, do it in a usual PCI way. 350 */ 351 cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR); 352 /* 353 * Walk the capabilities searching for pci express capability 354 */ 355 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 356 cap_id = pci_config_get8(confhdl, 357 cap_ptr + PCI_CAP_ID); 358 if (cap_id == PCI_CAP_ID_PCI_E) { 359 pcie = 1; 360 break; 361 } 362 cap_ptr = pci_config_get8(confhdl, 363 cap_ptr + PCI_CAP_NEXT_PTR); 364 } 365 366 if (pcie) { 367 /* PCI express device. Can have data in all 4k space */ 368 regbuf = (uint32_t *)kmem_zalloc((size_t)PCIE_CONF_HDR_SIZE, 369 KM_SLEEP); 370 p = regbuf; 371 /* 372 * Allocate space for mask. 373 * mask size is 128 bytes (4096 / 4 / 8 ) 374 */ 375 maskbufsz = (size_t)((PCIE_CONF_HDR_SIZE/ sizeof (uint32_t)) >> 376 INDEX_SHIFT); 377 maskbuf = (uint8_t *)kmem_zalloc(maskbufsz, KM_SLEEP); 378 hp = impl_acc_hdl_get(confhdl); 379 for (i = 0; i < (PCIE_CONF_HDR_SIZE / sizeof (uint32_t)); i++) { 380 if (ddi_peek32(dip, (int32_t *)(hp->ah_addr + offset), 381 (int32_t *)p) == DDI_SUCCESS) { 382 /* it is readable register. set the bit */ 383 maskbuf[i >> INDEX_SHIFT] |= 384 (uint8_t)(1 << (i & BITMASK)); 385 } 386 p++; 387 offset += sizeof (uint32_t); 388 } 389 390 if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 391 SAVED_CONFIG_REGS_MASK, (uchar_t *)maskbuf, 392 maskbufsz)) != DDI_PROP_SUCCESS) { 393 cmn_err(CE_WARN, "couldn't create %s property while" 394 "saving config space for %s@%d\n", 395 SAVED_CONFIG_REGS_MASK, ddi_driver_name(dip), 396 ddi_get_instance(dip)); 397 } else if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, 398 dip, SAVED_CONFIG_REGS, (uchar_t *)regbuf, 399 (size_t)PCIE_CONF_HDR_SIZE)) != DDI_PROP_SUCCESS) { 400 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 401 SAVED_CONFIG_REGS_MASK); 402 cmn_err(CE_WARN, "%s%d can't update prop %s", 403 ddi_driver_name(dip), ddi_get_instance(dip), 404 SAVED_CONFIG_REGS); 405 } 406 407 kmem_free(maskbuf, (size_t)maskbufsz); 408 kmem_free(regbuf, (size_t)PCIE_CONF_HDR_SIZE); 409 } else { 410 regbuf = (uint32_t *)kmem_zalloc((size_t)PCI_CONF_HDR_SIZE, 411 KM_SLEEP); 412 chsp = (pci_config_header_state_t *)regbuf; 413 414 chsp->chs_command = pci_config_get16(confhdl, PCI_CONF_COMM); 415 chsp->chs_header_type = pci_config_get8(confhdl, 416 PCI_CONF_HEADER); 417 if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) == 418 PCI_HEADER_ONE) 419 chsp->chs_bridge_control = 420 pci_config_get16(confhdl, PCI_BCNF_BCNTRL); 421 chsp->chs_cache_line_size = pci_config_get8(confhdl, 422 PCI_CONF_CACHE_LINESZ); 423 chsp->chs_latency_timer = pci_config_get8(confhdl, 424 PCI_CONF_LATENCY_TIMER); 425 if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) == 426 PCI_HEADER_ONE) { 427 chsp->chs_sec_latency_timer = 428 pci_config_get8(confhdl, PCI_BCNF_LATENCY_TIMER); 429 } 430 431 chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0); 432 chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1); 433 chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2); 434 chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3); 435 chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4); 436 chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5); 437 438 /* 439 * Allocate maximum space required for capability descriptions. 440 * The maximum number of capabilties saved is the number of 441 * capabilities listed in the pci_cap_table. 442 */ 443 ncaps = (sizeof (pci_cap_table) / sizeof (pci_cap_entry_t)); 444 capbufsz = ncaps * sizeof (pci_cap_save_desc_t); 445 pci_cap_descp = (pci_cap_save_desc_t *)kmem_zalloc( 446 capbufsz, KM_SLEEP); 447 p = (uint32_t *)((caddr_t)regbuf + 448 sizeof (pci_config_header_state_t)); 449 nwords = pci_save_caps(confhdl, p, pci_cap_descp, &ncaps); 450 regbufsz = sizeof (pci_config_header_state_t) + 451 nwords * sizeof (uint32_t); 452 453 if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 454 SAVED_CONFIG_REGS, (uchar_t *)regbuf, regbufsz)) != 455 DDI_PROP_SUCCESS) { 456 cmn_err(CE_WARN, "%s%d can't update prop %s", 457 ddi_driver_name(dip), ddi_get_instance(dip), 458 SAVED_CONFIG_REGS); 459 } else if (ncaps) { 460 ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 461 SAVED_CONFIG_REGS_CAPINFO, (uchar_t *)pci_cap_descp, 462 ncaps * sizeof (pci_cap_save_desc_t)); 463 if (ret != DDI_PROP_SUCCESS) 464 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 465 SAVED_CONFIG_REGS); 466 } 467 kmem_free(regbuf, (size_t)PCI_CONF_HDR_SIZE); 468 kmem_free(pci_cap_descp, capbufsz); 469 } 470 pci_config_teardown(&confhdl); 471 472 if (ret != DDI_PROP_SUCCESS) 473 return (DDI_FAILURE); 474 475 return (DDI_SUCCESS); 476 } 477 478 /* 479 * Saves registers associated with PCI capabilities. 480 * Returns number of 32 bit words saved. 481 * Number of capabilities saved is returned in ncapsp. 482 */ 483 static uint32_t 484 pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 485 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp) 486 { 487 return (cap_walk_and_save(confhdl, regbuf, cap_descp, ncapsp, 0)); 488 } 489 490 static uint32_t 491 cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf, 492 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace) 493 { 494 pci_cap_entry_t *pci_cap_entp; 495 uint16_t cap_id, offset; 496 uint32_t words_saved = 0, nwords = 0; 497 uint16_t cap_ptr = PCI_CAP_NEXT_PTR_NULL; 498 499 *ncapsp = 0; 500 if (!xspace) 501 cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR); 502 /* 503 * Walk the capabilities 504 */ 505 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 506 cap_id = CAP_ID(confhdl, cap_ptr, xspace); 507 /* Search for this cap id in our table */ 508 if (!xspace) 509 pci_cap_entp = pci_cap_table; 510 while (pci_cap_entp->cap_id != PCI_CAP_NEXT_PTR_NULL && 511 pci_cap_entp->cap_id != cap_id) 512 pci_cap_entp++; 513 514 offset = cap_ptr; 515 cap_ptr = NEXT_CAP(confhdl, cap_ptr, xspace); 516 /* 517 * If this cap id is not found in the table, there is nothing 518 * to save. 519 */ 520 if (pci_cap_entp->cap_id == PCI_CAP_NEXT_PTR_NULL) 521 continue; 522 if (pci_cap_entp->cap_save_func) { 523 if ((nwords = pci_cap_entp->cap_save_func(confhdl, 524 offset, regbuf, pci_cap_entp->cap_ndwords))) { 525 cap_descp->cap_nregs = nwords; 526 cap_descp->cap_offset = offset; 527 cap_descp->cap_id = cap_id; 528 regbuf += nwords; 529 cap_descp++; 530 words_saved += nwords; 531 (*ncapsp)++; 532 } 533 } 534 535 } 536 return (words_saved); 537 } 538 539 static void 540 pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 541 uint32_t *regbuf, uint32_t nwords) 542 { 543 int i; 544 545 for (i = 0; i < nwords; i++) { 546 *regbuf = pci_config_get32(confhdl, cap_ptr); 547 regbuf++; 548 cap_ptr += 4; 549 } 550 } 551 552 static uint32_t 553 pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 554 uint32_t nwords) 555 { 556 pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 557 return (nwords); 558 } 559 560 /*ARGSUSED*/ 561 static uint32_t 562 pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 563 uint32_t notused) 564 { 565 uint32_t nwords = PCI_MSI_MIN_WORDS; 566 uint16_t msi_ctrl; 567 568 /* Figure out how many registers to be saved */ 569 msi_ctrl = pci_config_get16(confhdl, cap_ptr + PCI_MSI_CTRL); 570 /* If 64 bit address capable add one word */ 571 if (msi_ctrl & PCI_MSI_64BIT_MASK) 572 nwords++; 573 /* If per vector masking capable, add two more words */ 574 if (msi_ctrl & PCI_MSI_PVM_MASK) 575 nwords += 2; 576 pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 577 578 return (nwords); 579 } 580 581 /*ARGSUSED*/ 582 static uint32_t 583 pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 584 uint32_t notused) 585 { 586 uint32_t nwords = PCI_PCIX_MIN_WORDS; 587 uint16_t pcix_command; 588 589 /* Figure out how many registers to be saved */ 590 pcix_command = pci_config_get16(confhdl, cap_ptr + PCI_PCIX_COMMAND); 591 /* If it is version 1 or version 2, add 4 words */ 592 if (((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_1) || 593 ((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_2)) 594 nwords += 4; 595 pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 596 597 return (nwords); 598 } 599 600 /*ARGSUSED*/ 601 static uint32_t 602 pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 603 uint32_t notused) 604 { 605 return (0); 606 } 607 608 static void 609 pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf, 610 uint16_t pmcap_offset) 611 { 612 uint16_t pmcsr; 613 uint16_t pmcsr_offset = pmcap_offset + PCI_PMCSR; 614 uint32_t *saved_pmcsrp = (uint32_t *)((caddr_t)regbuf + PCI_PMCSR); 615 616 /* 617 * Copy the power state bits from the PMCSR to our saved copy. 618 * This is to make sure that we don't change the D state when 619 * we restore config space of the device. 620 */ 621 pmcsr = pci_config_get16(confhdl, pmcsr_offset); 622 (*saved_pmcsrp) &= ~PCI_PMCSR_STATE_MASK; 623 (*saved_pmcsrp) |= (pmcsr & PCI_PMCSR_STATE_MASK); 624 } 625 626 static void 627 pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 628 pci_cap_save_desc_t *cap_descp, uint32_t elements) 629 { 630 int i, j; 631 uint16_t offset; 632 633 for (i = 0; i < (elements / sizeof (pci_cap_save_desc_t)); i++) { 634 offset = cap_descp->cap_offset; 635 if (cap_descp->cap_id == PCI_CAP_ID_PM) 636 pci_pmcap_check(confhdl, regbuf, offset); 637 for (j = 0; j < cap_descp->cap_nregs; j++) { 638 pci_config_put32(confhdl, offset, *regbuf); 639 regbuf++; 640 offset += 4; 641 } 642 cap_descp++; 643 } 644 } 645 646 /* 647 * Restore config_regs from a single devinfo node. 648 */ 649 int 650 pci_restore_config_regs(dev_info_t *dip) 651 { 652 ddi_acc_handle_t confhdl; 653 pci_config_header_state_t *chs_p; 654 pci_cap_save_desc_t *cap_descp; 655 uint32_t elements, i; 656 uint8_t *maskbuf; 657 uint32_t *regbuf, *p; 658 off_t offset = 0; 659 660 if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) { 661 cmn_err(CE_WARN, "%s%d can't get config handle", 662 ddi_driver_name(dip), ddi_get_instance(dip)); 663 return (DDI_FAILURE); 664 } 665 666 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 667 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS_MASK, 668 (uchar_t **)&maskbuf, &elements) == DDI_PROP_SUCCESS) { 669 670 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 671 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS, 672 (uchar_t **)®buf, &elements) != DDI_PROP_SUCCESS) { 673 goto restoreconfig_err; 674 } 675 ASSERT(elements == PCIE_CONF_HDR_SIZE); 676 /* pcie device and has 4k config space saved */ 677 p = regbuf; 678 for (i = 0; i < PCIE_CONF_HDR_SIZE / sizeof (uint32_t); i++) { 679 /* If the word is readable then restore it */ 680 if (maskbuf[i >> INDEX_SHIFT] & 681 (uint8_t)(1 << (i & BITMASK))) 682 pci_config_put32(confhdl, offset, *p); 683 p++; 684 offset += sizeof (uint32_t); 685 } 686 ddi_prop_free(regbuf); 687 ddi_prop_free(maskbuf); 688 if (ndi_prop_remove(DDI_DEV_T_NONE, dip, 689 SAVED_CONFIG_REGS_MASK) != DDI_PROP_SUCCESS) { 690 cmn_err(CE_WARN, "%s%d can't remove prop %s", 691 ddi_driver_name(dip), ddi_get_instance(dip), 692 SAVED_CONFIG_REGS_MASK); 693 } 694 } else { 695 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 696 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS, 697 (uchar_t **)®buf, &elements) != DDI_PROP_SUCCESS) { 698 699 pci_config_teardown(&confhdl); 700 return (DDI_FAILURE); 701 } 702 703 chs_p = (pci_config_header_state_t *)regbuf; 704 pci_config_put16(confhdl, PCI_CONF_COMM, 705 chs_p->chs_command); 706 if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) == 707 PCI_HEADER_ONE) { 708 pci_config_put16(confhdl, PCI_BCNF_BCNTRL, 709 chs_p->chs_bridge_control); 710 } 711 pci_config_put8(confhdl, PCI_CONF_CACHE_LINESZ, 712 chs_p->chs_cache_line_size); 713 pci_config_put8(confhdl, PCI_CONF_LATENCY_TIMER, 714 chs_p->chs_latency_timer); 715 if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) == 716 PCI_HEADER_ONE) 717 pci_config_put8(confhdl, PCI_BCNF_LATENCY_TIMER, 718 chs_p->chs_sec_latency_timer); 719 720 pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0); 721 pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1); 722 pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2); 723 pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3); 724 pci_config_put32(confhdl, PCI_CONF_BASE4, chs_p->chs_base4); 725 pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5); 726 727 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 728 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 729 SAVED_CONFIG_REGS_CAPINFO, 730 (uchar_t **)&cap_descp, &elements) == DDI_PROP_SUCCESS) { 731 /* 732 * PCI capability related regsiters are saved. 733 * Restore them based on the description. 734 */ 735 p = (uint32_t *)((caddr_t)regbuf + 736 sizeof (pci_config_header_state_t)); 737 pci_restore_caps(confhdl, p, cap_descp, elements); 738 ddi_prop_free(cap_descp); 739 } 740 741 ddi_prop_free(regbuf); 742 } 743 744 /* 745 * Make sure registers are flushed 746 */ 747 (void) pci_config_get32(confhdl, PCI_CONF_BASE5); 748 749 750 if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS) != 751 DDI_PROP_SUCCESS) { 752 cmn_err(CE_WARN, "%s%d can't remove prop %s", 753 ddi_driver_name(dip), ddi_get_instance(dip), 754 SAVED_CONFIG_REGS); 755 } 756 757 pci_config_teardown(&confhdl); 758 759 return (DDI_SUCCESS); 760 761 restoreconfig_err: 762 ddi_prop_free(maskbuf); 763 if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS_MASK) != 764 DDI_PROP_SUCCESS) { 765 cmn_err(CE_WARN, "%s%d can't remove prop %s", 766 ddi_driver_name(dip), ddi_get_instance(dip), 767 SAVED_CONFIG_REGS_MASK); 768 } 769 pci_config_teardown(&confhdl); 770 return (DDI_FAILURE); 771 } 772 773 /*ARGSUSED*/ 774 static int 775 pci_lookup_pmcap(dev_info_t *dip, ddi_acc_handle_t conf_hdl, 776 uint16_t *pmcap_offsetp) 777 { 778 uint8_t cap_ptr; 779 uint8_t cap_id; 780 uint8_t header_type; 781 uint16_t status; 782 783 header_type = pci_config_get8(conf_hdl, PCI_CONF_HEADER); 784 header_type &= PCI_HEADER_TYPE_M; 785 786 /* we don't deal with bridges, etc here */ 787 if (header_type != PCI_HEADER_ZERO) { 788 return (DDI_FAILURE); 789 } 790 791 status = pci_config_get16(conf_hdl, PCI_CONF_STAT); 792 if ((status & PCI_STAT_CAP) == 0) { 793 return (DDI_FAILURE); 794 } 795 796 cap_ptr = pci_config_get8(conf_hdl, PCI_CONF_CAP_PTR); 797 798 /* 799 * Walk the capabilities searching for a PM entry. 800 */ 801 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 802 cap_id = pci_config_get8(conf_hdl, cap_ptr + PCI_CAP_ID); 803 if (cap_id == PCI_CAP_ID_PM) { 804 break; 805 } 806 cap_ptr = pci_config_get8(conf_hdl, 807 cap_ptr + PCI_CAP_NEXT_PTR); 808 } 809 810 if (cap_ptr == PCI_CAP_NEXT_PTR_NULL) { 811 return (DDI_FAILURE); 812 } 813 *pmcap_offsetp = cap_ptr; 814 return (DDI_SUCCESS); 815 } 816 817 /* 818 * Do common pci-specific suspend actions: 819 * - enable wakeup if appropriate for the device 820 * - put device in lowest D-state that supports wakeup, or D3 if none 821 * - turn off bus mastering in control register 822 * For lack of per-dip storage (parent private date is pretty busy) 823 * we use properties to store the necessary context 824 * To avoid grotting through pci config space on every suspend, 825 * we leave the prop in existence after resume, cause we know that 826 * the detach framework code will dispose of it for us. 827 */ 828 829 typedef struct pci_pm_context { 830 int ppc_flags; 831 uint16_t ppc_cap_offset; /* offset in config space to pm cap */ 832 uint16_t ppc_pmcsr; /* need this too */ 833 uint16_t ppc_suspend_level; 834 } pci_pm_context_t; 835 836 #define SAVED_PM_CONTEXT "pci-pm-context" 837 838 /* values for ppc_flags */ 839 #define PPCF_NOPMCAP 1 840 841 /* 842 * Handle pci-specific suspend processing 843 * PM CSR and PCI CMD are saved by pci_save_config_regs(). 844 * If device can wake up system via PME, enable it to do so 845 * Set device power level to lowest that can generate PME, or D3 if none can 846 * Turn off bus master enable in pci command register 847 */ 848 #if defined(__x86) 849 extern int acpi_ddi_setwake(dev_info_t *dip, int level); 850 #endif 851 852 int 853 pci_post_suspend(dev_info_t *dip) 854 { 855 pci_pm_context_t *p; 856 uint16_t pmcap, pmcsr, pcicmd; 857 uint_t length; 858 int ret; 859 int fromprop = 1; /* source of memory *p */ 860 ddi_acc_handle_t hdl; 861 862 PMD(PMD_SX, ("pci_post_suspend %s:%d\n", 863 ddi_driver_name(dip), ddi_get_instance(dip))) 864 865 if (pci_save_config_regs(dip) != DDI_SUCCESS) { 866 return (DDI_FAILURE); 867 } 868 869 if (pci_config_setup(dip, &hdl) != DDI_SUCCESS) { 870 return (DDI_FAILURE); 871 } 872 873 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 874 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 875 SAVED_PM_CONTEXT, (uchar_t **)&p, &length) != DDI_PROP_SUCCESS) { 876 p = (pci_pm_context_t *)kmem_zalloc(sizeof (*p), KM_SLEEP); 877 fromprop = 0; 878 if (pci_lookup_pmcap(dip, hdl, 879 &p->ppc_cap_offset) != DDI_SUCCESS) { 880 p->ppc_flags |= PPCF_NOPMCAP; 881 ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 882 SAVED_PM_CONTEXT, (uchar_t *)p, 883 sizeof (pci_pm_context_t)); 884 if (ret != DDI_PROP_SUCCESS) { 885 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 886 SAVED_PM_CONTEXT); 887 ret = DDI_FAILURE; 888 } else { 889 ret = DDI_SUCCESS; 890 } 891 kmem_free(p, sizeof (*p)); 892 pci_config_teardown(&hdl); 893 return (DDI_SUCCESS); 894 } 895 /* 896 * Upon suspend, set the power level to the lowest that can 897 * wake the system. If none can, then set to lowest. 898 * XXX later we will need to check policy to see if this 899 * XXX device has had wakeup disabled 900 */ 901 pmcap = pci_config_get16(hdl, p->ppc_cap_offset + PCI_PMCAP); 902 if ((pmcap & PCI_PMCAP_D3COLD_PME) != 0) 903 p->ppc_suspend_level = 904 (PCI_PMCSR_PME_EN | PCI_PMCSR_D3HOT); 905 else if ((pmcap & (PCI_PMCAP_D3HOT_PME | PCI_PMCAP_D2_PME)) != 906 0) 907 p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D2; 908 else if ((pmcap & PCI_PMCAP_D1_PME) != 0) 909 p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D1; 910 else if ((pmcap & PCI_PMCAP_D0_PME) != 0) 911 p->ppc_suspend_level = PCI_PMCSR_PME_EN | PCI_PMCSR_D0; 912 else 913 p->ppc_suspend_level = PCI_PMCSR_D3HOT; 914 915 /* 916 * we defer updating the property to catch the saved 917 * register values as well 918 */ 919 } 920 /* If we set this in kmem_zalloc'd memory, we already returned above */ 921 if ((p->ppc_flags & PPCF_NOPMCAP) != 0) { 922 ddi_prop_free(p); 923 pci_config_teardown(&hdl); 924 return (DDI_SUCCESS); 925 } 926 927 928 /* 929 * Turn off (Bus) Master Enable, since acpica will be turning off 930 * bus master aribitration 931 */ 932 pcicmd = pci_config_get16(hdl, PCI_CONF_COMM); 933 pcicmd &= ~PCI_COMM_ME; 934 pci_config_put16(hdl, PCI_CONF_COMM, pcicmd); 935 936 /* 937 * set pm csr 938 */ 939 pmcsr = pci_config_get16(hdl, p->ppc_cap_offset + PCI_PMCSR); 940 p->ppc_pmcsr = pmcsr; 941 pmcsr &= (PCI_PMCSR_STATE_MASK); 942 pmcsr |= (PCI_PMCSR_PME_STAT | p->ppc_suspend_level); 943 pci_config_put16(hdl, p->ppc_cap_offset + PCI_PMCSR, pmcsr); 944 945 #if defined(__x86) 946 /* 947 * Arrange for platform wakeup enabling 948 */ 949 if ((p->ppc_suspend_level & PCI_PMCSR_PME_EN) != 0) { 950 int retval; 951 952 retval = acpi_ddi_setwake(dip, 3); /* XXX 3 for now */ 953 if (retval) { 954 PMD(PMD_SX, ("pci_post_suspend, setwake %s@%s rets " 955 "%x\n", PM_NAME(dip), PM_ADDR(dip), retval)); 956 } 957 } 958 #endif 959 960 /* 961 * Push out saved register values 962 */ 963 ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, SAVED_PM_CONTEXT, 964 (uchar_t *)p, sizeof (pci_pm_context_t)); 965 if (ret == DDI_PROP_SUCCESS) { 966 if (fromprop) 967 ddi_prop_free(p); 968 else 969 kmem_free(p, sizeof (*p)); 970 pci_config_teardown(&hdl); 971 return (DDI_SUCCESS); 972 } 973 /* Failed; put things back the way we found them */ 974 (void) pci_restore_config_regs(dip); 975 if (fromprop) 976 ddi_prop_free(p); 977 else 978 kmem_free(p, sizeof (*p)); 979 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_PM_CONTEXT); 980 pci_config_teardown(&hdl); 981 return (DDI_FAILURE); 982 } 983 984 /* 985 * The inverse of pci_post_suspend; handle pci-specific resume processing 986 * First, turn device back on, then restore config space. 987 */ 988 989 int 990 pci_pre_resume(dev_info_t *dip) 991 { 992 ddi_acc_handle_t hdl; 993 pci_pm_context_t *p; 994 /* E_FUNC_SET_NOT_USED */ 995 uint16_t pmcap, pmcsr; 996 int flags; 997 uint_t length; 998 clock_t drv_usectohz(clock_t microsecs); 999 #if defined(__x86) 1000 uint16_t suspend_level; 1001 #endif 1002 1003 PMD(PMD_SX, ("pci_pre_resume %s:%d\n", ddi_driver_name(dip), 1004 ddi_get_instance(dip))) 1005 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 1006 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 1007 SAVED_PM_CONTEXT, (uchar_t **)&p, &length) != DDI_PROP_SUCCESS) { 1008 return (DDI_FAILURE); 1009 } 1010 flags = p->ppc_flags; 1011 pmcap = p->ppc_cap_offset; 1012 pmcsr = p->ppc_pmcsr; 1013 #if defined(__x86) 1014 suspend_level = p->ppc_suspend_level; 1015 #endif 1016 ddi_prop_free(p); 1017 if ((flags & PPCF_NOPMCAP) != 0) { 1018 return (DDI_SUCCESS); 1019 } 1020 #if defined(__x86) 1021 /* 1022 * Turn platform wake enable back off 1023 */ 1024 if ((suspend_level & PCI_PMCSR_PME_EN) != 0) { 1025 int retval; 1026 1027 retval = acpi_ddi_setwake(dip, 0); /* 0 for now */ 1028 if (retval) { 1029 PMD(PMD_SX, ("pci_pre_resume, setwake %s@%s rets " 1030 "%x\n", PM_NAME(dip), PM_ADDR(dip), retval)); 1031 } 1032 } 1033 #endif 1034 if (pci_config_setup(dip, &hdl) != DDI_SUCCESS) { 1035 return (DDI_FAILURE); 1036 } 1037 pci_config_put16(hdl, pmcap + PCI_PMCSR, pmcsr); 1038 delay(drv_usectohz(10000)); /* PCI PM spec D3->D0 (10ms) */ 1039 pci_config_teardown(&hdl); 1040 (void) pci_restore_config_regs(dip); /* fudges D-state! */ 1041 return (DDI_SUCCESS); 1042 } 1043