1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/sunndi.h> 31 #include <sys/sysmacros.h> 32 #include <sys/pci.h> 33 #include <sys/pcie.h> 34 #include <sys/pci_impl.h> 35 #include <sys/epm.h> 36 37 int 38 pci_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 39 { 40 caddr_t cfgaddr; 41 ddi_device_acc_attr_t attr; 42 43 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 44 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 45 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 46 47 /* Check for fault management capabilities */ 48 if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(dip))) { 49 attr.devacc_attr_version = DDI_DEVICE_ATTR_V1; 50 attr.devacc_attr_access = DDI_FLAGERR_ACC; 51 } 52 53 return (ddi_regs_map_setup(dip, 0, &cfgaddr, 0, 0, &attr, handle)); 54 } 55 56 void 57 pci_config_teardown(ddi_acc_handle_t *handle) 58 { 59 ddi_regs_map_free(handle); 60 } 61 62 uint8_t 63 pci_config_get8(ddi_acc_handle_t handle, off_t offset) 64 { 65 caddr_t cfgaddr; 66 ddi_acc_hdl_t *hp; 67 68 hp = impl_acc_hdl_get(handle); 69 cfgaddr = hp->ah_addr + offset; 70 return (ddi_get8(handle, (uint8_t *)cfgaddr)); 71 } 72 73 uint16_t 74 pci_config_get16(ddi_acc_handle_t handle, off_t offset) 75 { 76 caddr_t cfgaddr; 77 ddi_acc_hdl_t *hp; 78 79 hp = impl_acc_hdl_get(handle); 80 cfgaddr = hp->ah_addr + offset; 81 return (ddi_get16(handle, (uint16_t *)cfgaddr)); 82 } 83 84 uint32_t 85 pci_config_get32(ddi_acc_handle_t handle, off_t offset) 86 { 87 caddr_t cfgaddr; 88 ddi_acc_hdl_t *hp; 89 90 hp = impl_acc_hdl_get(handle); 91 cfgaddr = hp->ah_addr + offset; 92 return (ddi_get32(handle, (uint32_t *)cfgaddr)); 93 } 94 95 uint64_t 96 pci_config_get64(ddi_acc_handle_t handle, off_t offset) 97 { 98 caddr_t cfgaddr; 99 ddi_acc_hdl_t *hp; 100 101 hp = impl_acc_hdl_get(handle); 102 cfgaddr = hp->ah_addr + offset; 103 return (ddi_get64(handle, (uint64_t *)cfgaddr)); 104 } 105 106 void 107 pci_config_put8(ddi_acc_handle_t handle, off_t offset, uint8_t value) 108 { 109 caddr_t cfgaddr; 110 ddi_acc_hdl_t *hp; 111 112 hp = impl_acc_hdl_get(handle); 113 cfgaddr = hp->ah_addr + offset; 114 ddi_put8(handle, (uint8_t *)cfgaddr, value); 115 } 116 117 void 118 pci_config_put16(ddi_acc_handle_t handle, off_t offset, uint16_t value) 119 { 120 caddr_t cfgaddr; 121 ddi_acc_hdl_t *hp; 122 123 hp = impl_acc_hdl_get(handle); 124 cfgaddr = hp->ah_addr + offset; 125 ddi_put16(handle, (uint16_t *)cfgaddr, value); 126 } 127 128 void 129 pci_config_put32(ddi_acc_handle_t handle, off_t offset, uint32_t value) 130 { 131 caddr_t cfgaddr; 132 ddi_acc_hdl_t *hp; 133 134 hp = impl_acc_hdl_get(handle); 135 cfgaddr = hp->ah_addr + offset; 136 ddi_put32(handle, (uint32_t *)cfgaddr, value); 137 } 138 139 void 140 pci_config_put64(ddi_acc_handle_t handle, off_t offset, uint64_t value) 141 { 142 caddr_t cfgaddr; 143 ddi_acc_hdl_t *hp; 144 145 hp = impl_acc_hdl_get(handle); 146 cfgaddr = hp->ah_addr + offset; 147 ddi_put64(handle, (uint64_t *)cfgaddr, value); 148 } 149 150 /* 151 * We need to separate the old interfaces from the new ones and leave them 152 * in here for a while. Previous versions of the OS defined the new interfaces 153 * to the old interfaces. This way we can fix things up so that we can 154 * eventually remove these interfaces. 155 * e.g. A 3rd party module/driver using pci_config_get8 and built against S10 156 * or earlier will actually have a reference to pci_config_getb in the binary. 157 */ 158 #ifdef _ILP32 159 uint8_t 160 pci_config_getb(ddi_acc_handle_t handle, off_t offset) 161 { 162 caddr_t cfgaddr; 163 ddi_acc_hdl_t *hp; 164 165 hp = impl_acc_hdl_get(handle); 166 cfgaddr = hp->ah_addr + offset; 167 return (ddi_get8(handle, (uint8_t *)cfgaddr)); 168 } 169 170 uint16_t 171 pci_config_getw(ddi_acc_handle_t handle, off_t offset) 172 { 173 caddr_t cfgaddr; 174 ddi_acc_hdl_t *hp; 175 176 hp = impl_acc_hdl_get(handle); 177 cfgaddr = hp->ah_addr + offset; 178 return (ddi_get16(handle, (uint16_t *)cfgaddr)); 179 } 180 181 uint32_t 182 pci_config_getl(ddi_acc_handle_t handle, off_t offset) 183 { 184 caddr_t cfgaddr; 185 ddi_acc_hdl_t *hp; 186 187 hp = impl_acc_hdl_get(handle); 188 cfgaddr = hp->ah_addr + offset; 189 return (ddi_get32(handle, (uint32_t *)cfgaddr)); 190 } 191 192 uint64_t 193 pci_config_getll(ddi_acc_handle_t handle, off_t offset) 194 { 195 caddr_t cfgaddr; 196 ddi_acc_hdl_t *hp; 197 198 hp = impl_acc_hdl_get(handle); 199 cfgaddr = hp->ah_addr + offset; 200 return (ddi_get64(handle, (uint64_t *)cfgaddr)); 201 } 202 203 void 204 pci_config_putb(ddi_acc_handle_t handle, off_t offset, uint8_t value) 205 { 206 caddr_t cfgaddr; 207 ddi_acc_hdl_t *hp; 208 209 hp = impl_acc_hdl_get(handle); 210 cfgaddr = hp->ah_addr + offset; 211 ddi_put8(handle, (uint8_t *)cfgaddr, value); 212 } 213 214 void 215 pci_config_putw(ddi_acc_handle_t handle, off_t offset, uint16_t value) 216 { 217 caddr_t cfgaddr; 218 ddi_acc_hdl_t *hp; 219 220 hp = impl_acc_hdl_get(handle); 221 cfgaddr = hp->ah_addr + offset; 222 ddi_put16(handle, (uint16_t *)cfgaddr, value); 223 } 224 225 void 226 pci_config_putl(ddi_acc_handle_t handle, off_t offset, uint32_t value) 227 { 228 caddr_t cfgaddr; 229 ddi_acc_hdl_t *hp; 230 231 hp = impl_acc_hdl_get(handle); 232 cfgaddr = hp->ah_addr + offset; 233 ddi_put32(handle, (uint32_t *)cfgaddr, value); 234 } 235 236 void 237 pci_config_putll(ddi_acc_handle_t handle, off_t offset, uint64_t value) 238 { 239 caddr_t cfgaddr; 240 ddi_acc_hdl_t *hp; 241 242 hp = impl_acc_hdl_get(handle); 243 cfgaddr = hp->ah_addr + offset; 244 ddi_put64(handle, (uint64_t *)cfgaddr, value); 245 } 246 #endif /* _ILP32 */ 247 248 /*ARGSUSED*/ 249 int 250 pci_report_pmcap(dev_info_t *dip, int cap, void *arg) 251 { 252 return (DDI_SUCCESS); 253 } 254 255 /* 256 * Note about saving and restoring config space. 257 * PCI devices have only upto 256 bytes of config space while PCI Express 258 * devices can have upto 4k config space. In case of PCI Express device, 259 * we save all 4k config space and restore it even if it doesn't make use 260 * of all 4k. But some devices don't respond to reads to non-existent 261 * registers within the config space. To avoid any panics, we use ddi_peek 262 * to do the reads. A bit mask is used to indicate which words of the 263 * config space are accessible. While restoring the config space, only those 264 * readable words are restored. We do all this in 32 bit size words. 265 */ 266 #define INDEX_SHIFT 3 267 #define BITMASK 0x7 268 269 static uint32_t pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 270 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp); 271 static void pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 272 pci_cap_save_desc_t *cap_descp, uint32_t elements); 273 static uint32_t pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 274 uint32_t *regbuf, uint32_t nwords); 275 static uint32_t pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 276 uint32_t *regbuf, uint32_t notused); 277 static uint32_t pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 278 uint32_t *regbuf, uint32_t notused); 279 static uint32_t pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 280 uint32_t *regbuf, uint32_t notused); 281 static void pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 282 uint32_t *regbuf, uint32_t nwords); 283 static uint32_t cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf, 284 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace); 285 static void pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf, 286 uint16_t pmcap_offset); 287 288 /* 289 * Table below specifies the number of registers to be saved for each PCI 290 * capability. pci_generic_save saves the number of words specified in the 291 * table. Any special considerations will be taken care by the capability 292 * specific save function e.g. use pci_msi_save to save registers associated 293 * with MSI capability. PCI_UNKNOWN_SIZE indicates that number of registers 294 * to be saved is variable and will be determined by the specific save function. 295 * Currently we save/restore all the registers associated with the capability 296 * including read only registers. Regsiters are saved and restored in 32 bit 297 * size words. 298 */ 299 static pci_cap_entry_t pci_cap_table[] = { 300 {PCI_CAP_ID_PM, PCI_PMCAP_NDWORDS, pci_generic_save}, 301 {PCI_CAP_ID_AGP, PCI_AGP_NDWORDS, pci_generic_save}, 302 {PCI_CAP_ID_SLOT_ID, PCI_SLOTID_NDWORDS, pci_generic_save}, 303 {PCI_CAP_ID_MSI_X, PCI_MSIX_NDWORDS, pci_generic_save}, 304 {PCI_CAP_ID_MSI, PCI_CAP_SZUNKNOWN, pci_msi_save}, 305 {PCI_CAP_ID_PCIX, PCI_CAP_SZUNKNOWN, pci_pcix_save}, 306 {PCI_CAP_ID_PCI_E, PCI_CAP_SZUNKNOWN, pci_pcie_save}, 307 /* 308 * {PCI_CAP_ID_cPCI_CRC, 0, NULL}, 309 * {PCI_CAP_ID_VPD, 0, NULL}, 310 * {PCI_CAP_ID_cPCI_HS, 0, NULL}, 311 * {PCI_CAP_ID_PCI_HOTPLUG, 0, NULL}, 312 * {PCI_CAP_ID_AGP_8X, 0, NULL}, 313 * {PCI_CAP_ID_SECURE_DEV, 0, NULL}, 314 */ 315 {PCI_CAP_NEXT_PTR_NULL, 0, NULL} 316 }; 317 318 /* 319 * Save the configuration registers for cdip as a property 320 * so that it persists after detach/uninitchild. 321 */ 322 int 323 pci_save_config_regs(dev_info_t *dip) 324 { 325 ddi_acc_handle_t confhdl; 326 pci_config_header_state_t *chsp; 327 pci_cap_save_desc_t *pci_cap_descp; 328 int ret; 329 uint32_t i, ncaps, nwords; 330 uint32_t *regbuf, *p; 331 uint8_t *maskbuf; 332 size_t maskbufsz, regbufsz, capbufsz; 333 ddi_acc_hdl_t *hp; 334 off_t offset = 0; 335 uint8_t cap_ptr, cap_id; 336 int pcie = 0; 337 338 if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) { 339 cmn_err(CE_WARN, "%s%d can't get config handle", 340 ddi_driver_name(dip), ddi_get_instance(dip)); 341 342 return (DDI_FAILURE); 343 } 344 /* 345 * Determine if it is a pci express device. If it is, save entire 346 * 4k config space treating it as a array of 32 bit integers. 347 * If it is not, do it in a usual PCI way. 348 */ 349 cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR); 350 /* 351 * Walk the capabilities searching for pci express capability 352 */ 353 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 354 cap_id = pci_config_get8(confhdl, 355 cap_ptr + PCI_CAP_ID); 356 if (cap_id == PCI_CAP_ID_PCI_E) { 357 pcie = 1; 358 break; 359 } 360 cap_ptr = pci_config_get8(confhdl, 361 cap_ptr + PCI_CAP_NEXT_PTR); 362 } 363 364 if (pcie) { 365 /* PCI express device. Can have data in all 4k space */ 366 regbuf = (uint32_t *)kmem_zalloc((size_t)PCIE_CONF_HDR_SIZE, 367 KM_SLEEP); 368 p = regbuf; 369 /* 370 * Allocate space for mask. 371 * mask size is 128 bytes (4096 / 4 / 8 ) 372 */ 373 maskbufsz = (size_t)((PCIE_CONF_HDR_SIZE/ sizeof (uint32_t)) >> 374 INDEX_SHIFT); 375 maskbuf = (uint8_t *)kmem_zalloc(maskbufsz, KM_SLEEP); 376 hp = impl_acc_hdl_get(confhdl); 377 for (i = 0; i < (PCIE_CONF_HDR_SIZE / sizeof (uint32_t)); i++) { 378 if (ddi_peek32(dip, (int32_t *)(hp->ah_addr + offset), 379 (int32_t *)p) == DDI_SUCCESS) { 380 /* it is readable register. set the bit */ 381 maskbuf[i >> INDEX_SHIFT] |= 382 (uint8_t)(1 << (i & BITMASK)); 383 } 384 p++; 385 offset += sizeof (uint32_t); 386 } 387 388 if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 389 SAVED_CONFIG_REGS_MASK, (uchar_t *)maskbuf, 390 maskbufsz)) != DDI_PROP_SUCCESS) { 391 cmn_err(CE_WARN, "couldn't create %s property while" 392 "saving config space for %s@%d\n", 393 SAVED_CONFIG_REGS_MASK, ddi_driver_name(dip), 394 ddi_get_instance(dip)); 395 } else if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, 396 dip, SAVED_CONFIG_REGS, (uchar_t *)regbuf, 397 (size_t)PCIE_CONF_HDR_SIZE)) != DDI_PROP_SUCCESS) { 398 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 399 SAVED_CONFIG_REGS_MASK); 400 cmn_err(CE_WARN, "%s%d can't update prop %s", 401 ddi_driver_name(dip), ddi_get_instance(dip), 402 SAVED_CONFIG_REGS); 403 } 404 405 kmem_free(maskbuf, (size_t)maskbufsz); 406 kmem_free(regbuf, (size_t)PCIE_CONF_HDR_SIZE); 407 } else { 408 regbuf = (uint32_t *)kmem_zalloc((size_t)PCI_CONF_HDR_SIZE, 409 KM_SLEEP); 410 chsp = (pci_config_header_state_t *)regbuf; 411 412 chsp->chs_command = pci_config_get16(confhdl, PCI_CONF_COMM); 413 chsp->chs_header_type = pci_config_get8(confhdl, 414 PCI_CONF_HEADER); 415 if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) == 416 PCI_HEADER_ONE) 417 chsp->chs_bridge_control = 418 pci_config_get16(confhdl, PCI_BCNF_BCNTRL); 419 chsp->chs_cache_line_size = pci_config_get8(confhdl, 420 PCI_CONF_CACHE_LINESZ); 421 chsp->chs_latency_timer = pci_config_get8(confhdl, 422 PCI_CONF_LATENCY_TIMER); 423 if ((chsp->chs_header_type & PCI_HEADER_TYPE_M) == 424 PCI_HEADER_ONE) { 425 chsp->chs_sec_latency_timer = 426 pci_config_get8(confhdl, PCI_BCNF_LATENCY_TIMER); 427 } 428 429 chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0); 430 chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1); 431 chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2); 432 chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3); 433 chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4); 434 chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5); 435 436 /* 437 * Allocate maximum space required for capability descriptions. 438 * The maximum number of capabilties saved is the number of 439 * capabilities listed in the pci_cap_table. 440 */ 441 ncaps = (sizeof (pci_cap_table) / sizeof (pci_cap_entry_t)); 442 capbufsz = ncaps * sizeof (pci_cap_save_desc_t); 443 pci_cap_descp = (pci_cap_save_desc_t *)kmem_zalloc( 444 capbufsz, KM_SLEEP); 445 p = (uint32_t *)((caddr_t)regbuf + 446 sizeof (pci_config_header_state_t)); 447 nwords = pci_save_caps(confhdl, p, pci_cap_descp, &ncaps); 448 regbufsz = sizeof (pci_config_header_state_t) + 449 nwords * sizeof (uint32_t); 450 451 if ((ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 452 SAVED_CONFIG_REGS, (uchar_t *)regbuf, regbufsz)) != 453 DDI_PROP_SUCCESS) { 454 cmn_err(CE_WARN, "%s%d can't update prop %s", 455 ddi_driver_name(dip), ddi_get_instance(dip), 456 SAVED_CONFIG_REGS); 457 } else if (ncaps) { 458 ret = ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, 459 SAVED_CONFIG_REGS_CAPINFO, (uchar_t *)pci_cap_descp, 460 ncaps * sizeof (pci_cap_save_desc_t)); 461 if (ret != DDI_PROP_SUCCESS) 462 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 463 SAVED_CONFIG_REGS); 464 } 465 kmem_free(regbuf, (size_t)PCI_CONF_HDR_SIZE); 466 kmem_free(pci_cap_descp, capbufsz); 467 } 468 pci_config_teardown(&confhdl); 469 470 if (ret != DDI_PROP_SUCCESS) 471 return (DDI_FAILURE); 472 473 return (DDI_SUCCESS); 474 } 475 476 /* 477 * Saves registers associated with PCI capabilities. 478 * Returns number of 32 bit words saved. 479 * Number of capabilities saved is returned in ncapsp. 480 */ 481 static uint32_t 482 pci_save_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 483 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp) 484 { 485 return (cap_walk_and_save(confhdl, regbuf, cap_descp, ncapsp, 0)); 486 } 487 488 static uint32_t 489 cap_walk_and_save(ddi_acc_handle_t confhdl, uint32_t *regbuf, 490 pci_cap_save_desc_t *cap_descp, uint32_t *ncapsp, int xspace) 491 { 492 pci_cap_entry_t *pci_cap_entp; 493 uint16_t cap_id, offset; 494 uint32_t words_saved = 0, nwords = 0; 495 uint16_t cap_ptr = PCI_CAP_NEXT_PTR_NULL; 496 497 *ncapsp = 0; 498 if (!xspace) 499 cap_ptr = pci_config_get8(confhdl, PCI_BCNF_CAP_PTR); 500 /* 501 * Walk the capabilities 502 */ 503 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 504 cap_id = CAP_ID(confhdl, cap_ptr, xspace); 505 /* Search for this cap id in our table */ 506 if (!xspace) 507 pci_cap_entp = pci_cap_table; 508 while (pci_cap_entp->cap_id != PCI_CAP_NEXT_PTR_NULL && 509 pci_cap_entp->cap_id != cap_id) 510 pci_cap_entp++; 511 512 offset = cap_ptr; 513 cap_ptr = NEXT_CAP(confhdl, cap_ptr, xspace); 514 /* 515 * If this cap id is not found in the table, there is nothing 516 * to save. 517 */ 518 if (pci_cap_entp->cap_id == PCI_CAP_NEXT_PTR_NULL) 519 continue; 520 if (pci_cap_entp->cap_save_func) { 521 if ((nwords = pci_cap_entp->cap_save_func(confhdl, 522 offset, regbuf, pci_cap_entp->cap_ndwords))) { 523 cap_descp->cap_nregs = nwords; 524 cap_descp->cap_offset = offset; 525 cap_descp->cap_id = cap_id; 526 regbuf += nwords; 527 cap_descp++; 528 words_saved += nwords; 529 (*ncapsp)++; 530 } 531 } 532 533 } 534 return (words_saved); 535 } 536 537 static void 538 pci_fill_buf(ddi_acc_handle_t confhdl, uint16_t cap_ptr, 539 uint32_t *regbuf, uint32_t nwords) 540 { 541 int i; 542 543 for (i = 0; i < nwords; i++) { 544 *regbuf = pci_config_get32(confhdl, cap_ptr); 545 regbuf++; 546 cap_ptr += 4; 547 } 548 } 549 550 static uint32_t 551 pci_generic_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 552 uint32_t nwords) 553 { 554 pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 555 return (nwords); 556 } 557 558 /*ARGSUSED*/ 559 static uint32_t 560 pci_msi_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 561 uint32_t notused) 562 { 563 uint32_t nwords = PCI_MSI_MIN_WORDS; 564 uint16_t msi_ctrl; 565 566 /* Figure out how many registers to be saved */ 567 msi_ctrl = pci_config_get16(confhdl, cap_ptr + PCI_MSI_CTRL); 568 /* If 64 bit address capable add one word */ 569 if (msi_ctrl & PCI_MSI_64BIT_MASK) 570 nwords++; 571 /* If per vector masking capable, add two more words */ 572 if (msi_ctrl & PCI_MSI_PVM_MASK) 573 nwords += 2; 574 pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 575 576 return (nwords); 577 } 578 579 /*ARGSUSED*/ 580 static uint32_t 581 pci_pcix_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 582 uint32_t notused) 583 { 584 uint32_t nwords = PCI_PCIX_MIN_WORDS; 585 uint16_t pcix_command; 586 587 /* Figure out how many registers to be saved */ 588 pcix_command = pci_config_get16(confhdl, cap_ptr + PCI_PCIX_COMMAND); 589 /* If it is version 1 or version 2, add 4 words */ 590 if (((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_1) || 591 ((pcix_command & PCI_PCIX_VER_MASK) == PCI_PCIX_VER_2)) 592 nwords += 4; 593 pci_fill_buf(confhdl, cap_ptr, regbuf, nwords); 594 595 return (nwords); 596 } 597 598 /*ARGSUSED*/ 599 static uint32_t 600 pci_pcie_save(ddi_acc_handle_t confhdl, uint16_t cap_ptr, uint32_t *regbuf, 601 uint32_t notused) 602 { 603 return (0); 604 } 605 606 static void 607 pci_pmcap_check(ddi_acc_handle_t confhdl, uint32_t *regbuf, 608 uint16_t pmcap_offset) 609 { 610 uint16_t pmcsr; 611 uint16_t pmcsr_offset = pmcap_offset + PCI_PMCSR; 612 uint32_t *saved_pmcsrp = (uint32_t *)((caddr_t)regbuf + PCI_PMCSR); 613 614 /* 615 * Copy the power state bits from the PMCSR to our saved copy. 616 * This is to make sure that we don't change the D state when 617 * we restore config space of the device. 618 */ 619 pmcsr = pci_config_get16(confhdl, pmcsr_offset); 620 (*saved_pmcsrp) &= ~PCI_PMCSR_STATE_MASK; 621 (*saved_pmcsrp) |= (pmcsr & PCI_PMCSR_STATE_MASK); 622 } 623 624 static void 625 pci_restore_caps(ddi_acc_handle_t confhdl, uint32_t *regbuf, 626 pci_cap_save_desc_t *cap_descp, uint32_t elements) 627 { 628 int i, j; 629 uint16_t offset; 630 631 for (i = 0; i < (elements / sizeof (pci_cap_save_desc_t)); i++) { 632 offset = cap_descp->cap_offset; 633 if (cap_descp->cap_id == PCI_CAP_ID_PM) 634 pci_pmcap_check(confhdl, regbuf, offset); 635 for (j = 0; j < cap_descp->cap_nregs; j++) { 636 pci_config_put32(confhdl, offset, *regbuf); 637 regbuf++; 638 offset += 4; 639 } 640 cap_descp++; 641 } 642 } 643 644 /* 645 * Restore config_regs from a single devinfo node. 646 */ 647 int 648 pci_restore_config_regs(dev_info_t *dip) 649 { 650 ddi_acc_handle_t confhdl; 651 pci_config_header_state_t *chs_p; 652 pci_cap_save_desc_t *cap_descp; 653 uint32_t elements, i; 654 uint8_t *maskbuf; 655 uint32_t *regbuf, *p; 656 off_t offset = 0; 657 658 if (pci_config_setup(dip, &confhdl) != DDI_SUCCESS) { 659 cmn_err(CE_WARN, "%s%d can't get config handle", 660 ddi_driver_name(dip), ddi_get_instance(dip)); 661 return (DDI_FAILURE); 662 } 663 664 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 665 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS_MASK, 666 (uchar_t **)&maskbuf, &elements) == DDI_PROP_SUCCESS) { 667 668 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 669 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS, 670 (uchar_t **)®buf, &elements) != DDI_PROP_SUCCESS) { 671 goto restoreconfig_err; 672 } 673 ASSERT(elements == PCIE_CONF_HDR_SIZE); 674 /* pcie device and has 4k config space saved */ 675 p = regbuf; 676 for (i = 0; i < PCIE_CONF_HDR_SIZE / sizeof (uint32_t); i++) { 677 /* If the word is readable then restore it */ 678 if (maskbuf[i >> INDEX_SHIFT] & 679 (uint8_t)(1 << (i & BITMASK))) 680 pci_config_put32(confhdl, offset, *p); 681 p++; 682 offset += sizeof (uint32_t); 683 } 684 ddi_prop_free(regbuf); 685 ddi_prop_free(maskbuf); 686 if (ndi_prop_remove(DDI_DEV_T_NONE, dip, 687 SAVED_CONFIG_REGS_MASK) != DDI_PROP_SUCCESS) { 688 cmn_err(CE_WARN, "%s%d can't remove prop %s", 689 ddi_driver_name(dip), ddi_get_instance(dip), 690 SAVED_CONFIG_REGS_MASK); 691 } 692 } else { 693 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 694 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, SAVED_CONFIG_REGS, 695 (uchar_t **)®buf, &elements) != DDI_PROP_SUCCESS) { 696 697 pci_config_teardown(&confhdl); 698 return (DDI_FAILURE); 699 } 700 701 chs_p = (pci_config_header_state_t *)regbuf; 702 pci_config_put16(confhdl, PCI_CONF_COMM, 703 chs_p->chs_command); 704 if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) == 705 PCI_HEADER_ONE) { 706 pci_config_put16(confhdl, PCI_BCNF_BCNTRL, 707 chs_p->chs_bridge_control); 708 } 709 pci_config_put8(confhdl, PCI_CONF_CACHE_LINESZ, 710 chs_p->chs_cache_line_size); 711 pci_config_put8(confhdl, PCI_CONF_LATENCY_TIMER, 712 chs_p->chs_latency_timer); 713 if ((chs_p->chs_header_type & PCI_HEADER_TYPE_M) == 714 PCI_HEADER_ONE) 715 pci_config_put8(confhdl, PCI_BCNF_LATENCY_TIMER, 716 chs_p->chs_sec_latency_timer); 717 718 pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0); 719 pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1); 720 pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2); 721 pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3); 722 pci_config_put32(confhdl, PCI_CONF_BASE4, chs_p->chs_base4); 723 pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5); 724 725 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 726 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 727 SAVED_CONFIG_REGS_CAPINFO, 728 (uchar_t **)&cap_descp, &elements) == DDI_PROP_SUCCESS) { 729 /* 730 * PCI capability related regsiters are saved. 731 * Restore them based on the description. 732 */ 733 p = (uint32_t *)((caddr_t)regbuf + 734 sizeof (pci_config_header_state_t)); 735 pci_restore_caps(confhdl, p, cap_descp, elements); 736 ddi_prop_free(cap_descp); 737 } 738 739 ddi_prop_free(regbuf); 740 } 741 742 /* 743 * Make sure registers are flushed 744 */ 745 (void) pci_config_get32(confhdl, PCI_CONF_BASE5); 746 747 748 if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS) != 749 DDI_PROP_SUCCESS) { 750 cmn_err(CE_WARN, "%s%d can't remove prop %s", 751 ddi_driver_name(dip), ddi_get_instance(dip), 752 SAVED_CONFIG_REGS); 753 } 754 755 pci_config_teardown(&confhdl); 756 757 return (DDI_SUCCESS); 758 759 restoreconfig_err: 760 ddi_prop_free(maskbuf); 761 if (ndi_prop_remove(DDI_DEV_T_NONE, dip, SAVED_CONFIG_REGS_MASK) != 762 DDI_PROP_SUCCESS) { 763 cmn_err(CE_WARN, "%s%d can't remove prop %s", 764 ddi_driver_name(dip), ddi_get_instance(dip), 765 SAVED_CONFIG_REGS_MASK); 766 } 767 pci_config_teardown(&confhdl); 768 return (DDI_FAILURE); 769 } 770