1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #include "xgehal-mgmt.h" 25 #include "xgehal-driver.h" 26 #include "xgehal-device.h" 27 28 #ifdef XGE_OS_HAS_SNPRINTF 29 #define __hal_aux_snprintf(retbuf, bufsize, fmt, key, value, retsize) \ 30 if (bufsize <= 0) return XGE_HAL_ERR_OUT_OF_SPACE; \ 31 retsize = xge_os_snprintf(retbuf, bufsize, fmt, key, \ 32 XGE_HAL_AUX_SEPA, value); \ 33 if (retsize < 0 || retsize >= bufsize) return XGE_HAL_ERR_OUT_OF_SPACE; 34 #else 35 #define __hal_aux_snprintf(retbuf, bufsize, fmt, key, value, retsize) \ 36 if (bufsize <= 0) return XGE_HAL_ERR_OUT_OF_SPACE; \ 37 retsize = xge_os_sprintf(retbuf, fmt, key, XGE_HAL_AUX_SEPA, value); \ 38 xge_assert(retsize < bufsize); \ 39 if (retsize < 0 || retsize >= bufsize) \ 40 return XGE_HAL_ERR_OUT_OF_SPACE; 41 #endif 42 43 #define __HAL_AUX_ENTRY_DECLARE(size, buf) \ 44 int entrysize = 0, leftsize = size; \ 45 char *ptr = buf; 46 47 #define __HAL_AUX_ENTRY(key, value, fmt) \ 48 ptr += entrysize; leftsize -= entrysize; \ 49 __hal_aux_snprintf(ptr, leftsize, "%s%c"fmt"\n", key, value, entrysize) 50 51 #define __HAL_AUX_ENTRY_END(bufsize, retsize) \ 52 leftsize -= entrysize; \ 53 *retsize = bufsize - leftsize; 54 55 #define __hal_aux_pci_link_info(name, index, var) { \ 56 __HAL_AUX_ENTRY(name, \ 57 (unsigned long long)pcim.link_info[index].var, "%llu") \ 58 } 59 60 #define __hal_aux_pci_aggr_info(name, index, var) { \ 61 __HAL_AUX_ENTRY(name, \ 62 (unsigned long long)pcim.aggr_info[index].var, "%llu") \ 63 } 64 65 /** 66 * xge_hal_aux_bar0_read - Read and format Xframe BAR0 register. 67 * @devh: HAL device handle. 68 * @offset: Register offset in the BAR0 space. 69 * @bufsize: Buffer size. 70 * @retbuf: Buffer pointer. 71 * @retsize: Size of the result. Cannot be greater than @bufsize. 72 * 73 * Read Xframe register from BAR0 space. The result is formatted as an ascii string. 74 * 75 * Returns: XGE_HAL_OK - success. 76 * XGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small. 77 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 78 * XGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not 79 * valid. 80 * XGE_HAL_ERR_INVALID_BAR_ID - BAR id is not valid. 81 * 82 * See also: xge_hal_mgmt_reg_read(). 83 */ 84 xge_hal_status_e xge_hal_aux_bar0_read(xge_hal_device_h devh, 85 unsigned int offset, int bufsize, char *retbuf, 86 int *retsize) 87 { 88 xge_hal_status_e status; 89 u64 retval; 90 91 status = xge_hal_mgmt_reg_read(devh, 0, offset, &retval); 92 if (status != XGE_HAL_OK) { 93 return status; 94 } 95 96 if (bufsize < XGE_OS_SPRINTF_STRLEN) { 97 return XGE_HAL_ERR_OUT_OF_SPACE; 98 } 99 100 *retsize = xge_os_snprintf(retbuf, bufsize, "0x%04X%c0x%08X%08X\n", 101 offset, XGE_HAL_AUX_SEPA, (u32)(retval>>32), (u32)retval); 102 103 return XGE_HAL_OK; 104 } 105 106 /** 107 * xge_hal_aux_bar1_read - Read and format Xframe BAR1 register. 108 * @devh: HAL device handle. 109 * @offset: Register offset in the BAR1 space. 110 * @bufsize: Buffer size. 111 * @retbuf: Buffer pointer. 112 * @retsize: Size of the result. Cannot be greater than @bufsize. 113 * 114 * Read Xframe register from BAR1 space. The result is formatted as ascii string. 115 * Returns: XGE_HAL_OK - success. 116 * XGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small. 117 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 118 * XGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not 119 * valid. 120 * XGE_HAL_ERR_INVALID_BAR_ID - BAR id is not valid. 121 * 122 * See also: xge_hal_mgmt_reg_read(). 123 */ 124 xge_hal_status_e xge_hal_aux_bar1_read(xge_hal_device_h devh, 125 unsigned int offset, int bufsize, char *retbuf, 126 int *retsize) 127 { 128 xge_hal_status_e status; 129 u64 retval; 130 131 status = xge_hal_mgmt_reg_read(devh, 1, offset, &retval); 132 if (status != XGE_HAL_OK) 133 return status; 134 135 if (bufsize < XGE_OS_SPRINTF_STRLEN) 136 return XGE_HAL_ERR_OUT_OF_SPACE; 137 138 *retsize = xge_os_snprintf(retbuf, bufsize, "0x%04X%c0x%08X%08X\n", 139 offset, XGE_HAL_AUX_SEPA, (u32)(retval>>32), (u32)retval); 140 141 return XGE_HAL_OK; 142 } 143 144 /** 145 * xge_hal_aux_bar0_write - Write BAR0 register. 146 * @devh: HAL device handle. 147 * @offset: Register offset in the BAR0 space. 148 * @value: Regsister value (to write). 149 * 150 * Write BAR0 register. 151 * 152 * Returns: XGE_HAL_OK - success. 153 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 154 * XGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not 155 * valid. 156 * XGE_HAL_ERR_INVALID_BAR_ID - BAR id is not valid. 157 * 158 * See also: xge_hal_mgmt_reg_write(). 159 */ 160 xge_hal_status_e xge_hal_aux_bar0_write(xge_hal_device_h devh, 161 unsigned int offset, u64 value) 162 { 163 xge_hal_status_e status; 164 165 status = xge_hal_mgmt_reg_write(devh, 0, offset, value); 166 if (status != XGE_HAL_OK) { 167 return status; 168 } 169 170 return XGE_HAL_OK; 171 } 172 173 /** 174 * xge_hal_aux_about_read - Retrieve and format about info. 175 * @devh: HAL device handle. 176 * @bufsize: Buffer size. 177 * @retbuf: Buffer pointer. 178 * @retsize: Size of the result. Cannot be greater than @bufsize. 179 * 180 * Retrieve about info (using xge_hal_mgmt_about()) and sprintf it 181 * into the provided @retbuf. 182 * 183 * Returns: XGE_HAL_OK - success. 184 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 185 * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 186 * XGE_HAL_FAIL - Failed to retrieve the information. 187 * 188 * See also: xge_hal_mgmt_about(), xge_hal_aux_device_dump(). 189 */ 190 xge_hal_status_e xge_hal_aux_about_read(xge_hal_device_h devh, int bufsize, 191 char *retbuf, int *retsize) 192 { 193 xge_hal_status_e status; 194 xge_hal_mgmt_about_info_t about_info; 195 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 196 197 status = xge_hal_mgmt_about(devh, &about_info, 198 sizeof(xge_hal_mgmt_about_info_t)); 199 if (status != XGE_HAL_OK) { 200 return status; 201 } 202 203 __HAL_AUX_ENTRY("vendor", about_info.vendor, "0x%x"); 204 __HAL_AUX_ENTRY("device", about_info.device, "0x%x"); 205 __HAL_AUX_ENTRY("subsys_vendor", about_info.subsys_vendor, "0x%x"); 206 __HAL_AUX_ENTRY("subsys_device", about_info.subsys_device, "0x%x"); 207 __HAL_AUX_ENTRY("board_rev", about_info.board_rev, "0x%x"); 208 __HAL_AUX_ENTRY("vendor_name", about_info.vendor_name, "%s"); 209 __HAL_AUX_ENTRY("chip_name", about_info.chip_name, "%s"); 210 __HAL_AUX_ENTRY("media", about_info.media, "%s"); 211 __HAL_AUX_ENTRY("hal_major", about_info.hal_major, "%s"); 212 __HAL_AUX_ENTRY("hal_minor", about_info.hal_minor, "%s"); 213 __HAL_AUX_ENTRY("hal_fix", about_info.hal_fix, "%s"); 214 __HAL_AUX_ENTRY("hal_build", about_info.hal_build, "%s"); 215 __HAL_AUX_ENTRY("ll_major", about_info.ll_major, "%s"); 216 __HAL_AUX_ENTRY("ll_minor", about_info.ll_minor, "%s"); 217 __HAL_AUX_ENTRY("ll_fix", about_info.ll_fix, "%s"); 218 __HAL_AUX_ENTRY("ll_build", about_info.ll_build, "%s"); 219 220 __HAL_AUX_ENTRY("transponder_temperature", 221 about_info.transponder_temperature, "%d C"); 222 223 __HAL_AUX_ENTRY_END(bufsize, retsize); 224 225 return XGE_HAL_OK; 226 } 227 228 /** 229 * xge_hal_aux_stats_tmac_read - Read TMAC hardware statistics. 230 * @devh: HAL device handle. 231 * @bufsize: Buffer size. 232 * @retbuf: Buffer pointer. 233 * @retsize: Size of the result. Cannot be greater than @bufsize. 234 * 235 * Read TMAC hardware statistics. This is a subset of stats counters 236 * from xge_hal_stats_hw_info_t{}. 237 * 238 * Returns: XGE_HAL_OK - success. 239 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 240 * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 241 * 242 * See also: xge_hal_mgmt_hw_stats{}, xge_hal_stats_hw_info_t{}, 243 * xge_hal_aux_stats_pci_read(), 244 * xge_hal_aux_device_dump(). 245 */ 246 xge_hal_status_e xge_hal_aux_stats_tmac_read(xge_hal_device_h devh, int bufsize, 247 char *retbuf, int *retsize) 248 { 249 xge_hal_status_e status; 250 xge_hal_device_t *hldev = (xge_hal_device_t*)devh; 251 252 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 253 254 if (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN) { 255 xge_hal_mgmt_hw_stats_t hw; 256 257 status = xge_hal_mgmt_hw_stats(devh, &hw, 258 sizeof(xge_hal_mgmt_hw_stats_t)); 259 if (status != XGE_HAL_OK) { 260 return status; 261 } 262 263 __HAL_AUX_ENTRY("tmac_data_octets", hw.tmac_data_octets, "%u"); 264 __HAL_AUX_ENTRY("tmac_frms", hw.tmac_frms, "%u"); 265 __HAL_AUX_ENTRY("tmac_drop_frms", (unsigned long long) 266 hw.tmac_drop_frms, "%llu"); 267 __HAL_AUX_ENTRY("tmac_bcst_frms", hw.tmac_bcst_frms, "%u"); 268 __HAL_AUX_ENTRY("tmac_mcst_frms", hw.tmac_mcst_frms, "%u"); 269 __HAL_AUX_ENTRY("tmac_pause_ctrl_frms", (unsigned long long) 270 hw.tmac_pause_ctrl_frms, "%llu"); 271 __HAL_AUX_ENTRY("tmac_ucst_frms", hw.tmac_ucst_frms, "%u"); 272 __HAL_AUX_ENTRY("tmac_ttl_octets", hw.tmac_ttl_octets, "%u"); 273 __HAL_AUX_ENTRY("tmac_any_err_frms", hw.tmac_any_err_frms, "%u"); 274 __HAL_AUX_ENTRY("tmac_nucst_frms", hw.tmac_nucst_frms, "%u"); 275 __HAL_AUX_ENTRY("tmac_ttl_less_fb_octets", (unsigned long long) 276 hw.tmac_ttl_less_fb_octets, "%llu"); 277 __HAL_AUX_ENTRY("tmac_vld_ip_octets", (unsigned long long) 278 hw.tmac_vld_ip_octets, "%llu"); 279 __HAL_AUX_ENTRY("tmac_drop_ip", hw.tmac_drop_ip, "%u"); 280 __HAL_AUX_ENTRY("tmac_vld_ip", hw.tmac_vld_ip, "%u"); 281 __HAL_AUX_ENTRY("tmac_rst_tcp", hw.tmac_rst_tcp, "%u"); 282 __HAL_AUX_ENTRY("tmac_icmp", hw.tmac_icmp, "%u"); 283 __HAL_AUX_ENTRY("tmac_tcp", (unsigned long long) 284 hw.tmac_tcp, "%llu"); 285 __HAL_AUX_ENTRY("reserved_0", hw.reserved_0, "%u"); 286 __HAL_AUX_ENTRY("tmac_udp", hw.tmac_udp, "%u"); 287 } else { 288 int i; 289 xge_hal_mgmt_pcim_stats_t pcim; 290 status = xge_hal_mgmt_pcim_stats(devh, &pcim, 291 sizeof(xge_hal_mgmt_pcim_stats_t)); 292 if (status != XGE_HAL_OK) { 293 return status; 294 } 295 296 for (i = 0; i < XGE_HAL_MAC_LINKS; i++) { 297 __hal_aux_pci_link_info("tx_frms", i, 298 tx_frms); 299 __hal_aux_pci_link_info("tx_ttl_eth_octets", 300 i, tx_ttl_eth_octets ); 301 __hal_aux_pci_link_info("tx_data_octets", i, 302 tx_data_octets); 303 __hal_aux_pci_link_info("tx_mcst_frms", i, 304 tx_mcst_frms); 305 __hal_aux_pci_link_info("tx_bcst_frms", i, 306 tx_bcst_frms); 307 __hal_aux_pci_link_info("tx_ucst_frms", i, 308 tx_ucst_frms); 309 __hal_aux_pci_link_info("tx_tagged_frms", i, 310 tx_tagged_frms); 311 __hal_aux_pci_link_info("tx_vld_ip", i, 312 tx_vld_ip); 313 __hal_aux_pci_link_info("tx_vld_ip_octets", i, 314 tx_vld_ip_octets); 315 __hal_aux_pci_link_info("tx_icmp", i, 316 tx_icmp); 317 __hal_aux_pci_link_info("tx_tcp", i, 318 tx_tcp); 319 __hal_aux_pci_link_info("tx_rst_tcp", i, 320 tx_rst_tcp); 321 __hal_aux_pci_link_info("tx_udp", i, 322 tx_udp); 323 __hal_aux_pci_link_info("tx_unknown_protocol", i, 324 tx_unknown_protocol); 325 __hal_aux_pci_link_info("tx_parse_error", i, 326 tx_parse_error); 327 __hal_aux_pci_link_info("tx_pause_ctrl_frms", i, 328 tx_pause_ctrl_frms); 329 __hal_aux_pci_link_info("tx_lacpdu_frms", i, 330 tx_lacpdu_frms); 331 __hal_aux_pci_link_info("tx_marker_pdu_frms", i, 332 tx_marker_pdu_frms); 333 __hal_aux_pci_link_info("tx_marker_resp_pdu_frms", i, 334 tx_marker_resp_pdu_frms); 335 __hal_aux_pci_link_info("tx_drop_ip", i, 336 tx_drop_ip); 337 __hal_aux_pci_link_info("tx_xgmii_char1_match", i, 338 tx_xgmii_char1_match); 339 __hal_aux_pci_link_info("tx_xgmii_char2_match", i, 340 tx_xgmii_char2_match); 341 __hal_aux_pci_link_info("tx_xgmii_column1_match", i, 342 tx_xgmii_column1_match); 343 __hal_aux_pci_link_info("tx_xgmii_column2_match", i, 344 tx_xgmii_column2_match); 345 __hal_aux_pci_link_info("tx_drop_frms", i, 346 tx_drop_frms); 347 __hal_aux_pci_link_info("tx_any_err_frms", i, 348 tx_any_err_frms); 349 } 350 351 for (i = 0; i < XGE_HAL_MAC_AGGREGATORS; i++) { 352 __hal_aux_pci_aggr_info("tx_frms", i, tx_frms); 353 __hal_aux_pci_aggr_info("tx_mcst_frms", i, 354 tx_mcst_frms); 355 __hal_aux_pci_aggr_info("tx_bcst_frms", i, 356 tx_bcst_frms); 357 __hal_aux_pci_aggr_info("tx_discarded_frms", i, 358 tx_discarded_frms); 359 __hal_aux_pci_aggr_info("tx_errored_frms", i, 360 tx_errored_frms); 361 } 362 } 363 364 __HAL_AUX_ENTRY_END(bufsize, retsize); 365 366 return XGE_HAL_OK; 367 } 368 369 /** 370 * xge_hal_aux_stats_rmac_read - Read RMAC hardware statistics. 371 * @devh: HAL device handle. 372 * @bufsize: Buffer size. 373 * @retbuf: Buffer pointer. 374 * @retsize: Size of the result. Cannot be greater than @bufsize. 375 * 376 * Read RMAC hardware statistics. This is a subset of stats counters 377 * from xge_hal_stats_hw_info_t{}. 378 * 379 * Returns: XGE_HAL_OK - success. 380 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 381 * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 382 * 383 * See also: xge_hal_mgmt_hw_stats{}, xge_hal_stats_hw_info_t{}, 384 * xge_hal_aux_stats_pci_read(), xge_hal_aux_stats_tmac_read(), 385 * xge_hal_aux_device_dump(). 386 */ 387 xge_hal_status_e xge_hal_aux_stats_rmac_read(xge_hal_device_h devh, int bufsize, 388 char *retbuf, int *retsize) 389 { 390 xge_hal_status_e status; 391 xge_hal_device_t *hldev = (xge_hal_device_t*)devh; 392 393 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 394 395 if (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN) { 396 xge_hal_mgmt_hw_stats_t hw; 397 398 status = xge_hal_mgmt_hw_stats(devh, &hw, 399 sizeof(xge_hal_mgmt_hw_stats_t)); 400 if (status != XGE_HAL_OK) { 401 return status; 402 } 403 404 __HAL_AUX_ENTRY("rmac_data_octets", hw.rmac_data_octets, "%u"); 405 __HAL_AUX_ENTRY("rmac_vld_frms", hw.rmac_vld_frms, "%u"); 406 __HAL_AUX_ENTRY("rmac_fcs_err_frms", (unsigned long long) 407 hw.rmac_fcs_err_frms, "%llu"); 408 __HAL_AUX_ENTRY("mac_drop_frms", (unsigned long long) 409 hw.rmac_drop_frms, "%llu"); 410 __HAL_AUX_ENTRY("rmac_vld_bcst_frms", hw.rmac_vld_bcst_frms, 411 "%u"); 412 __HAL_AUX_ENTRY("rmac_vld_mcst_frms", hw.rmac_vld_mcst_frms, 413 "%u"); 414 __HAL_AUX_ENTRY("rmac_out_rng_len_err_frms", 415 hw.rmac_out_rng_len_err_frms, "%u"); 416 __HAL_AUX_ENTRY("rmac_in_rng_len_err_frms", 417 hw.rmac_in_rng_len_err_frms, "%u"); 418 __HAL_AUX_ENTRY("rmac_long_frms", (unsigned long long) 419 hw.rmac_long_frms, "%llu"); 420 __HAL_AUX_ENTRY("rmac_pause_ctrl_frms", (unsigned long long) 421 hw.rmac_pause_ctrl_frms, "%llu"); 422 __HAL_AUX_ENTRY("rmac_unsup_ctrl_frms", (unsigned long long) 423 hw.rmac_unsup_ctrl_frms, "%llu"); 424 __HAL_AUX_ENTRY("rmac_accepted_ucst_frms", 425 hw.rmac_accepted_ucst_frms, "%u"); 426 __HAL_AUX_ENTRY("rmac_ttl_octets", hw.rmac_ttl_octets, "%u"); 427 __HAL_AUX_ENTRY("rmac_discarded_frms", hw.rmac_discarded_frms, 428 "%u"); 429 __HAL_AUX_ENTRY("rmac_accepted_nucst_frms", 430 hw.rmac_accepted_nucst_frms, "%u"); 431 __HAL_AUX_ENTRY("reserved_1", hw.reserved_1, "%u"); 432 __HAL_AUX_ENTRY("rmac_drop_events", hw.rmac_drop_events, "%u"); 433 __HAL_AUX_ENTRY("rmac_ttl_less_fb_octets", (unsigned long long) 434 hw.rmac_ttl_less_fb_octets, "%llu"); 435 __HAL_AUX_ENTRY("rmac_ttl_frms", (unsigned long long) 436 hw.rmac_ttl_frms, "%llu"); 437 __HAL_AUX_ENTRY("reserved_2", (unsigned long long) 438 hw.reserved_2, "%llu"); 439 __HAL_AUX_ENTRY("rmac_usized_frms", hw.rmac_usized_frms, "%u"); 440 __HAL_AUX_ENTRY("reserved_3", hw.reserved_3, "%u"); 441 __HAL_AUX_ENTRY("rmac_frag_frms", hw.rmac_frag_frms, "%u"); 442 __HAL_AUX_ENTRY("rmac_osized_frms", hw.rmac_osized_frms, "%u"); 443 __HAL_AUX_ENTRY("reserved_4", hw.reserved_4, "%u"); 444 __HAL_AUX_ENTRY("rmac_jabber_frms", hw.rmac_jabber_frms, "%u"); 445 __HAL_AUX_ENTRY("rmac_ttl_64_frms", (unsigned long long) 446 hw.rmac_ttl_64_frms, "%llu"); 447 __HAL_AUX_ENTRY("rmac_ttl_65_127_frms", (unsigned long long) 448 hw.rmac_ttl_65_127_frms, "%llu"); 449 __HAL_AUX_ENTRY("reserved_5", (unsigned long long) 450 hw.reserved_5, "%llu"); 451 __HAL_AUX_ENTRY("rmac_ttl_128_255_frms", (unsigned long long) 452 hw.rmac_ttl_128_255_frms, "%llu"); 453 __HAL_AUX_ENTRY("rmac_ttl_256_511_frms", (unsigned long long) 454 hw.rmac_ttl_256_511_frms, "%llu"); 455 __HAL_AUX_ENTRY("reserved_6", (unsigned long long) 456 hw.reserved_6, "%llu"); 457 __HAL_AUX_ENTRY("rmac_ttl_512_1023_frms", (unsigned long long) 458 hw.rmac_ttl_512_1023_frms, "%llu"); 459 __HAL_AUX_ENTRY("rmac_ttl_1024_1518_frms", (unsigned long long) 460 hw.rmac_ttl_1024_1518_frms, "%llu"); 461 __HAL_AUX_ENTRY("rmac_ip", hw.rmac_ip, "%u"); 462 __HAL_AUX_ENTRY("reserved_7", hw.reserved_7, "%u"); 463 __HAL_AUX_ENTRY("rmac_ip_octets", (unsigned long long) 464 hw.rmac_ip_octets, "%llu"); 465 __HAL_AUX_ENTRY("rmac_drop_ip", hw.rmac_drop_ip, "%u"); 466 __HAL_AUX_ENTRY("rmac_hdr_err_ip", hw.rmac_hdr_err_ip, "%u"); 467 __HAL_AUX_ENTRY("reserved_8", hw.reserved_8, "%u"); 468 __HAL_AUX_ENTRY("rmac_icmp", hw.rmac_icmp, "%u"); 469 __HAL_AUX_ENTRY("rmac_tcp", (unsigned long long) 470 hw.rmac_tcp, "%llu"); 471 __HAL_AUX_ENTRY("rmac_err_drp_udp", hw.rmac_err_drp_udp, "%u"); 472 __HAL_AUX_ENTRY("rmac_udp", hw.rmac_udp, "%u"); 473 __HAL_AUX_ENTRY("rmac_xgmii_err_sym", (unsigned long long) 474 hw.rmac_xgmii_err_sym, "%llu"); 475 __HAL_AUX_ENTRY("rmac_frms_q0", (unsigned long long) 476 hw.rmac_frms_q0, "%llu"); 477 __HAL_AUX_ENTRY("rmac_frms_q1", (unsigned long long) 478 hw.rmac_frms_q1, "%llu"); 479 __HAL_AUX_ENTRY("rmac_frms_q2", (unsigned long long) 480 hw.rmac_frms_q2, "%llu"); 481 __HAL_AUX_ENTRY("rmac_frms_q3", (unsigned long long) 482 hw.rmac_frms_q3, "%llu"); 483 __HAL_AUX_ENTRY("rmac_frms_q4", (unsigned long long) 484 hw.rmac_frms_q4, "%llu"); 485 __HAL_AUX_ENTRY("rmac_frms_q5", (unsigned long long) 486 hw.rmac_frms_q5, "%llu"); 487 __HAL_AUX_ENTRY("rmac_frms_q6", (unsigned long long) 488 hw.rmac_frms_q6, "%llu"); 489 __HAL_AUX_ENTRY("rmac_frms_q7", (unsigned long long) 490 hw.rmac_frms_q7, "%llu"); 491 __HAL_AUX_ENTRY("rmac_full_q3", hw.rmac_full_q3, "%d"); 492 __HAL_AUX_ENTRY("rmac_full_q2", hw.rmac_full_q2, "%d"); 493 __HAL_AUX_ENTRY("rmac_full_q1", hw.rmac_full_q1, "%d"); 494 __HAL_AUX_ENTRY("rmac_full_q0", hw.rmac_full_q0, "%d"); 495 __HAL_AUX_ENTRY("rmac_full_q7", hw.rmac_full_q7, "%d"); 496 __HAL_AUX_ENTRY("rmac_full_q6", hw.rmac_full_q6, "%d"); 497 __HAL_AUX_ENTRY("rmac_full_q5", hw.rmac_full_q5, "%d"); 498 __HAL_AUX_ENTRY("rmac_full_q4", hw.rmac_full_q4, "%d"); 499 __HAL_AUX_ENTRY("reserved_9", hw.reserved_9, "%u"); 500 __HAL_AUX_ENTRY("rmac_pause_cnt", hw.rmac_pause_cnt, "%u"); 501 __HAL_AUX_ENTRY("rmac_xgmii_data_err_cnt", (unsigned long long) 502 hw.rmac_xgmii_data_err_cnt, "%llu"); 503 __HAL_AUX_ENTRY("rmac_xgmii_ctrl_err_cnt", (unsigned long long) 504 hw.rmac_xgmii_ctrl_err_cnt, "%llu"); 505 __HAL_AUX_ENTRY("rmac_err_tcp", hw.rmac_err_tcp, "%u"); 506 __HAL_AUX_ENTRY("rmac_accepted_ip", hw.rmac_accepted_ip, "%u"); 507 } else { 508 int i; 509 xge_hal_mgmt_pcim_stats_t pcim; 510 status = xge_hal_mgmt_pcim_stats(devh, &pcim, 511 sizeof(xge_hal_mgmt_pcim_stats_t)); 512 if (status != XGE_HAL_OK) { 513 return status; 514 } 515 for (i = 0; i < XGE_HAL_MAC_LINKS; i++) { 516 __hal_aux_pci_link_info("rx_ttl_frms", i, 517 rx_ttl_frms); 518 __hal_aux_pci_link_info("rx_vld_frms", i, 519 rx_vld_frms); 520 __hal_aux_pci_link_info("rx_offld_frms", i, 521 rx_offld_frms); 522 __hal_aux_pci_link_info("rx_ttl_eth_octets", i, 523 rx_ttl_eth_octets); 524 __hal_aux_pci_link_info("rx_data_octets", i, 525 rx_data_octets); 526 __hal_aux_pci_link_info("rx_offld_octets", i, 527 rx_offld_octets); 528 __hal_aux_pci_link_info("rx_vld_mcst_frms", i, 529 rx_vld_mcst_frms); 530 __hal_aux_pci_link_info("rx_vld_bcst_frms", i, 531 rx_vld_bcst_frms); 532 __hal_aux_pci_link_info("rx_accepted_ucst_frms", i, 533 rx_accepted_ucst_frms); 534 __hal_aux_pci_link_info("rx_accepted_nucst_frms", i, 535 rx_accepted_nucst_frms); 536 __hal_aux_pci_link_info("rx_tagged_frms", i, 537 rx_tagged_frms); 538 __hal_aux_pci_link_info("rx_long_frms", i, 539 rx_long_frms); 540 __hal_aux_pci_link_info("rx_usized_frms", i, 541 rx_usized_frms); 542 __hal_aux_pci_link_info("rx_osized_frms", i, 543 rx_osized_frms); 544 __hal_aux_pci_link_info("rx_frag_frms", i, 545 rx_frag_frms); 546 __hal_aux_pci_link_info("rx_jabber_frms", i, 547 rx_jabber_frms); 548 __hal_aux_pci_link_info("rx_ttl_64_frms", i, 549 rx_ttl_64_frms); 550 __hal_aux_pci_link_info("rx_ttl_65_127_frms", i, 551 rx_ttl_65_127_frms); 552 __hal_aux_pci_link_info("rx_ttl_128_255_frms", i, 553 rx_ttl_128_255_frms); 554 __hal_aux_pci_link_info("rx_ttl_256_511_frms", i, 555 rx_ttl_256_511_frms); 556 __hal_aux_pci_link_info("rx_ttl_512_1023_frms", i, 557 rx_ttl_512_1023_frms); 558 __hal_aux_pci_link_info("rx_ttl_1024_1518_frms", i, 559 rx_ttl_1024_1518_frms); 560 __hal_aux_pci_link_info("rx_ttl_1519_4095_frms", i, 561 rx_ttl_1519_4095_frms); 562 __hal_aux_pci_link_info("rx_ttl_40956_8191_frms", i, 563 rx_ttl_40956_8191_frms); 564 __hal_aux_pci_link_info("rx_ttl_8192_max_frms", i, 565 rx_ttl_8192_max_frms); 566 __hal_aux_pci_link_info("rx_ttl_gt_max_frms", i, 567 rx_ttl_gt_max_frms); 568 __hal_aux_pci_link_info("rx_ip", i, 569 rx_ip); 570 __hal_aux_pci_link_info("rx_ip_octets", i, 571 rx_ip_octets); 572 573 __hal_aux_pci_link_info("rx_hdr_err_ip", i, 574 rx_hdr_err_ip); 575 576 __hal_aux_pci_link_info("rx_icmp", i, 577 rx_icmp); 578 __hal_aux_pci_link_info("rx_tcp", i, 579 rx_tcp); 580 __hal_aux_pci_link_info("rx_udp", i, 581 rx_udp); 582 __hal_aux_pci_link_info("rx_err_tcp", i, 583 rx_err_tcp); 584 __hal_aux_pci_link_info("rx_pause_cnt", i, 585 rx_pause_cnt); 586 __hal_aux_pci_link_info("rx_pause_ctrl_frms", i, 587 rx_pause_ctrl_frms); 588 __hal_aux_pci_link_info("rx_unsup_ctrl_frms", i, 589 rx_pause_cnt); 590 __hal_aux_pci_link_info("rx_in_rng_len_err_frms", i, 591 rx_in_rng_len_err_frms); 592 __hal_aux_pci_link_info("rx_out_rng_len_err_frms", i, 593 rx_out_rng_len_err_frms); 594 __hal_aux_pci_link_info("rx_drop_frms", i, 595 rx_drop_frms); 596 __hal_aux_pci_link_info("rx_discarded_frms", i, 597 rx_discarded_frms); 598 __hal_aux_pci_link_info("rx_drop_ip", i, 599 rx_drop_ip); 600 __hal_aux_pci_link_info("rx_err_drp_udp", i, 601 rx_err_drp_udp); 602 __hal_aux_pci_link_info("rx_lacpdu_frms", i, 603 rx_lacpdu_frms); 604 __hal_aux_pci_link_info("rx_marker_pdu_frms", i, 605 rx_marker_pdu_frms); 606 __hal_aux_pci_link_info("rx_marker_resp_pdu_frms", i, 607 rx_marker_resp_pdu_frms); 608 __hal_aux_pci_link_info("rx_unknown_pdu_frms", i, 609 rx_unknown_pdu_frms); 610 __hal_aux_pci_link_info("rx_illegal_pdu_frms", i, 611 rx_illegal_pdu_frms); 612 __hal_aux_pci_link_info("rx_fcs_discard", i, 613 rx_fcs_discard); 614 __hal_aux_pci_link_info("rx_len_discard", i, 615 rx_len_discard); 616 __hal_aux_pci_link_info("rx_pf_discard", i, 617 rx_pf_discard); 618 __hal_aux_pci_link_info("rx_trash_discard", i, 619 rx_trash_discard); 620 __hal_aux_pci_link_info("rx_rts_discard", i, 621 rx_trash_discard); 622 __hal_aux_pci_link_info("rx_wol_discard", i, 623 rx_wol_discard); 624 __hal_aux_pci_link_info("rx_red_discard", i, 625 rx_red_discard); 626 __hal_aux_pci_link_info("rx_ingm_full_discard", i, 627 rx_ingm_full_discard); 628 __hal_aux_pci_link_info("rx_xgmii_data_err_cnt", i, 629 rx_xgmii_data_err_cnt); 630 __hal_aux_pci_link_info("rx_xgmii_ctrl_err_cnt", i, 631 rx_xgmii_ctrl_err_cnt); 632 __hal_aux_pci_link_info("rx_xgmii_err_sym", i, 633 rx_xgmii_err_sym); 634 __hal_aux_pci_link_info("rx_xgmii_char1_match", i, 635 rx_xgmii_char1_match); 636 __hal_aux_pci_link_info("rx_xgmii_char2_match", i, 637 rx_xgmii_char2_match); 638 __hal_aux_pci_link_info("rx_xgmii_column1_match", i, 639 rx_xgmii_column1_match); 640 __hal_aux_pci_link_info("rx_xgmii_column2_match", i, 641 rx_xgmii_column2_match); 642 __hal_aux_pci_link_info("rx_local_fault", i, 643 rx_local_fault); 644 __hal_aux_pci_link_info("rx_remote_fault", i, 645 rx_remote_fault); 646 __hal_aux_pci_link_info("rx_queue_full", i, 647 rx_queue_full); 648 } 649 for (i = 0; i < XGE_HAL_MAC_AGGREGATORS; i++) { 650 __hal_aux_pci_aggr_info("rx_frms", i, rx_frms); 651 __hal_aux_pci_link_info("rx_data_octets", i, 652 rx_data_octets); 653 __hal_aux_pci_aggr_info("rx_mcst_frms", i, 654 rx_mcst_frms); 655 __hal_aux_pci_aggr_info("rx_bcst_frms", i, 656 rx_bcst_frms); 657 __hal_aux_pci_aggr_info("rx_discarded_frms", i, 658 rx_discarded_frms); 659 __hal_aux_pci_aggr_info("rx_errored_frms", i, 660 rx_errored_frms); 661 __hal_aux_pci_aggr_info("rx_unknown_protocol_frms", i, 662 rx_unknown_protocol_frms); 663 } 664 665 } 666 __HAL_AUX_ENTRY_END(bufsize, retsize); 667 668 return XGE_HAL_OK; 669 } 670 671 /** 672 * xge_hal_aux_stats_herc_enchanced - Get Hercules hardware statistics. 673 * @devh: HAL device handle. 674 * @bufsize: Buffer size. 675 * @retbuf: Buffer pointer. 676 * @retsize: Size of the result. Cannot be greater than @bufsize. 677 * 678 * Read Hercules device hardware statistics. 679 * 680 * Returns: XGE_HAL_OK - success. 681 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 682 * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 683 * 684 * See also: xge_hal_mgmt_hw_stats{}, xge_hal_stats_hw_info_t{}, 685 * xge_hal_aux_stats_tmac_read(), xge_hal_aux_stats_rmac_read(), 686 * xge_hal_aux_device_dump(). 687 */ 688 xge_hal_status_e xge_hal_aux_stats_herc_enchanced(xge_hal_device_h devh, 689 int bufsize, char *retbuf, int *retsize) 690 { 691 xge_hal_status_e status; 692 xge_hal_mgmt_hw_stats_t hw; 693 xge_hal_device_t *hldev = (xge_hal_device_t*)devh; 694 695 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 696 697 if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_TITAN) { 698 699 __HAL_AUX_ENTRY_END(bufsize, retsize); 700 701 return XGE_HAL_OK; 702 } 703 704 705 status = xge_hal_mgmt_hw_stats(devh, &hw, 706 sizeof(xge_hal_mgmt_hw_stats_t)); 707 if (status != XGE_HAL_OK) { 708 return status; 709 } 710 __HAL_AUX_ENTRY("tmac_frms_oflow", hw.tmac_frms_oflow, "%u"); 711 __HAL_AUX_ENTRY("tmac_data_octets_oflow", hw.tmac_data_octets_oflow, 712 "%u"); 713 __HAL_AUX_ENTRY("tmac_mcst_frms_oflow", hw.tmac_mcst_frms_oflow, "%u"); 714 __HAL_AUX_ENTRY("tmac_bcst_frms_oflow", hw.tmac_bcst_frms_oflow, "%u"); 715 __HAL_AUX_ENTRY("tmac_ttl_octets_oflow", hw.tmac_ttl_octets_oflow, 716 "%u"); 717 __HAL_AUX_ENTRY("tmac_ucst_frms_oflow", hw.tmac_ucst_frms_oflow, "%u"); 718 __HAL_AUX_ENTRY("tmac_nucst_frms_oflow", hw.tmac_nucst_frms_oflow, 719 "%u"); 720 __HAL_AUX_ENTRY("tmac_any_err_frms_oflow", hw.tmac_any_err_frms_oflow, 721 "%u"); 722 __HAL_AUX_ENTRY("tmac_vlan_frms", (unsigned long long)hw.tmac_vlan_frms, 723 "%llu"); 724 __HAL_AUX_ENTRY("tmac_vld_ip_oflow", hw.tmac_vld_ip_oflow, "%u"); 725 __HAL_AUX_ENTRY("tmac_drop_ip_oflow", hw.tmac_drop_ip_oflow, "%u"); 726 __HAL_AUX_ENTRY("tmac_icmp_oflow", hw.tmac_icmp_oflow, "%u"); 727 __HAL_AUX_ENTRY("tmac_rst_tcp_oflow", hw.tmac_rst_tcp_oflow, "%u"); 728 __HAL_AUX_ENTRY("tmac_udp_oflow", hw.tmac_udp_oflow, "%u"); 729 __HAL_AUX_ENTRY("tpa_unknown_protocol", hw.tpa_unknown_protocol, "%u"); 730 __HAL_AUX_ENTRY("tpa_parse_failure", hw.tpa_parse_failure, "%u"); 731 __HAL_AUX_ENTRY("rmac_vld_frms_oflow", hw.rmac_vld_frms_oflow, "%u"); 732 __HAL_AUX_ENTRY("rmac_data_octets_oflow", hw.rmac_data_octets_oflow, 733 "%u"); 734 __HAL_AUX_ENTRY("rmac_vld_mcst_frms_oflow", hw.rmac_vld_mcst_frms_oflow, 735 "%u"); 736 __HAL_AUX_ENTRY("rmac_vld_bcst_frms_oflow", hw.rmac_vld_bcst_frms_oflow, 737 "%u"); 738 __HAL_AUX_ENTRY("rmac_ttl_octets_oflow", hw.rmac_ttl_octets_oflow, 739 "%u"); 740 __HAL_AUX_ENTRY("rmac_accepted_ucst_frms_oflow", 741 hw.rmac_accepted_ucst_frms_oflow, "%u"); 742 __HAL_AUX_ENTRY("rmac_accepted_nucst_frms_oflow", 743 hw.rmac_accepted_nucst_frms_oflow, "%u"); 744 __HAL_AUX_ENTRY("rmac_discarded_frms_oflow", 745 hw.rmac_discarded_frms_oflow, "%u"); 746 __HAL_AUX_ENTRY("rmac_drop_events_oflow", hw.rmac_drop_events_oflow, 747 "%u"); 748 __HAL_AUX_ENTRY("rmac_usized_frms_oflow", hw.rmac_usized_frms_oflow, 749 "%u"); 750 __HAL_AUX_ENTRY("rmac_osized_frms_oflow", hw.rmac_osized_frms_oflow, 751 "%u"); 752 __HAL_AUX_ENTRY("rmac_frag_frms_oflow", hw.rmac_frag_frms_oflow, "%u"); 753 __HAL_AUX_ENTRY("rmac_jabber_frms_oflow", hw.rmac_jabber_frms_oflow, 754 "%u"); 755 __HAL_AUX_ENTRY("rmac_ip_oflow", hw.rmac_ip_oflow, "%u"); 756 __HAL_AUX_ENTRY("rmac_drop_ip_oflow", hw.rmac_drop_ip_oflow, "%u"); 757 __HAL_AUX_ENTRY("rmac_icmp_oflow", hw.rmac_icmp_oflow, "%u"); 758 __HAL_AUX_ENTRY("rmac_udp_oflow", hw.rmac_udp_oflow, "%u"); 759 __HAL_AUX_ENTRY("rmac_err_drp_udp_oflow", hw.rmac_err_drp_udp_oflow, 760 "%u"); 761 __HAL_AUX_ENTRY("rmac_pause_cnt_oflow", hw.rmac_pause_cnt_oflow, "%u"); 762 __HAL_AUX_ENTRY("rmac_ttl_1519_4095_frms", 763 (unsigned long long)hw.rmac_ttl_1519_4095_frms, "%llu"); 764 __HAL_AUX_ENTRY("rmac_ttl_4096_8191_frms", 765 (unsigned long long)hw.rmac_ttl_4096_8191_frms, "%llu"); 766 __HAL_AUX_ENTRY("rmac_ttl_8192_max_frms", 767 (unsigned long long)hw.rmac_ttl_8192_max_frms, "%llu"); 768 __HAL_AUX_ENTRY("rmac_ttl_gt_max_frms", 769 (unsigned long long)hw.rmac_ttl_gt_max_frms, "%llu"); 770 __HAL_AUX_ENTRY("rmac_osized_alt_frms", 771 (unsigned long long)hw.rmac_osized_alt_frms, "%llu"); 772 __HAL_AUX_ENTRY("rmac_jabber_alt_frms", 773 (unsigned long long)hw.rmac_jabber_alt_frms, "%llu"); 774 __HAL_AUX_ENTRY("rmac_gt_max_alt_frms", 775 (unsigned long long)hw.rmac_gt_max_alt_frms, "%llu"); 776 __HAL_AUX_ENTRY("rmac_vlan_frms", 777 (unsigned long long)hw.rmac_vlan_frms, "%llu"); 778 __HAL_AUX_ENTRY("rmac_fcs_discard", hw.rmac_fcs_discard, "%u"); 779 __HAL_AUX_ENTRY("rmac_len_discard", hw.rmac_len_discard, "%u"); 780 __HAL_AUX_ENTRY("rmac_da_discard", hw.rmac_da_discard, "%u"); 781 __HAL_AUX_ENTRY("rmac_pf_discard", hw.rmac_pf_discard, "%u"); 782 __HAL_AUX_ENTRY("rmac_rts_discard", hw.rmac_rts_discard, "%u"); 783 __HAL_AUX_ENTRY("rmac_red_discard", hw.rmac_red_discard, "%u"); 784 __HAL_AUX_ENTRY("rmac_ingm_full_discard", hw.rmac_ingm_full_discard, 785 "%u"); 786 __HAL_AUX_ENTRY("rmac_accepted_ip_oflow", hw.rmac_accepted_ip_oflow, 787 "%u"); 788 __HAL_AUX_ENTRY("link_fault_cnt", hw.link_fault_cnt, "%u"); 789 790 __HAL_AUX_ENTRY_END(bufsize, retsize); 791 792 return XGE_HAL_OK; 793 } 794 795 /** 796 * xge_hal_aux_stats_rmac_read - Read PCI hardware statistics. 797 * @devh: HAL device handle. 798 * @bufsize: Buffer size. 799 * @retbuf: Buffer pointer. 800 * @retsize: Size of the result. Cannot be greater than @bufsize. 801 * 802 * Read PCI statistics counters, including number of PCI read and 803 * write transactions, PCI retries, discards, etc. 804 * This is a subset of stats counters from xge_hal_stats_hw_info_t{}. 805 * 806 * Returns: XGE_HAL_OK - success. 807 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 808 * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 809 * 810 * See also: xge_hal_mgmt_hw_stats{}, xge_hal_stats_hw_info_t{}, 811 * xge_hal_aux_stats_tmac_read(), xge_hal_aux_stats_rmac_read(), 812 * xge_hal_aux_device_dump(). 813 */ 814 xge_hal_status_e xge_hal_aux_stats_pci_read(xge_hal_device_h devh, int bufsize, 815 char *retbuf, int *retsize) 816 { 817 xge_hal_status_e status; 818 xge_hal_mgmt_hw_stats_t hw; 819 xge_hal_device_t *hldev = (xge_hal_device_t*)devh; 820 821 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 822 823 if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_TITAN) { 824 825 __HAL_AUX_ENTRY_END(bufsize, retsize); 826 827 return XGE_HAL_OK; 828 } 829 830 831 status = xge_hal_mgmt_hw_stats(devh, &hw, 832 sizeof(xge_hal_mgmt_hw_stats_t)); 833 if (status != XGE_HAL_OK) { 834 return status; 835 } 836 837 __HAL_AUX_ENTRY("new_rd_req_cnt", hw.new_rd_req_cnt, "%u"); 838 __HAL_AUX_ENTRY("rd_req_cnt", hw.rd_req_cnt, "%u"); 839 __HAL_AUX_ENTRY("rd_rtry_cnt", hw.rd_rtry_cnt, "%u"); 840 __HAL_AUX_ENTRY("new_rd_req_rtry_cnt", hw.new_rd_req_rtry_cnt, "%u"); 841 __HAL_AUX_ENTRY("wr_req_cnt", hw.wr_req_cnt, "%u"); 842 __HAL_AUX_ENTRY("wr_rtry_rd_ack_cnt", hw.wr_rtry_rd_ack_cnt, "%u"); 843 __HAL_AUX_ENTRY("new_wr_req_rtry_cnt", hw.new_wr_req_rtry_cnt, "%u"); 844 __HAL_AUX_ENTRY("new_wr_req_cnt", hw.new_wr_req_cnt, "%u"); 845 __HAL_AUX_ENTRY("wr_disc_cnt", hw.wr_disc_cnt, "%u"); 846 __HAL_AUX_ENTRY("wr_rtry_cnt", hw.wr_rtry_cnt, "%u"); 847 __HAL_AUX_ENTRY("txp_wr_cnt", hw.txp_wr_cnt, "%u"); 848 __HAL_AUX_ENTRY("rd_rtry_wr_ack_cnt", hw.rd_rtry_wr_ack_cnt, "%u"); 849 __HAL_AUX_ENTRY("txd_wr_cnt", hw.txd_wr_cnt, "%u"); 850 __HAL_AUX_ENTRY("txd_rd_cnt", hw.txd_rd_cnt, "%u"); 851 __HAL_AUX_ENTRY("rxd_wr_cnt", hw.rxd_wr_cnt, "%u"); 852 __HAL_AUX_ENTRY("rxd_rd_cnt", hw.rxd_rd_cnt, "%u"); 853 __HAL_AUX_ENTRY("rxf_wr_cnt", hw.rxf_wr_cnt, "%u"); 854 __HAL_AUX_ENTRY("txf_rd_cnt", hw.txf_rd_cnt, "%u"); 855 856 __HAL_AUX_ENTRY_END(bufsize, retsize); 857 858 return XGE_HAL_OK; 859 } 860 861 /** 862 * xge_hal_aux_stats_hal_read - Read HAL (layer) statistics. 863 * @devh: HAL device handle. 864 * @bufsize: Buffer size. 865 * @retbuf: Buffer pointer. 866 * @retsize: Size of the result. Cannot be greater than @bufsize. 867 * 868 * Read HAL statistics. 869 * 870 * Returns: XGE_HAL_OK - success. 871 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 872 * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 873 * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not 874 * currently available. 875 * 876 * See also: xge_hal_aux_device_dump(). 877 */ 878 xge_hal_status_e xge_hal_aux_stats_hal_read(xge_hal_device_h devh, 879 int bufsize, char *retbuf, int *retsize) 880 { 881 xge_list_t *item; 882 xge_hal_channel_t *channel; 883 xge_hal_device_t *hldev = (xge_hal_device_t*)devh; 884 xge_hal_status_e status; 885 xge_hal_mgmt_device_stats_t devstat; 886 xge_hal_mgmt_channel_stats_t chstat; 887 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 888 889 int dest_size; 890 char *dest_addr; 891 char key[XGE_OS_SPRINTF_STRLEN]; 892 893 status = xge_hal_mgmt_device_stats(hldev, &devstat, 894 sizeof(xge_hal_mgmt_device_stats_t)); 895 if (status != XGE_HAL_OK) { 896 return status; 897 } 898 899 if (!hldev->config.bimodal_interrupts) { 900 __HAL_AUX_ENTRY("rx_traffic_intr_cnt", 901 devstat.rx_traffic_intr_cnt, "%u"); 902 } 903 __HAL_AUX_ENTRY("tx_traffic_intr_cnt", devstat.tx_traffic_intr_cnt, "%u"); 904 __HAL_AUX_ENTRY("txpic_intr_cnt", devstat.txpic_intr_cnt, "%u"); 905 __HAL_AUX_ENTRY("txdma_intr_cnt", devstat.txdma_intr_cnt, "%u"); 906 __HAL_AUX_ENTRY("txmac_intr_cnt", devstat.txmac_intr_cnt, "%u"); 907 __HAL_AUX_ENTRY("txxgxs_intr_cnt", devstat.txxgxs_intr_cnt, "%u"); 908 __HAL_AUX_ENTRY("rxpic_intr_cnt", devstat.rxpic_intr_cnt, "%u"); 909 __HAL_AUX_ENTRY("rxdma_intr_cnt", devstat.rxdma_intr_cnt, "%u"); 910 __HAL_AUX_ENTRY("rxmac_intr_cnt", devstat.rxmac_intr_cnt, "%u"); 911 __HAL_AUX_ENTRY("rxxgxs_intr_cnt", devstat.rxxgxs_intr_cnt, "%u"); 912 __HAL_AUX_ENTRY("mc_intr_cnt", devstat.mc_intr_cnt, "%u"); 913 __HAL_AUX_ENTRY("not_xge_intr_cnt", devstat.not_xge_intr_cnt, "%u"); 914 __HAL_AUX_ENTRY("not_traffic_intr_cnt", 915 devstat.not_traffic_intr_cnt, "%u"); 916 __HAL_AUX_ENTRY("traffic_intr_cnt", devstat.traffic_intr_cnt, "%u"); 917 __HAL_AUX_ENTRY("total_intr_cnt", devstat.total_intr_cnt, "%u"); 918 __HAL_AUX_ENTRY("soft_reset_cnt", devstat.soft_reset_cnt, "%u"); 919 920 if (hldev->config.rxufca_hi_lim != hldev->config.rxufca_lo_lim && 921 hldev->config.rxufca_lo_lim != 0) { 922 __HAL_AUX_ENTRY("rxufca_lo_adjust_cnt", 923 devstat.rxufca_lo_adjust_cnt, "%u"); 924 __HAL_AUX_ENTRY("rxufca_hi_adjust_cnt", 925 devstat.rxufca_hi_adjust_cnt, "%u"); 926 } 927 928 if (hldev->config.bimodal_interrupts) { 929 __HAL_AUX_ENTRY("bimodal_lo_adjust_cnt", 930 devstat.bimodal_lo_adjust_cnt, "%u"); 931 __HAL_AUX_ENTRY("bimodal_hi_adjust_cnt", 932 devstat.bimodal_hi_adjust_cnt, "%u"); 933 } 934 935 #if defined(XGE_HAL_CONFIG_LRO) 936 __HAL_AUX_ENTRY("tot_frms_lroised", 937 devstat.tot_frms_lroised, "%u"); 938 __HAL_AUX_ENTRY("tot_lro_sessions", 939 devstat.tot_lro_sessions, "%u"); 940 __HAL_AUX_ENTRY("lro_frm_len_exceed_cnt", 941 devstat.lro_frm_len_exceed_cnt, "%u"); 942 __HAL_AUX_ENTRY("lro_sg_exceed_cnt", 943 devstat.lro_sg_exceed_cnt, "%u"); 944 __HAL_AUX_ENTRY("lro_out_of_seq_pkt_cnt", 945 devstat.lro_out_of_seq_pkt_cnt, "%u"); 946 __HAL_AUX_ENTRY("lro_dup_pkt_cnt", 947 devstat.lro_dup_pkt_cnt, "%u"); 948 #endif 949 950 /* for each opened rx channel */ 951 xge_list_for_each(item, &hldev->ring_channels) { 952 channel = xge_container_of(item, xge_hal_channel_t, item); 953 status = xge_hal_mgmt_channel_stats(channel, &chstat, 954 sizeof(xge_hal_mgmt_channel_stats_t)); 955 if (status != XGE_HAL_OK) { 956 return status; 957 } 958 959 (void) xge_os_snprintf(key, sizeof(key), "ring%d_", channel->post_qid); 960 961 dest_addr = key + strlen(key); 962 dest_size = sizeof(key) - strlen(key); 963 964 xge_os_strlcpy(dest_addr, "full_cnt", dest_size); 965 __HAL_AUX_ENTRY(key, chstat.full_cnt, "%u"); 966 967 xge_os_strlcpy(dest_addr, "usage_max", dest_size); 968 __HAL_AUX_ENTRY(key, chstat.usage_max, "%u"); 969 970 xge_os_strlcpy(dest_addr, "usage_cnt", dest_size); 971 __HAL_AUX_ENTRY(key, channel->usage_cnt, "%u"); 972 973 xge_os_strlcpy(dest_addr, "reserve_free_swaps_cnt", dest_size); 974 __HAL_AUX_ENTRY(key, chstat.reserve_free_swaps_cnt, "%u"); 975 976 if (!hldev->config.bimodal_interrupts) { 977 xge_os_strlcpy(dest_addr, "avg_compl_per_intr_cnt", dest_size); 978 __HAL_AUX_ENTRY(key, chstat.avg_compl_per_intr_cnt, "%u"); 979 } 980 981 xge_os_strlcpy(dest_addr, "total_compl_cnt", dest_size); 982 __HAL_AUX_ENTRY(key, chstat.total_compl_cnt, "%u"); 983 984 xge_os_strlcpy(dest_addr, "bump_cnt", dest_size); 985 __HAL_AUX_ENTRY(key, chstat.ring_bump_cnt, "%u"); 986 } 987 988 /* for each opened tx channel */ 989 xge_list_for_each(item, &hldev->fifo_channels) { 990 channel = xge_container_of(item, xge_hal_channel_t, item); 991 992 status = xge_hal_mgmt_channel_stats(channel, &chstat, 993 sizeof(xge_hal_mgmt_channel_stats_t)); 994 if (status != XGE_HAL_OK) { 995 return status; 996 } 997 998 (void) xge_os_snprintf(key, sizeof(key), "fifo%d_", channel->post_qid); 999 1000 dest_addr = key + strlen(key); 1001 dest_size = sizeof(key) - strlen(key); 1002 1003 xge_os_strlcpy(dest_addr, "full_cnt", dest_size); 1004 __HAL_AUX_ENTRY(key, chstat.full_cnt, "%u"); 1005 1006 xge_os_strlcpy(dest_addr, "usage_max", dest_size); 1007 __HAL_AUX_ENTRY(key, chstat.usage_max, "%u"); 1008 1009 xge_os_strlcpy(dest_addr, "usage_cnt", dest_size); 1010 __HAL_AUX_ENTRY(key, channel->usage_cnt, "%u"); 1011 1012 xge_os_strlcpy(dest_addr, "reserve_free_swaps_cnt", dest_size); 1013 __HAL_AUX_ENTRY(key, chstat.reserve_free_swaps_cnt, "%u"); 1014 1015 xge_os_strlcpy(dest_addr, "avg_compl_per_intr_cnt", dest_size); 1016 __HAL_AUX_ENTRY(key, chstat.avg_compl_per_intr_cnt, "%u"); 1017 1018 xge_os_strlcpy(dest_addr, "total_compl_cnt", dest_size); 1019 __HAL_AUX_ENTRY(key, chstat.total_compl_cnt, "%u"); 1020 1021 xge_os_strlcpy(dest_addr, "total_posts", dest_size); 1022 __HAL_AUX_ENTRY(key, chstat.total_posts, "%u"); 1023 1024 xge_os_strlcpy(dest_addr, "total_posts_many", dest_size); 1025 __HAL_AUX_ENTRY(key, chstat.total_posts_many, "%u"); 1026 1027 xge_os_strlcpy(dest_addr, "copied_frags", dest_size); 1028 __HAL_AUX_ENTRY(key, chstat.copied_frags, "%u"); 1029 1030 xge_os_strlcpy(dest_addr, "copied_buffers", dest_size); 1031 __HAL_AUX_ENTRY(key, chstat.copied_buffers, "%u"); 1032 1033 xge_os_strlcpy(dest_addr, "total_buffers", dest_size); 1034 __HAL_AUX_ENTRY(key, chstat.total_buffers, "%u"); 1035 1036 xge_os_strlcpy(dest_addr, "avg_buffers_per_post", dest_size); 1037 __HAL_AUX_ENTRY(key, chstat.avg_buffers_per_post, "%u"); 1038 1039 xge_os_strlcpy(dest_addr, "avg_buffer_size", dest_size); 1040 __HAL_AUX_ENTRY(key, chstat.avg_buffer_size, "%u"); 1041 1042 xge_os_strlcpy(dest_addr, "avg_post_size", dest_size); 1043 __HAL_AUX_ENTRY(key, chstat.avg_post_size, "%u"); 1044 1045 xge_os_strlcpy(dest_addr, "total_posts_dtrs_many", dest_size); 1046 __HAL_AUX_ENTRY(key, chstat.total_posts_dtrs_many, "%u"); 1047 1048 xge_os_strlcpy(dest_addr, "total_posts_frags_many", dest_size); 1049 __HAL_AUX_ENTRY(key, chstat.total_posts_frags_many, "%u"); 1050 1051 xge_os_strlcpy(dest_addr, "total_posts_dang_dtrs", dest_size); 1052 __HAL_AUX_ENTRY(key, chstat.total_posts_dang_dtrs, "%u"); 1053 1054 xge_os_strlcpy(dest_addr, "total_posts_dang_frags", dest_size); 1055 __HAL_AUX_ENTRY(key, chstat.total_posts_dang_frags, "%u"); 1056 } 1057 1058 __HAL_AUX_ENTRY_END(bufsize, retsize); 1059 1060 return XGE_HAL_OK; 1061 } 1062 1063 1064 1065 /** 1066 * xge_hal_aux_stats_sw_dev_read - Read software device statistics. 1067 * @devh: HAL device handle. 1068 * @bufsize: Buffer size. 1069 * @retbuf: Buffer pointer. 1070 * @retsize: Size of the result. Cannot be greater than @bufsize. 1071 * 1072 * Read software-maintained device statistics. 1073 * 1074 * Returns: XGE_HAL_OK - success. 1075 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 1076 * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 1077 * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not 1078 * currently available. 1079 * 1080 * See also: xge_hal_aux_device_dump(). 1081 */ 1082 xge_hal_status_e xge_hal_aux_stats_sw_dev_read(xge_hal_device_h devh, 1083 int bufsize, char *retbuf, int *retsize) 1084 { 1085 xge_hal_device_t *hldev = (xge_hal_device_t*)devh; 1086 xge_hal_status_e status; 1087 xge_hal_mgmt_sw_stats_t sw_dev_err_stats; 1088 int t_code, t_code_cnt; 1089 char buf[XGE_OS_SPRINTF_STRLEN]; 1090 1091 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 1092 1093 status = xge_hal_mgmt_sw_stats(hldev, &sw_dev_err_stats, 1094 sizeof(xge_hal_mgmt_sw_stats_t)); 1095 if (status != XGE_HAL_OK) { 1096 return status; 1097 } 1098 1099 __HAL_AUX_ENTRY("sm_err_cnt",sw_dev_err_stats.sm_err_cnt, "%u"); 1100 __HAL_AUX_ENTRY("single_ecc_err_cnt",sw_dev_err_stats.single_ecc_err_cnt, "%u"); 1101 __HAL_AUX_ENTRY("double_ecc_err_cnt",sw_dev_err_stats.double_ecc_err_cnt, "%u"); 1102 __HAL_AUX_ENTRY("ecc_err_cnt", sw_dev_err_stats.ecc_err_cnt, "%u"); 1103 __HAL_AUX_ENTRY("parity_err_cnt",sw_dev_err_stats.parity_err_cnt, "%u"); 1104 __HAL_AUX_ENTRY("serr_cnt",sw_dev_err_stats.serr_cnt, "%u"); 1105 1106 for (t_code = 1; t_code < 16; t_code++) { 1107 t_code_cnt = sw_dev_err_stats.rxd_t_code_err_cnt[t_code]; 1108 if (t_code_cnt) { 1109 (void) xge_os_snprintf(buf, sizeof(buf), "rxd_t_code_%d", t_code); 1110 __HAL_AUX_ENTRY(buf, t_code_cnt, "%u"); 1111 } 1112 t_code_cnt = sw_dev_err_stats.txd_t_code_err_cnt[t_code]; 1113 if (t_code_cnt) { 1114 (void) xge_os_snprintf(buf, sizeof(buf), "txd_t_code_%d", t_code); 1115 __HAL_AUX_ENTRY(buf, t_code_cnt, "%u"); 1116 } 1117 } 1118 __HAL_AUX_ENTRY("alarm_transceiver_temp_high",sw_dev_err_stats. 1119 stats_xpak.alarm_transceiver_temp_high, "%u"); 1120 __HAL_AUX_ENTRY("alarm_transceiver_temp_low",sw_dev_err_stats. 1121 stats_xpak.alarm_transceiver_temp_low, "%u"); 1122 __HAL_AUX_ENTRY("alarm_laser_bias_current_high",sw_dev_err_stats. 1123 stats_xpak.alarm_laser_bias_current_high, "%u"); 1124 __HAL_AUX_ENTRY("alarm_laser_bias_current_low",sw_dev_err_stats. 1125 stats_xpak.alarm_laser_bias_current_low, "%u"); 1126 __HAL_AUX_ENTRY("alarm_laser_output_power_high",sw_dev_err_stats. 1127 stats_xpak.alarm_laser_output_power_high, "%u"); 1128 __HAL_AUX_ENTRY("alarm_laser_output_power_low",sw_dev_err_stats. 1129 stats_xpak.alarm_laser_output_power_low, "%u"); 1130 __HAL_AUX_ENTRY("warn_transceiver_temp_high",sw_dev_err_stats. 1131 stats_xpak.warn_transceiver_temp_high, "%u"); 1132 __HAL_AUX_ENTRY("warn_transceiver_temp_low",sw_dev_err_stats. 1133 stats_xpak.warn_transceiver_temp_low, "%u"); 1134 __HAL_AUX_ENTRY("warn_laser_bias_current_high",sw_dev_err_stats. 1135 stats_xpak.warn_laser_bias_current_high, "%u"); 1136 __HAL_AUX_ENTRY("warn_laser_bias_current_low",sw_dev_err_stats. 1137 stats_xpak.warn_laser_bias_current_low, "%u"); 1138 __HAL_AUX_ENTRY("warn_laser_output_power_high",sw_dev_err_stats. 1139 stats_xpak.warn_laser_output_power_high, "%u"); 1140 __HAL_AUX_ENTRY("warn_laser_output_power_low",sw_dev_err_stats. 1141 stats_xpak.warn_laser_output_power_low, "%u"); 1142 1143 __HAL_AUX_ENTRY_END(bufsize, retsize); 1144 1145 return XGE_HAL_OK; 1146 } 1147 1148 /** 1149 * xge_hal_aux_pci_config_read - Retrieve and format PCI Configuration 1150 * info. 1151 * @devh: HAL device handle. 1152 * @bufsize: Buffer size. 1153 * @retbuf: Buffer pointer. 1154 * @retsize: Size of the result. Cannot be greater than @bufsize. 1155 * 1156 * Retrieve about info (using xge_hal_mgmt_pci_config()) and sprintf it 1157 * into the provided @retbuf. 1158 * 1159 * Returns: XGE_HAL_OK - success. 1160 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 1161 * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 1162 * 1163 * See also: xge_hal_mgmt_pci_config(), xge_hal_aux_device_dump(). 1164 */ 1165 xge_hal_status_e xge_hal_aux_pci_config_read(xge_hal_device_h devh, int bufsize, 1166 char *retbuf, int *retsize) 1167 { 1168 int i; 1169 xge_hal_status_e status; 1170 xge_hal_mgmt_pci_config_t pci_config; 1171 char key[XGE_OS_SPRINTF_STRLEN]; 1172 1173 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 1174 1175 status = xge_hal_mgmt_pci_config(devh, &pci_config, 1176 sizeof(xge_hal_mgmt_pci_config_t)); 1177 if (status != XGE_HAL_OK) { 1178 return status; 1179 } 1180 1181 __HAL_AUX_ENTRY("vendor_id", pci_config.vendor_id, "0x%04X"); 1182 __HAL_AUX_ENTRY("device_id", pci_config.device_id, "0x%04X"); 1183 __HAL_AUX_ENTRY("command", pci_config.command, "0x%04X"); 1184 __HAL_AUX_ENTRY("status", pci_config.status, "0x%04X"); 1185 __HAL_AUX_ENTRY("revision", pci_config.revision, "0x%02X"); 1186 __HAL_AUX_ENTRY("pciClass1", pci_config.pciClass[0], "0x%02X"); 1187 __HAL_AUX_ENTRY("pciClass2", pci_config.pciClass[1], "0x%02X"); 1188 __HAL_AUX_ENTRY("pciClass3", pci_config.pciClass[2], "0x%02X"); 1189 __HAL_AUX_ENTRY("cache_line_size", 1190 pci_config.cache_line_size, "0x%02X"); 1191 __HAL_AUX_ENTRY("latency_timer", pci_config.latency_timer, "0x%02X"); 1192 __HAL_AUX_ENTRY("header_type", pci_config.header_type, "0x%02X"); 1193 __HAL_AUX_ENTRY("bist", pci_config.bist, "0x%02X"); 1194 __HAL_AUX_ENTRY("base_addr0_lo", pci_config.base_addr0_lo, "0x%08X"); 1195 __HAL_AUX_ENTRY("base_addr0_hi", pci_config.base_addr0_hi, "0x%08X"); 1196 __HAL_AUX_ENTRY("base_addr1_lo", pci_config.base_addr1_lo, "0x%08X"); 1197 __HAL_AUX_ENTRY("base_addr1_hi", pci_config.base_addr1_hi, "0x%08X"); 1198 __HAL_AUX_ENTRY("not_Implemented1", 1199 pci_config.not_Implemented1, "0x%08X"); 1200 __HAL_AUX_ENTRY("not_Implemented2", pci_config.not_Implemented2, 1201 "0x%08X"); 1202 __HAL_AUX_ENTRY("cardbus_cis_pointer", pci_config.cardbus_cis_pointer, 1203 "0x%08X"); 1204 __HAL_AUX_ENTRY("subsystem_vendor_id", pci_config.subsystem_vendor_id, 1205 "0x%04X"); 1206 __HAL_AUX_ENTRY("subsystem_id", pci_config.subsystem_id, "0x%04X"); 1207 __HAL_AUX_ENTRY("rom_base", pci_config.rom_base, "0x%08X"); 1208 __HAL_AUX_ENTRY("capabilities_pointer", 1209 pci_config.capabilities_pointer, "0x%02X"); 1210 __HAL_AUX_ENTRY("interrupt_line", pci_config.interrupt_line, "0x%02X"); 1211 __HAL_AUX_ENTRY("interrupt_pin", pci_config.interrupt_pin, "0x%02X"); 1212 __HAL_AUX_ENTRY("min_grant", pci_config.min_grant, "0x%02X"); 1213 __HAL_AUX_ENTRY("max_latency", pci_config.max_latency, "0x%02X"); 1214 __HAL_AUX_ENTRY("msi_cap_id", pci_config.msi_cap_id, "0x%02X"); 1215 __HAL_AUX_ENTRY("msi_next_ptr", pci_config.msi_next_ptr, "0x%02X"); 1216 __HAL_AUX_ENTRY("msi_control", pci_config.msi_control, "0x%04X"); 1217 __HAL_AUX_ENTRY("msi_lower_address", pci_config.msi_lower_address, 1218 "0x%08X"); 1219 __HAL_AUX_ENTRY("msi_higher_address", pci_config.msi_higher_address, 1220 "0x%08X"); 1221 __HAL_AUX_ENTRY("msi_data", pci_config.msi_data, "0x%04X"); 1222 __HAL_AUX_ENTRY("msi_unused", pci_config.msi_unused, "0x%04X"); 1223 __HAL_AUX_ENTRY("vpd_cap_id", pci_config.vpd_cap_id, "0x%02X"); 1224 __HAL_AUX_ENTRY("vpd_next_cap", pci_config.vpd_next_cap, "0x%02X"); 1225 __HAL_AUX_ENTRY("vpd_addr", pci_config.vpd_addr, "0x%04X"); 1226 __HAL_AUX_ENTRY("vpd_data", pci_config.vpd_data, "0x%08X"); 1227 __HAL_AUX_ENTRY("pcix_cap", pci_config.pcix_cap, "0x%02X"); 1228 __HAL_AUX_ENTRY("pcix_next_cap", pci_config.pcix_next_cap, "0x%02X"); 1229 __HAL_AUX_ENTRY("pcix_command", pci_config.pcix_command, "0x%04X"); 1230 __HAL_AUX_ENTRY("pcix_status", pci_config.pcix_status, "0x%08X"); 1231 1232 if (xge_hal_device_check_id(devh) == XGE_HAL_CARD_HERC) { 1233 for (i = 0; i < (XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE - 0x68)/4; i++) { 1234 (void) xge_os_snprintf(key, sizeof(key), "%03x:", 4*i + 0x68); 1235 __HAL_AUX_ENTRY(key, *((int *)pci_config.rsvd_b1 + i), "0x%08X"); 1236 } 1237 } 1238 1239 __HAL_AUX_ENTRY_END(bufsize, retsize); 1240 1241 return XGE_HAL_OK; 1242 } 1243 1244 1245 /** 1246 * xge_hal_aux_channel_read - Read channels information. 1247 * @devh: HAL device handle. 1248 * @bufsize: Buffer size. 1249 * @retbuf: Buffer pointer. 1250 * @retsize: Size of the result. Cannot be greater than @bufsize. 1251 * 1252 * Read HAL statistics. 1253 * 1254 * Returns: XGE_HAL_OK - success. 1255 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 1256 * XGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small. 1257 * See also: xge_hal_aux_device_dump(). 1258 */ 1259 xge_hal_status_e xge_hal_aux_channel_read(xge_hal_device_h devh, 1260 int bufsize, char *retbuf, int *retsize) 1261 { 1262 xge_list_t *item; 1263 xge_hal_channel_t *channel; 1264 xge_hal_device_t *hldev = (xge_hal_device_t*)devh; 1265 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 1266 1267 int dest_size; 1268 char *dest_addr; 1269 char key[XGE_OS_SPRINTF_STRLEN]; 1270 1271 if (hldev->magic != XGE_HAL_MAGIC) { 1272 return XGE_HAL_ERR_INVALID_DEVICE; 1273 } 1274 1275 /* for each opened rx channel */ 1276 xge_list_for_each(item, &hldev->ring_channels) { 1277 channel = xge_container_of(item, xge_hal_channel_t, item); 1278 1279 if (channel->is_open != 1) 1280 continue; 1281 1282 (void) xge_os_snprintf(key, sizeof(key), "ring%d_", channel->post_qid); 1283 1284 dest_addr = key + strlen(key); 1285 dest_size = sizeof(key) - strlen(key); 1286 1287 xge_os_strlcpy(dest_addr, "type", dest_size); 1288 __HAL_AUX_ENTRY(key, channel->type, "%u"); 1289 1290 xge_os_strlcpy(dest_addr, "length", dest_size); 1291 __HAL_AUX_ENTRY(key, channel->length, "%u"); 1292 1293 xge_os_strlcpy(dest_addr, "is_open", dest_size); 1294 __HAL_AUX_ENTRY(key, channel->is_open, "%u"); 1295 1296 xge_os_strlcpy(dest_addr, "reserve_initial", dest_size); 1297 __HAL_AUX_ENTRY(key, channel->reserve_initial, "%u"); 1298 1299 xge_os_strlcpy(dest_addr, "reserve_max", dest_size); 1300 __HAL_AUX_ENTRY(key, channel->reserve_max, "%u"); 1301 1302 xge_os_strlcpy(dest_addr, "reserve_length", dest_size); 1303 __HAL_AUX_ENTRY(key, channel->reserve_length, "%u"); 1304 1305 xge_os_strlcpy(dest_addr, "reserve_top", dest_size); 1306 __HAL_AUX_ENTRY(key, channel->reserve_top, "%u"); 1307 1308 xge_os_strlcpy(dest_addr, "reserve_threshold", dest_size); 1309 __HAL_AUX_ENTRY(key, channel->reserve_threshold, "%u"); 1310 1311 xge_os_strlcpy(dest_addr, "free_length", dest_size); 1312 __HAL_AUX_ENTRY(key, channel->free_length, "%u"); 1313 1314 xge_os_strlcpy(dest_addr, "post_index", dest_size); 1315 __HAL_AUX_ENTRY(key, channel->post_index, "%u"); 1316 1317 xge_os_strlcpy(dest_addr, "compl_index", dest_size); 1318 __HAL_AUX_ENTRY(key, channel->compl_index, "%u"); 1319 1320 xge_os_strlcpy(dest_addr, "per_dtr_space", dest_size); 1321 __HAL_AUX_ENTRY(key, channel->per_dtr_space, "%u"); 1322 1323 xge_os_strlcpy(dest_addr, "usage_cnt", dest_size); 1324 __HAL_AUX_ENTRY(key, channel->usage_cnt, "%u"); 1325 } 1326 1327 /* for each opened tx channel */ 1328 xge_list_for_each(item, &hldev->fifo_channels) { 1329 channel = xge_container_of(item, xge_hal_channel_t, item); 1330 if (channel->is_open != 1) 1331 continue; 1332 1333 (void) xge_os_snprintf(key, sizeof(key), "fifo%d_", channel->post_qid); 1334 1335 dest_addr = key + strlen(key); 1336 dest_size = sizeof(key) - strlen(key); 1337 1338 xge_os_strlcpy(dest_addr, "type", dest_size); 1339 __HAL_AUX_ENTRY(key, channel->type, "%u"); 1340 1341 xge_os_strlcpy(dest_addr, "length", dest_size); 1342 __HAL_AUX_ENTRY(key, channel->length, "%u"); 1343 1344 xge_os_strlcpy(dest_addr, "is_open", dest_size); 1345 __HAL_AUX_ENTRY(key, channel->is_open, "%u"); 1346 1347 xge_os_strlcpy(dest_addr, "reserve_initial", dest_size); 1348 __HAL_AUX_ENTRY(key, channel->reserve_initial, "%u"); 1349 1350 xge_os_strlcpy(dest_addr, "reserve_max", dest_size); 1351 __HAL_AUX_ENTRY(key, channel->reserve_max, "%u"); 1352 1353 xge_os_strlcpy(dest_addr, "reserve_length", dest_size); 1354 __HAL_AUX_ENTRY(key, channel->reserve_length, "%u"); 1355 1356 xge_os_strlcpy(dest_addr, "reserve_top", dest_size); 1357 __HAL_AUX_ENTRY(key, channel->reserve_top, "%u"); 1358 1359 xge_os_strlcpy(dest_addr, "reserve_threshold", dest_size); 1360 __HAL_AUX_ENTRY(key, channel->reserve_threshold, "%u"); 1361 1362 xge_os_strlcpy(dest_addr, "free_length", dest_size); 1363 __HAL_AUX_ENTRY(key, channel->free_length, "%u"); 1364 1365 xge_os_strlcpy(dest_addr, "post_index", dest_size); 1366 __HAL_AUX_ENTRY(key, channel->post_index, "%u"); 1367 1368 xge_os_strlcpy(dest_addr, "compl_index", dest_size); 1369 __HAL_AUX_ENTRY(key, channel->compl_index, "%u"); 1370 1371 xge_os_strlcpy(dest_addr, "per_dtr_space", dest_size); 1372 __HAL_AUX_ENTRY(key, channel->per_dtr_space, "%u"); 1373 1374 xge_os_strlcpy(dest_addr, "usage_cnt", dest_size); 1375 __HAL_AUX_ENTRY(key, channel->usage_cnt, "%u"); 1376 } 1377 1378 __HAL_AUX_ENTRY_END(bufsize, retsize); 1379 1380 return XGE_HAL_OK; 1381 } 1382 1383 /** 1384 * xge_hal_aux_device_dump - Dump driver "about" info and device state. 1385 * @devh: HAL device handle. 1386 * 1387 * Dump driver & device "about" info and device state, 1388 * including all BAR0 registers, hardware and software statistics, PCI 1389 * configuration space. 1390 * See also: xge_hal_aux_about_read(), xge_hal_mgmt_reg_read(), 1391 * xge_hal_aux_pci_config_read(), xge_hal_aux_stats_sw_dev_read(), 1392 * xge_hal_aux_stats_tmac_read(), xge_hal_aux_stats_rmac_read(), 1393 * xge_hal_aux_channel_read(), xge_hal_aux_stats_hal_read(). 1394 * Returns: 1395 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 1396 * XGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small. 1397 */ 1398 xge_hal_status_e 1399 xge_hal_aux_device_dump(xge_hal_device_h devh) 1400 { 1401 xge_hal_device_t *hldev = (xge_hal_device_t*)devh; 1402 xge_hal_status_e status; 1403 int retsize; 1404 int offset; 1405 u64 retval; 1406 1407 xge_assert(hldev->dump_buf != NULL); 1408 1409 xge_os_println("********* xge DEVICE DUMP BEGIN **********"); 1410 1411 status = xge_hal_aux_about_read(hldev, XGE_HAL_DUMP_BUF_SIZE, 1412 hldev->dump_buf, 1413 &retsize); 1414 if (status != XGE_HAL_OK) { 1415 goto error; 1416 } 1417 xge_os_println(hldev->dump_buf); 1418 1419 1420 for (offset = 0; offset < 1574; offset++) { 1421 1422 status = xge_hal_mgmt_reg_read(hldev, 0, offset*8, &retval); 1423 if (status != XGE_HAL_OK) { 1424 goto error; 1425 } 1426 1427 if (!retval) continue; 1428 1429 xge_os_printf("0x%04x 0x%08x%08x", offset*8, 1430 (u32)(retval>>32), (u32)retval); 1431 } 1432 xge_os_println("\n"); 1433 1434 status = xge_hal_aux_pci_config_read(hldev, XGE_HAL_DUMP_BUF_SIZE, 1435 hldev->dump_buf, 1436 &retsize); 1437 if (status != XGE_HAL_OK) { 1438 goto error; 1439 } 1440 xge_os_println(hldev->dump_buf); 1441 1442 status = xge_hal_aux_stats_tmac_read(hldev, XGE_HAL_DUMP_BUF_SIZE, 1443 hldev->dump_buf, 1444 &retsize); 1445 if (status != XGE_HAL_OK) { 1446 goto error; 1447 } 1448 xge_os_println(hldev->dump_buf); 1449 1450 status = xge_hal_aux_stats_rmac_read(hldev, XGE_HAL_DUMP_BUF_SIZE, 1451 hldev->dump_buf, 1452 &retsize); 1453 if (status != XGE_HAL_OK) { 1454 goto error; 1455 } 1456 xge_os_println(hldev->dump_buf); 1457 1458 status = xge_hal_aux_stats_pci_read(hldev, XGE_HAL_DUMP_BUF_SIZE, 1459 hldev->dump_buf, 1460 &retsize); 1461 if (status != XGE_HAL_OK) { 1462 goto error; 1463 } 1464 xge_os_println(hldev->dump_buf); 1465 1466 if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { 1467 status = xge_hal_aux_stats_herc_enchanced(hldev, 1468 XGE_HAL_DUMP_BUF_SIZE, hldev->dump_buf, &retsize); 1469 if (status != XGE_HAL_OK) { 1470 goto error; 1471 } 1472 xge_os_println(hldev->dump_buf); 1473 } 1474 1475 status = xge_hal_aux_stats_sw_dev_read(hldev, XGE_HAL_DUMP_BUF_SIZE, 1476 hldev->dump_buf, &retsize); 1477 if (status != XGE_HAL_OK) { 1478 goto error; 1479 } 1480 xge_os_println(hldev->dump_buf); 1481 1482 status = xge_hal_aux_channel_read(hldev, XGE_HAL_DUMP_BUF_SIZE, 1483 hldev->dump_buf, 1484 &retsize); 1485 if (status != XGE_HAL_OK) { 1486 goto error; 1487 } 1488 xge_os_println(hldev->dump_buf); 1489 1490 status = xge_hal_aux_stats_hal_read(hldev, XGE_HAL_DUMP_BUF_SIZE, 1491 hldev->dump_buf, 1492 &retsize); 1493 if (status != XGE_HAL_OK) { 1494 goto error; 1495 } 1496 xge_os_println(hldev->dump_buf); 1497 1498 xge_os_println("********* XFRAME DEVICE DUMP END **********"); 1499 1500 error: 1501 return status; 1502 } 1503 1504 1505 /** 1506 * xge_hal_aux_driver_config_read - Read Driver configuration. 1507 * @bufsize: Buffer size. 1508 * @retbuf: Buffer pointer. 1509 * @retsize: Size of the result. Cannot be greater than @bufsize. 1510 * 1511 * Read driver configuration, 1512 * 1513 * Returns: XGE_HAL_OK - success. 1514 * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 1515 * 1516 * See also: xge_hal_aux_device_config_read(). 1517 */ 1518 xge_hal_status_e 1519 xge_hal_aux_driver_config_read(int bufsize, char *retbuf, int *retsize) 1520 { 1521 xge_hal_status_e status; 1522 xge_hal_driver_config_t drv_config; 1523 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 1524 1525 status = xge_hal_mgmt_driver_config(&drv_config, 1526 sizeof(xge_hal_driver_config_t)); 1527 if (status != XGE_HAL_OK) { 1528 return status; 1529 } 1530 1531 __HAL_AUX_ENTRY("queue size initial", 1532 drv_config.queue_size_initial, "%u"); 1533 __HAL_AUX_ENTRY("queue size max", drv_config.queue_size_max, "%u"); 1534 __HAL_AUX_ENTRY_END(bufsize, retsize); 1535 1536 return XGE_HAL_OK; 1537 } 1538 1539 1540 /** 1541 * xge_hal_aux_device_config_read - Read device configuration. 1542 * @devh: HAL device handle. 1543 * @bufsize: Buffer size. 1544 * @retbuf: Buffer pointer. 1545 * @retsize: Size of the result. Cannot be greater than @bufsize. 1546 * 1547 * Read device configuration, 1548 * 1549 * Returns: XGE_HAL_OK - success. 1550 * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. 1551 * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. 1552 * 1553 * See also: xge_hal_aux_driver_config_read(). 1554 */ 1555 xge_hal_status_e xge_hal_aux_device_config_read(xge_hal_device_h devh, 1556 int bufsize, char *retbuf, int *retsize) 1557 { 1558 int i, j; 1559 xge_hal_status_e status; 1560 xge_hal_device_config_t *dev_config; 1561 xge_hal_ring_queue_t *ring; 1562 xge_hal_fifo_queue_t *fifo; 1563 xge_hal_rti_config_t *rti; 1564 xge_hal_tti_config_t *tti; 1565 xge_hal_mac_config_t *mac; 1566 1567 int dest_size; 1568 char *dest_addr; 1569 char key[XGE_OS_SPRINTF_STRLEN]; 1570 1571 xge_hal_device_t *hldev = (xge_hal_device_t*)devh; 1572 __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); 1573 1574 dev_config = (xge_hal_device_config_t *) xge_os_malloc(hldev->pdev, 1575 sizeof(xge_hal_device_config_t)); 1576 if (dev_config == NULL) { 1577 return XGE_HAL_FAIL; 1578 } 1579 1580 status = xge_hal_mgmt_device_config(devh, dev_config, 1581 sizeof(xge_hal_device_config_t)); 1582 if (status != XGE_HAL_OK) { 1583 xge_os_free(hldev->pdev, dev_config, 1584 sizeof(xge_hal_device_config_t)); 1585 return status; 1586 } 1587 1588 __HAL_AUX_ENTRY("mtu", dev_config->mtu, "%u"); 1589 __HAL_AUX_ENTRY("isr_polling_count", dev_config->isr_polling_cnt, "%u"); 1590 __HAL_AUX_ENTRY("latency_timer", dev_config->latency_timer, "%u"); 1591 __HAL_AUX_ENTRY("max_splits_trans", 1592 dev_config->max_splits_trans, "%u"); 1593 __HAL_AUX_ENTRY("mmrb_count", dev_config->mmrb_count, "%d"); 1594 __HAL_AUX_ENTRY("shared_splits", dev_config->shared_splits, "%u"); 1595 __HAL_AUX_ENTRY("stats_refresh_time_sec", 1596 dev_config->stats_refresh_time_sec, "%u"); 1597 __HAL_AUX_ENTRY("pci_freq_mherz", dev_config->pci_freq_mherz, "%u"); 1598 __HAL_AUX_ENTRY("intr_mode", dev_config->intr_mode, "%u"); 1599 __HAL_AUX_ENTRY("ring_memblock_size", 1600 dev_config->ring.memblock_size, "%u"); 1601 1602 __HAL_AUX_ENTRY("sched_timer_us", dev_config->sched_timer_us, "%u"); 1603 __HAL_AUX_ENTRY("sched_timer_one_shot", 1604 dev_config->sched_timer_one_shot, "%u"); 1605 __HAL_AUX_ENTRY("rxufca_intr_thres", dev_config->rxufca_intr_thres, "%u"); 1606 __HAL_AUX_ENTRY("rxufca_lo_lim", dev_config->rxufca_lo_lim, "%u"); 1607 __HAL_AUX_ENTRY("rxufca_hi_lim", dev_config->rxufca_hi_lim, "%u"); 1608 __HAL_AUX_ENTRY("rxufca_lbolt_period", dev_config->rxufca_lbolt_period, "%u"); 1609 1610 for(i = 0; i < XGE_HAL_MAX_RING_NUM; i++) 1611 { 1612 ring = &dev_config->ring.queue[i]; 1613 rti = &ring->rti; 1614 1615 if (!ring->configured) 1616 continue; 1617 1618 (void) xge_os_snprintf(key, sizeof(key), "ring%d_", i); 1619 1620 dest_addr = key + strlen(key); 1621 dest_size = sizeof(key) - strlen(key); 1622 1623 xge_os_strlcpy(dest_addr, "inital", dest_size); 1624 __HAL_AUX_ENTRY(key, ring->initial, "%u"); 1625 1626 xge_os_strlcpy(dest_addr, "max", dest_size); 1627 __HAL_AUX_ENTRY(key, ring->max, "%u"); 1628 1629 xge_os_strlcpy(dest_addr, "buffer_mode", dest_size); 1630 __HAL_AUX_ENTRY(key, ring->buffer_mode, "%u"); 1631 1632 xge_os_strlcpy(dest_addr, "dram_size_mb", dest_size); 1633 __HAL_AUX_ENTRY(key, ring->dram_size_mb, "%u"); 1634 1635 xge_os_strlcpy(dest_addr, "backoff_interval_us", dest_size); 1636 __HAL_AUX_ENTRY(key, ring->backoff_interval_us, "%u"); 1637 1638 xge_os_strlcpy(dest_addr, "max_frame_len", dest_size); 1639 __HAL_AUX_ENTRY(key, ring->max_frm_len, "%d"); 1640 1641 xge_os_strlcpy(dest_addr, "priority", dest_size); 1642 __HAL_AUX_ENTRY(key, ring->priority, "%u"); 1643 1644 xge_os_strlcpy(dest_addr, "rth_en", dest_size); 1645 __HAL_AUX_ENTRY(key, ring->rth_en, "%u"); 1646 1647 xge_os_strlcpy(dest_addr, "no_snoop_bits", dest_size); 1648 __HAL_AUX_ENTRY(key, ring->no_snoop_bits, "%u"); 1649 1650 xge_os_strlcpy(dest_addr, "indicate_max_pkts", dest_size); 1651 __HAL_AUX_ENTRY(key, ring->indicate_max_pkts, "%u"); 1652 1653 xge_os_strlcpy(dest_addr, "urange_a", dest_size); 1654 __HAL_AUX_ENTRY(key, rti->urange_a, "%u"); 1655 1656 xge_os_strlcpy(dest_addr, "ufc_a", dest_size); 1657 __HAL_AUX_ENTRY(key, rti->ufc_a, "%u"); 1658 1659 xge_os_strlcpy(dest_addr, "urange_b", dest_size); 1660 __HAL_AUX_ENTRY(key, rti->urange_b, "%u"); 1661 1662 xge_os_strlcpy(dest_addr, "ufc_b", dest_size); 1663 __HAL_AUX_ENTRY(key, rti->ufc_b, "%u"); 1664 1665 xge_os_strlcpy(dest_addr, "urange_c", dest_size); 1666 __HAL_AUX_ENTRY(key, rti->urange_c, "%u"); 1667 1668 xge_os_strlcpy(dest_addr, "ufc_c", dest_size); 1669 __HAL_AUX_ENTRY(key, rti->ufc_c, "%u"); 1670 1671 xge_os_strlcpy(dest_addr, "ufc_d", dest_size); 1672 __HAL_AUX_ENTRY(key, rti->ufc_d, "%u"); 1673 1674 xge_os_strlcpy(dest_addr, "timer_val_us", dest_size); 1675 __HAL_AUX_ENTRY(key, rti->timer_val_us, "%u"); 1676 } 1677 1678 1679 { 1680 mac= &dev_config->mac; 1681 1682 __HAL_AUX_ENTRY("tmac_util_period", 1683 mac->tmac_util_period, "%u"); 1684 __HAL_AUX_ENTRY("rmac_util_period", 1685 mac->rmac_util_period, "%u"); 1686 __HAL_AUX_ENTRY("rmac_bcast_en", 1687 mac->rmac_bcast_en, "%u"); 1688 __HAL_AUX_ENTRY("rmac_pause_gen_en", 1689 mac->rmac_pause_gen_en, "%d"); 1690 __HAL_AUX_ENTRY("rmac_pause_rcv_en", 1691 mac->rmac_pause_rcv_en, "%d"); 1692 __HAL_AUX_ENTRY("rmac_pause_time", 1693 mac->rmac_pause_time, "%u"); 1694 __HAL_AUX_ENTRY("mc_pause_threshold_q0q3", 1695 mac->mc_pause_threshold_q0q3, "%u"); 1696 __HAL_AUX_ENTRY("mc_pause_threshold_q4q7", 1697 mac->mc_pause_threshold_q4q7, "%u"); 1698 } 1699 1700 1701 __HAL_AUX_ENTRY("fifo_max_frags", 1702 dev_config->fifo.max_frags, "%u"); 1703 __HAL_AUX_ENTRY("fifo_reserve_threshold", 1704 dev_config->fifo.reserve_threshold, "%u"); 1705 __HAL_AUX_ENTRY("fifo_memblock_size", 1706 dev_config->fifo.memblock_size, "%u"); 1707 #ifdef XGE_HAL_ALIGN_XMIT 1708 __HAL_AUX_ENTRY("fifo_alignment_size", 1709 dev_config->fifo.alignment_size, "%u"); 1710 #endif 1711 1712 for (i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) { 1713 fifo = &dev_config->fifo.queue[i]; 1714 1715 if (!fifo->configured) 1716 continue; 1717 1718 (void) xge_os_snprintf(key, sizeof(key), "fifo%d_", i); 1719 1720 dest_addr = key + strlen(key); 1721 dest_size = sizeof(key) - strlen(key); 1722 1723 xge_os_strlcpy(dest_addr, "initial", dest_size); 1724 __HAL_AUX_ENTRY(key, fifo->initial, "%u"); 1725 1726 xge_os_strlcpy(dest_addr, "max", dest_size); 1727 __HAL_AUX_ENTRY(key, fifo->max, "%u"); 1728 1729 xge_os_strlcpy(dest_addr, "intr", dest_size); 1730 __HAL_AUX_ENTRY(key, fifo->intr, "%u"); 1731 1732 xge_os_strlcpy(dest_addr, "no_snoop_bits", dest_size); 1733 __HAL_AUX_ENTRY(key, fifo->no_snoop_bits, "%u"); 1734 1735 for (j = 0; j < XGE_HAL_MAX_FIFO_TTI_NUM; j++) { 1736 tti = &dev_config->fifo.queue[i].tti[j]; 1737 if (!tti->enabled) 1738 continue; 1739 1740 (void) xge_os_snprintf(key, sizeof(key), "fifo%d_tti%02d_", i, 1741 i * XGE_HAL_MAX_FIFO_TTI_NUM + j); 1742 1743 dest_addr = key + strlen(key); 1744 dest_size = sizeof(key) - strlen(key); 1745 1746 xge_os_strlcpy(dest_addr, "urange_a", dest_size); 1747 __HAL_AUX_ENTRY(key, tti->urange_a, "%u"); 1748 1749 xge_os_strlcpy(dest_addr, "ufc_a", dest_size); 1750 __HAL_AUX_ENTRY(key, tti->ufc_a, "%u"); 1751 1752 xge_os_strlcpy(dest_addr, "urange_b", dest_size); 1753 __HAL_AUX_ENTRY(key, tti->urange_b, "%u"); 1754 1755 xge_os_strlcpy(dest_addr, "ufc_b", dest_size); 1756 __HAL_AUX_ENTRY(key, tti->ufc_b, "%u"); 1757 1758 xge_os_strlcpy(dest_addr, "urange_c", dest_size); 1759 __HAL_AUX_ENTRY(key, tti->urange_c, "%u"); 1760 1761 xge_os_strlcpy(dest_addr, "ufc_c", dest_size); 1762 __HAL_AUX_ENTRY(key, tti->ufc_c, "%u"); 1763 1764 xge_os_strlcpy(dest_addr, "ufc_d", dest_size); 1765 __HAL_AUX_ENTRY(key, tti->ufc_d, "%u"); 1766 1767 xge_os_strlcpy(dest_addr, "timer_val_us", dest_size); 1768 __HAL_AUX_ENTRY(key, tti->timer_val_us, "%u"); 1769 1770 xge_os_strlcpy(dest_addr, "timer_ci_en", dest_size); 1771 __HAL_AUX_ENTRY(key, tti->timer_ci_en, "%u"); 1772 } 1773 } 1774 1775 /* and bimodal TTIs */ 1776 for (i=0; i<XGE_HAL_MAX_RING_NUM; i++) { 1777 tti = &hldev->bimodal_tti[i]; 1778 if (!tti->enabled) 1779 continue; 1780 1781 (void) xge_os_snprintf(key, sizeof(key), "tti%02d_", 1782 XGE_HAL_MAX_FIFO_TTI_RING_0 + i); 1783 1784 dest_addr = key + strlen(key); 1785 dest_size = sizeof(key) - strlen(key); 1786 1787 xge_os_strlcpy(dest_addr, "urange_a", dest_size); 1788 __HAL_AUX_ENTRY(key, tti->urange_a, "%u"); 1789 1790 xge_os_strlcpy(dest_addr, "ufc_a", dest_size); 1791 __HAL_AUX_ENTRY(key, tti->ufc_a, "%u"); 1792 1793 xge_os_strlcpy(dest_addr, "urange_b", dest_size); 1794 __HAL_AUX_ENTRY(key, tti->urange_b, "%u"); 1795 1796 xge_os_strlcpy(dest_addr, "ufc_b", dest_size); 1797 __HAL_AUX_ENTRY(key, tti->ufc_b, "%u"); 1798 1799 xge_os_strlcpy(dest_addr, "urange_c", dest_size); 1800 __HAL_AUX_ENTRY(key, tti->urange_c, "%u"); 1801 1802 xge_os_strlcpy(dest_addr, "ufc_c", dest_size); 1803 __HAL_AUX_ENTRY(key, tti->ufc_c, "%u"); 1804 1805 xge_os_strlcpy(dest_addr, "ufc_d", dest_size); 1806 __HAL_AUX_ENTRY(key, tti->ufc_d, "%u"); 1807 1808 xge_os_strlcpy(dest_addr, "timer_val_us", dest_size); 1809 __HAL_AUX_ENTRY(key, tti->timer_val_us, "%u"); 1810 1811 xge_os_strlcpy(dest_addr, "timer_ac_en", dest_size); 1812 __HAL_AUX_ENTRY(key, tti->timer_ac_en, "%u"); 1813 1814 xge_os_strlcpy(dest_addr, "timer_ci_en", dest_size); 1815 __HAL_AUX_ENTRY(key, tti->timer_ci_en, "%u"); 1816 } 1817 __HAL_AUX_ENTRY("dump_on_serr", dev_config->dump_on_serr, "%u"); 1818 __HAL_AUX_ENTRY("dump_on_eccerr", 1819 dev_config->dump_on_eccerr, "%u"); 1820 __HAL_AUX_ENTRY("dump_on_parityerr", 1821 dev_config->dump_on_parityerr, "%u"); 1822 __HAL_AUX_ENTRY("rth_en", dev_config->rth_en, "%u"); 1823 __HAL_AUX_ENTRY("rth_bucket_size", dev_config->rth_bucket_size, "%u"); 1824 1825 __HAL_AUX_ENTRY_END(bufsize, retsize); 1826 1827 xge_os_free(hldev->pdev, dev_config, 1828 sizeof(xge_hal_device_config_t)); 1829 1830 return XGE_HAL_OK; 1831 } 1832 1833