1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2002-2005 Neterion, Inc. 24 * All right Reserved. 25 * 26 * FileName : xgehal-config.c 27 * 28 * Description: configuration functionality 29 * 30 * Created: 14 May 2004 31 */ 32 33 #include "xgehal-config.h" 34 #include "xge-debug.h" 35 36 /* 37 * __hal_tti_config_check - Check tti configuration 38 * @new_config: tti configuration information 39 * 40 * Returns: XGE_HAL_OK - success, 41 * otherwise one of the xge_hal_status_e{} enumerated error codes. 42 */ 43 static xge_hal_status_e 44 __hal_tti_config_check (xge_hal_tti_config_t *new_config) 45 { 46 if ((new_config->urange_a < XGE_HAL_MIN_TX_URANGE_A) || 47 (new_config->urange_a > XGE_HAL_MAX_TX_URANGE_A)) { 48 return XGE_HAL_BADCFG_TX_URANGE_A; 49 } 50 51 if ((new_config->ufc_a < XGE_HAL_MIN_TX_UFC_A) || 52 (new_config->ufc_a > XGE_HAL_MAX_TX_UFC_A)) { 53 return XGE_HAL_BADCFG_TX_UFC_A; 54 } 55 56 if ((new_config->urange_b < XGE_HAL_MIN_TX_URANGE_B) || 57 (new_config->urange_b > XGE_HAL_MAX_TX_URANGE_B)) { 58 return XGE_HAL_BADCFG_TX_URANGE_B; 59 } 60 61 if ((new_config->ufc_b < XGE_HAL_MIN_TX_UFC_B) || 62 (new_config->ufc_b > XGE_HAL_MAX_TX_UFC_B)) { 63 return XGE_HAL_BADCFG_TX_UFC_B; 64 } 65 66 if ((new_config->urange_c < XGE_HAL_MIN_TX_URANGE_C) || 67 (new_config->urange_c > XGE_HAL_MAX_TX_URANGE_C)) { 68 return XGE_HAL_BADCFG_TX_URANGE_C; 69 } 70 71 if ((new_config->ufc_c < XGE_HAL_MIN_TX_UFC_C) || 72 (new_config->ufc_c > XGE_HAL_MAX_TX_UFC_C)) { 73 return XGE_HAL_BADCFG_TX_UFC_C; 74 } 75 76 if ((new_config->urange_d < XGE_HAL_MIN_TX_URANGE_D) || 77 (new_config->urange_d > XGE_HAL_MAX_TX_URANGE_D)) { 78 return XGE_HAL_BADCFG_TX_URANGE_D; 79 } 80 81 if ((new_config->ufc_d < XGE_HAL_MIN_TX_UFC_D) || 82 (new_config->ufc_d > XGE_HAL_MAX_TX_UFC_D)) { 83 return XGE_HAL_BADCFG_TX_UFC_D; 84 } 85 86 if ((new_config->timer_val_us < XGE_HAL_MIN_TX_TIMER_VAL) || 87 (new_config->timer_val_us > XGE_HAL_MAX_TX_TIMER_VAL)) { 88 return XGE_HAL_BADCFG_TX_TIMER_VAL; 89 } 90 91 if ((new_config->timer_ci_en < XGE_HAL_MIN_TX_TIMER_CI_EN) || 92 (new_config->timer_ci_en > XGE_HAL_MAX_TX_TIMER_CI_EN)) { 93 return XGE_HAL_BADCFG_TX_TIMER_CI_EN; 94 } 95 96 if ((new_config->timer_ac_en < XGE_HAL_MIN_TX_TIMER_AC_EN) || 97 (new_config->timer_ac_en > XGE_HAL_MAX_TX_TIMER_AC_EN)) { 98 return XGE_HAL_BADCFG_TX_TIMER_AC_EN; 99 } 100 101 return XGE_HAL_OK; 102 } 103 104 /* 105 * __hal_rti_config_check - Check rti configuration 106 * @new_config: rti configuration information 107 * 108 * Returns: XGE_HAL_OK - success, 109 * otherwise one of the xge_hal_status_e{} enumerated error codes. 110 */ 111 static xge_hal_status_e 112 __hal_rti_config_check (xge_hal_rti_config_t *new_config) 113 { 114 if ((new_config->urange_a < XGE_HAL_MIN_RX_URANGE_A) || 115 (new_config->urange_a > XGE_HAL_MAX_RX_URANGE_A)) { 116 return XGE_HAL_BADCFG_RX_URANGE_A; 117 } 118 119 if ((new_config->ufc_a < XGE_HAL_MIN_RX_UFC_A) || 120 (new_config->ufc_a > XGE_HAL_MAX_RX_UFC_A)) { 121 return XGE_HAL_BADCFG_RX_UFC_A; 122 } 123 124 if ((new_config->urange_b < XGE_HAL_MIN_RX_URANGE_B) || 125 (new_config->urange_b > XGE_HAL_MAX_RX_URANGE_B)) { 126 return XGE_HAL_BADCFG_RX_URANGE_B; 127 } 128 129 if ((new_config->ufc_b < XGE_HAL_MIN_RX_UFC_B) || 130 (new_config->ufc_b > XGE_HAL_MAX_RX_UFC_B)) { 131 return XGE_HAL_BADCFG_RX_UFC_B; 132 } 133 134 if ((new_config->urange_c < XGE_HAL_MIN_RX_URANGE_C) || 135 (new_config->urange_c > XGE_HAL_MAX_RX_URANGE_C)) { 136 return XGE_HAL_BADCFG_RX_URANGE_C; 137 } 138 139 if ((new_config->ufc_c < XGE_HAL_MIN_RX_UFC_C) || 140 (new_config->ufc_c > XGE_HAL_MAX_RX_UFC_C)) { 141 return XGE_HAL_BADCFG_RX_UFC_C; 142 } 143 144 if ((new_config->ufc_d < XGE_HAL_MIN_RX_UFC_D) || 145 (new_config->ufc_d > XGE_HAL_MAX_RX_UFC_D)) { 146 return XGE_HAL_BADCFG_RX_UFC_D; 147 } 148 149 if ((new_config->timer_val_us < XGE_HAL_MIN_RX_TIMER_VAL) || 150 (new_config->timer_val_us > XGE_HAL_MAX_RX_TIMER_VAL)) { 151 return XGE_HAL_BADCFG_RX_TIMER_VAL; 152 } 153 154 if ((new_config->timer_ac_en < XGE_HAL_MIN_RX_TIMER_AC_EN) || 155 (new_config->timer_ac_en > XGE_HAL_MAX_RX_TIMER_AC_EN)) { 156 return XGE_HAL_BADCFG_RX_TIMER_AC_EN; 157 } 158 159 return XGE_HAL_OK; 160 } 161 162 163 /* 164 * __hal_fifo_queue_check - Check fifo queue configuration 165 * @new_config: fifo queue configuration information 166 * 167 * Returns: XGE_HAL_OK - success, 168 * otherwise one of the xge_hal_status_e{} enumerated error codes. 169 */ 170 static xge_hal_status_e 171 __hal_fifo_queue_check (xge_hal_fifo_queue_t *new_config) 172 { 173 if ((new_config->initial < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) || 174 (new_config->initial > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) { 175 return XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH; 176 } 177 178 /* FIXME: queue "grow" feature is not supported. 179 * Use "initial" queue size as the "maximum"; 180 * Remove the next line when fixed. */ 181 new_config->max = new_config->initial; 182 183 if ((new_config->max < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) || 184 (new_config->max > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) { 185 return XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH; 186 } 187 188 if ((new_config->intr < XGE_HAL_MIN_FIFO_QUEUE_INTR) || 189 (new_config->intr > XGE_HAL_MAX_FIFO_QUEUE_INTR)) { 190 return XGE_HAL_BADCFG_FIFO_QUEUE_INTR; 191 } 192 193 return XGE_HAL_OK; 194 } 195 196 /* 197 * __hal_ring_queue_check - Check ring queue configuration 198 * @new_config: ring queue configuration information 199 * 200 * Returns: XGE_HAL_OK - success, 201 * otherwise one of the xge_hal_status_e{} enumerated error codes. 202 */ 203 static xge_hal_status_e 204 __hal_ring_queue_check (xge_hal_ring_queue_t *new_config) 205 { 206 207 if ((new_config->initial < XGE_HAL_MIN_RING_QUEUE_BLOCKS) || 208 (new_config->initial > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) { 209 return XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS; 210 } 211 212 /* FIXME: queue "grow" feature is not supported. 213 * Use "initial" queue size as the "maximum"; 214 * Remove the next line when fixed. */ 215 new_config->max = new_config->initial; 216 217 if ((new_config->max < XGE_HAL_MIN_RING_QUEUE_BLOCKS) || 218 (new_config->max > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) { 219 return XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS; 220 } 221 222 if ((new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_1) && 223 (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_3) && 224 (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_5)) { 225 return XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE; 226 } 227 228 /* 229 * Herc has less DRAM; the check is done later inside 230 * device_initialize() 231 */ 232 if (((new_config->dram_size_mb < XGE_HAL_MIN_RING_QUEUE_SIZE) || 233 (new_config->dram_size_mb > XGE_HAL_MAX_RING_QUEUE_SIZE_XENA)) && 234 new_config->dram_size_mb != XGE_HAL_DEFAULT_USE_HARDCODE) 235 return XGE_HAL_BADCFG_RING_QUEUE_SIZE; 236 237 if ((new_config->backoff_interval_us < 238 XGE_HAL_MIN_BACKOFF_INTERVAL_US) || 239 (new_config->backoff_interval_us > 240 XGE_HAL_MAX_BACKOFF_INTERVAL_US)) { 241 return XGE_HAL_BADCFG_BACKOFF_INTERVAL_US; 242 } 243 244 if ((new_config->max_frm_len < XGE_HAL_MIN_MAX_FRM_LEN) || 245 (new_config->max_frm_len > XGE_HAL_MAX_MAX_FRM_LEN)) { 246 return XGE_HAL_BADCFG_MAX_FRM_LEN; 247 } 248 249 if ((new_config->priority < XGE_HAL_MIN_RING_PRIORITY) || 250 (new_config->priority > XGE_HAL_MAX_RING_PRIORITY)) { 251 return XGE_HAL_BADCFG_RING_PRIORITY; 252 } 253 254 if ((new_config->rth_en < XGE_HAL_MIN_RING_RTH_EN) || 255 (new_config->rth_en > XGE_HAL_MAX_RING_RTH_EN)) { 256 return XGE_HAL_BADCFG_RING_RTH_EN; 257 } 258 259 if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_MAC_EN) || 260 (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_MAC_EN)) { 261 return XGE_HAL_BADCFG_RING_RTS_MAC_EN; 262 } 263 264 if (new_config->indicate_max_pkts < 265 XGE_HAL_MIN_RING_INDICATE_MAX_PKTS || 266 new_config->indicate_max_pkts > 267 XGE_HAL_MAX_RING_INDICATE_MAX_PKTS) { 268 return XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS; 269 } 270 271 return __hal_rti_config_check(&new_config->rti); 272 } 273 274 /* 275 * __hal_mac_config_check - Check mac configuration 276 * @new_config: mac configuration information 277 * 278 * Returns: XGE_HAL_OK - success, 279 * otherwise one of the xge_hal_status_e{} enumerated error codes. 280 */ 281 static xge_hal_status_e 282 __hal_mac_config_check (xge_hal_mac_config_t *new_config) 283 { 284 if ((new_config->tmac_util_period < XGE_HAL_MIN_TMAC_UTIL_PERIOD) || 285 (new_config->tmac_util_period > XGE_HAL_MAX_TMAC_UTIL_PERIOD)) { 286 return XGE_HAL_BADCFG_TMAC_UTIL_PERIOD; 287 } 288 289 if ((new_config->rmac_util_period < XGE_HAL_MIN_RMAC_UTIL_PERIOD) || 290 (new_config->rmac_util_period > XGE_HAL_MAX_RMAC_UTIL_PERIOD)) { 291 return XGE_HAL_BADCFG_RMAC_UTIL_PERIOD; 292 } 293 294 if ((new_config->rmac_bcast_en < XGE_HAL_MIN_RMAC_BCAST_EN) || 295 (new_config->rmac_bcast_en > XGE_HAL_MAX_RMAC_BCAST_EN)) { 296 return XGE_HAL_BADCFG_RMAC_BCAST_EN; 297 } 298 299 if ((new_config->rmac_pause_gen_en < XGE_HAL_MIN_RMAC_PAUSE_GEN_EN) || 300 (new_config->rmac_pause_gen_en>XGE_HAL_MAX_RMAC_PAUSE_GEN_EN)) { 301 return XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN; 302 } 303 304 if ((new_config->rmac_pause_rcv_en < XGE_HAL_MIN_RMAC_PAUSE_RCV_EN) || 305 (new_config->rmac_pause_rcv_en>XGE_HAL_MAX_RMAC_PAUSE_RCV_EN)) { 306 return XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN; 307 } 308 309 if ((new_config->rmac_pause_time < XGE_HAL_MIN_RMAC_HIGH_PTIME) || 310 (new_config->rmac_pause_time > XGE_HAL_MAX_RMAC_HIGH_PTIME)) { 311 return XGE_HAL_BADCFG_RMAC_HIGH_PTIME; 312 } 313 314 if ((new_config->media < XGE_HAL_MIN_MEDIA) || 315 (new_config->media > XGE_HAL_MAX_MEDIA)) { 316 return XGE_HAL_BADCFG_MEDIA; 317 } 318 319 if ((new_config->mc_pause_threshold_q0q3 < 320 XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3) || 321 (new_config->mc_pause_threshold_q0q3 > 322 XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3)) { 323 return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3; 324 } 325 326 if ((new_config->mc_pause_threshold_q4q7 < 327 XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7) || 328 (new_config->mc_pause_threshold_q4q7 > 329 XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7)) { 330 return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7; 331 } 332 333 return XGE_HAL_OK; 334 } 335 336 /* 337 * __hal_fifo_config_check - Check fifo configuration 338 * @new_config: fifo configuration information 339 * 340 * Returns: XGE_HAL_OK - success, 341 * otherwise one of the xge_hal_status_e{} enumerated error codes. 342 */ 343 static xge_hal_status_e 344 __hal_fifo_config_check (xge_hal_fifo_config_t *new_config) 345 { 346 int i; 347 348 /* 349 * recompute max_frags to be multiple of 4, 350 * which means, multiple of 128 for TxDL 351 */ 352 new_config->max_frags = ((new_config->max_frags + 3) >> 2) << 2; 353 354 if ((new_config->max_frags < XGE_HAL_MIN_FIFO_FRAGS) || 355 (new_config->max_frags > XGE_HAL_MAX_FIFO_FRAGS)) { 356 return XGE_HAL_BADCFG_FIFO_FRAGS; 357 } 358 359 if ((new_config->reserve_threshold < 360 XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD) || 361 (new_config->reserve_threshold > 362 XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD)) { 363 return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD; 364 } 365 366 if ((new_config->memblock_size < XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE) || 367 (new_config->memblock_size > XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE)) { 368 return XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE; 369 } 370 371 for(i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) { 372 xge_hal_status_e status; 373 374 if (!new_config->queue[i].configured) 375 continue; 376 377 if ((status = __hal_fifo_queue_check(&new_config->queue[i])) 378 != XGE_HAL_OK) { 379 return status; 380 } 381 } 382 383 return XGE_HAL_OK; 384 } 385 386 /* 387 * __hal_ring_config_check - Check ring configuration 388 * @new_config: Ring configuration information 389 * 390 * Returns: XGE_HAL_OK - success, 391 * otherwise one of the xge_hal_status_e{} enumerated error codes. 392 */ 393 static xge_hal_status_e 394 __hal_ring_config_check (xge_hal_ring_config_t *new_config) 395 { 396 int i; 397 398 if ((new_config->memblock_size < XGE_HAL_MIN_RING_MEMBLOCK_SIZE) || 399 (new_config->memblock_size > XGE_HAL_MAX_RING_MEMBLOCK_SIZE)) { 400 return XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE; 401 } 402 403 for(i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { 404 xge_hal_status_e status; 405 406 if (!new_config->queue[i].configured) 407 continue; 408 409 if ((status = __hal_ring_queue_check(&new_config->queue[i])) 410 != XGE_HAL_OK) { 411 return status; 412 } 413 } 414 415 return XGE_HAL_OK; 416 } 417 418 419 /* 420 * __hal_device_config_check_common - Check device configuration. 421 * @new_config: Device configuration information 422 * 423 * Check part of configuration that is common to 424 * Xframe-I and Xframe-II. 425 * 426 * Returns: XGE_HAL_OK - success, 427 * otherwise one of the xge_hal_status_e{} enumerated error codes. 428 * 429 * See also: __hal_device_config_check_xena(). 430 */ 431 xge_hal_status_e 432 __hal_device_config_check_common (xge_hal_device_config_t *new_config) 433 { 434 xge_hal_status_e status; 435 436 if ((new_config->mtu < XGE_HAL_MIN_MTU) || 437 (new_config->mtu > XGE_HAL_MAX_MTU)) { 438 return XGE_HAL_BADCFG_MAX_MTU; 439 } 440 441 if ((new_config->no_isr_events < XGE_HAL_NO_ISR_EVENTS_MIN) || 442 (new_config->no_isr_events > XGE_HAL_NO_ISR_EVENTS_MAX)) { 443 return XGE_HAL_BADCFG_NO_ISR_EVENTS; 444 } 445 446 if ((new_config->isr_polling_cnt < XGE_HAL_MIN_ISR_POLLING_CNT) || 447 (new_config->isr_polling_cnt > XGE_HAL_MAX_ISR_POLLING_CNT)) { 448 return XGE_HAL_BADCFG_ISR_POLLING_CNT; 449 } 450 451 if (new_config->latency_timer && 452 new_config->latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY) { 453 if ((new_config->latency_timer < XGE_HAL_MIN_LATENCY_TIMER) || 454 (new_config->latency_timer > XGE_HAL_MAX_LATENCY_TIMER)) { 455 return XGE_HAL_BADCFG_LATENCY_TIMER; 456 } 457 } 458 459 if (new_config->max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS) { 460 if ((new_config->max_splits_trans < 461 XGE_HAL_ONE_SPLIT_TRANSACTION) || 462 (new_config->max_splits_trans > 463 XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION)) 464 return XGE_HAL_BADCFG_MAX_SPLITS_TRANS; 465 } 466 467 if (new_config->mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT) 468 { 469 if ((new_config->mmrb_count < XGE_HAL_MIN_MMRB_COUNT) || 470 (new_config->mmrb_count > XGE_HAL_MAX_MMRB_COUNT)) { 471 return XGE_HAL_BADCFG_MMRB_COUNT; 472 } 473 } 474 475 if ((new_config->shared_splits < XGE_HAL_MIN_SHARED_SPLITS) || 476 (new_config->shared_splits > XGE_HAL_MAX_SHARED_SPLITS)) { 477 return XGE_HAL_BADCFG_SHARED_SPLITS; 478 } 479 480 if (new_config->stats_refresh_time_sec != 481 XGE_HAL_STATS_REFRESH_DISABLE) { 482 if ((new_config->stats_refresh_time_sec < 483 XGE_HAL_MIN_STATS_REFRESH_TIME) || 484 (new_config->stats_refresh_time_sec > 485 XGE_HAL_MAX_STATS_REFRESH_TIME)) { 486 return XGE_HAL_BADCFG_STATS_REFRESH_TIME; 487 } 488 } 489 490 if ((new_config->intr_mode != XGE_HAL_INTR_MODE_IRQLINE) && 491 (new_config->intr_mode != XGE_HAL_INTR_MODE_MSI) && 492 (new_config->intr_mode != XGE_HAL_INTR_MODE_MSIX)) { 493 return XGE_HAL_BADCFG_INTR_MODE; 494 } 495 496 if ((new_config->sched_timer_us < XGE_HAL_SCHED_TIMER_MIN) || 497 (new_config->sched_timer_us > XGE_HAL_SCHED_TIMER_MAX)) { 498 return XGE_HAL_BADCFG_SCHED_TIMER_US; 499 } 500 501 if ((new_config->sched_timer_one_shot != 502 XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE) && 503 (new_config->sched_timer_one_shot != 504 XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE)) { 505 return XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT; 506 } 507 508 if (new_config->sched_timer_us) { 509 if ((new_config->rxufca_intr_thres < 510 XGE_HAL_RXUFCA_INTR_THRES_MIN) || 511 (new_config->rxufca_intr_thres > 512 XGE_HAL_RXUFCA_INTR_THRES_MAX)) { 513 return XGE_HAL_BADCFG_RXUFCA_INTR_THRES; 514 } 515 516 if ((new_config->rxufca_hi_lim < XGE_HAL_RXUFCA_HI_LIM_MIN) || 517 (new_config->rxufca_hi_lim > XGE_HAL_RXUFCA_HI_LIM_MAX)) { 518 return XGE_HAL_BADCFG_RXUFCA_HI_LIM; 519 } 520 521 if ((new_config->rxufca_lo_lim < XGE_HAL_RXUFCA_LO_LIM_MIN) || 522 (new_config->rxufca_lo_lim > XGE_HAL_RXUFCA_LO_LIM_MAX) || 523 (new_config->rxufca_lo_lim > new_config->rxufca_hi_lim)) { 524 return XGE_HAL_BADCFG_RXUFCA_LO_LIM; 525 } 526 527 if ((new_config->rxufca_lbolt_period < 528 XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN) || 529 (new_config->rxufca_lbolt_period > 530 XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX)) { 531 return XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD; 532 } 533 } 534 535 if ((new_config->link_valid_cnt < XGE_HAL_LINK_VALID_CNT_MIN) || 536 (new_config->link_valid_cnt > XGE_HAL_LINK_VALID_CNT_MAX)) { 537 return XGE_HAL_BADCFG_LINK_VALID_CNT; 538 } 539 540 if ((new_config->link_retry_cnt < XGE_HAL_LINK_RETRY_CNT_MIN) || 541 (new_config->link_retry_cnt > XGE_HAL_LINK_RETRY_CNT_MAX)) { 542 return XGE_HAL_BADCFG_LINK_RETRY_CNT; 543 } 544 545 if (new_config->link_valid_cnt > new_config->link_retry_cnt) 546 return XGE_HAL_BADCFG_LINK_VALID_CNT; 547 548 if (new_config->link_stability_period != XGE_HAL_DEFAULT_USE_HARDCODE) { 549 if ((new_config->link_stability_period < 550 XGE_HAL_MIN_LINK_STABILITY_PERIOD) || 551 (new_config->link_stability_period > 552 XGE_HAL_MAX_LINK_STABILITY_PERIOD)) { 553 return XGE_HAL_BADCFG_LINK_STABILITY_PERIOD; 554 } 555 } 556 557 if (new_config->device_poll_millis != 558 XGE_HAL_DEFAULT_USE_HARDCODE) { 559 if ((new_config->device_poll_millis < 560 XGE_HAL_MIN_DEVICE_POLL_MILLIS) || 561 (new_config->device_poll_millis > 562 XGE_HAL_MAX_DEVICE_POLL_MILLIS)) { 563 return XGE_HAL_BADCFG_DEVICE_POLL_MILLIS; 564 } 565 } 566 567 if ((status = __hal_ring_config_check(&new_config->ring)) 568 != XGE_HAL_OK) { 569 return status; 570 } 571 572 if ((status = __hal_mac_config_check(&new_config->mac)) != 573 XGE_HAL_OK) { 574 return status; 575 } 576 577 /* 578 * Validate the tti configuration parameters only if the TTI 579 * feature is enabled. 580 */ 581 if (new_config->tti.enabled) { 582 if ((status = __hal_tti_config_check(&new_config->tti)) != 583 XGE_HAL_OK) { 584 return status; 585 } 586 } 587 588 if ((status = __hal_fifo_config_check(&new_config->fifo)) != 589 XGE_HAL_OK) { 590 return status; 591 } 592 593 return XGE_HAL_OK; 594 } 595 596 /* 597 * __hal_device_config_check_xena - Check Xframe-I configuration 598 * @new_config: Device configuration. 599 * 600 * Check part of configuration that is relevant only to Xframe-I. 601 * 602 * Returns: XGE_HAL_OK - success, 603 * otherwise one of the xge_hal_status_e{} enumerated error codes. 604 * 605 * See also: __hal_device_config_check_common(). 606 */ 607 xge_hal_status_e 608 __hal_device_config_check_xena (xge_hal_device_config_t *new_config) 609 { 610 if ((new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_33) && 611 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_66) && 612 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_100) && 613 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_133) && 614 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_266)) { 615 return XGE_HAL_BADCFG_PCI_FREQ_MHERZ; 616 } 617 618 return XGE_HAL_OK; 619 } 620 621 /* 622 * __hal_device_config_check_herc - Check device configuration 623 * @new_config: Device configuration. 624 * 625 * Check part of configuration that is relevant only to Xframe-II. 626 * 627 * Returns: XGE_HAL_OK - success, 628 * otherwise one of the xge_hal_status_e{} enumerated error codes. 629 * 630 * See also: __hal_device_config_check_common(). 631 */ 632 xge_hal_status_e 633 __hal_device_config_check_herc (xge_hal_device_config_t *new_config) 634 { 635 return XGE_HAL_OK; 636 } 637 638 639 /** 640 * __hal_driver_config_check - Check HAL configuration 641 * @new_config: Driver configuration information 642 * 643 * Returns: XGE_HAL_OK - success, 644 * otherwise one of the xge_hal_status_e{} enumerated error codes. 645 */ 646 xge_hal_status_e 647 __hal_driver_config_check (xge_hal_driver_config_t *new_config) 648 { 649 if ((new_config->queue_size_initial < 650 XGE_HAL_MIN_QUEUE_SIZE_INITIAL) || 651 (new_config->queue_size_initial > 652 XGE_HAL_MAX_QUEUE_SIZE_INITIAL)) { 653 return XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL; 654 } 655 656 if ((new_config->queue_size_max < XGE_HAL_MIN_QUEUE_SIZE_MAX) || 657 (new_config->queue_size_max > XGE_HAL_MAX_QUEUE_SIZE_MAX)) { 658 return XGE_HAL_BADCFG_QUEUE_SIZE_MAX; 659 } 660 661 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR 662 if ((new_config->tracebuf_size < XGE_HAL_MIN_CIRCULAR_ARR) || 663 (new_config->tracebuf_size > XGE_HAL_MAX_CIRCULAR_ARR)) { 664 return XGE_HAL_BADCFG_TRACEBUF_SIZE; 665 } 666 #endif 667 668 return XGE_HAL_OK; 669 } 670