1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #include "xgehal-config.h" 25 #include "xge-debug.h" 26 27 /* 28 * __hal_tti_config_check - Check tti configuration 29 * @new_config: tti configuration information 30 * 31 * Returns: XGE_HAL_OK - success, 32 * otherwise one of the xge_hal_status_e{} enumerated error codes. 33 */ 34 static xge_hal_status_e 35 __hal_tti_config_check (xge_hal_tti_config_t *new_config) 36 { 37 if ((new_config->urange_a < XGE_HAL_MIN_TX_URANGE_A) || 38 (new_config->urange_a > XGE_HAL_MAX_TX_URANGE_A)) { 39 return XGE_HAL_BADCFG_TX_URANGE_A; 40 } 41 42 if ((new_config->ufc_a < XGE_HAL_MIN_TX_UFC_A) || 43 (new_config->ufc_a > XGE_HAL_MAX_TX_UFC_A)) { 44 return XGE_HAL_BADCFG_TX_UFC_A; 45 } 46 47 if ((new_config->urange_b < XGE_HAL_MIN_TX_URANGE_B) || 48 (new_config->urange_b > XGE_HAL_MAX_TX_URANGE_B)) { 49 return XGE_HAL_BADCFG_TX_URANGE_B; 50 } 51 52 if ((new_config->ufc_b < XGE_HAL_MIN_TX_UFC_B) || 53 (new_config->ufc_b > XGE_HAL_MAX_TX_UFC_B)) { 54 return XGE_HAL_BADCFG_TX_UFC_B; 55 } 56 57 if ((new_config->urange_c < XGE_HAL_MIN_TX_URANGE_C) || 58 (new_config->urange_c > XGE_HAL_MAX_TX_URANGE_C)) { 59 return XGE_HAL_BADCFG_TX_URANGE_C; 60 } 61 62 if ((new_config->ufc_c < XGE_HAL_MIN_TX_UFC_C) || 63 (new_config->ufc_c > XGE_HAL_MAX_TX_UFC_C)) { 64 return XGE_HAL_BADCFG_TX_UFC_C; 65 } 66 67 if ((new_config->ufc_d < XGE_HAL_MIN_TX_UFC_D) || 68 (new_config->ufc_d > XGE_HAL_MAX_TX_UFC_D)) { 69 return XGE_HAL_BADCFG_TX_UFC_D; 70 } 71 72 if ((new_config->timer_val_us < XGE_HAL_MIN_TX_TIMER_VAL) || 73 (new_config->timer_val_us > XGE_HAL_MAX_TX_TIMER_VAL)) { 74 return XGE_HAL_BADCFG_TX_TIMER_VAL; 75 } 76 77 if ((new_config->timer_ci_en < XGE_HAL_MIN_TX_TIMER_CI_EN) || 78 (new_config->timer_ci_en > XGE_HAL_MAX_TX_TIMER_CI_EN)) { 79 return XGE_HAL_BADCFG_TX_TIMER_CI_EN; 80 } 81 82 if ((new_config->timer_ac_en < XGE_HAL_MIN_TX_TIMER_AC_EN) || 83 (new_config->timer_ac_en > XGE_HAL_MAX_TX_TIMER_AC_EN)) { 84 return XGE_HAL_BADCFG_TX_TIMER_AC_EN; 85 } 86 87 return XGE_HAL_OK; 88 } 89 90 /* 91 * __hal_rti_config_check - Check rti configuration 92 * @new_config: rti configuration information 93 * 94 * Returns: XGE_HAL_OK - success, 95 * otherwise one of the xge_hal_status_e{} enumerated error codes. 96 */ 97 static xge_hal_status_e 98 __hal_rti_config_check (xge_hal_rti_config_t *new_config) 99 { 100 if ((new_config->urange_a < XGE_HAL_MIN_RX_URANGE_A) || 101 (new_config->urange_a > XGE_HAL_MAX_RX_URANGE_A)) { 102 return XGE_HAL_BADCFG_RX_URANGE_A; 103 } 104 105 if ((new_config->ufc_a < XGE_HAL_MIN_RX_UFC_A) || 106 (new_config->ufc_a > XGE_HAL_MAX_RX_UFC_A)) { 107 return XGE_HAL_BADCFG_RX_UFC_A; 108 } 109 110 if ((new_config->urange_b < XGE_HAL_MIN_RX_URANGE_B) || 111 (new_config->urange_b > XGE_HAL_MAX_RX_URANGE_B)) { 112 return XGE_HAL_BADCFG_RX_URANGE_B; 113 } 114 115 if ((new_config->ufc_b < XGE_HAL_MIN_RX_UFC_B) || 116 (new_config->ufc_b > XGE_HAL_MAX_RX_UFC_B)) { 117 return XGE_HAL_BADCFG_RX_UFC_B; 118 } 119 120 if ((new_config->urange_c < XGE_HAL_MIN_RX_URANGE_C) || 121 (new_config->urange_c > XGE_HAL_MAX_RX_URANGE_C)) { 122 return XGE_HAL_BADCFG_RX_URANGE_C; 123 } 124 125 if ((new_config->ufc_c < XGE_HAL_MIN_RX_UFC_C) || 126 (new_config->ufc_c > XGE_HAL_MAX_RX_UFC_C)) { 127 return XGE_HAL_BADCFG_RX_UFC_C; 128 } 129 130 if ((new_config->ufc_d < XGE_HAL_MIN_RX_UFC_D) || 131 (new_config->ufc_d > XGE_HAL_MAX_RX_UFC_D)) { 132 return XGE_HAL_BADCFG_RX_UFC_D; 133 } 134 135 if ((new_config->timer_val_us < XGE_HAL_MIN_RX_TIMER_VAL) || 136 (new_config->timer_val_us > XGE_HAL_MAX_RX_TIMER_VAL)) { 137 return XGE_HAL_BADCFG_RX_TIMER_VAL; 138 } 139 140 if ((new_config->timer_ac_en < XGE_HAL_MIN_RX_TIMER_AC_EN) || 141 (new_config->timer_ac_en > XGE_HAL_MAX_RX_TIMER_AC_EN)) { 142 return XGE_HAL_BADCFG_RX_TIMER_AC_EN; 143 } 144 145 return XGE_HAL_OK; 146 } 147 148 149 /* 150 * __hal_fifo_queue_check - Check fifo queue configuration 151 * @new_config: fifo queue configuration information 152 * 153 * Returns: XGE_HAL_OK - success, 154 * otherwise one of the xge_hal_status_e{} enumerated error codes. 155 */ 156 static xge_hal_status_e 157 __hal_fifo_queue_check (xge_hal_fifo_config_t *new_config, 158 xge_hal_fifo_queue_t *new_queue) 159 { 160 int i; 161 162 if ((new_queue->initial < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) || 163 (new_queue->initial > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) { 164 return XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH; 165 } 166 167 /* FIXME: queue "grow" feature is not supported. 168 * Use "initial" queue size as the "maximum"; 169 * Remove the next line when fixed. */ 170 new_queue->max = new_queue->initial; 171 172 if ((new_queue->max < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) || 173 (new_queue->max > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) { 174 return XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH; 175 } 176 177 if (new_queue->max < new_config->reserve_threshold) { 178 return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD; 179 } 180 181 if ((new_queue->intr < XGE_HAL_MIN_FIFO_QUEUE_INTR) || 182 (new_queue->intr > XGE_HAL_MAX_FIFO_QUEUE_INTR)) { 183 return XGE_HAL_BADCFG_FIFO_QUEUE_INTR; 184 } 185 186 if ((new_queue->intr_vector < XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR) || 187 (new_queue->intr_vector > XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR)) { 188 return XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR; 189 } 190 191 for(i = 0; i < XGE_HAL_MAX_FIFO_TTI_NUM; i++) { 192 /* 193 * Validate the tti configuration parameters only if 194 * the TTI feature is enabled. 195 */ 196 if (new_queue->tti[i].enabled) { 197 xge_hal_status_e status; 198 199 if ((status = __hal_tti_config_check( 200 &new_queue->tti[i])) != XGE_HAL_OK) { 201 return status; 202 } 203 } 204 } 205 206 return XGE_HAL_OK; 207 } 208 209 /* 210 * __hal_ring_queue_check - Check ring queue configuration 211 * @new_config: ring queue configuration information 212 * 213 * Returns: XGE_HAL_OK - success, 214 * otherwise one of the xge_hal_status_e{} enumerated error codes. 215 */ 216 static xge_hal_status_e 217 __hal_ring_queue_check (xge_hal_ring_queue_t *new_config) 218 { 219 220 if ((new_config->initial < XGE_HAL_MIN_RING_QUEUE_BLOCKS) || 221 (new_config->initial > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) { 222 return XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS; 223 } 224 225 /* FIXME: queue "grow" feature is not supported. 226 * Use "initial" queue size as the "maximum"; 227 * Remove the next line when fixed. */ 228 new_config->max = new_config->initial; 229 230 if ((new_config->max < XGE_HAL_MIN_RING_QUEUE_BLOCKS) || 231 (new_config->max > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) { 232 return XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS; 233 } 234 235 if ((new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_1) && 236 (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_3) && 237 (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_5)) { 238 return XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE; 239 } 240 241 /* 242 * Herc has less DRAM; the check is done later inside 243 * device_initialize() 244 */ 245 if (((new_config->dram_size_mb < XGE_HAL_MIN_RING_QUEUE_SIZE) || 246 (new_config->dram_size_mb > XGE_HAL_MAX_RING_QUEUE_SIZE_XENA)) && 247 new_config->dram_size_mb != XGE_HAL_DEFAULT_USE_HARDCODE) 248 return XGE_HAL_BADCFG_RING_QUEUE_SIZE; 249 250 if ((new_config->backoff_interval_us < 251 XGE_HAL_MIN_BACKOFF_INTERVAL_US) || 252 (new_config->backoff_interval_us > 253 XGE_HAL_MAX_BACKOFF_INTERVAL_US)) { 254 return XGE_HAL_BADCFG_BACKOFF_INTERVAL_US; 255 } 256 257 if ((new_config->max_frm_len < XGE_HAL_MIN_MAX_FRM_LEN) || 258 (new_config->max_frm_len > XGE_HAL_MAX_MAX_FRM_LEN)) { 259 return XGE_HAL_BADCFG_MAX_FRM_LEN; 260 } 261 262 if ((new_config->priority < XGE_HAL_MIN_RING_PRIORITY) || 263 (new_config->priority > XGE_HAL_MAX_RING_PRIORITY)) { 264 return XGE_HAL_BADCFG_RING_PRIORITY; 265 } 266 267 if ((new_config->rth_en < XGE_HAL_MIN_RING_RTH_EN) || 268 (new_config->rth_en > XGE_HAL_MAX_RING_RTH_EN)) { 269 return XGE_HAL_BADCFG_RING_RTH_EN; 270 } 271 272 if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_MAC_EN) || 273 (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_MAC_EN)) { 274 return XGE_HAL_BADCFG_RING_RTS_MAC_EN; 275 } 276 277 if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_PORT_EN) || 278 (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_PORT_EN)) { 279 return XGE_HAL_BADCFG_RING_RTS_PORT_EN; 280 } 281 282 if ((new_config->intr_vector < XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR) || 283 (new_config->intr_vector > XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR)) { 284 return XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR; 285 } 286 287 if (new_config->indicate_max_pkts < 288 XGE_HAL_MIN_RING_INDICATE_MAX_PKTS || 289 new_config->indicate_max_pkts > 290 XGE_HAL_MAX_RING_INDICATE_MAX_PKTS) { 291 return XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS; 292 } 293 294 return __hal_rti_config_check(&new_config->rti); 295 } 296 297 /* 298 * __hal_mac_config_check - Check mac configuration 299 * @new_config: mac configuration information 300 * 301 * Returns: XGE_HAL_OK - success, 302 * otherwise one of the xge_hal_status_e{} enumerated error codes. 303 */ 304 static xge_hal_status_e 305 __hal_mac_config_check (xge_hal_mac_config_t *new_config) 306 { 307 if ((new_config->tmac_util_period < XGE_HAL_MIN_TMAC_UTIL_PERIOD) || 308 (new_config->tmac_util_period > XGE_HAL_MAX_TMAC_UTIL_PERIOD)) { 309 return XGE_HAL_BADCFG_TMAC_UTIL_PERIOD; 310 } 311 312 if ((new_config->rmac_util_period < XGE_HAL_MIN_RMAC_UTIL_PERIOD) || 313 (new_config->rmac_util_period > XGE_HAL_MAX_RMAC_UTIL_PERIOD)) { 314 return XGE_HAL_BADCFG_RMAC_UTIL_PERIOD; 315 } 316 317 if ((new_config->rmac_bcast_en < XGE_HAL_MIN_RMAC_BCAST_EN) || 318 (new_config->rmac_bcast_en > XGE_HAL_MAX_RMAC_BCAST_EN)) { 319 return XGE_HAL_BADCFG_RMAC_BCAST_EN; 320 } 321 322 if ((new_config->rmac_pause_gen_en < XGE_HAL_MIN_RMAC_PAUSE_GEN_EN) || 323 (new_config->rmac_pause_gen_en>XGE_HAL_MAX_RMAC_PAUSE_GEN_EN)) { 324 return XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN; 325 } 326 327 if ((new_config->rmac_pause_rcv_en < XGE_HAL_MIN_RMAC_PAUSE_RCV_EN) || 328 (new_config->rmac_pause_rcv_en>XGE_HAL_MAX_RMAC_PAUSE_RCV_EN)) { 329 return XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN; 330 } 331 332 if ((new_config->rmac_pause_time < XGE_HAL_MIN_RMAC_HIGH_PTIME) || 333 (new_config->rmac_pause_time > XGE_HAL_MAX_RMAC_HIGH_PTIME)) { 334 return XGE_HAL_BADCFG_RMAC_HIGH_PTIME; 335 } 336 337 if ((new_config->media < XGE_HAL_MIN_MEDIA) || 338 (new_config->media > XGE_HAL_MAX_MEDIA)) { 339 return XGE_HAL_BADCFG_MEDIA; 340 } 341 342 if ((new_config->mc_pause_threshold_q0q3 < 343 XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3) || 344 (new_config->mc_pause_threshold_q0q3 > 345 XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3)) { 346 return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3; 347 } 348 349 if ((new_config->mc_pause_threshold_q4q7 < 350 XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7) || 351 (new_config->mc_pause_threshold_q4q7 > 352 XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7)) { 353 return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7; 354 } 355 356 return XGE_HAL_OK; 357 } 358 359 /* 360 * __hal_fifo_config_check - Check fifo configuration 361 * @new_config: fifo configuration information 362 * 363 * Returns: XGE_HAL_OK - success, 364 * otherwise one of the xge_hal_status_e{} enumerated error codes. 365 */ 366 static xge_hal_status_e 367 __hal_fifo_config_check (xge_hal_fifo_config_t *new_config) 368 { 369 int i; 370 int total_fifo_length = 0; 371 372 /* 373 * recompute max_frags to be multiple of 4, 374 * which means, multiple of 128 for TxDL 375 */ 376 new_config->max_frags = ((new_config->max_frags + 3) >> 2) << 2; 377 378 if ((new_config->max_frags < XGE_HAL_MIN_FIFO_FRAGS) || 379 (new_config->max_frags > XGE_HAL_MAX_FIFO_FRAGS)) { 380 return XGE_HAL_BADCFG_FIFO_FRAGS; 381 } 382 383 if ((new_config->reserve_threshold < 384 XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD) || 385 (new_config->reserve_threshold > 386 XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD)) { 387 return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD; 388 } 389 390 if ((new_config->memblock_size < XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE) || 391 (new_config->memblock_size > XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE)) { 392 return XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE; 393 } 394 395 for(i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) { 396 xge_hal_status_e status; 397 398 if (!new_config->queue[i].configured) 399 continue; 400 401 if ((status = __hal_fifo_queue_check(new_config, 402 &new_config->queue[i])) != XGE_HAL_OK) { 403 return status; 404 } 405 406 total_fifo_length += new_config->queue[i].max; 407 } 408 409 if(total_fifo_length > XGE_HAL_MAX_FIFO_QUEUE_LENGTH){ 410 return XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH; 411 } 412 413 return XGE_HAL_OK; 414 } 415 416 /* 417 * __hal_ring_config_check - Check ring configuration 418 * @new_config: Ring configuration information 419 * 420 * Returns: XGE_HAL_OK - success, 421 * otherwise one of the xge_hal_status_e{} enumerated error codes. 422 */ 423 static xge_hal_status_e 424 __hal_ring_config_check (xge_hal_ring_config_t *new_config) 425 { 426 int i; 427 428 if ((new_config->memblock_size < XGE_HAL_MIN_RING_MEMBLOCK_SIZE) || 429 (new_config->memblock_size > XGE_HAL_MAX_RING_MEMBLOCK_SIZE)) { 430 return XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE; 431 } 432 433 for(i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { 434 xge_hal_status_e status; 435 436 if (!new_config->queue[i].configured) 437 continue; 438 439 if ((status = __hal_ring_queue_check(&new_config->queue[i])) 440 != XGE_HAL_OK) { 441 return status; 442 } 443 } 444 445 return XGE_HAL_OK; 446 } 447 448 449 /* 450 * __hal_device_config_check_common - Check device configuration. 451 * @new_config: Device configuration information 452 * 453 * Check part of configuration that is common to 454 * Xframe-I and Xframe-II. 455 * 456 * Returns: XGE_HAL_OK - success, 457 * otherwise one of the xge_hal_status_e{} enumerated error codes. 458 * 459 * See also: __hal_device_config_check_xena(). 460 */ 461 xge_hal_status_e 462 __hal_device_config_check_common (xge_hal_device_config_t *new_config) 463 { 464 xge_hal_status_e status; 465 466 if ((new_config->mtu < XGE_HAL_MIN_MTU) || 467 (new_config->mtu > XGE_HAL_MAX_MTU)) { 468 return XGE_HAL_BADCFG_MAX_MTU; 469 } 470 471 if ((new_config->bimodal_interrupts < XGE_HAL_BIMODAL_INTR_MIN) || 472 (new_config->bimodal_interrupts > XGE_HAL_BIMODAL_INTR_MAX)) { 473 return XGE_HAL_BADCFG_BIMODAL_INTR; 474 } 475 476 if (new_config->bimodal_interrupts && 477 ((new_config->bimodal_timer_lo_us < XGE_HAL_BIMODAL_TIMER_LO_US_MIN) || 478 (new_config->bimodal_timer_lo_us > XGE_HAL_BIMODAL_TIMER_LO_US_MAX))) { 479 return XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US; 480 } 481 482 if (new_config->bimodal_interrupts && 483 ((new_config->bimodal_timer_hi_us < XGE_HAL_BIMODAL_TIMER_HI_US_MIN) || 484 (new_config->bimodal_timer_hi_us > XGE_HAL_BIMODAL_TIMER_HI_US_MAX))) { 485 return XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US; 486 } 487 488 if ((new_config->no_isr_events < XGE_HAL_NO_ISR_EVENTS_MIN) || 489 (new_config->no_isr_events > XGE_HAL_NO_ISR_EVENTS_MAX)) { 490 return XGE_HAL_BADCFG_NO_ISR_EVENTS; 491 } 492 493 if ((new_config->isr_polling_cnt < XGE_HAL_MIN_ISR_POLLING_CNT) || 494 (new_config->isr_polling_cnt > XGE_HAL_MAX_ISR_POLLING_CNT)) { 495 return XGE_HAL_BADCFG_ISR_POLLING_CNT; 496 } 497 498 if (new_config->latency_timer && 499 new_config->latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY) { 500 if ((new_config->latency_timer < XGE_HAL_MIN_LATENCY_TIMER) || 501 (new_config->latency_timer > XGE_HAL_MAX_LATENCY_TIMER)) { 502 return XGE_HAL_BADCFG_LATENCY_TIMER; 503 } 504 } 505 506 if (new_config->max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS) { 507 if ((new_config->max_splits_trans < 508 XGE_HAL_ONE_SPLIT_TRANSACTION) || 509 (new_config->max_splits_trans > 510 XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION)) 511 return XGE_HAL_BADCFG_MAX_SPLITS_TRANS; 512 } 513 514 if (new_config->mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT) 515 { 516 if ((new_config->mmrb_count < XGE_HAL_MIN_MMRB_COUNT) || 517 (new_config->mmrb_count > XGE_HAL_MAX_MMRB_COUNT)) { 518 return XGE_HAL_BADCFG_MMRB_COUNT; 519 } 520 } 521 522 if ((new_config->shared_splits < XGE_HAL_MIN_SHARED_SPLITS) || 523 (new_config->shared_splits > XGE_HAL_MAX_SHARED_SPLITS)) { 524 return XGE_HAL_BADCFG_SHARED_SPLITS; 525 } 526 527 if (new_config->stats_refresh_time_sec != 528 XGE_HAL_STATS_REFRESH_DISABLE) { 529 if ((new_config->stats_refresh_time_sec < 530 XGE_HAL_MIN_STATS_REFRESH_TIME) || 531 (new_config->stats_refresh_time_sec > 532 XGE_HAL_MAX_STATS_REFRESH_TIME)) { 533 return XGE_HAL_BADCFG_STATS_REFRESH_TIME; 534 } 535 } 536 537 if ((new_config->intr_mode != XGE_HAL_INTR_MODE_IRQLINE) && 538 (new_config->intr_mode != XGE_HAL_INTR_MODE_MSI) && 539 (new_config->intr_mode != XGE_HAL_INTR_MODE_MSIX)) { 540 return XGE_HAL_BADCFG_INTR_MODE; 541 } 542 543 if ((new_config->sched_timer_us < XGE_HAL_SCHED_TIMER_MIN) || 544 (new_config->sched_timer_us > XGE_HAL_SCHED_TIMER_MAX)) { 545 return XGE_HAL_BADCFG_SCHED_TIMER_US; 546 } 547 548 if ((new_config->sched_timer_one_shot != 549 XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE) && 550 (new_config->sched_timer_one_shot != 551 XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE)) { 552 return XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT; 553 } 554 555 /* 556 * Check adaptive schema parameters. Note that there are two 557 * configuration variables needs to be enabled in ULD: 558 * 559 * a) sched_timer_us should not be zero; 560 * b) rxufca_hi_lim should not be equal to rxufca_lo_lim. 561 * 562 * The code bellow checking for those conditions. 563 */ 564 if (new_config->sched_timer_us && 565 new_config->rxufca_hi_lim != new_config->rxufca_lo_lim) { 566 if ((new_config->rxufca_intr_thres < 567 XGE_HAL_RXUFCA_INTR_THRES_MIN) || 568 (new_config->rxufca_intr_thres > 569 XGE_HAL_RXUFCA_INTR_THRES_MAX)) { 570 return XGE_HAL_BADCFG_RXUFCA_INTR_THRES; 571 } 572 573 if ((new_config->rxufca_hi_lim < XGE_HAL_RXUFCA_HI_LIM_MIN) || 574 (new_config->rxufca_hi_lim > XGE_HAL_RXUFCA_HI_LIM_MAX)) { 575 return XGE_HAL_BADCFG_RXUFCA_HI_LIM; 576 } 577 578 if ((new_config->rxufca_lo_lim < XGE_HAL_RXUFCA_LO_LIM_MIN) || 579 (new_config->rxufca_lo_lim > XGE_HAL_RXUFCA_LO_LIM_MAX) || 580 (new_config->rxufca_lo_lim > new_config->rxufca_hi_lim)) { 581 return XGE_HAL_BADCFG_RXUFCA_LO_LIM; 582 } 583 584 if ((new_config->rxufca_lbolt_period < 585 XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN) || 586 (new_config->rxufca_lbolt_period > 587 XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX)) { 588 return XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD; 589 } 590 } 591 592 if ((new_config->link_valid_cnt < XGE_HAL_LINK_VALID_CNT_MIN) || 593 (new_config->link_valid_cnt > XGE_HAL_LINK_VALID_CNT_MAX)) { 594 return XGE_HAL_BADCFG_LINK_VALID_CNT; 595 } 596 597 if ((new_config->link_retry_cnt < XGE_HAL_LINK_RETRY_CNT_MIN) || 598 (new_config->link_retry_cnt > XGE_HAL_LINK_RETRY_CNT_MAX)) { 599 return XGE_HAL_BADCFG_LINK_RETRY_CNT; 600 } 601 602 if (new_config->link_valid_cnt > new_config->link_retry_cnt) 603 return XGE_HAL_BADCFG_LINK_VALID_CNT; 604 605 if (new_config->link_stability_period != XGE_HAL_DEFAULT_USE_HARDCODE) { 606 if ((new_config->link_stability_period < 607 XGE_HAL_MIN_LINK_STABILITY_PERIOD) || 608 (new_config->link_stability_period > 609 XGE_HAL_MAX_LINK_STABILITY_PERIOD)) { 610 return XGE_HAL_BADCFG_LINK_STABILITY_PERIOD; 611 } 612 } 613 614 if (new_config->device_poll_millis != 615 XGE_HAL_DEFAULT_USE_HARDCODE) { 616 if ((new_config->device_poll_millis < 617 XGE_HAL_MIN_DEVICE_POLL_MILLIS) || 618 (new_config->device_poll_millis > 619 XGE_HAL_MAX_DEVICE_POLL_MILLIS)) { 620 return XGE_HAL_BADCFG_DEVICE_POLL_MILLIS; 621 } 622 } 623 624 if ((new_config->rts_port_en < XGE_HAL_MIN_RING_RTS_PORT_EN) || 625 (new_config->rts_port_en > XGE_HAL_MAX_RING_RTS_PORT_EN)) { 626 return XGE_HAL_BADCFG_RTS_PORT_EN; 627 } 628 629 if ((new_config->rts_qos_en < XGE_HAL_RTS_QOS_DISABLE) || 630 (new_config->rts_qos_en > XGE_HAL_RTS_QOS_ENABLE)) { 631 return XGE_HAL_BADCFG_RTS_QOS_EN; 632 } 633 634 #if defined(XGE_HAL_CONFIG_LRO) 635 if (new_config->lro_sg_size != 636 XGE_HAL_DEFAULT_USE_HARDCODE) { 637 if ((new_config->lro_sg_size < XGE_HAL_LRO_MIN_SG_SIZE) || 638 (new_config->lro_sg_size > XGE_HAL_LRO_MAX_SG_SIZE)) { 639 return XGE_HAL_BADCFG_LRO_SG_SIZE; 640 } 641 } 642 643 if (new_config->lro_frm_len != 644 XGE_HAL_DEFAULT_USE_HARDCODE) { 645 if ((new_config->lro_frm_len < XGE_HAL_LRO_MIN_FRM_LEN) || 646 (new_config->lro_frm_len > XGE_HAL_LRO_MAX_FRM_LEN)) { 647 return XGE_HAL_BADCFG_LRO_FRM_LEN; 648 } 649 } 650 #endif 651 652 if ((status = __hal_ring_config_check(&new_config->ring)) 653 != XGE_HAL_OK) { 654 return status; 655 } 656 657 if ((status = __hal_mac_config_check(&new_config->mac)) != 658 XGE_HAL_OK) { 659 return status; 660 } 661 662 if ((status = __hal_fifo_config_check(&new_config->fifo)) != 663 XGE_HAL_OK) { 664 return status; 665 } 666 667 return XGE_HAL_OK; 668 } 669 670 /* 671 * __hal_device_config_check_xena - Check Xframe-I configuration 672 * @new_config: Device configuration. 673 * 674 * Check part of configuration that is relevant only to Xframe-I. 675 * 676 * Returns: XGE_HAL_OK - success, 677 * otherwise one of the xge_hal_status_e{} enumerated error codes. 678 * 679 * See also: __hal_device_config_check_common(). 680 */ 681 xge_hal_status_e 682 __hal_device_config_check_xena (xge_hal_device_config_t *new_config) 683 { 684 if ((new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_33) && 685 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_66) && 686 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_100) && 687 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_133) && 688 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_266) && 689 (new_config->pci_freq_mherz != XGE_HAL_DEFAULT_USE_HARDCODE)) { 690 return XGE_HAL_BADCFG_PCI_FREQ_MHERZ; 691 } 692 693 return XGE_HAL_OK; 694 } 695 696 /* 697 * __hal_device_config_check_herc - Check device configuration 698 * @new_config: Device configuration. 699 * 700 * Check part of configuration that is relevant only to Xframe-II. 701 * 702 * Returns: XGE_HAL_OK - success, 703 * otherwise one of the xge_hal_status_e{} enumerated error codes. 704 * 705 * See also: __hal_device_config_check_common(). 706 */ 707 xge_hal_status_e 708 __hal_device_config_check_herc (xge_hal_device_config_t *new_config) 709 { 710 return XGE_HAL_OK; 711 } 712 713 714 /* 715 * __hal_driver_config_check - Check HAL configuration 716 * @new_config: Driver configuration information 717 * 718 * Returns: XGE_HAL_OK - success, 719 * otherwise one of the xge_hal_status_e{} enumerated error codes. 720 */ 721 xge_hal_status_e 722 __hal_driver_config_check (xge_hal_driver_config_t *new_config) 723 { 724 if ((new_config->queue_size_initial < 725 XGE_HAL_MIN_QUEUE_SIZE_INITIAL) || 726 (new_config->queue_size_initial > 727 XGE_HAL_MAX_QUEUE_SIZE_INITIAL)) { 728 return XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL; 729 } 730 731 if ((new_config->queue_size_max < XGE_HAL_MIN_QUEUE_SIZE_MAX) || 732 (new_config->queue_size_max > XGE_HAL_MAX_QUEUE_SIZE_MAX)) { 733 return XGE_HAL_BADCFG_QUEUE_SIZE_MAX; 734 } 735 736 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR 737 if ((new_config->tracebuf_size < XGE_HAL_MIN_CIRCULAR_ARR) || 738 (new_config->tracebuf_size > XGE_HAL_MAX_CIRCULAR_ARR)) { 739 return XGE_HAL_BADCFG_TRACEBUF_SIZE; 740 } 741 if ((new_config->tracebuf_timestamp_en < XGE_HAL_MIN_TIMESTAMP_EN) || 742 (new_config->tracebuf_timestamp_en > XGE_HAL_MAX_TIMESTAMP_EN)) { 743 return XGE_HAL_BADCFG_TRACEBUF_SIZE; 744 } 745 #endif 746 747 return XGE_HAL_OK; 748 } 749