1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef XGE_HAL_REGS_H 30 #define XGE_HAL_REGS_H 31 32 __EXTERN_BEGIN_DECLS 33 34 typedef struct { 35 36 /* General Control-Status Registers */ 37 u64 general_int_status; 38 #define XGE_HAL_GEN_INTR_TXPIC BIT(0) 39 #define XGE_HAL_GEN_INTR_TXDMA BIT(1) 40 #define XGE_HAL_GEN_INTR_TXMAC BIT(2) 41 #define XGE_HAL_GEN_INTR_TXXGXS BIT(3) 42 #define XGE_HAL_GEN_INTR_TXTRAFFIC BIT(8) 43 #define XGE_HAL_GEN_INTR_RXPIC BIT(32) 44 #define XGE_HAL_GEN_INTR_RXDMA BIT(33) 45 #define XGE_HAL_GEN_INTR_RXMAC BIT(34) 46 #define XGE_HAL_GEN_INTR_MC BIT(35) 47 #define XGE_HAL_GEN_INTR_RXXGXS BIT(36) 48 #define XGE_HAL_GEN_INTR_RXTRAFFIC BIT(40) 49 #define XGE_HAL_GEN_ERROR_INTR (XGE_HAL_GEN_INTR_TXPIC | \ 50 XGE_HAL_GEN_INTR_RXPIC | \ 51 XGE_HAL_GEN_INTR_TXDMA | \ 52 XGE_HAL_GEN_INTR_RXDMA | \ 53 XGE_HAL_GEN_INTR_TXMAC | \ 54 XGE_HAL_GEN_INTR_RXMAC | \ 55 XGE_HAL_GEN_INTR_TXXGXS | \ 56 XGE_HAL_GEN_INTR_RXXGXS | \ 57 XGE_HAL_GEN_INTR_MC) 58 59 u64 general_int_mask; 60 61 u8 unused0[0x100 - 0x10]; 62 63 u64 sw_reset; 64 65 /* XGXS must be removed from reset only once. */ 66 #define XGE_HAL_SW_RESET_XENA vBIT(0xA5,0,8) 67 #define XGE_HAL_SW_RESET_FLASH vBIT(0xA5,8,8) 68 #define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8) 69 #define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8) 70 #define XGE_HAL_SW_RESET_ALL (XGE_HAL_SW_RESET_XENA | \ 71 XGE_HAL_SW_RESET_FLASH | \ 72 XGE_HAL_SW_RESET_EOI | \ 73 XGE_HAL_SW_RESET_XGXS) 74 75 /* The SW_RESET register must read this value after a successful reset. */ 76 #if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN) 77 #define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA500000000ULL 78 #define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A500000000ULL 79 #else 80 #define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA5000000ULL 81 #define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A50000ULL 82 #endif 83 84 85 u64 adapter_status; 86 #define XGE_HAL_ADAPTER_STATUS_TDMA_READY BIT(0) 87 #define XGE_HAL_ADAPTER_STATUS_RDMA_READY BIT(1) 88 #define XGE_HAL_ADAPTER_STATUS_PFC_READY BIT(2) 89 #define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3) 90 #define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT BIT(5) 91 #define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6) 92 #define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7) 93 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) 94 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8) 95 #define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR vBIT(0x0F,0,8) 96 97 #define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) 98 #define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY BIT(24) 99 #define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY BIT(25) 100 #define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK BIT(30) 101 #define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK BIT(31) 102 103 u64 adapter_control; 104 #define XGE_HAL_ADAPTER_CNTL_EN BIT(7) 105 #define XGE_HAL_ADAPTER_EOI_TX_ON BIT(15) 106 #define XGE_HAL_ADAPTER_LED_ON BIT(23) 107 #define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4) 108 #define XGE_HAL_ADAPTER_WAIT_INT BIT(48) 109 #define XGE_HAL_ADAPTER_ECC_EN BIT(55) 110 111 u64 serr_source; 112 #define XGE_HAL_SERR_SOURCE_PIC BIT(0) 113 #define XGE_HAL_SERR_SOURCE_TXDMA BIT(1) 114 #define XGE_HAL_SERR_SOURCE_RXDMA BIT(2) 115 #define XGE_HAL_SERR_SOURCE_MAC BIT(3) 116 #define XGE_HAL_SERR_SOURCE_MC BIT(4) 117 #define XGE_HAL_SERR_SOURCE_XGXS BIT(5) 118 #define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \ 119 XGE_HAL_SERR_SOURCE_TXDMA | \ 120 XGE_HAL_SERR_SOURCE_RXDMA | \ 121 XGE_HAL_SERR_SOURCE_MAC | \ 122 XGE_HAL_SERR_SOURCE_MC | \ 123 XGE_HAL_SERR_SOURCE_XGXS) 124 125 u64 pci_info; 126 #define XGE_HAL_PCI_INFO vBIT(0xF,0,4) 127 #define XGE_HAL_PCI_32_BIT BIT(8) 128 129 u8 unused0_1[0x160 - 0x128]; 130 131 u64 ric_status; 132 133 u8 unused0_2[0x558 - 0x168]; 134 135 u64 mbist_status; 136 137 u8 unused0_3[0x800 - 0x560]; 138 139 /* PCI-X Controller registers */ 140 u64 pic_int_status; 141 u64 pic_int_mask; 142 #define XGE_HAL_PIC_INT_TX BIT(0) 143 #define XGE_HAL_PIC_INT_FLSH BIT(1) 144 #define XGE_HAL_PIC_INT_MDIO BIT(2) 145 #define XGE_HAL_PIC_INT_IIC BIT(3) 146 #define XGE_HAL_PIC_INT_MISC BIT(4) 147 #define XGE_HAL_PIC_INT_RX BIT(32) 148 149 u64 txpic_int_reg; 150 #define XGE_HAL_TXPIC_INT_SCHED_INTR BIT(42) 151 u64 txpic_int_mask; 152 #define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR BIT(0) 153 #define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR BIT(1) 154 #define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8) 155 #define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9) 156 #define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR BIT(10) 157 #define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11) 158 #define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR BIT(13) 159 #define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR BIT(14) 160 #define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR BIT(15) 161 #define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21) 162 #define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23) 163 #define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR BIT(48) 164 #define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR BIT(50) 165 /* 166 #define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52) 167 #define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54) 168 #define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58) 169 */ 170 u64 txpic_alarms; 171 u64 rxpic_int_reg; 172 #define XGE_HAL_RX_PIC_INT_REG_SPDM_READY BIT(0) 173 #define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR BIT(44) 174 #define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR BIT(55) 175 u64 rxpic_int_mask; 176 u64 rxpic_alarms; 177 178 u64 flsh_int_reg; 179 u64 flsh_int_mask; 180 #define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63) 181 #define XGE_HAL_PIC_FLSH_INT_REG_ERR BIT(62) 182 u64 flash_alarms; 183 184 u64 mdio_int_reg; 185 u64 mdio_int_mask; 186 #define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR BIT(0) 187 #define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR BIT(8) 188 #define XGE_HAL_MDIO_INT_REG_LASI BIT(39) 189 u64 mdio_alarms; 190 191 u64 iic_int_reg; 192 u64 iic_int_mask; 193 #define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR BIT(4) 194 #define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR BIT(5) 195 #define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR BIT(6) 196 #define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR BIT(7) 197 #define XGE_HAL_IIC_INT_REG_ACK_ERR BIT(8) 198 u64 iic_alarms; 199 200 u64 msi_pending_reg; 201 202 u64 misc_int_reg; 203 #define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0) 204 #define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1) 205 #define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2) 206 u64 misc_int_mask; 207 u64 misc_alarms; 208 209 u64 msi_triggered_reg; 210 211 u64 xfp_gpio_int_reg; 212 u64 xfp_gpio_int_mask; 213 u64 xfp_alarms; 214 215 u8 unused5[0x8E0 - 0x8C8]; 216 217 u64 tx_traffic_int; 218 #define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n) 219 u64 tx_traffic_mask; 220 221 u64 rx_traffic_int; 222 #define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n) 223 u64 rx_traffic_mask; 224 225 /* PIC Control registers */ 226 u64 pic_control; 227 #define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1 BIT(0) 228 #define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT BIT(1) 229 #define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4) 230 231 u64 swapper_ctrl; 232 #define XGE_HAL_SWAPPER_CTRL_PIF_R_FE BIT(0) 233 #define XGE_HAL_SWAPPER_CTRL_PIF_R_SE BIT(1) 234 #define XGE_HAL_SWAPPER_CTRL_PIF_W_FE BIT(8) 235 #define XGE_HAL_SWAPPER_CTRL_PIF_W_SE BIT(9) 236 #define XGE_HAL_SWAPPER_CTRL_RTH_FE BIT(10) 237 #define XGE_HAL_SWAPPER_CTRL_RTH_SE BIT(11) 238 #define XGE_HAL_SWAPPER_CTRL_TXP_FE BIT(16) 239 #define XGE_HAL_SWAPPER_CTRL_TXP_SE BIT(17) 240 #define XGE_HAL_SWAPPER_CTRL_TXD_R_FE BIT(18) 241 #define XGE_HAL_SWAPPER_CTRL_TXD_R_SE BIT(19) 242 #define XGE_HAL_SWAPPER_CTRL_TXD_W_FE BIT(20) 243 #define XGE_HAL_SWAPPER_CTRL_TXD_W_SE BIT(21) 244 #define XGE_HAL_SWAPPER_CTRL_TXF_R_FE BIT(22) 245 #define XGE_HAL_SWAPPER_CTRL_TXF_R_SE BIT(23) 246 #define XGE_HAL_SWAPPER_CTRL_RXD_R_FE BIT(32) 247 #define XGE_HAL_SWAPPER_CTRL_RXD_R_SE BIT(33) 248 #define XGE_HAL_SWAPPER_CTRL_RXD_W_FE BIT(34) 249 #define XGE_HAL_SWAPPER_CTRL_RXD_W_SE BIT(35) 250 #define XGE_HAL_SWAPPER_CTRL_RXF_W_FE BIT(36) 251 #define XGE_HAL_SWAPPER_CTRL_RXF_W_SE BIT(37) 252 #define XGE_HAL_SWAPPER_CTRL_XMSI_FE BIT(40) 253 #define XGE_HAL_SWAPPER_CTRL_XMSI_SE BIT(41) 254 #define XGE_HAL_SWAPPER_CTRL_STATS_FE BIT(48) 255 #define XGE_HAL_SWAPPER_CTRL_STATS_SE BIT(49) 256 257 u64 pif_rd_swapper_fb; 258 #define XGE_HAL_IF_RD_SWAPPER_FB 0x0123456789ABCDEFULL 259 260 u64 scheduled_int_ctrl; 261 #define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0) 262 #define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT BIT(1) 263 #define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) 264 #define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32) 265 #define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL 266 267 268 u64 txreqtimeout; 269 #define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32) 270 #define XGE_HAL_TXREQTO_EN BIT(63) 271 272 u64 statsreqtimeout; 273 #define XGE_HAL_STATREQTO_VAL(n) TBD 274 #define XGE_HAL_STATREQTO_EN BIT(63) 275 276 u64 read_retry_delay; 277 u64 read_retry_acceleration; 278 u64 write_retry_delay; 279 u64 write_retry_acceleration; 280 281 u64 xmsi_control; 282 #define XGE_HAL_XMSI_EN BIT(0) 283 #define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1) 284 #define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3) 285 286 u64 xmsi_access; 287 #define XGE_HAL_XMSI_WR_RDN BIT(7) 288 #define XGE_HAL_XMSI_STROBE BIT(15) 289 #define XGE_HAL_XMSI_NO(val) vBIT(val,26,6) 290 291 u64 xmsi_address; 292 u64 xmsi_data; 293 294 u64 rx_mat; 295 #define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8) 296 297 u8 unused6[0x8]; 298 299 u64 tx_mat[8]; 300 #define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8) 301 302 u64 xmsi_mask_reg; 303 304 /* Automated statistics collection */ 305 u64 stat_byte_cnt; 306 #define XGE_HAL_STAT_BYTE_CNT(n) vBIT(n, 4, 12) 307 u64 stat_cfg; 308 #define XGE_HAL_STAT_CFG_STAT_EN BIT(0) 309 #define XGE_HAL_STAT_CFG_ONE_SHOT_EN BIT(1) 310 #define XGE_HAL_STAT_CFG_STAT_NS_EN BIT(8) 311 #define XGE_HAL_STAT_CFG_STAT_RO BIT(9) 312 #define XGE_HAL_XENA_PER_SEC 0x208d5 313 #define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32) 314 315 u64 stat_addr; 316 317 /* General Configuration */ 318 u64 mdio_control; 319 #define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16) 320 #define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n) vBIT(n,19,5) 321 #define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n) vBIT(n,27,5) 322 #define XGE_HAL_MDIO_CONTROL_MMD_DATA(n) vBIT(n,32,16) 323 #define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n) vBIT(n,56,4) 324 #define XGE_HAL_MDIO_CONTROL_MMD_OP(n) vBIT(n,60,2) 325 #define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n) ((n>>16)&0xFFFF) 326 #define XGE_HAL_MDIO_MMD_PMA_DEV_ADDR 0x01 327 #define XGE_HAL_MDIO_DOM_REG_ADDR 0xA100 328 #define XGE_HAL_MDIO_ALARM_FLAGS_ADDR 0xA070 329 #define XGE_HAL_MDIO_WARN_FLAGS_ADDR 0xA074 330 #define XGE_HAL_MDIO_CTRL_START 0xE 331 #define XGE_HAL_MDIO_OP_ADDRESS 0x0 332 #define XGE_HAL_MDIO_OP_WRITE 0x1 333 #define XGE_HAL_MDIO_OP_READ 0x3 334 #define XGE_HAL_MDIO_OP_READ_POST_INCREMENT 0x2 335 #define XGE_HAL_MDIO_ALARM_TEMPHIGH 0x0080 336 #define XGE_HAL_MDIO_ALARM_TEMPLOW 0x0040 337 #define XGE_HAL_MDIO_ALARM_BIASHIGH 0x0008 338 #define XGE_HAL_MDIO_ALARM_BIASLOW 0x0004 339 #define XGE_HAL_MDIO_ALARM_POUTPUTHIGH 0x0002 340 #define XGE_HAL_MDIO_ALARM_POUTPUTLOW 0x0001 341 #define XGE_HAL_MDIO_WARN_TEMPHIGH 0x0080 342 #define XGE_HAL_MDIO_WARN_TEMPLOW 0x0040 343 #define XGE_HAL_MDIO_WARN_BIASHIGH 0x0008 344 #define XGE_HAL_MDIO_WARN_BIASLOW 0x0004 345 #define XGE_HAL_MDIO_WARN_POUTPUTHIGH 0x0002 346 #define XGE_HAL_MDIO_WARN_POUTPUTLOW 0x0001 347 348 u64 dtx_control; 349 350 u64 i2c_control; 351 #define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) 352 #define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) 353 #define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) 354 #define XGE_HAL_I2C_CONTROL_READ BIT(24) 355 #define XGE_HAL_I2C_CONTROL_NACK BIT(25) 356 #define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4) 357 #define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) 358 #define XGE_HAL_I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) 359 #define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) 360 361 u64 beacon_control; 362 u64 misc_control; 363 #define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3) 364 #define XGE_HAL_MISC_CONTROL_EXT_REQ_EN BIT(1) 365 #define XGE_HAL_MISC_CONTROL_LINK_FAULT BIT(0) 366 367 u64 xfb_control; 368 u64 gpio_control; 369 #define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8) 370 371 u64 txfifo_dw_mask; 372 u64 split_table_line_no; 373 u64 sc_timeout; 374 u64 pic_control_2; 375 #define XGE_HAL_TXD_WRITE_BC(n) vBIT(n, 13, 3) 376 u64 ini_dperr_ctrl; 377 u64 wreq_split_mask; 378 u64 qw_per_rxd; 379 u8 unused7[0x300 - 0x250]; 380 381 u64 pic_status; 382 u64 txp_status; 383 u64 txp_err_context; 384 u64 spdm_bir_offset; 385 #define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset) \ 386 (u8)(spdm_bir_offset >> 61) 387 #define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \ 388 (u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF) 389 u64 spdm_overwrite; 390 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite) \ 391 (u8)((spdm_overwrite >> 48) & 0xff) 392 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \ 393 (u8)((spdm_overwrite >> 40) & 0x3) 394 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite) \ 395 (u8)((spdm_overwrite >> 32) & 0x7) 396 u64 cfg_addr_on_dperr; 397 u64 pif_addr_on_dperr; 398 u64 tags_in_use; 399 u64 rd_req_types; 400 u64 split_table_line; 401 u64 unxp_split_add_ph; 402 u64 unexp_split_attr_ph; 403 u64 split_message; 404 u64 spdm_structure; 405 #define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure) (u16)(spdm_structure >> 48) 406 #define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure) \ 407 (u8)((spdm_structure >> 40) & 0xff) 408 #define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure) \ 409 (u8)((spdm_structure >> 32) & 0xff) 410 411 u64 txdw_ptr_cnt_0; 412 u64 txdw_ptr_cnt_1; 413 u64 txdw_ptr_cnt_2; 414 u64 txdw_ptr_cnt_3; 415 u64 txdw_ptr_cnt_4; 416 u64 txdw_ptr_cnt_5; 417 u64 txdw_ptr_cnt_6; 418 u64 txdw_ptr_cnt_7; 419 u64 rxdw_cnt_ring_0; 420 u64 rxdw_cnt_ring_1; 421 u64 rxdw_cnt_ring_2; 422 u64 rxdw_cnt_ring_3; 423 u64 rxdw_cnt_ring_4; 424 u64 rxdw_cnt_ring_5; 425 u64 rxdw_cnt_ring_6; 426 u64 rxdw_cnt_ring_7; 427 428 u8 unused8[0x410]; 429 430 /* TxDMA registers */ 431 u64 txdma_int_status; 432 u64 txdma_int_mask; 433 #define XGE_HAL_TXDMA_PFC_INT BIT(0) 434 #define XGE_HAL_TXDMA_TDA_INT BIT(1) 435 #define XGE_HAL_TXDMA_PCC_INT BIT(2) 436 #define XGE_HAL_TXDMA_TTI_INT BIT(3) 437 #define XGE_HAL_TXDMA_LSO_INT BIT(4) 438 #define XGE_HAL_TXDMA_TPA_INT BIT(5) 439 #define XGE_HAL_TXDMA_SM_INT BIT(6) 440 u64 pfc_err_reg; 441 #define XGE_HAL_PFC_ECC_SG_ERR BIT(7) 442 #define XGE_HAL_PFC_ECC_DB_ERR BIT(15) 443 #define XGE_HAL_PFC_SM_ERR_ALARM BIT(23) 444 #define XGE_HAL_PFC_MISC_0_ERR BIT(31) 445 #define XGE_HAL_PFC_MISC_1_ERR BIT(32) 446 #define XGE_HAL_PFC_PCIX_ERR BIT(39) 447 u64 pfc_err_mask; 448 u64 pfc_err_alarm; 449 450 u64 tda_err_reg; 451 #define XGE_HAL_TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8) 452 #define XGE_HAL_TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8) 453 #define XGE_HAL_TDA_SM0_ERR_ALARM BIT(22) 454 #define XGE_HAL_TDA_SM1_ERR_ALARM BIT(23) 455 #define XGE_HAL_TDA_PCIX_ERR BIT(39) 456 u64 tda_err_mask; 457 u64 tda_err_alarm; 458 459 u64 pcc_err_reg; 460 #define XGE_HAL_PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8) 461 #define XGE_HAL_PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8) 462 #define XGE_HAL_PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8) 463 #define XGE_HAL_PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8) 464 #define XGE_HAL_PCC_SM_ERR_ALARM vBIT(0xff,32,8) 465 #define XGE_HAL_PCC_WR_ERR_ALARM vBIT(0xff,40,8) 466 #define XGE_HAL_PCC_N_SERR vBIT(0xff,48,8) 467 #define XGE_HAL_PCC_ENABLE_FOUR vBIT(0x0F,0,8) 468 #define XGE_HAL_PCC_6_COF_OV_ERR BIT(56) 469 #define XGE_HAL_PCC_7_COF_OV_ERR BIT(57) 470 #define XGE_HAL_PCC_6_LSO_OV_ERR BIT(58) 471 #define XGE_HAL_PCC_7_LSO_OV_ERR BIT(59) 472 u64 pcc_err_mask; 473 u64 pcc_err_alarm; 474 475 u64 tti_err_reg; 476 #define XGE_HAL_TTI_ECC_SG_ERR BIT(7) 477 #define XGE_HAL_TTI_ECC_DB_ERR BIT(15) 478 #define XGE_HAL_TTI_SM_ERR_ALARM BIT(23) 479 u64 tti_err_mask; 480 u64 tti_err_alarm; 481 482 u64 lso_err_reg; 483 #define XGE_HAL_LSO6_SEND_OFLOW BIT(12) 484 #define XGE_HAL_LSO7_SEND_OFLOW BIT(13) 485 #define XGE_HAL_LSO6_ABORT BIT(14) 486 #define XGE_HAL_LSO7_ABORT BIT(15) 487 #define XGE_HAL_LSO6_SM_ERR_ALARM BIT(22) 488 #define XGE_HAL_LSO7_SM_ERR_ALARM BIT(23) 489 u64 lso_err_mask; 490 u64 lso_err_alarm; 491 492 u64 tpa_err_reg; 493 #define XGE_HAL_TPA_TX_FRM_DROP BIT(7) 494 #define XGE_HAL_TPA_SM_ERR_ALARM BIT(23) 495 u64 tpa_err_mask; 496 u64 tpa_err_alarm; 497 498 u64 sm_err_reg; 499 #define XGE_HAL_SM_SM_ERR_ALARM BIT(15) 500 u64 sm_err_mask; 501 u64 sm_err_alarm; 502 503 u8 unused9[0x100 - 0xB8]; 504 505 /* TxDMA arbiter */ 506 u64 tx_dma_wrap_stat; 507 508 /* Tx FIFO controller */ 509 #define XGE_HAL_X_MAX_FIFOS 8 510 #define XGE_HAL_X_FIFO_MAX_LEN 0x1FFF /*8191 */ 511 u64 tx_fifo_partition_0; 512 #define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0) 513 #define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) 514 #define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) 515 #define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) 516 #define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) 517 518 u64 tx_fifo_partition_1; 519 #define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) 520 #define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) 521 #define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) 522 #define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) 523 524 u64 tx_fifo_partition_2; 525 #define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) 526 #define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) 527 #define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) 528 #define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) 529 530 u64 tx_fifo_partition_3; 531 #define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) 532 #define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) 533 #define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) 534 #define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) 535 536 #define XGE_HAL_TX_FIFO_PARTITION_PRI_0 0 /* highest */ 537 #define XGE_HAL_TX_FIFO_PARTITION_PRI_1 1 538 #define XGE_HAL_TX_FIFO_PARTITION_PRI_2 2 539 #define XGE_HAL_TX_FIFO_PARTITION_PRI_3 3 540 #define XGE_HAL_TX_FIFO_PARTITION_PRI_4 4 541 #define XGE_HAL_TX_FIFO_PARTITION_PRI_5 5 542 #define XGE_HAL_TX_FIFO_PARTITION_PRI_6 6 543 #define XGE_HAL_TX_FIFO_PARTITION_PRI_7 7 /* lowest */ 544 545 u64 tx_w_round_robin_0; 546 u64 tx_w_round_robin_1; 547 u64 tx_w_round_robin_2; 548 u64 tx_w_round_robin_3; 549 u64 tx_w_round_robin_4; 550 551 u64 tti_command_mem; 552 #define XGE_HAL_TTI_CMD_MEM_WE BIT(7) 553 #define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 554 #define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15) 555 #define XGE_HAL_TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) 556 557 u64 tti_data1_mem; 558 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) 559 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) 560 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38) 561 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39) 562 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) 563 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) 564 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) 565 566 u64 tti_data2_mem; 567 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) 568 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) 569 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) 570 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) 571 572 /* Tx Protocol assist */ 573 u64 tx_pa_cfg; 574 #define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR BIT(1) 575 #define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 576 #define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 577 #define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6) 578 579 /* Recent add, used only debug purposes. */ 580 u64 pcc_enable; 581 582 u64 pfc_monitor_0; 583 u64 pfc_monitor_1; 584 u64 pfc_monitor_2; 585 u64 pfc_monitor_3; 586 u64 txd_ownership_ctrl; 587 u64 pfc_read_cntrl; 588 u64 pfc_read_data; 589 590 u8 unused10[0x1700 - 0x11B0]; 591 592 u64 txdma_debug_ctrl; 593 594 u8 unused11[0x1800 - 0x1708]; 595 596 /* RxDMA Registers */ 597 u64 rxdma_int_status; 598 #define XGE_HAL_RXDMA_RC_INT BIT(0) 599 #define XGE_HAL_RXDMA_RPA_INT BIT(1) 600 #define XGE_HAL_RXDMA_RDA_INT BIT(2) 601 #define XGE_HAL_RXDMA_RTI_INT BIT(3) 602 603 u64 rxdma_int_mask; 604 #define XGE_HAL_RXDMA_INT_RC_INT_M BIT(0) 605 #define XGE_HAL_RXDMA_INT_RPA_INT_M BIT(1) 606 #define XGE_HAL_RXDMA_INT_RDA_INT_M BIT(2) 607 #define XGE_HAL_RXDMA_INT_RTI_INT_M BIT(3) 608 609 u64 rda_err_reg; 610 #define XGE_HAL_RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8) 611 #define XGE_HAL_RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8) 612 #define XGE_HAL_RDA_FRM_ECC_SG_ERR BIT(23) 613 #define XGE_HAL_RDA_FRM_ECC_DB_N_AERR BIT(31) 614 #define XGE_HAL_RDA_SM1_ERR_ALARM BIT(38) 615 #define XGE_HAL_RDA_SM0_ERR_ALARM BIT(39) 616 #define XGE_HAL_RDA_MISC_ERR BIT(47) 617 #define XGE_HAL_RDA_PCIX_ERR BIT(55) 618 #define XGE_HAL_RDA_RXD_ECC_DB_SERR BIT(63) 619 u64 rda_err_mask; 620 u64 rda_err_alarm; 621 622 u64 rc_err_reg; 623 #define XGE_HAL_RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8) 624 #define XGE_HAL_RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8) 625 #define XGE_HAL_RC_FTC_ECC_SG_ERR BIT(23) 626 #define XGE_HAL_RC_FTC_ECC_DB_ERR BIT(31) 627 #define XGE_HAL_RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8) 628 #define XGE_HAL_RC_FTC_SM_ERR_ALARM BIT(47) 629 #define XGE_HAL_RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) 630 u64 rc_err_mask; 631 u64 rc_err_alarm; 632 633 u64 prc_pcix_err_reg; 634 #define XGE_HAL_PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8) 635 #define XGE_HAL_PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8) 636 #define XGE_HAL_PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8) 637 #define XGE_HAL_PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8) 638 #define XGE_HAL_PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8) 639 #define XGE_HAL_PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8) 640 u64 prc_pcix_err_mask; 641 u64 prc_pcix_err_alarm; 642 643 u64 rpa_err_reg; 644 #define XGE_HAL_RPA_ECC_SG_ERR BIT(7) 645 #define XGE_HAL_RPA_ECC_DB_ERR BIT(15) 646 #define XGE_HAL_RPA_FLUSH_REQUEST BIT(22) 647 #define XGE_HAL_RPA_SM_ERR_ALARM BIT(23) 648 #define XGE_HAL_RPA_CREDIT_ERR BIT(31) 649 u64 rpa_err_mask; 650 u64 rpa_err_alarm; 651 652 u64 rti_err_reg; 653 #define XGE_HAL_RTI_ECC_SG_ERR BIT(7) 654 #define XGE_HAL_RTI_ECC_DB_ERR BIT(15) 655 #define XGE_HAL_RTI_SM_ERR_ALARM BIT(23) 656 u64 rti_err_mask; 657 u64 rti_err_alarm; 658 659 u8 unused12[0x100 - 0x88]; 660 661 /* DMA arbiter */ 662 u64 rx_queue_priority; 663 #define XGE_HAL_RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) 664 #define XGE_HAL_RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) 665 #define XGE_HAL_RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) 666 #define XGE_HAL_RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) 667 #define XGE_HAL_RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) 668 #define XGE_HAL_RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) 669 #define XGE_HAL_RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) 670 #define XGE_HAL_RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) 671 672 #define XGE_HAL_RX_QUEUE_PRI_0 0 /* highest */ 673 #define XGE_HAL_RX_QUEUE_PRI_1 1 674 #define XGE_HAL_RX_QUEUE_PRI_2 2 675 #define XGE_HAL_RX_QUEUE_PRI_3 3 676 #define XGE_HAL_RX_QUEUE_PRI_4 4 677 #define XGE_HAL_RX_QUEUE_PRI_5 5 678 #define XGE_HAL_RX_QUEUE_PRI_6 6 679 #define XGE_HAL_RX_QUEUE_PRI_7 7 /* lowest */ 680 681 u64 rx_w_round_robin_0; 682 u64 rx_w_round_robin_1; 683 u64 rx_w_round_robin_2; 684 u64 rx_w_round_robin_3; 685 u64 rx_w_round_robin_4; 686 687 /* Per-ring controller regs */ 688 #define XGE_HAL_RX_MAX_RINGS 8 689 u64 prc_rxd0_n[XGE_HAL_RX_MAX_RINGS]; 690 u64 prc_ctrl_n[XGE_HAL_RX_MAX_RINGS]; 691 #define XGE_HAL_PRC_CTRL_RC_ENABLED BIT(7) 692 #define XGE_HAL_PRC_CTRL_RING_MODE (BIT(14)|BIT(15)) 693 #define XGE_HAL_PRC_CTRL_RING_MODE_1 vBIT(0,14,2) 694 #define XGE_HAL_PRC_CTRL_RING_MODE_3 vBIT(1,14,2) 695 #define XGE_HAL_PRC_CTRL_RING_MODE_5 vBIT(2,14,2) 696 #define XGE_HAL_PRC_CTRL_RING_MODE_x vBIT(3,14,2) 697 #define XGE_HAL_PRC_CTRL_NO_SNOOP(n) vBIT(n,22,2) 698 #define XGE_HAL_PRC_CTRL_RTH_DISABLE BIT(31) 699 #define XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT BIT(37) 700 #define XGE_HAL_PRC_CTRL_GROUP_READS BIT(38) 701 #define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) 702 703 u64 prc_alarm_action; 704 #define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP BIT(3) 705 #define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP BIT(7) 706 #define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP BIT(11) 707 #define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP BIT(15) 708 #define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP BIT(19) 709 #define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP BIT(23) 710 #define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP BIT(27) 711 #define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP BIT(31) 712 #define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP BIT(35) 713 #define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP BIT(39) 714 #define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP BIT(43) 715 #define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP BIT(47) 716 #define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP BIT(51) 717 #define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP BIT(55) 718 #define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP BIT(59) 719 #define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP BIT(63) 720 721 /* Receive traffic interrupts */ 722 u64 rti_command_mem; 723 #define XGE_HAL_RTI_CMD_MEM_WE BIT(7) 724 #define XGE_HAL_RTI_CMD_MEM_STROBE BIT(15) 725 #define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 726 #define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15) 727 #define XGE_HAL_RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) 728 729 u64 rti_data1_mem; 730 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) 731 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38) 732 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39) 733 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) 734 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) 735 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) 736 737 u64 rti_data2_mem; 738 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) 739 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) 740 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) 741 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) 742 743 u64 rx_pa_cfg; 744 #define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR BIT(1) 745 #define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 746 #define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 747 #define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n) vBIT(n,6,1) 748 #define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n) vBIT(n,15,1) 749 750 u8 unused13_0[0x8]; 751 752 u64 ring_bump_counter1; 753 u64 ring_bump_counter2; 754 #define XGE_HAL_RING_BUMP_CNT(i, val) (u16)(val >> (48 - (16 * (i % 4)))) 755 756 u8 unused13[0x700 - 0x1f0]; 757 758 u64 rxdma_debug_ctrl; 759 760 u8 unused14[0x2000 - 0x1f08]; 761 762 /* Media Access Controller Register */ 763 u64 mac_int_status; 764 u64 mac_int_mask; 765 #define XGE_HAL_MAC_INT_STATUS_TMAC_INT BIT(0) 766 #define XGE_HAL_MAC_INT_STATUS_RMAC_INT BIT(1) 767 768 u64 mac_tmac_err_reg; 769 #define XGE_HAL_TMAC_ECC_DB_ERR BIT(15) 770 #define XGE_HAL_TMAC_TX_BUF_OVRN BIT(23) 771 #define XGE_HAL_TMAC_TX_CRI_ERR BIT(31) 772 #define XGE_HAL_TMAC_TX_SM_ERR BIT(39) 773 u64 mac_tmac_err_mask; 774 u64 mac_tmac_err_alarm; 775 776 u64 mac_rmac_err_reg; 777 #define XGE_HAL_RMAC_RX_BUFF_OVRN BIT(0) 778 #define XGE_HAL_RMAC_RTH_SPDM_ECC_SG_ERR BIT(0) 779 #define XGE_HAL_RMAC_RTS_ECC_DB_ERR BIT(0) 780 #define XGE_HAL_RMAC_ECC_DB_ERR BIT(0) 781 #define XGE_HAL_RMAC_RTH_SPDM_ECC_DB_ERR BIT(0) 782 #define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT BIT(0) 783 #define XGE_HAL_RMAC_RX_SM_ERR BIT(39) 784 u64 mac_rmac_err_mask; 785 u64 mac_rmac_err_alarm; 786 787 u8 unused15[0x100 - 0x40]; 788 789 u64 mac_cfg; 790 #define XGE_HAL_MAC_CFG_TMAC_ENABLE BIT(0) 791 #define XGE_HAL_MAC_CFG_RMAC_ENABLE BIT(1) 792 #define XGE_HAL_MAC_CFG_LAN_NOT_WAN BIT(2) 793 #define XGE_HAL_MAC_CFG_TMAC_LOOPBACK BIT(3) 794 #define XGE_HAL_MAC_CFG_TMAC_APPEND_PAD BIT(4) 795 #define XGE_HAL_MAC_CFG_RMAC_STRIP_FCS BIT(5) 796 #define XGE_HAL_MAC_CFG_RMAC_STRIP_PAD BIT(6) 797 #define XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE BIT(7) 798 #define XGE_HAL_MAC_RMAC_DISCARD_PFRM BIT(8) 799 #define XGE_HAL_MAC_RMAC_BCAST_ENABLE BIT(9) 800 #define XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE BIT(10) 801 #define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) 802 803 u64 tmac_avg_ipg; 804 #define XGE_HAL_TMAC_AVG_IPG(val) vBIT(val,0,8) 805 806 u64 rmac_max_pyld_len; 807 #define XGE_HAL_RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) 808 809 u64 rmac_err_cfg; 810 #define XGE_HAL_RMAC_ERR_FCS BIT(0) 811 #define XGE_HAL_RMAC_ERR_FCS_ACCEPT BIT(1) 812 #define XGE_HAL_RMAC_ERR_TOO_LONG BIT(1) 813 #define XGE_HAL_RMAC_ERR_TOO_LONG_ACCEPT BIT(1) 814 #define XGE_HAL_RMAC_ERR_RUNT BIT(2) 815 #define XGE_HAL_RMAC_ERR_RUNT_ACCEPT BIT(2) 816 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH BIT(3) 817 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3) 818 819 u64 rmac_cfg_key; 820 #define XGE_HAL_RMAC_CFG_KEY(val) vBIT(val,0,16) 821 822 #define XGE_HAL_MAX_MAC_ADDRESSES 256 823 #define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET 255 824 #define XGE_HAL_MAX_MAC_ADDRESSES_HERC 256 825 #define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET_HERC 255 826 827 u64 rmac_addr_cmd_mem; 828 #define XGE_HAL_RMAC_ADDR_CMD_MEM_WE BIT(7) 829 #define XGE_HAL_RMAC_ADDR_CMD_MEM_RD 0 830 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15) 831 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15) 832 #define XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) 833 834 u64 rmac_addr_data0_mem; 835 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) 836 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_USER BIT(48) 837 838 u64 rmac_addr_data1_mem; 839 #define XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) 840 841 u8 unused16[0x8]; 842 843 /* 844 u64 rmac_addr_cfg; 845 #define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) 846 #define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) 847 #define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48 848 #define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 849 */ 850 u64 tmac_ipg_cfg; 851 852 u64 rmac_pause_cfg; 853 #define XGE_HAL_RMAC_PAUSE_GEN_EN BIT(0) 854 #define XGE_HAL_RMAC_PAUSE_RCV_EN BIT(1) 855 #define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) 856 #define XGE_HAL_RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) 857 858 u64 rmac_red_cfg; 859 860 u64 rmac_red_rate_q0q3; 861 u64 rmac_red_rate_q4q7; 862 863 u64 mac_link_util; 864 #define XGE_HAL_MAC_TX_LINK_UTIL vBIT(0xFE,1,7) 865 #define XGE_HAL_MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4) 866 #define XGE_HAL_MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) 867 #define XGE_HAL_MAC_RX_LINK_UTIL vBIT(0xFE,33,7) 868 #define XGE_HAL_MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4) 869 #define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) 870 871 #define XGE_HAL_MAC_LINK_UTIL_DISABLE (XGE_HAL_MAC_TX_LINK_UTIL_DISABLE | \ 872 XGE_HAL_MAC_RX_LINK_UTIL_DISABLE) 873 874 u64 rmac_invalid_ipg; 875 876 /* rx traffic steering */ 877 #define XGE_HAL_MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) 878 u64 rts_frm_len_n[8]; 879 880 u64 rts_qos_steering; 881 882 #define XGE_HAL_MAX_DIX_MAP 4 883 u64 rts_dix_map_n[XGE_HAL_MAX_DIX_MAP]; 884 #define XGE_HAL_RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) 885 #define XGE_HAL_RTS_DIX_MAP_SCW(val) BIT(val,21) 886 887 u64 rts_q_alternates; 888 u64 rts_default_q; 889 #define XGE_HAL_RTS_DEFAULT_Q(n) vBIT(n,5,3) 890 891 u64 rts_ctrl; 892 #define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI BIT(2) 893 #define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL BIT(3) 894 #define XGE_HAL_RTS_CTRL_ENHANCED_MODE BIT(7) 895 896 u64 rts_pn_cam_ctrl; 897 #define XGE_HAL_RTS_PN_CAM_CTRL_WE BIT(7) 898 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15) 899 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15) 900 #define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) 901 u64 rts_pn_cam_data; 902 #define XGE_HAL_RTS_PN_CAM_DATA_TCP_SELECT BIT(7) 903 #define XGE_HAL_RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) 904 #define XGE_HAL_RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) 905 906 u64 rts_ds_mem_ctrl; 907 #define XGE_HAL_RTS_DS_MEM_CTRL_WE BIT(7) 908 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15) 909 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15) 910 #define XGE_HAL_RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) 911 u64 rts_ds_mem_data; 912 #define XGE_HAL_RTS_DS_MEM_DATA(n) vBIT(n,0,8) 913 914 u8 unused16_1[0x308 - 0x220]; 915 916 u64 rts_vid_mem_ctrl; 917 u64 rts_vid_mem_data; 918 u64 rts_p0_p3_map; 919 u64 rts_p4_p7_map; 920 u64 rts_p8_p11_map; 921 u64 rts_p12_p15_map; 922 923 u64 rts_mac_cfg; 924 #define XGE_HAL_RTS_MAC_SECT0_EN BIT(0) 925 #define XGE_HAL_RTS_MAC_SECT1_EN BIT(1) 926 #define XGE_HAL_RTS_MAC_SECT2_EN BIT(2) 927 #define XGE_HAL_RTS_MAC_SECT3_EN BIT(3) 928 #define XGE_HAL_RTS_MAC_SECT4_EN BIT(4) 929 #define XGE_HAL_RTS_MAC_SECT5_EN BIT(5) 930 #define XGE_HAL_RTS_MAC_SECT6_EN BIT(6) 931 #define XGE_HAL_RTS_MAC_SECT7_EN BIT(7) 932 933 u8 unused16_2[0x380 - 0x340]; 934 935 u64 rts_rth_cfg; 936 #define XGE_HAL_RTS_RTH_EN BIT(3) 937 #define XGE_HAL_RTS_RTH_BUCKET_SIZE(n) vBIT(n,4,4) 938 #define XGE_HAL_RTS_RTH_ALG_SEL_MS BIT(11) 939 #define XGE_HAL_RTS_RTH_TCP_IPV4_EN BIT(15) 940 #define XGE_HAL_RTS_RTH_UDP_IPV4_EN BIT(19) 941 #define XGE_HAL_RTS_RTH_IPV4_EN BIT(23) 942 #define XGE_HAL_RTS_RTH_TCP_IPV6_EN BIT(27) 943 #define XGE_HAL_RTS_RTH_UDP_IPV6_EN BIT(31) 944 #define XGE_HAL_RTS_RTH_IPV6_EN BIT(35) 945 #define XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN BIT(39) 946 #define XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN BIT(43) 947 #define XGE_HAL_RTS_RTH_IPV6_EX_EN BIT(47) 948 949 u64 rts_rth_map_mem_ctrl; 950 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE BIT(7) 951 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE BIT(15) 952 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 953 954 u64 rts_rth_map_mem_data; 955 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN BIT(3) 956 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA(n) vBIT(n,5,3) 957 958 u64 rts_rth_spdm_mem_ctrl; 959 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE BIT(15) 960 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n) vBIT(n,21,3) 961 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 962 963 u64 rts_rth_spdm_mem_data; 964 965 u64 rts_rth_jhash_cfg; 966 #define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n) vBIT(n,0,32) 967 #define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n) vBIT(n,32,32) 968 969 u64 rts_rth_hash_mask[5]; /* rth mask's 0...4 */ 970 u64 rts_rth_hash_mask_5; 971 #define XGE_HAL_RTH_HASH_MASK_5(n) vBIT(n,0,32) 972 973 u64 rts_rth_status; 974 #define XGE_HAL_RTH_STATUS_SPDM_USE_L4 BIT(3) 975 976 u8 unused17[0x400 - 0x3E8]; 977 978 u64 rmac_red_fine_q0q3; 979 u64 rmac_red_fine_q4q7; 980 u64 rmac_pthresh_cross; 981 u64 rmac_rthresh_cross; 982 u64 rmac_pnum_range[32]; 983 984 u64 rmac_mp_crc_0; 985 u64 rmac_mp_mask_a_0; 986 u64 rmac_mp_mask_b_0; 987 988 u64 rmac_mp_crc_1; 989 u64 rmac_mp_mask_a_1; 990 u64 rmac_mp_mask_b_1; 991 992 u64 rmac_mp_crc_2; 993 u64 rmac_mp_mask_a_2; 994 u64 rmac_mp_mask_b_2; 995 996 u64 rmac_mp_crc_3; 997 u64 rmac_mp_mask_a_3; 998 u64 rmac_mp_mask_b_3; 999 1000 u64 rmac_mp_crc_4; 1001 u64 rmac_mp_mask_a_4; 1002 u64 rmac_mp_mask_b_4; 1003 1004 u64 rmac_mp_crc_5; 1005 u64 rmac_mp_mask_a_5; 1006 u64 rmac_mp_mask_b_5; 1007 1008 u64 rmac_mp_crc_6; 1009 u64 rmac_mp_mask_a_6; 1010 u64 rmac_mp_mask_b_6; 1011 1012 u64 rmac_mp_crc_7; 1013 u64 rmac_mp_mask_a_7; 1014 u64 rmac_mp_mask_b_7; 1015 1016 u64 mac_ctrl; 1017 u64 activity_control; 1018 1019 u8 unused17_2[0x700 - 0x5F0]; 1020 1021 u64 mac_debug_ctrl; 1022 #define XGE_HAL_MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL 1023 1024 u8 unused18[0x2800 - 0x2708]; 1025 1026 /* memory controller registers */ 1027 u64 mc_int_status; 1028 #define XGE_HAL_MC_INT_STATUS_MC_INT BIT(0) 1029 u64 mc_int_mask; 1030 #define XGE_HAL_MC_INT_MASK_MC_INT BIT(0) 1031 1032 u64 mc_err_reg; 1033 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L BIT(2) /* non-Xena */ 1034 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U BIT(3) /* non-Xena */ 1035 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L BIT(4) /* non-Xena */ 1036 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U BIT(5) /* non-Xena */ 1037 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L BIT(6) 1038 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U BIT(7) 1039 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L BIT(10) /* non-Xena */ 1040 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U BIT(11) /* non-Xena */ 1041 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L BIT(12) /* non-Xena */ 1042 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U BIT(13) /* non-Xena */ 1043 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L BIT(14) 1044 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U BIT(15) 1045 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 BIT(17) 1046 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) /* Xena: reset */ 1047 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 BIT(19) 1048 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) /* Xena: reset */ 1049 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22) 1050 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23) 1051 #define XGE_HAL_MC_ERR_REG_SM_ERR BIT(31) 1052 #define XGE_HAL_MC_ERR_REG_PL_LOCK_N BIT(39) 1053 1054 u64 mc_err_mask; 1055 u64 mc_err_alarm; 1056 1057 u8 unused19[0x100 - 0x28]; 1058 1059 /* MC configuration */ 1060 u64 rx_queue_cfg; 1061 #define XGE_HAL_RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) 1062 #define XGE_HAL_RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) 1063 #define XGE_HAL_RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) 1064 #define XGE_HAL_RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) 1065 #define XGE_HAL_RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) 1066 #define XGE_HAL_RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) 1067 #define XGE_HAL_RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) 1068 #define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) 1069 1070 u64 mc_rldram_mrs; 1071 #define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) 1072 #define XGE_HAL_MC_RLDRAM_MRS_ENABLE BIT(47) 1073 1074 u64 mc_rldram_interleave; 1075 1076 u64 mc_pause_thresh_q0q3; 1077 u64 mc_pause_thresh_q4q7; 1078 1079 u64 mc_red_thresh_q[8]; 1080 1081 u8 unused20[0x200 - 0x168]; 1082 u64 mc_rldram_ref_per; 1083 u8 unused21[0x220 - 0x208]; 1084 u64 mc_rldram_test_ctrl; 1085 #define XGE_HAL_MC_RLDRAM_TEST_MODE BIT(47) 1086 #define XGE_HAL_MC_RLDRAM_TEST_WRITE BIT(7) 1087 #define XGE_HAL_MC_RLDRAM_TEST_GO BIT(15) 1088 #define XGE_HAL_MC_RLDRAM_TEST_DONE BIT(23) 1089 #define XGE_HAL_MC_RLDRAM_TEST_PASS BIT(31) 1090 1091 u8 unused22[0x240 - 0x228]; 1092 u64 mc_rldram_test_add; 1093 u8 unused23[0x260 - 0x248]; 1094 u64 mc_rldram_test_d0; 1095 u8 unused24[0x280 - 0x268]; 1096 u64 mc_rldram_test_d1; 1097 u8 unused25[0x300 - 0x288]; 1098 u64 mc_rldram_test_d2; 1099 u8 unused26_1[0x2C00 - 0x2B08]; 1100 u64 mc_rldram_test_read_d0; 1101 u8 unused26_2[0x20 - 0x8]; 1102 u64 mc_rldram_test_read_d1; 1103 u8 unused26_3[0x40 - 0x28]; 1104 u64 mc_rldram_test_read_d2; 1105 u8 unused26_4[0x60 - 0x48]; 1106 u64 mc_rldram_test_add_bkg; 1107 u8 unused26_5[0x80 - 0x68]; 1108 u64 mc_rldram_test_d0_bkg; 1109 u8 unused26_6[0xD00 - 0xC88]; 1110 u64 mc_rldram_test_d1_bkg; 1111 u8 unused26_7[0x20 - 0x8]; 1112 u64 mc_rldram_test_d2_bkg; 1113 u8 unused26_8[0x40 - 0x28]; 1114 u64 mc_rldram_test_read_d0_bkg; 1115 u8 unused26_9[0x60 - 0x48]; 1116 u64 mc_rldram_test_read_d1_bkg; 1117 u8 unused26_10[0x80 - 0x68]; 1118 u64 mc_rldram_test_read_d2_bkg; 1119 u8 unused26_11[0xE00 - 0xD88]; 1120 u64 mc_rldram_generation; 1121 u8 unused26_12[0x20 - 0x8]; 1122 u64 mc_driver; 1123 u8 unused26_13[0x40 - 0x28]; 1124 u64 mc_rldram_ref_per_herc; 1125 #define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n) vBIT(n, 0, 16) 1126 u8 unused26_14[0x660 - 0x648]; 1127 u64 mc_rldram_mrs_herc; 1128 #define XGE_HAL_MC_RLDRAM_MRS(n) vBIT(n, 14, 17) 1129 u8 unused26_15[0x700 - 0x668]; 1130 u64 mc_debug_ctrl; 1131 1132 u8 unused27[0x3000 - 0x2f08]; 1133 1134 /* XGXG */ 1135 /* XGXS control registers */ 1136 1137 u64 xgxs_int_status; 1138 #define XGE_HAL_XGXS_INT_STATUS_TXGXS BIT(0) 1139 #define XGE_HAL_XGXS_INT_STATUS_RXGXS BIT(1) 1140 u64 xgxs_int_mask; 1141 #define XGE_HAL_XGXS_INT_MASK_TXGXS BIT(0) 1142 #define XGE_HAL_XGXS_INT_MASK_RXGXS BIT(1) 1143 1144 u64 xgxs_txgxs_err_reg; 1145 #define XGE_HAL_TXGXS_ECC_SG_ERR BIT(7) 1146 #define XGE_HAL_TXGXS_ECC_DB_ERR BIT(15) 1147 #define XGE_HAL_TXGXS_ESTORE_UFLOW BIT(31) 1148 #define XGE_HAL_TXGXS_TX_SM_ERR BIT(39) 1149 u64 xgxs_txgxs_err_mask; 1150 u64 xgxs_txgxs_err_alarm; 1151 1152 u64 xgxs_rxgxs_err_reg; 1153 #define XGE_HAL_RXGXS_ESTORE_OFLOW BIT(7) 1154 #define XGE_HAL_RXGXS_RX_SM_ERR BIT(39) 1155 u64 xgxs_rxgxs_err_mask; 1156 u64 xgxs_rxgxs_err_alarm; 1157 1158 u64 spi_err_reg; 1159 u64 spi_err_mask; 1160 u64 spi_err_alarm; 1161 1162 u8 unused28[0x100 - 0x58]; 1163 1164 u64 xgxs_cfg; 1165 u64 xgxs_status; 1166 1167 u64 xgxs_cfg_key; 1168 u64 xgxs_efifo_cfg; /* CHANGED */ 1169 u64 rxgxs_ber_0; /* CHANGED */ 1170 u64 rxgxs_ber_1; /* CHANGED */ 1171 1172 u64 spi_control; 1173 u64 spi_data; 1174 u64 spi_write_protect; 1175 1176 u8 unused29[0x80 - 0x48]; 1177 1178 u64 xgxs_cfg_1; 1179 } xge_hal_pci_bar0_t; 1180 1181 /* Using this strcture to calculate offsets */ 1182 typedef struct xge_hal_pci_config_le_t { 1183 u16 vendor_id; // 0x00 1184 u16 device_id; // 0x02 1185 1186 u16 command; // 0x04 1187 u16 status; // 0x06 1188 1189 u8 revision; // 0x08 1190 u8 pciClass[3]; // 0x09 1191 1192 u8 cache_line_size; // 0x0c 1193 u8 latency_timer; // 0x0d 1194 u8 header_type; // 0x0e 1195 u8 bist; // 0x0f 1196 1197 u32 base_addr0_lo; // 0x10 1198 u32 base_addr0_hi; // 0x14 1199 1200 u32 base_addr1_lo; // 0x18 1201 u32 base_addr1_hi; // 0x1C 1202 1203 u32 not_Implemented1; // 0x20 1204 u32 not_Implemented2; // 0x24 1205 1206 u32 cardbus_cis_pointer; // 0x28 1207 1208 u16 subsystem_vendor_id; // 0x2c 1209 u16 subsystem_id; // 0x2e 1210 1211 u32 rom_base; // 0x30 1212 u8 capabilities_pointer; // 0x34 1213 u8 rsvd_35[3]; // 0x35 1214 u32 rsvd_38; // 0x38 1215 1216 u8 interrupt_line; // 0x3c 1217 u8 interrupt_pin; // 0x3d 1218 u8 min_grant; // 0x3e 1219 u8 max_latency; // 0x3f 1220 1221 u8 msi_cap_id; // 0x40 1222 u8 msi_next_ptr; // 0x41 1223 u16 msi_control; // 0x42 1224 u32 msi_lower_address; // 0x44 1225 u32 msi_higher_address; // 0x48 1226 u16 msi_data; // 0x4c 1227 u16 msi_unused; // 0x4e 1228 1229 u8 vpd_cap_id; // 0x50 1230 u8 vpd_next_cap; // 0x51 1231 u16 vpd_addr; // 0x52 1232 u32 vpd_data; // 0x54 1233 1234 u8 rsvd_b0[8]; // 0x58 1235 1236 u8 pcix_cap; // 0x60 1237 u8 pcix_next_cap; // 0x61 1238 u16 pcix_command; // 0x62 1239 1240 u32 pcix_status; // 0x64 1241 1242 u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1243 } xge_hal_pci_config_le_t; // 0x100 1244 1245 typedef struct xge_hal_pci_config_t { 1246 #ifdef XGE_OS_HOST_BIG_ENDIAN 1247 u16 device_id; // 0x02 1248 u16 vendor_id; // 0x00 1249 1250 u16 status; // 0x06 1251 u16 command; // 0x04 1252 1253 u8 pciClass[3]; // 0x09 1254 u8 revision; // 0x08 1255 1256 u8 bist; // 0x0f 1257 u8 header_type; // 0x0e 1258 u8 latency_timer; // 0x0d 1259 u8 cache_line_size; // 0x0c 1260 1261 u32 base_addr0_lo; // 0x10 1262 u32 base_addr0_hi; // 0x14 1263 1264 u32 base_addr1_lo; // 0x18 1265 u32 base_addr1_hi; // 0x1C 1266 1267 u32 not_Implemented1; // 0x20 1268 u32 not_Implemented2; // 0x24 1269 1270 u32 cardbus_cis_pointer; // 0x28 1271 1272 u16 subsystem_id; // 0x2e 1273 u16 subsystem_vendor_id; // 0x2c 1274 1275 u32 rom_base; // 0x30 1276 u8 rsvd_35[3]; // 0x35 1277 u8 capabilities_pointer; // 0x34 1278 u32 rsvd_38; // 0x38 1279 1280 u8 max_latency; // 0x3f 1281 u8 min_grant; // 0x3e 1282 u8 interrupt_pin; // 0x3d 1283 u8 interrupt_line; // 0x3c 1284 1285 u16 msi_control; // 0x42 1286 u8 msi_next_ptr; // 0x41 1287 u8 msi_cap_id; // 0x40 1288 u32 msi_lower_address; // 0x44 1289 u32 msi_higher_address; // 0x48 1290 u16 msi_unused; // 0x4e 1291 u16 msi_data; // 0x4c 1292 1293 u16 vpd_addr; // 0x52 1294 u8 vpd_next_cap; // 0x51 1295 u8 vpd_cap_id; // 0x50 1296 u32 vpd_data; // 0x54 1297 1298 u8 rsvd_b0[8]; // 0x58 1299 1300 u16 pcix_command; // 0x62 1301 u8 pcix_next_cap; // 0x61 1302 u8 pcix_cap; // 0x60 1303 1304 u32 pcix_status; // 0x64 1305 #else 1306 u16 vendor_id; // 0x00 1307 u16 device_id; // 0x02 1308 1309 u16 command; // 0x04 1310 u16 status; // 0x06 1311 1312 u8 revision; // 0x08 1313 u8 pciClass[3]; // 0x09 1314 1315 u8 cache_line_size; // 0x0c 1316 u8 latency_timer; // 0x0d 1317 u8 header_type; // 0x0e 1318 u8 bist; // 0x0f 1319 1320 u32 base_addr0_lo; // 0x10 1321 u32 base_addr0_hi; // 0x14 1322 1323 u32 base_addr1_lo; // 0x18 1324 u32 base_addr1_hi; // 0x1C 1325 1326 u32 not_Implemented1; // 0x20 1327 u32 not_Implemented2; // 0x24 1328 1329 u32 cardbus_cis_pointer; // 0x28 1330 1331 u16 subsystem_vendor_id; // 0x2c 1332 u16 subsystem_id; // 0x2e 1333 1334 u32 rom_base; // 0x30 1335 u8 capabilities_pointer; // 0x34 1336 u8 rsvd_35[3]; // 0x35 1337 u32 rsvd_38; // 0x38 1338 1339 u8 interrupt_line; // 0x3c 1340 u8 interrupt_pin; // 0x3d 1341 u8 min_grant; // 0x3e 1342 u8 max_latency; // 0x3f 1343 1344 u8 msi_cap_id; // 0x40 1345 u8 msi_next_ptr; // 0x41 1346 u16 msi_control; // 0x42 1347 u32 msi_lower_address; // 0x44 1348 u32 msi_higher_address; // 0x48 1349 u16 msi_data; // 0x4c 1350 u16 msi_unused; // 0x4e 1351 1352 u8 vpd_cap_id; // 0x50 1353 u8 vpd_next_cap; // 0x51 1354 u16 vpd_addr; // 0x52 1355 u32 vpd_data; // 0x54 1356 1357 u8 rsvd_b0[8]; // 0x58 1358 1359 u8 pcix_cap; // 0x60 1360 u8 pcix_next_cap; // 0x61 1361 u16 pcix_command; // 0x62 1362 1363 u32 pcix_status; // 0x64 1364 1365 #endif 1366 u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1367 } xge_hal_pci_config_t; // 0x100 1368 1369 #define XGE_HAL_REG_SPACE sizeof(xge_hal_pci_bar0_t) 1370 #define XGE_HAL_EEPROM_SIZE (0x01 << 11) 1371 1372 __EXTERN_END_DECLS 1373 1374 #endif /* XGE_HAL_REGS_H */ 1375