1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2002-2005 Neterion, Inc. 24 * All right Reserved. 25 * 26 * FileName : xgehal-regs.h 27 * 28 * Description: Xframe mem-mapped register space 29 * 30 * Created: 14 May 2004 31 */ 32 33 #ifndef XGE_HAL_REGS_H 34 #define XGE_HAL_REGS_H 35 36 typedef struct { 37 38 /* General Control-Status Registers */ 39 u64 general_int_status; 40 #define XGE_HAL_GEN_INTR_TXPIC BIT(0) 41 #define XGE_HAL_GEN_INTR_TXDMA BIT(1) 42 #define XGE_HAL_GEN_INTR_TXMAC BIT(2) 43 #define XGE_HAL_GEN_INTR_TXXGXS BIT(3) 44 #define XGE_HAL_GEN_INTR_TXTRAFFIC BIT(8) 45 #define XGE_HAL_GEN_INTR_RXPIC BIT(32) 46 #define XGE_HAL_GEN_INTR_RXDMA BIT(33) 47 #define XGE_HAL_GEN_INTR_RXMAC BIT(34) 48 #define XGE_HAL_GEN_INTR_MC BIT(35) 49 #define XGE_HAL_GEN_INTR_RXXGXS BIT(36) 50 #define XGE_HAL_GEN_INTR_RXTRAFFIC BIT(40) 51 #define XGE_HAL_GEN_ERROR_INTR (XGE_HAL_GEN_INTR_TXPIC | \ 52 XGE_HAL_GEN_INTR_RXPIC | \ 53 XGE_HAL_GEN_INTR_TXDMA | \ 54 XGE_HAL_GEN_INTR_RXDMA | \ 55 XGE_HAL_GEN_INTR_TXMAC | \ 56 XGE_HAL_GEN_INTR_RXMAC | \ 57 XGE_HAL_GEN_INTR_TXXGXS | \ 58 XGE_HAL_GEN_INTR_RXXGXS | \ 59 XGE_HAL_GEN_INTR_MC) 60 61 u64 general_int_mask; 62 63 u8 unused0[0x100 - 0x10]; 64 65 u64 sw_reset; 66 67 /* XGXS must be removed from reset only once. */ 68 #define XGE_HAL_SW_RESET_XENA vBIT(0xA5,0,8) 69 #define XGE_HAL_SW_RESET_FLASH vBIT(0xA5,8,8) 70 #define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8) 71 #define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8) 72 #define XGE_HAL_SW_RESET_ALL (XGE_HAL_SW_RESET_XENA | \ 73 XGE_HAL_SW_RESET_FLASH | \ 74 XGE_HAL_SW_RESET_EOI | \ 75 XGE_HAL_SW_RESET_XGXS) 76 77 /* The SW_RESET register must read this value after a successful reset. */ 78 #if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN) 79 #define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA500000000ULL 80 #define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A500000000ULL 81 #else 82 #define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA5000000ULL 83 #define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A50000ULL 84 #endif 85 86 87 u64 adapter_status; 88 #define XGE_HAL_ADAPTER_STATUS_TDMA_READY BIT(0) 89 #define XGE_HAL_ADAPTER_STATUS_RDMA_READY BIT(1) 90 #define XGE_HAL_ADAPTER_STATUS_PFC_READY BIT(2) 91 #define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3) 92 #define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT BIT(5) 93 #define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6) 94 #define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7) 95 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) 96 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8) 97 #define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR vBIT(0x0F,0,8) 98 99 #define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) 100 #define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY BIT(24) 101 #define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY BIT(25) 102 #define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK BIT(30) 103 #define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK BIT(31) 104 105 u64 adapter_control; 106 #define XGE_HAL_ADAPTER_CNTL_EN BIT(7) 107 #define XGE_HAL_ADAPTER_EOI_TX_ON BIT(15) 108 #define XGE_HAL_ADAPTER_LED_ON BIT(23) 109 #define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4) 110 #define XGE_HAL_ADAPTER_WAIT_INT BIT(48) 111 #define XGE_HAL_ADAPTER_ECC_EN BIT(55) 112 113 u64 serr_source; 114 #define XGE_HAL_SERR_SOURCE_PIC BIT(0) 115 #define XGE_HAL_SERR_SOURCE_TXDMA BIT(1) 116 #define XGE_HAL_SERR_SOURCE_RXDMA BIT(2) 117 #define XGE_HAL_SERR_SOURCE_MAC BIT(3) 118 #define XGE_HAL_SERR_SOURCE_MC BIT(4) 119 #define XGE_HAL_SERR_SOURCE_XGXS BIT(5) 120 #define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \ 121 XGE_HAL_SERR_SOURCE_TXDMA | \ 122 XGE_HAL_SERR_SOURCE_RXDMA | \ 123 XGE_HAL_SERR_SOURCE_MAC | \ 124 XGE_HAL_SERR_SOURCE_MC | \ 125 XGE_HAL_SERR_SOURCE_XGXS) 126 127 u64 pci_info; 128 #define XGE_HAL_PCI_INFO vBIT(0xF,0,4) 129 #define XGE_HAL_PCI_32_BIT BIT(8) 130 u8 unused_0[0x800 - 0x128]; 131 132 /* PCI-X Controller registers */ 133 u64 pic_int_status; 134 u64 pic_int_mask; 135 #define XGE_HAL_PIC_INT_TX BIT(0) 136 #define XGE_HAL_PIC_INT_FLSH BIT(1) 137 #define XGE_HAL_PIC_INT_MDIO BIT(2) 138 #define XGE_HAL_PIC_INT_IIC BIT(3) 139 #define XGE_HAL_PIC_INT_MISC BIT(4) 140 #define XGE_HAL_PIC_INT_RX BIT(32) 141 142 u64 txpic_int_reg; 143 #define XGE_HAL_TXPIC_INT_SCHED_INTR BIT(42) 144 u64 txpic_int_mask; 145 #define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR BIT(0) 146 #define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR BIT(1) 147 #define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8) 148 #define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9) 149 #define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR BIT(10) 150 #define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11) 151 #define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR BIT(13) 152 #define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR BIT(14) 153 #define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR BIT(15) 154 #define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21) 155 #define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23) 156 #define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR BIT(48) 157 #define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR BIT(50) 158 /* 159 #define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52) 160 #define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54) 161 #define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58) 162 */ 163 u64 txpic_alarms; 164 u64 rxpic_int_reg; 165 #define XGE_HAL_RX_PIC_INT_REG_SPDM_READY BIT(0) 166 #define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR BIT(44) 167 #define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR BIT(55) 168 u64 rxpic_int_mask; 169 u64 rxpic_alarms; 170 171 u64 flsh_int_reg; 172 u64 flsh_int_mask; 173 #define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63) 174 #define XGE_HAL_PIC_FLSH_INT_REG_ERR BIT(62) 175 u64 flash_alarms; 176 177 u64 mdio_int_reg; 178 u64 mdio_int_mask; 179 #define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR BIT(0) 180 #define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR BIT(8) 181 #define XGE_HAL_MDIO_INT_REG_LASI BIT(39) 182 u64 mdio_alarms; 183 184 u64 iic_int_reg; 185 u64 iic_int_mask; 186 #define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR BIT(4) 187 #define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR BIT(5) 188 #define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR BIT(6) 189 #define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR BIT(7) 190 #define XGE_HAL_IIC_INT_REG_ACK_ERR BIT(8) 191 u64 iic_alarms; 192 193 u8 unused4[0x08]; 194 195 u64 misc_int_reg; 196 #define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0) 197 #define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1) 198 #define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2) 199 u64 misc_int_mask; 200 u64 misc_alarms; 201 202 u8 unused5[0x38]; 203 204 u64 tx_traffic_int; 205 #define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n) 206 u64 tx_traffic_mask; 207 208 u64 rx_traffic_int; 209 #define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n) 210 u64 rx_traffic_mask; 211 212 /* PIC Control registers */ 213 u64 pic_control; 214 #define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1 BIT(0) 215 #define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT BIT(1) 216 #define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4) 217 218 u64 swapper_ctrl; 219 #define XGE_HAL_SWAPPER_CTRL_PIF_R_FE BIT(0) 220 #define XGE_HAL_SWAPPER_CTRL_PIF_R_SE BIT(1) 221 #define XGE_HAL_SWAPPER_CTRL_PIF_W_FE BIT(8) 222 #define XGE_HAL_SWAPPER_CTRL_PIF_W_SE BIT(9) 223 #define XGE_HAL_SWAPPER_CTRL_RTH_FE BIT(10) 224 #define XGE_HAL_SWAPPER_CTRL_RTH_SE BIT(11) 225 #define XGE_HAL_SWAPPER_CTRL_TXP_FE BIT(16) 226 #define XGE_HAL_SWAPPER_CTRL_TXP_SE BIT(17) 227 #define XGE_HAL_SWAPPER_CTRL_TXD_R_FE BIT(18) 228 #define XGE_HAL_SWAPPER_CTRL_TXD_R_SE BIT(19) 229 #define XGE_HAL_SWAPPER_CTRL_TXD_W_FE BIT(20) 230 #define XGE_HAL_SWAPPER_CTRL_TXD_W_SE BIT(21) 231 #define XGE_HAL_SWAPPER_CTRL_TXF_R_FE BIT(22) 232 #define XGE_HAL_SWAPPER_CTRL_TXF_R_SE BIT(23) 233 #define XGE_HAL_SWAPPER_CTRL_RXD_R_FE BIT(32) 234 #define XGE_HAL_SWAPPER_CTRL_RXD_R_SE BIT(33) 235 #define XGE_HAL_SWAPPER_CTRL_RXD_W_FE BIT(34) 236 #define XGE_HAL_SWAPPER_CTRL_RXD_W_SE BIT(35) 237 #define XGE_HAL_SWAPPER_CTRL_RXF_W_FE BIT(36) 238 #define XGE_HAL_SWAPPER_CTRL_RXF_W_SE BIT(37) 239 #define XGE_HAL_SWAPPER_CTRL_XMSI_FE BIT(40) 240 #define XGE_HAL_SWAPPER_CTRL_XMSI_SE BIT(41) 241 #define XGE_HAL_SWAPPER_CTRL_STATS_FE BIT(48) 242 #define XGE_HAL_SWAPPER_CTRL_STATS_SE BIT(49) 243 244 u64 pif_rd_swapper_fb; 245 #define XGE_HAL_IF_RD_SWAPPER_FB 0x0123456789ABCDEFULL 246 247 u64 scheduled_int_ctrl; 248 #define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0) 249 #define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT BIT(1) 250 #define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) 251 #define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32) 252 #define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL 253 254 255 u64 txreqtimeout; 256 #define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32) 257 #define XGE_HAL_TXREQTO_EN BIT(63) 258 259 u64 statsreqtimeout; 260 #define XGE_HAL_STATREQTO_VAL(n) TBD 261 #define XGE_HAL_STATREQTO_EN BIT(63) 262 263 u64 read_retry_delay; 264 u64 read_retry_acceleration; 265 u64 write_retry_delay; 266 u64 write_retry_acceleration; 267 268 u64 xmsi_control; 269 #define XGE_HAL_XMSI_EN BIT(0) 270 #define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1) 271 #define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,2) 272 273 u64 xmsi_access; 274 #define XGE_HAL_XMSI_WR_RDN BIT(7) 275 #define XGE_HAL_XMSI_STROBE BIT(15) 276 #define XGE_HAL_XMSI_NO(val) vBIT(val,26,6) 277 278 u64 xmsi_address; 279 u64 xmsi_data; 280 281 u64 rx_mat; 282 #define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8) 283 284 u8 unused6[0x8]; 285 286 u64 tx_mat[8]; 287 #define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8) 288 289 u64 xmsi_mask_reg; 290 291 /* Automated statistics collection */ 292 u64 stat_byte_cnt; 293 u64 stat_cfg; 294 #define XGE_HAL_STAT_CFG_STAT_EN BIT(0) 295 #define XGE_HAL_STAT_CFG_ONE_SHOT_EN BIT(1) 296 #define XGE_HAL_STAT_CFG_STAT_NS_EN BIT(8) 297 #define XGE_HAL_STAT_CFG_STAT_RO BIT(9) 298 #define XGE_HAL_XENA_PER_SEC 0x208d5 299 #define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32) 300 301 u64 stat_addr; 302 303 /* General Configuration */ 304 u64 mdio_control; 305 306 u64 dtx_control; 307 308 u64 i2c_control; 309 #define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) 310 #define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) 311 #define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) 312 #define XGE_HAL_I2C_CONTROL_READ BIT(24) 313 #define XGE_HAL_I2C_CONTROL_NACK BIT(25) 314 #define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4) 315 #define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) 316 #define XGE_HAL_I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) 317 #define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) 318 319 u64 beacon_control; 320 u64 misc_control; 321 #define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3) 322 #define XGE_HAL_MISC_CONTROL_EXT_REQ_EN BIT(1) 323 324 u64 xfb_control; 325 u64 gpio_control; 326 #define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8) 327 328 u64 txfifo_dw_mask; 329 u64 split_table_line_no; 330 u64 sc_timeout; 331 u64 pic_control_2; 332 u64 ini_dperr_ctrl; 333 u64 wreq_split_mask; 334 u64 qw_per_rxd; 335 u8 unused7[0x300 - 0x250]; 336 337 u64 pic_status; 338 u64 txp_status; 339 u64 txp_err_context; 340 u64 spdm_bir_offset; 341 #define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset) \ 342 (u8)(spdm_bir_offset >> 61) 343 #define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \ 344 (u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF) 345 u64 spdm_overwrite; 346 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite) \ 347 (u8)((spdm_overwrite >> 48) & 0xff) 348 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \ 349 (u8)((spdm_overwrite >> 40) & 0x3) 350 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite) \ 351 (u8)((spdm_overwrite >> 32) & 0x7) 352 u64 cfg_addr_on_dperr; 353 u64 pif_addr_on_dperr; 354 u64 tags_in_use; 355 u64 rd_req_types; 356 u64 split_table_line; 357 u64 unxp_split_add_ph; 358 u64 unexp_split_attr_ph; 359 u64 split_message; 360 u64 spdm_structure; 361 #define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure) (u16)(spdm_structure >> 48) 362 #define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure) \ 363 (u8)((spdm_structure >> 40) & 0xff) 364 #define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure) \ 365 (u8)((spdm_structure >> 32) & 0xff) 366 367 u64 txdw_ptr_cnt_0; 368 u64 txdw_ptr_cnt_1; 369 u64 txdw_ptr_cnt_2; 370 u64 txdw_ptr_cnt_3; 371 u64 txdw_ptr_cnt_4; 372 u64 txdw_ptr_cnt_5; 373 u64 txdw_ptr_cnt_6; 374 u64 txdw_ptr_cnt_7; 375 u64 rxdw_cnt_ring_0; 376 u64 rxdw_cnt_ring_1; 377 u64 rxdw_cnt_ring_2; 378 u64 rxdw_cnt_ring_3; 379 u64 rxdw_cnt_ring_4; 380 u64 rxdw_cnt_ring_5; 381 u64 rxdw_cnt_ring_6; 382 u64 rxdw_cnt_ring_7; 383 384 u8 unused8[0x410]; 385 386 /* TxDMA registers */ 387 u64 txdma_int_status; 388 u64 txdma_int_mask; 389 #define XGE_HAL_TXDMA_PFC_INT BIT(0) 390 #define XGE_HAL_TXDMA_TDA_INT BIT(1) 391 #define XGE_HAL_TXDMA_PCC_INT BIT(2) 392 #define XGE_HAL_TXDMA_TTI_INT BIT(3) 393 #define XGE_HAL_TXDMA_LSO_INT BIT(4) 394 #define XGE_HAL_TXDMA_TPA_INT BIT(5) 395 #define XGE_HAL_TXDMA_SM_INT BIT(6) 396 u64 pfc_err_reg; 397 u64 pfc_err_mask; 398 u64 pfc_err_alarm; 399 400 u64 tda_err_reg; 401 u64 tda_err_mask; 402 u64 tda_err_alarm; 403 404 u64 pcc_err_reg; 405 u64 pcc_err_mask; 406 u64 pcc_err_alarm; 407 408 u64 tti_err_reg; 409 u64 tti_err_mask; 410 u64 tti_err_alarm; 411 412 u64 lso_err_reg; 413 u64 lso_err_mask; 414 u64 lso_err_alarm; 415 416 u64 tpa_err_reg; 417 u64 tpa_err_mask; 418 u64 tpa_err_alarm; 419 420 u64 sm_err_reg; 421 u64 sm_err_mask; 422 u64 sm_err_alarm; 423 424 u8 unused9[0x100 - 0xB8]; 425 426 /* TxDMA arbiter */ 427 u64 tx_dma_wrap_stat; 428 429 /* Tx FIFO controller */ 430 #define XGE_HAL_X_MAX_FIFOS 8 431 #define XGE_HAL_X_FIFO_MAX_LEN 0x1FFF /*8191 */ 432 u64 tx_fifo_partition_0; 433 #define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0) 434 #define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) 435 #define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) 436 #define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) 437 #define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) 438 439 u64 tx_fifo_partition_1; 440 #define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) 441 #define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) 442 #define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) 443 #define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) 444 445 u64 tx_fifo_partition_2; 446 #define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) 447 #define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) 448 #define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) 449 #define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) 450 451 u64 tx_fifo_partition_3; 452 #define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) 453 #define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) 454 #define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) 455 #define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) 456 457 #define XGE_HAL_TX_FIFO_PARTITION_PRI_0 0 /* highest */ 458 #define XGE_HAL_TX_FIFO_PARTITION_PRI_1 1 459 #define XGE_HAL_TX_FIFO_PARTITION_PRI_2 2 460 #define XGE_HAL_TX_FIFO_PARTITION_PRI_3 3 461 #define XGE_HAL_TX_FIFO_PARTITION_PRI_4 4 462 #define XGE_HAL_TX_FIFO_PARTITION_PRI_5 5 463 #define XGE_HAL_TX_FIFO_PARTITION_PRI_6 6 464 #define XGE_HAL_TX_FIFO_PARTITION_PRI_7 7 /* lowest */ 465 466 u64 tx_w_round_robin_0; 467 u64 tx_w_round_robin_1; 468 u64 tx_w_round_robin_2; 469 u64 tx_w_round_robin_3; 470 u64 tx_w_round_robin_4; 471 472 u64 tti_command_mem; 473 #define XGE_HAL_TTI_CMD_MEM_WE BIT(7) 474 #define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 475 #define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15) 476 #define XGE_HAL_TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) 477 478 u64 tti_data1_mem; 479 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) 480 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) 481 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38) 482 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39) 483 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) 484 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) 485 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) 486 487 u64 tti_data2_mem; 488 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) 489 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) 490 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) 491 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) 492 493 /* Tx Protocol assist */ 494 u64 tx_pa_cfg; 495 #define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR BIT(1) 496 #define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 497 #define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 498 #define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6) 499 500 /* Recent add, used only debug purposes. */ 501 u64 pcc_enable; 502 503 u8 unused10[0x700 - 0x178]; 504 505 u64 txdma_debug_ctrl; 506 507 u8 unused11[0x1800 - 0x1708]; 508 509 /* RxDMA Registers */ 510 u64 rxdma_int_status; 511 #define XGE_HAL_RXDMA_RC_INT BIT(0) 512 #define XGE_HAL_RXDMA_RPA_INT BIT(1) 513 #define XGE_HAL_RXDMA_RDA_INT BIT(2) 514 #define XGE_HAL_RXDMA_RTI_INT BIT(3) 515 516 u64 rxdma_int_mask; 517 #define XGE_HAL_RXDMA_INT_RC_INT_M BIT(0) 518 #define XGE_HAL_RXDMA_INT_RPA_INT_M BIT(1) 519 #define XGE_HAL_RXDMA_INT_RDA_INT_M BIT(2) 520 #define XGE_HAL_RXDMA_INT_RTI_INT_M BIT(3) 521 522 u64 rda_err_reg; 523 u64 rda_err_mask; 524 u64 rda_err_alarm; 525 526 u64 rc_err_reg; 527 u64 rc_err_mask; 528 u64 rc_err_alarm; 529 530 u64 prc_pcix_err_reg; 531 u64 prc_pcix_err_mask; 532 u64 prc_pcix_err_alarm; 533 534 u64 rpa_err_reg; 535 u64 rpa_err_mask; 536 u64 rpa_err_alarm; 537 538 u64 rti_err_reg; 539 u64 rti_err_mask; 540 u64 rti_err_alarm; 541 542 u8 unused12[0x100 - 0x88]; 543 544 /* DMA arbiter */ 545 u64 rx_queue_priority; 546 #define XGE_HAL_RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) 547 #define XGE_HAL_RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) 548 #define XGE_HAL_RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) 549 #define XGE_HAL_RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) 550 #define XGE_HAL_RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) 551 #define XGE_HAL_RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) 552 #define XGE_HAL_RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) 553 #define XGE_HAL_RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) 554 555 #define XGE_HAL_RX_QUEUE_PRI_0 0 /* highest */ 556 #define XGE_HAL_RX_QUEUE_PRI_1 1 557 #define XGE_HAL_RX_QUEUE_PRI_2 2 558 #define XGE_HAL_RX_QUEUE_PRI_3 3 559 #define XGE_HAL_RX_QUEUE_PRI_4 4 560 #define XGE_HAL_RX_QUEUE_PRI_5 5 561 #define XGE_HAL_RX_QUEUE_PRI_6 6 562 #define XGE_HAL_RX_QUEUE_PRI_7 7 /* lowest */ 563 564 u64 rx_w_round_robin_0; 565 u64 rx_w_round_robin_1; 566 u64 rx_w_round_robin_2; 567 u64 rx_w_round_robin_3; 568 u64 rx_w_round_robin_4; 569 570 /* Per-ring controller regs */ 571 #define XGE_HAL_RX_MAX_RINGS 8 572 u64 prc_rxd0_n[XGE_HAL_RX_MAX_RINGS]; 573 u64 prc_ctrl_n[XGE_HAL_RX_MAX_RINGS]; 574 #define XGE_HAL_PRC_CTRL_RC_ENABLED BIT(7) 575 #define XGE_HAL_PRC_CTRL_RING_MODE (BIT(14)|BIT(15)) 576 #define XGE_HAL_PRC_CTRL_RING_MODE_1 vBIT(0,14,2) 577 #define XGE_HAL_PRC_CTRL_RING_MODE_3 vBIT(1,14,2) 578 #define XGE_HAL_PRC_CTRL_RING_MODE_5 vBIT(2,14,2) 579 #define XGE_HAL_PRC_CTRL_RING_MODE_x vBIT(3,14,2) 580 #define XGE_HAL_PRC_CTRL_NO_SNOOP(n) vBIT(n,22,2) 581 #define XGE_HAL_PRC_CTRL_RTH_DISABLE BIT(31) 582 #define XGE_HAL_PRC_CTRL_GROUP_READS BIT(38) 583 #define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) 584 585 u64 prc_alarm_action; 586 #define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP BIT(3) 587 #define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP BIT(7) 588 #define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP BIT(11) 589 #define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP BIT(15) 590 #define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP BIT(19) 591 #define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP BIT(23) 592 #define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP BIT(27) 593 #define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP BIT(31) 594 #define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP BIT(35) 595 #define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP BIT(39) 596 #define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP BIT(43) 597 #define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP BIT(47) 598 #define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP BIT(51) 599 #define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP BIT(55) 600 #define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP BIT(59) 601 #define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP BIT(63) 602 603 /* Receive traffic interrupts */ 604 u64 rti_command_mem; 605 #define XGE_HAL_RTI_CMD_MEM_WE BIT(7) 606 #define XGE_HAL_RTI_CMD_MEM_STROBE BIT(15) 607 #define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 608 #define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15) 609 #define XGE_HAL_RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) 610 611 u64 rti_data1_mem; 612 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) 613 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38) 614 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39) 615 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) 616 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) 617 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) 618 619 u64 rti_data2_mem; 620 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) 621 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) 622 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) 623 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) 624 625 u64 rx_pa_cfg; 626 #define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR BIT(1) 627 #define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 628 #define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 629 #define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n) vBIT(n,6,1) 630 #define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n) vBIT(n,15,1) 631 632 u8 unused13_0[0x8]; 633 634 u64 ring_bump_counter1; 635 u64 ring_bump_counter2; 636 #define XGE_HAL_RING_BUMP_CNT(i, val) (u16)(val >> (48 - (16 * (i % 4)))) 637 638 u8 unused13[0x700 - 0x1f0]; 639 640 u64 rxdma_debug_ctrl; 641 642 u8 unused14[0x2000 - 0x1f08]; 643 644 /* Media Access Controller Register */ 645 u64 mac_int_status; 646 u64 mac_int_mask; 647 #define XGE_HAL_MAC_INT_STATUS_TMAC_INT BIT(0) 648 #define XGE_HAL_MAC_INT_STATUS_RMAC_INT BIT(1) 649 650 u64 mac_tmac_err_reg; 651 #define XGE_HAL_TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15) 652 #define XGE_HAL_TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23) 653 #define XGE_HAL_TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31) 654 u64 mac_tmac_err_mask; 655 u64 mac_tmac_err_alarm; 656 657 u64 mac_rmac_err_reg; 658 #define XGE_HAL_RMAC_ERR_REG_RX_BUFF_OVRN BIT(0) 659 #define XGE_HAL_RMAC_ERR_REG_RTH_SPDM_ECC_SG_ERR BIT(9) 660 #define XGE_HAL_RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14) 661 #define XGE_HAL_RMAC_ERR_REG_ECC_DB_ERR BIT(15) 662 #define XGE_HAL_RMAC_ERR_REG_RTH_SPDM_ECC_DB_ERR BIT(17) 663 #define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT BIT(31) 664 u64 mac_rmac_err_mask; 665 u64 mac_rmac_err_alarm; 666 667 u8 unused15[0x100 - 0x40]; 668 669 u64 mac_cfg; 670 #define XGE_HAL_MAC_CFG_TMAC_ENABLE BIT(0) 671 #define XGE_HAL_MAC_CFG_RMAC_ENABLE BIT(1) 672 #define XGE_HAL_MAC_CFG_LAN_NOT_WAN BIT(2) 673 #define XGE_HAL_MAC_CFG_TMAC_LOOPBACK BIT(3) 674 #define XGE_HAL_MAC_CFG_TMAC_APPEND_PAD BIT(4) 675 #define XGE_HAL_MAC_CFG_RMAC_STRIP_FCS BIT(5) 676 #define XGE_HAL_MAC_CFG_RMAC_STRIP_PAD BIT(6) 677 #define XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE BIT(7) 678 #define XGE_HAL_MAC_RMAC_DISCARD_PFRM BIT(8) 679 #define XGE_HAL_MAC_RMAC_BCAST_ENABLE BIT(9) 680 #define XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE BIT(10) 681 #define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) 682 683 u64 tmac_avg_ipg; 684 #define XGE_HAL_TMAC_AVG_IPG(val) vBIT(val,0,8) 685 686 u64 rmac_max_pyld_len; 687 #define XGE_HAL_RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) 688 689 u64 rmac_err_cfg; 690 #define XGE_HAL_RMAC_ERR_FCS BIT(0) 691 #define XGE_HAL_RMAC_ERR_FCS_ACCEPT BIT(1) 692 #define XGE_HAL_RMAC_ERR_TOO_LONG BIT(1) 693 #define XGE_HAL_RMAC_ERR_TOO_LONG_ACCEPT BIT(1) 694 #define XGE_HAL_RMAC_ERR_RUNT BIT(2) 695 #define XGE_HAL_RMAC_ERR_RUNT_ACCEPT BIT(2) 696 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH BIT(3) 697 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3) 698 699 u64 rmac_cfg_key; 700 #define XGE_HAL_RMAC_CFG_KEY(val) vBIT(val,0,16) 701 702 #define XGE_HAL_MAX_MAC_ADDRESSES 64 703 #define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast 704 pkts */ 705 u64 rmac_addr_cmd_mem; 706 #define XGE_HAL_RMAC_ADDR_CMD_MEM_WE BIT(7) 707 #define XGE_HAL_RMAC_ADDR_CMD_MEM_RD 0 708 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15) 709 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15) 710 #define XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) 711 712 u64 rmac_addr_data0_mem; 713 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) 714 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_USER BIT(48) 715 716 u64 rmac_addr_data1_mem; 717 #define XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) 718 719 u8 unused16[0x8]; 720 721 /* 722 u64 rmac_addr_cfg; 723 #define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) 724 #define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) 725 #define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48 726 #define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 727 */ 728 u64 tmac_ipg_cfg; 729 730 u64 rmac_pause_cfg; 731 #define XGE_HAL_RMAC_PAUSE_GEN_EN BIT(0) 732 #define XGE_HAL_RMAC_PAUSE_RCV_EN BIT(1) 733 #define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) 734 #define XGE_HAL_RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) 735 736 u64 rmac_red_cfg; 737 738 u64 rmac_red_rate_q0q3; 739 u64 rmac_red_rate_q4q7; 740 741 u64 mac_link_util; 742 #define XGE_HAL_MAC_TX_LINK_UTIL vBIT(0xFE,1,7) 743 #define XGE_HAL_MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4) 744 #define XGE_HAL_MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) 745 #define XGE_HAL_MAC_RX_LINK_UTIL vBIT(0xFE,33,7) 746 #define XGE_HAL_MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4) 747 #define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) 748 749 #define XGE_HAL_MAC_LINK_UTIL_DISABLE (XGE_HAL_MAC_TX_LINK_UTIL_DISABLE | \ 750 XGE_HAL_MAC_RX_LINK_UTIL_DISABLE) 751 752 u64 rmac_invalid_ipg; 753 754 /* rx traffic steering */ 755 #define XGE_HAL_MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) 756 u64 rts_frm_len_n[8]; 757 758 u64 rts_qos_steering; 759 760 #define XGE_HAL_MAX_DIX_MAP 4 761 u64 rts_dix_map_n[XGE_HAL_MAX_DIX_MAP]; 762 #define XGE_HAL_RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) 763 #define XGE_HAL_RTS_DIX_MAP_SCW(val) BIT(val,21) 764 765 u64 rts_q_alternates; 766 u64 rts_default_q; 767 #define XGE_HAL_RTS_DEFAULT_Q(n) vBIT(n,5,3) 768 769 u64 rts_ctrl; 770 #define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI BIT(2) 771 #define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL BIT(3) 772 #define XGE_HAL_RTS_CTRL_ENHANCED_MODE BIT(7) 773 774 u64 rts_pn_cam_ctrl; 775 #define XGE_HAL_RTS_PN_CAM_CTRL_WE BIT(7) 776 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15) 777 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15) 778 #define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) 779 u64 rts_pn_cam_data; 780 #define XGE_HAL_RTS_PN_CAM_DATA_TCP_SELECT BIT(7) 781 #define XGE_HAL_RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) 782 #define XGE_HAL_RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) 783 784 u64 rts_ds_mem_ctrl; 785 #define XGE_HAL_RTS_DS_MEM_CTRL_WE BIT(7) 786 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15) 787 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15) 788 #define XGE_HAL_RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) 789 u64 rts_ds_mem_data; 790 #define XGE_HAL_RTS_DS_MEM_DATA(n) vBIT(n,0,8) 791 792 u8 unused16_0[0x338 - 0x220]; 793 794 u64 rts_mac_cfg; 795 #define XGE_HAL_RTS_MAC_SECT0_EN BIT(0) 796 #define XGE_HAL_RTS_MAC_SECT1_EN BIT(1) 797 #define XGE_HAL_RTS_MAC_SECT2_EN BIT(2) 798 #define XGE_HAL_RTS_MAC_SECT3_EN BIT(3) 799 #define XGE_HAL_RTS_MAC_SECT4_EN BIT(4) 800 #define XGE_HAL_RTS_MAC_SECT5_EN BIT(5) 801 #define XGE_HAL_RTS_MAC_SECT6_EN BIT(6) 802 #define XGE_HAL_RTS_MAC_SECT7_EN BIT(7) 803 804 u8 unused16_1[0x380 - 0x340]; 805 806 u64 rts_rth_cfg; 807 #define XGE_HAL_RTS_RTH_EN BIT(3) 808 #define XGE_HAL_RTS_RTH_BUCKET_SIZE(n) vBIT(n,4,4) 809 #define XGE_HAL_RTS_RTH_ALG_SEL_MS BIT(11) 810 #define XGE_HAL_RTS_RTH_TCP_IPV4_EN BIT(15) 811 #define XGE_HAL_RTS_RTH_UDP_IPV4_EN BIT(19) 812 #define XGE_HAL_RTS_RTH_IPV4_EN BIT(23) 813 #define XGE_HAL_RTS_RTH_TCP_IPV6_EN BIT(27) 814 #define XGE_HAL_RTS_RTH_UDP_IPV6_EN BIT(31) 815 #define XGE_HAL_RTS_RTH_IPV6_EN BIT(35) 816 #define XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN BIT(39) 817 #define XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN BIT(43) 818 #define XGE_HAL_RTS_RTH_IPV6_EX_EN BIT(47) 819 820 u64 rts_rth_map_mem_ctrl; 821 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE BIT(7) 822 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE BIT(15) 823 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 824 825 u64 rts_rth_map_mem_data; 826 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN BIT(3) 827 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA(n) vBIT(n,5,3) 828 829 u64 rts_rth_spdm_mem_ctrl; 830 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE BIT(15) 831 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n) vBIT(n,21,3) 832 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 833 834 u64 rts_rth_spdm_mem_data; 835 836 u64 rts_rth_jhash_cfg; 837 #define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n) vBIT(n,0,32) 838 #define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n) vBIT(n,32,32) 839 840 u64 rts_rth_hash_mask[5]; /* rth mask's 0...4 */ 841 u64 rts_rth_hash_mask_5; 842 #define XGE_HAL_RTH_HASH_MASK_5(n) vBIT(n,0,32) 843 844 u64 rts_rth_status; 845 #define XGE_HAL_RTH_STATUS_SPDM_USE_L4 BIT(3) 846 847 u8 unused17[0x700 - 0x3e8]; 848 849 u64 mac_debug_ctrl; 850 #define XGE_HAL_MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL 851 852 u8 unused18[0x2800 - 0x2708]; 853 854 /* memory controller registers */ 855 u64 mc_int_status; 856 #define XGE_HAL_MC_INT_STATUS_MC_INT BIT(0) 857 u64 mc_int_mask; 858 #define XGE_HAL_MC_INT_MASK_MC_INT BIT(0) 859 860 u64 mc_err_reg; 861 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L BIT(2) /* non-Xena */ 862 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U BIT(3) /* non-Xena */ 863 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L BIT(4) /* non-Xena */ 864 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U BIT(5) /* non-Xena */ 865 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L BIT(6) 866 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U BIT(7) 867 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L BIT(10) /* non-Xena */ 868 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U BIT(11) /* non-Xena */ 869 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L BIT(12) /* non-Xena */ 870 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U BIT(13) /* non-Xena */ 871 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L BIT(14) 872 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U BIT(15) 873 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 BIT(17) 874 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) /* Xena: reset */ 875 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 BIT(19) 876 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) /* Xena: reset */ 877 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22) 878 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23) 879 #define XGE_HAL_MC_ERR_REG_SM_ERR BIT(31) 880 #define XGE_HAL_MC_ERR_REG_PL_LOCK_N BIT(39) 881 882 u64 mc_err_mask; 883 u64 mc_err_alarm; 884 885 u8 unused19[0x100 - 0x28]; 886 887 /* MC configuration */ 888 u64 rx_queue_cfg; 889 #define XGE_HAL_RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) 890 #define XGE_HAL_RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) 891 #define XGE_HAL_RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) 892 #define XGE_HAL_RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) 893 #define XGE_HAL_RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) 894 #define XGE_HAL_RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) 895 #define XGE_HAL_RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) 896 #define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) 897 898 u64 mc_rldram_mrs; 899 #define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) 900 #define XGE_HAL_MC_RLDRAM_MRS_ENABLE BIT(47) 901 902 u64 mc_rldram_interleave; 903 904 u64 mc_pause_thresh_q0q3; 905 u64 mc_pause_thresh_q4q7; 906 907 u64 mc_red_thresh_q[8]; 908 909 u8 unused20[0x200 - 0x168]; 910 u64 mc_rldram_ref_per; 911 u8 unused21[0x220 - 0x208]; 912 u64 mc_rldram_test_ctrl; 913 #define XGE_HAL_MC_RLDRAM_TEST_MODE BIT(47) 914 #define XGE_HAL_MC_RLDRAM_TEST_WRITE BIT(7) 915 #define XGE_HAL_MC_RLDRAM_TEST_GO BIT(15) 916 #define XGE_HAL_MC_RLDRAM_TEST_DONE BIT(23) 917 #define XGE_HAL_MC_RLDRAM_TEST_PASS BIT(31) 918 919 u8 unused22[0x240 - 0x228]; 920 u64 mc_rldram_test_add; 921 u8 unused23[0x260 - 0x248]; 922 u64 mc_rldram_test_d0; 923 u8 unused24[0x280 - 0x268]; 924 u64 mc_rldram_test_d1; 925 u8 unused25[0x300 - 0x288]; 926 u64 mc_rldram_test_d2; 927 u8 unused26_1[0x640 - 0x308]; 928 u64 mc_rldram_ref_per_herc; 929 #define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n) vBIT(n, 0, 16) 930 u8 unused26_2[0x660 - 0x648]; 931 u64 mc_rldram_mrs_herc; 932 #define XGE_HAL_MC_RLDRAM_MRS(n) vBIT(n, 14, 17) 933 u8 unused26_3[0x700 - 0x668]; 934 u64 mc_debug_ctrl; 935 936 u8 unused27[0x3000 - 0x2f08]; 937 938 /* XGXG */ 939 /* XGXS control registers */ 940 941 u64 xgxs_int_status; 942 #define XGE_HAL_XGXS_INT_STATUS_TXGXS BIT(0) 943 #define XGE_HAL_XGXS_INT_STATUS_RXGXS BIT(1) 944 u64 xgxs_int_mask; 945 #define XGE_HAL_XGXS_INT_MASK_TXGXS BIT(0) 946 #define XGE_HAL_XGXS_INT_MASK_RXGXS BIT(1) 947 948 u64 xgxs_txgxs_err_reg; 949 #define XGE_HAL_TXGXS_ECC_DB_ERR BIT(15) 950 u64 xgxs_txgxs_err_mask; 951 u64 xgxs_txgxs_err_alarm; 952 953 u64 xgxs_rxgxs_err_reg; 954 u64 xgxs_rxgxs_err_mask; 955 u64 xgxs_rxgxs_err_alarm; 956 957 u8 unused28[0x100 - 0x40]; 958 959 u64 xgxs_cfg; 960 u64 xgxs_status; 961 962 u64 xgxs_cfg_key; 963 u64 xgxs_efifo_cfg; /* CHANGED */ 964 u64 rxgxs_ber_0; /* CHANGED */ 965 u64 rxgxs_ber_1; /* CHANGED */ 966 } xge_hal_pci_bar0_t; 967 968 /* Using this strcture to calculate offsets */ 969 typedef struct xge_hal_pci_config_le_t { 970 u16 vendor_id; // 0x00 971 u16 device_id; // 0x02 972 973 u16 command; // 0x04 974 u16 status; // 0x06 975 976 u8 revision; // 0x08 977 u8 pciClass[3]; // 0x09 978 979 u8 cache_line_size; // 0x0c 980 u8 latency_timer; // 0x0d 981 u8 header_type; // 0x0e 982 u8 bist; // 0x0f 983 984 u32 base_addr0_lo; // 0x10 985 u32 base_addr0_hi; // 0x14 986 987 u32 base_addr1_lo; // 0x18 988 u32 base_addr1_hi; // 0x1C 989 990 u32 not_Implemented1; // 0x20 991 u32 not_Implemented2; // 0x24 992 993 u32 cardbus_cis_pointer; // 0x28 994 995 u16 subsystem_vendor_id; // 0x2c 996 u16 subsystem_id; // 0x2e 997 998 u32 rom_base; // 0x30 999 u8 capabilities_pointer; // 0x34 1000 u8 rsvd_35[3]; // 0x35 1001 u32 rsvd_38; // 0x38 1002 1003 u8 interrupt_line; // 0x3c 1004 u8 interrupt_pin; // 0x3d 1005 u8 min_grant; // 0x3e 1006 u8 max_latency; // 0x3f 1007 1008 u8 msi_cap_id; // 0x40 1009 u8 msi_next_ptr; // 0x41 1010 u16 msi_control; // 0x42 1011 u32 msi_lower_address; // 0x44 1012 u32 msi_higher_address; // 0x48 1013 u16 msi_data; // 0x4c 1014 u16 msi_unused; // 0x4e 1015 1016 u8 vpd_cap_id; // 0x50 1017 u8 vpd_next_cap; // 0x51 1018 u16 vpd_addr; // 0x52 1019 u32 vpd_data; // 0x54 1020 1021 u8 rsvd_b0[8]; // 0x58 1022 1023 u8 pcix_cap; // 0x60 1024 u8 pcix_next_cap; // 0x61 1025 u16 pcix_command; // 0x62 1026 1027 u32 pcix_status; // 0x64 1028 1029 u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1030 } xge_hal_pci_config_le_t; // 0x100 1031 1032 typedef struct xge_hal_pci_config_t { 1033 #ifdef XGE_OS_HOST_BIG_ENDIAN 1034 u16 device_id; // 0x02 1035 u16 vendor_id; // 0x00 1036 1037 u16 status; // 0x06 1038 u16 command; // 0x04 1039 1040 u8 pciClass[3]; // 0x09 1041 u8 revision; // 0x08 1042 1043 u8 bist; // 0x0f 1044 u8 header_type; // 0x0e 1045 u8 latency_timer; // 0x0d 1046 u8 cache_line_size; // 0x0c 1047 1048 u32 base_addr0_lo; // 0x10 1049 u32 base_addr0_hi; // 0x14 1050 1051 u32 base_addr1_lo; // 0x18 1052 u32 base_addr1_hi; // 0x1C 1053 1054 u32 not_Implemented1; // 0x20 1055 u32 not_Implemented2; // 0x24 1056 1057 u32 cardbus_cis_pointer; // 0x28 1058 1059 u16 subsystem_id; // 0x2e 1060 u16 subsystem_vendor_id; // 0x2c 1061 1062 u32 rom_base; // 0x30 1063 u8 rsvd_35[3]; // 0x35 1064 u8 capabilities_pointer; // 0x34 1065 u32 rsvd_38; // 0x38 1066 1067 u8 max_latency; // 0x3f 1068 u8 min_grant; // 0x3e 1069 u8 interrupt_pin; // 0x3d 1070 u8 interrupt_line; // 0x3c 1071 1072 u16 msi_control; // 0x42 1073 u8 msi_next_ptr; // 0x41 1074 u8 msi_cap_id; // 0x40 1075 u32 msi_lower_address; // 0x44 1076 u32 msi_higher_address; // 0x48 1077 u16 msi_unused; // 0x4e 1078 u16 msi_data; // 0x4c 1079 1080 u16 vpd_addr; // 0x52 1081 u8 vpd_next_cap; // 0x51 1082 u8 vpd_cap_id; // 0x50 1083 u32 vpd_data; // 0x54 1084 1085 u8 rsvd_b0[8]; // 0x58 1086 1087 u16 pcix_command; // 0x62 1088 u8 pcix_next_cap; // 0x61 1089 u8 pcix_cap; // 0x60 1090 1091 u32 pcix_status; // 0x64 1092 #else 1093 u16 vendor_id; // 0x00 1094 u16 device_id; // 0x02 1095 1096 u16 command; // 0x04 1097 u16 status; // 0x06 1098 1099 u8 revision; // 0x08 1100 u8 pciClass[3]; // 0x09 1101 1102 u8 cache_line_size; // 0x0c 1103 u8 latency_timer; // 0x0d 1104 u8 header_type; // 0x0e 1105 u8 bist; // 0x0f 1106 1107 u32 base_addr0_lo; // 0x10 1108 u32 base_addr0_hi; // 0x14 1109 1110 u32 base_addr1_lo; // 0x18 1111 u32 base_addr1_hi; // 0x1C 1112 1113 u32 not_Implemented1; // 0x20 1114 u32 not_Implemented2; // 0x24 1115 1116 u32 cardbus_cis_pointer; // 0x28 1117 1118 u16 subsystem_vendor_id; // 0x2c 1119 u16 subsystem_id; // 0x2e 1120 1121 u32 rom_base; // 0x30 1122 u8 capabilities_pointer; // 0x34 1123 u8 rsvd_35[3]; // 0x35 1124 u32 rsvd_38; // 0x38 1125 1126 u8 interrupt_line; // 0x3c 1127 u8 interrupt_pin; // 0x3d 1128 u8 min_grant; // 0x3e 1129 u8 max_latency; // 0x3f 1130 1131 u8 msi_cap_id; // 0x40 1132 u8 msi_next_ptr; // 0x41 1133 u16 msi_control; // 0x42 1134 u32 msi_lower_address; // 0x44 1135 u32 msi_higher_address; // 0x48 1136 u16 msi_data; // 0x4c 1137 u16 msi_unused; // 0x4e 1138 1139 u8 vpd_cap_id; // 0x50 1140 u8 vpd_next_cap; // 0x51 1141 u16 vpd_addr; // 0x52 1142 u32 vpd_data; // 0x54 1143 1144 u8 rsvd_b0[8]; // 0x58 1145 1146 u8 pcix_cap; // 0x60 1147 u8 pcix_next_cap; // 0x61 1148 u16 pcix_command; // 0x62 1149 1150 u32 pcix_status; // 0x64 1151 1152 #endif 1153 u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1154 } xge_hal_pci_config_t; // 0x100 1155 1156 #define XGE_HAL_REG_SPACE sizeof(xge_hal_pci_bar0_t) 1157 #define XGE_HAL_EEPROM_SIZE (0x01 << 11) 1158 1159 #endif /* XGE_HAL_REGS_H */ 1160