1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #ifndef XGE_HAL_REGS_H 25 #define XGE_HAL_REGS_H 26 27 __EXTERN_BEGIN_DECLS 28 29 typedef struct { 30 31 /* General Control-Status Registers */ 32 u64 general_int_status; 33 #define XGE_HAL_GEN_INTR_TXPIC BIT(0) 34 #define XGE_HAL_GEN_INTR_TXDMA BIT(1) 35 #define XGE_HAL_GEN_INTR_TXMAC BIT(2) 36 #define XGE_HAL_GEN_INTR_TXXGXS BIT(3) 37 #define XGE_HAL_GEN_INTR_TXTRAFFIC BIT(8) 38 #define XGE_HAL_GEN_INTR_RXPIC BIT(32) 39 #define XGE_HAL_GEN_INTR_RXDMA BIT(33) 40 #define XGE_HAL_GEN_INTR_RXMAC BIT(34) 41 #define XGE_HAL_GEN_INTR_MC BIT(35) 42 #define XGE_HAL_GEN_INTR_RXXGXS BIT(36) 43 #define XGE_HAL_GEN_INTR_RXTRAFFIC BIT(40) 44 #define XGE_HAL_GEN_ERROR_INTR (XGE_HAL_GEN_INTR_TXPIC | \ 45 XGE_HAL_GEN_INTR_RXPIC | \ 46 XGE_HAL_GEN_INTR_TXDMA | \ 47 XGE_HAL_GEN_INTR_RXDMA | \ 48 XGE_HAL_GEN_INTR_TXMAC | \ 49 XGE_HAL_GEN_INTR_RXMAC | \ 50 XGE_HAL_GEN_INTR_TXXGXS | \ 51 XGE_HAL_GEN_INTR_RXXGXS | \ 52 XGE_HAL_GEN_INTR_MC) 53 54 u64 general_int_mask; 55 56 u8 unused0[0x100 - 0x10]; 57 58 u64 sw_reset; 59 60 /* XGXS must be removed from reset only once. */ 61 #define XGE_HAL_SW_RESET_XENA vBIT(0xA5,0,8) 62 #define XGE_HAL_SW_RESET_FLASH vBIT(0xA5,8,8) 63 #define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8) 64 #define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8) 65 #define XGE_HAL_SW_RESET_ALL (XGE_HAL_SW_RESET_XENA | \ 66 XGE_HAL_SW_RESET_FLASH | \ 67 XGE_HAL_SW_RESET_EOI | \ 68 XGE_HAL_SW_RESET_XGXS) 69 70 /* The SW_RESET register must read this value after a successful reset. */ 71 #if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN) 72 #define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA500000000ULL 73 #define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A500000000ULL 74 #else 75 #define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA5000000ULL 76 #define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A50000ULL 77 #endif 78 79 80 u64 adapter_status; 81 #define XGE_HAL_ADAPTER_STATUS_TDMA_READY BIT(0) 82 #define XGE_HAL_ADAPTER_STATUS_RDMA_READY BIT(1) 83 #define XGE_HAL_ADAPTER_STATUS_PFC_READY BIT(2) 84 #define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3) 85 #define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT BIT(5) 86 #define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6) 87 #define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7) 88 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) 89 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8) 90 #define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR vBIT(0x0F,0,8) 91 92 #define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) 93 #define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY BIT(24) 94 #define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY BIT(25) 95 #define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK BIT(30) 96 #define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK BIT(31) 97 98 u64 adapter_control; 99 #define XGE_HAL_ADAPTER_CNTL_EN BIT(7) 100 #define XGE_HAL_ADAPTER_EOI_TX_ON BIT(15) 101 #define XGE_HAL_ADAPTER_LED_ON BIT(23) 102 #define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4) 103 #define XGE_HAL_ADAPTER_WAIT_INT BIT(48) 104 #define XGE_HAL_ADAPTER_ECC_EN BIT(55) 105 106 u64 serr_source; 107 #define XGE_HAL_SERR_SOURCE_PIC BIT(0) 108 #define XGE_HAL_SERR_SOURCE_TXDMA BIT(1) 109 #define XGE_HAL_SERR_SOURCE_RXDMA BIT(2) 110 #define XGE_HAL_SERR_SOURCE_MAC BIT(3) 111 #define XGE_HAL_SERR_SOURCE_MC BIT(4) 112 #define XGE_HAL_SERR_SOURCE_XGXS BIT(5) 113 #define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \ 114 XGE_HAL_SERR_SOURCE_TXDMA | \ 115 XGE_HAL_SERR_SOURCE_RXDMA | \ 116 XGE_HAL_SERR_SOURCE_MAC | \ 117 XGE_HAL_SERR_SOURCE_MC | \ 118 XGE_HAL_SERR_SOURCE_XGXS) 119 120 u64 pci_info; 121 #define XGE_HAL_PCI_INFO vBIT(0xF,0,4) 122 #define XGE_HAL_PCI_32_BIT BIT(8) 123 124 u8 unused0_1[0x160 - 0x128]; 125 126 u64 ric_status; 127 128 u8 unused0_2[0x558 - 0x168]; 129 130 u64 mbist_status; 131 132 u8 unused0_3[0x800 - 0x560]; 133 134 /* PCI-X Controller registers */ 135 u64 pic_int_status; 136 u64 pic_int_mask; 137 #define XGE_HAL_PIC_INT_TX BIT(0) 138 #define XGE_HAL_PIC_INT_FLSH BIT(1) 139 #define XGE_HAL_PIC_INT_MDIO BIT(2) 140 #define XGE_HAL_PIC_INT_IIC BIT(3) 141 #define XGE_HAL_PIC_INT_MISC BIT(4) 142 #define XGE_HAL_PIC_INT_RX BIT(32) 143 144 u64 txpic_int_reg; 145 #define XGE_HAL_TXPIC_INT_SCHED_INTR BIT(42) 146 u64 txpic_int_mask; 147 #define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR BIT(0) 148 #define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR BIT(1) 149 #define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8) 150 #define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9) 151 #define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR BIT(10) 152 #define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11) 153 #define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR BIT(13) 154 #define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR BIT(14) 155 #define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR BIT(15) 156 #define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21) 157 #define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23) 158 #define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR BIT(48) 159 #define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR BIT(50) 160 /* 161 #define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52) 162 #define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54) 163 #define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58) 164 */ 165 u64 txpic_alarms; 166 u64 rxpic_int_reg; 167 #define XGE_HAL_RX_PIC_INT_REG_SPDM_READY BIT(0) 168 #define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR BIT(44) 169 #define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR BIT(55) 170 u64 rxpic_int_mask; 171 u64 rxpic_alarms; 172 173 u64 flsh_int_reg; 174 u64 flsh_int_mask; 175 #define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63) 176 #define XGE_HAL_PIC_FLSH_INT_REG_ERR BIT(62) 177 u64 flash_alarms; 178 179 u64 mdio_int_reg; 180 u64 mdio_int_mask; 181 #define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR BIT(0) 182 #define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR BIT(8) 183 #define XGE_HAL_MDIO_INT_REG_LASI BIT(39) 184 u64 mdio_alarms; 185 186 u64 iic_int_reg; 187 u64 iic_int_mask; 188 #define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR BIT(4) 189 #define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR BIT(5) 190 #define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR BIT(6) 191 #define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR BIT(7) 192 #define XGE_HAL_IIC_INT_REG_ACK_ERR BIT(8) 193 u64 iic_alarms; 194 195 u64 msi_pending_reg; 196 197 u64 misc_int_reg; 198 #define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0) 199 #define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1) 200 #define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2) 201 u64 misc_int_mask; 202 u64 misc_alarms; 203 204 u64 msi_triggered_reg; 205 206 u64 xfp_gpio_int_reg; 207 u64 xfp_gpio_int_mask; 208 u64 xfp_alarms; 209 210 u8 unused5[0x8E0 - 0x8C8]; 211 212 u64 tx_traffic_int; 213 #define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n) 214 u64 tx_traffic_mask; 215 216 u64 rx_traffic_int; 217 #define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n) 218 u64 rx_traffic_mask; 219 220 /* PIC Control registers */ 221 u64 pic_control; 222 #define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1 BIT(0) 223 #define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT BIT(1) 224 #define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4) 225 226 u64 swapper_ctrl; 227 #define XGE_HAL_SWAPPER_CTRL_PIF_R_FE BIT(0) 228 #define XGE_HAL_SWAPPER_CTRL_PIF_R_SE BIT(1) 229 #define XGE_HAL_SWAPPER_CTRL_PIF_W_FE BIT(8) 230 #define XGE_HAL_SWAPPER_CTRL_PIF_W_SE BIT(9) 231 #define XGE_HAL_SWAPPER_CTRL_RTH_FE BIT(10) 232 #define XGE_HAL_SWAPPER_CTRL_RTH_SE BIT(11) 233 #define XGE_HAL_SWAPPER_CTRL_TXP_FE BIT(16) 234 #define XGE_HAL_SWAPPER_CTRL_TXP_SE BIT(17) 235 #define XGE_HAL_SWAPPER_CTRL_TXD_R_FE BIT(18) 236 #define XGE_HAL_SWAPPER_CTRL_TXD_R_SE BIT(19) 237 #define XGE_HAL_SWAPPER_CTRL_TXD_W_FE BIT(20) 238 #define XGE_HAL_SWAPPER_CTRL_TXD_W_SE BIT(21) 239 #define XGE_HAL_SWAPPER_CTRL_TXF_R_FE BIT(22) 240 #define XGE_HAL_SWAPPER_CTRL_TXF_R_SE BIT(23) 241 #define XGE_HAL_SWAPPER_CTRL_RXD_R_FE BIT(32) 242 #define XGE_HAL_SWAPPER_CTRL_RXD_R_SE BIT(33) 243 #define XGE_HAL_SWAPPER_CTRL_RXD_W_FE BIT(34) 244 #define XGE_HAL_SWAPPER_CTRL_RXD_W_SE BIT(35) 245 #define XGE_HAL_SWAPPER_CTRL_RXF_W_FE BIT(36) 246 #define XGE_HAL_SWAPPER_CTRL_RXF_W_SE BIT(37) 247 #define XGE_HAL_SWAPPER_CTRL_XMSI_FE BIT(40) 248 #define XGE_HAL_SWAPPER_CTRL_XMSI_SE BIT(41) 249 #define XGE_HAL_SWAPPER_CTRL_STATS_FE BIT(48) 250 #define XGE_HAL_SWAPPER_CTRL_STATS_SE BIT(49) 251 252 u64 pif_rd_swapper_fb; 253 #define XGE_HAL_IF_RD_SWAPPER_FB 0x0123456789ABCDEFULL 254 255 u64 scheduled_int_ctrl; 256 #define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0) 257 #define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT BIT(1) 258 #define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) 259 #define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32) 260 #define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL 261 262 263 u64 txreqtimeout; 264 #define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32) 265 #define XGE_HAL_TXREQTO_EN BIT(63) 266 267 u64 statsreqtimeout; 268 #define XGE_HAL_STATREQTO_VAL(n) TBD 269 #define XGE_HAL_STATREQTO_EN BIT(63) 270 271 u64 read_retry_delay; 272 u64 read_retry_acceleration; 273 u64 write_retry_delay; 274 u64 write_retry_acceleration; 275 276 u64 xmsi_control; 277 #define XGE_HAL_XMSI_EN BIT(0) 278 #define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1) 279 #define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3) 280 281 u64 xmsi_access; 282 #define XGE_HAL_XMSI_WR_RDN BIT(7) 283 #define XGE_HAL_XMSI_STROBE BIT(15) 284 #define XGE_HAL_XMSI_NO(val) vBIT(val,26,6) 285 286 u64 xmsi_address; 287 u64 xmsi_data; 288 289 u64 rx_mat; 290 #define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8) 291 292 u8 unused6[0x8]; 293 294 u64 tx_mat[8]; 295 #define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8) 296 297 u64 xmsi_mask_reg; 298 299 /* Automated statistics collection */ 300 u64 stat_byte_cnt; 301 #define XGE_HAL_STAT_BYTE_CNT(n) vBIT(n, 4, 12) 302 u64 stat_cfg; 303 #define XGE_HAL_STAT_CFG_STAT_EN BIT(0) 304 #define XGE_HAL_STAT_CFG_ONE_SHOT_EN BIT(1) 305 #define XGE_HAL_STAT_CFG_STAT_NS_EN BIT(8) 306 #define XGE_HAL_STAT_CFG_STAT_RO BIT(9) 307 #define XGE_HAL_XENA_PER_SEC 0x208d5 308 #define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32) 309 310 u64 stat_addr; 311 312 /* General Configuration */ 313 u64 mdio_control; 314 #define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16) 315 #define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n) vBIT(n,19,5) 316 #define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n) vBIT(n,27,5) 317 #define XGE_HAL_MDIO_CONTROL_MMD_DATA(n) vBIT(n,32,16) 318 #define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n) vBIT(n,56,4) 319 #define XGE_HAL_MDIO_CONTROL_MMD_OP(n) vBIT(n,60,2) 320 #define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n) ((n>>16)&0xFFFF) 321 #define XGE_HAL_MDIO_MMD_PMA_DEV_ADDR 0x01 322 #define XGE_HAL_MDIO_DOM_REG_ADDR 0xA100 323 #define XGE_HAL_MDIO_ALARM_FLAGS_ADDR 0xA070 324 #define XGE_HAL_MDIO_WARN_FLAGS_ADDR 0xA074 325 #define XGE_HAL_MDIO_CTRL_START 0xE 326 #define XGE_HAL_MDIO_OP_ADDRESS 0x0 327 #define XGE_HAL_MDIO_OP_WRITE 0x1 328 #define XGE_HAL_MDIO_OP_READ 0x3 329 #define XGE_HAL_MDIO_OP_READ_POST_INCREMENT 0x2 330 #define XGE_HAL_MDIO_ALARM_TEMPHIGH 0x0080 331 #define XGE_HAL_MDIO_ALARM_TEMPLOW 0x0040 332 #define XGE_HAL_MDIO_ALARM_BIASHIGH 0x0008 333 #define XGE_HAL_MDIO_ALARM_BIASLOW 0x0004 334 #define XGE_HAL_MDIO_ALARM_POUTPUTHIGH 0x0002 335 #define XGE_HAL_MDIO_ALARM_POUTPUTLOW 0x0001 336 #define XGE_HAL_MDIO_WARN_TEMPHIGH 0x0080 337 #define XGE_HAL_MDIO_WARN_TEMPLOW 0x0040 338 #define XGE_HAL_MDIO_WARN_BIASHIGH 0x0008 339 #define XGE_HAL_MDIO_WARN_BIASLOW 0x0004 340 #define XGE_HAL_MDIO_WARN_POUTPUTHIGH 0x0002 341 #define XGE_HAL_MDIO_WARN_POUTPUTLOW 0x0001 342 343 u64 dtx_control; 344 345 u64 i2c_control; 346 #define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) 347 #define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) 348 #define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) 349 #define XGE_HAL_I2C_CONTROL_READ BIT(24) 350 #define XGE_HAL_I2C_CONTROL_NACK BIT(25) 351 #define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4) 352 #define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) 353 #define XGE_HAL_I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) 354 #define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) 355 356 u64 beacon_control; 357 u64 misc_control; 358 #define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3) 359 #define XGE_HAL_MISC_CONTROL_EXT_REQ_EN BIT(1) 360 #define XGE_HAL_MISC_CONTROL_LINK_FAULT BIT(0) 361 362 u64 xfb_control; 363 u64 gpio_control; 364 #define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8) 365 366 u64 txfifo_dw_mask; 367 u64 split_table_line_no; 368 u64 sc_timeout; 369 u64 pic_control_2; 370 #define XGE_HAL_TXD_WRITE_BC(n) vBIT(n, 13, 3) 371 u64 ini_dperr_ctrl; 372 u64 wreq_split_mask; 373 u64 qw_per_rxd; 374 u8 unused7[0x300 - 0x250]; 375 376 u64 pic_status; 377 u64 txp_status; 378 u64 txp_err_context; 379 u64 spdm_bir_offset; 380 #define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset) \ 381 (u8)(spdm_bir_offset >> 61) 382 #define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \ 383 (u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF) 384 u64 spdm_overwrite; 385 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite) \ 386 (u8)((spdm_overwrite >> 48) & 0xff) 387 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \ 388 (u8)((spdm_overwrite >> 40) & 0x3) 389 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite) \ 390 (u8)((spdm_overwrite >> 32) & 0x7) 391 u64 cfg_addr_on_dperr; 392 u64 pif_addr_on_dperr; 393 u64 tags_in_use; 394 u64 rd_req_types; 395 u64 split_table_line; 396 u64 unxp_split_add_ph; 397 u64 unexp_split_attr_ph; 398 u64 split_message; 399 u64 spdm_structure; 400 #define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure) (u16)(spdm_structure >> 48) 401 #define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure) \ 402 (u8)((spdm_structure >> 40) & 0xff) 403 #define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure) \ 404 (u8)((spdm_structure >> 32) & 0xff) 405 406 u64 txdw_ptr_cnt_0; 407 u64 txdw_ptr_cnt_1; 408 u64 txdw_ptr_cnt_2; 409 u64 txdw_ptr_cnt_3; 410 u64 txdw_ptr_cnt_4; 411 u64 txdw_ptr_cnt_5; 412 u64 txdw_ptr_cnt_6; 413 u64 txdw_ptr_cnt_7; 414 u64 rxdw_cnt_ring_0; 415 u64 rxdw_cnt_ring_1; 416 u64 rxdw_cnt_ring_2; 417 u64 rxdw_cnt_ring_3; 418 u64 rxdw_cnt_ring_4; 419 u64 rxdw_cnt_ring_5; 420 u64 rxdw_cnt_ring_6; 421 u64 rxdw_cnt_ring_7; 422 423 u8 unused8[0x410]; 424 425 /* TxDMA registers */ 426 u64 txdma_int_status; 427 u64 txdma_int_mask; 428 #define XGE_HAL_TXDMA_PFC_INT BIT(0) 429 #define XGE_HAL_TXDMA_TDA_INT BIT(1) 430 #define XGE_HAL_TXDMA_PCC_INT BIT(2) 431 #define XGE_HAL_TXDMA_TTI_INT BIT(3) 432 #define XGE_HAL_TXDMA_LSO_INT BIT(4) 433 #define XGE_HAL_TXDMA_TPA_INT BIT(5) 434 #define XGE_HAL_TXDMA_SM_INT BIT(6) 435 u64 pfc_err_reg; 436 #define XGE_HAL_PFC_ECC_SG_ERR BIT(7) 437 #define XGE_HAL_PFC_ECC_DB_ERR BIT(15) 438 #define XGE_HAL_PFC_SM_ERR_ALARM BIT(23) 439 #define XGE_HAL_PFC_MISC_0_ERR BIT(31) 440 #define XGE_HAL_PFC_MISC_1_ERR BIT(32) 441 #define XGE_HAL_PFC_PCIX_ERR BIT(39) 442 u64 pfc_err_mask; 443 u64 pfc_err_alarm; 444 445 u64 tda_err_reg; 446 #define XGE_HAL_TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8) 447 #define XGE_HAL_TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8) 448 #define XGE_HAL_TDA_SM0_ERR_ALARM BIT(22) 449 #define XGE_HAL_TDA_SM1_ERR_ALARM BIT(23) 450 #define XGE_HAL_TDA_PCIX_ERR BIT(39) 451 u64 tda_err_mask; 452 u64 tda_err_alarm; 453 454 u64 pcc_err_reg; 455 #define XGE_HAL_PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8) 456 #define XGE_HAL_PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8) 457 #define XGE_HAL_PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8) 458 #define XGE_HAL_PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8) 459 #define XGE_HAL_PCC_SM_ERR_ALARM vBIT(0xff,32,8) 460 #define XGE_HAL_PCC_WR_ERR_ALARM vBIT(0xff,40,8) 461 #define XGE_HAL_PCC_N_SERR vBIT(0xff,48,8) 462 #define XGE_HAL_PCC_ENABLE_FOUR vBIT(0x0F,0,8) 463 #define XGE_HAL_PCC_6_COF_OV_ERR BIT(56) 464 #define XGE_HAL_PCC_7_COF_OV_ERR BIT(57) 465 #define XGE_HAL_PCC_6_LSO_OV_ERR BIT(58) 466 #define XGE_HAL_PCC_7_LSO_OV_ERR BIT(59) 467 u64 pcc_err_mask; 468 u64 pcc_err_alarm; 469 470 u64 tti_err_reg; 471 #define XGE_HAL_TTI_ECC_SG_ERR BIT(7) 472 #define XGE_HAL_TTI_ECC_DB_ERR BIT(15) 473 #define XGE_HAL_TTI_SM_ERR_ALARM BIT(23) 474 u64 tti_err_mask; 475 u64 tti_err_alarm; 476 477 u64 lso_err_reg; 478 #define XGE_HAL_LSO6_SEND_OFLOW BIT(12) 479 #define XGE_HAL_LSO7_SEND_OFLOW BIT(13) 480 #define XGE_HAL_LSO6_ABORT BIT(14) 481 #define XGE_HAL_LSO7_ABORT BIT(15) 482 #define XGE_HAL_LSO6_SM_ERR_ALARM BIT(22) 483 #define XGE_HAL_LSO7_SM_ERR_ALARM BIT(23) 484 u64 lso_err_mask; 485 u64 lso_err_alarm; 486 487 u64 tpa_err_reg; 488 #define XGE_HAL_TPA_TX_FRM_DROP BIT(7) 489 #define XGE_HAL_TPA_SM_ERR_ALARM BIT(23) 490 u64 tpa_err_mask; 491 u64 tpa_err_alarm; 492 493 u64 sm_err_reg; 494 #define XGE_HAL_SM_SM_ERR_ALARM BIT(15) 495 u64 sm_err_mask; 496 u64 sm_err_alarm; 497 498 u8 unused9[0x100 - 0xB8]; 499 500 /* TxDMA arbiter */ 501 u64 tx_dma_wrap_stat; 502 503 /* Tx FIFO controller */ 504 #define XGE_HAL_X_MAX_FIFOS 8 505 #define XGE_HAL_X_FIFO_MAX_LEN 0x1FFF /*8191 */ 506 u64 tx_fifo_partition_0; 507 #define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0) 508 #define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) 509 #define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) 510 #define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) 511 #define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) 512 513 u64 tx_fifo_partition_1; 514 #define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) 515 #define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) 516 #define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) 517 #define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) 518 519 u64 tx_fifo_partition_2; 520 #define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) 521 #define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) 522 #define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) 523 #define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) 524 525 u64 tx_fifo_partition_3; 526 #define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) 527 #define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) 528 #define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) 529 #define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) 530 531 #define XGE_HAL_TX_FIFO_PARTITION_PRI_0 0 /* highest */ 532 #define XGE_HAL_TX_FIFO_PARTITION_PRI_1 1 533 #define XGE_HAL_TX_FIFO_PARTITION_PRI_2 2 534 #define XGE_HAL_TX_FIFO_PARTITION_PRI_3 3 535 #define XGE_HAL_TX_FIFO_PARTITION_PRI_4 4 536 #define XGE_HAL_TX_FIFO_PARTITION_PRI_5 5 537 #define XGE_HAL_TX_FIFO_PARTITION_PRI_6 6 538 #define XGE_HAL_TX_FIFO_PARTITION_PRI_7 7 /* lowest */ 539 540 u64 tx_w_round_robin_0; 541 u64 tx_w_round_robin_1; 542 u64 tx_w_round_robin_2; 543 u64 tx_w_round_robin_3; 544 u64 tx_w_round_robin_4; 545 546 u64 tti_command_mem; 547 #define XGE_HAL_TTI_CMD_MEM_WE BIT(7) 548 #define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 549 #define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15) 550 #define XGE_HAL_TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) 551 552 u64 tti_data1_mem; 553 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) 554 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) 555 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38) 556 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39) 557 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) 558 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) 559 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) 560 561 u64 tti_data2_mem; 562 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) 563 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) 564 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) 565 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) 566 567 /* Tx Protocol assist */ 568 u64 tx_pa_cfg; 569 #define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR BIT(1) 570 #define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 571 #define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 572 #define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6) 573 574 /* Recent add, used only debug purposes. */ 575 u64 pcc_enable; 576 577 u64 pfc_monitor_0; 578 u64 pfc_monitor_1; 579 u64 pfc_monitor_2; 580 u64 pfc_monitor_3; 581 u64 txd_ownership_ctrl; 582 u64 pfc_read_cntrl; 583 u64 pfc_read_data; 584 585 u8 unused10[0x1700 - 0x11B0]; 586 587 u64 txdma_debug_ctrl; 588 589 u8 unused11[0x1800 - 0x1708]; 590 591 /* RxDMA Registers */ 592 u64 rxdma_int_status; 593 #define XGE_HAL_RXDMA_RC_INT BIT(0) 594 #define XGE_HAL_RXDMA_RPA_INT BIT(1) 595 #define XGE_HAL_RXDMA_RDA_INT BIT(2) 596 #define XGE_HAL_RXDMA_RTI_INT BIT(3) 597 598 u64 rxdma_int_mask; 599 #define XGE_HAL_RXDMA_INT_RC_INT_M BIT(0) 600 #define XGE_HAL_RXDMA_INT_RPA_INT_M BIT(1) 601 #define XGE_HAL_RXDMA_INT_RDA_INT_M BIT(2) 602 #define XGE_HAL_RXDMA_INT_RTI_INT_M BIT(3) 603 604 u64 rda_err_reg; 605 #define XGE_HAL_RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8) 606 #define XGE_HAL_RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8) 607 #define XGE_HAL_RDA_FRM_ECC_SG_ERR BIT(23) 608 #define XGE_HAL_RDA_FRM_ECC_DB_N_AERR BIT(31) 609 #define XGE_HAL_RDA_SM1_ERR_ALARM BIT(38) 610 #define XGE_HAL_RDA_SM0_ERR_ALARM BIT(39) 611 #define XGE_HAL_RDA_MISC_ERR BIT(47) 612 #define XGE_HAL_RDA_PCIX_ERR BIT(55) 613 #define XGE_HAL_RDA_RXD_ECC_DB_SERR BIT(63) 614 u64 rda_err_mask; 615 u64 rda_err_alarm; 616 617 u64 rc_err_reg; 618 #define XGE_HAL_RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8) 619 #define XGE_HAL_RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8) 620 #define XGE_HAL_RC_FTC_ECC_SG_ERR BIT(23) 621 #define XGE_HAL_RC_FTC_ECC_DB_ERR BIT(31) 622 #define XGE_HAL_RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8) 623 #define XGE_HAL_RC_FTC_SM_ERR_ALARM BIT(47) 624 #define XGE_HAL_RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) 625 u64 rc_err_mask; 626 u64 rc_err_alarm; 627 628 u64 prc_pcix_err_reg; 629 #define XGE_HAL_PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8) 630 #define XGE_HAL_PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8) 631 #define XGE_HAL_PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8) 632 #define XGE_HAL_PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8) 633 #define XGE_HAL_PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8) 634 #define XGE_HAL_PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8) 635 u64 prc_pcix_err_mask; 636 u64 prc_pcix_err_alarm; 637 638 u64 rpa_err_reg; 639 #define XGE_HAL_RPA_ECC_SG_ERR BIT(7) 640 #define XGE_HAL_RPA_ECC_DB_ERR BIT(15) 641 #define XGE_HAL_RPA_FLUSH_REQUEST BIT(22) 642 #define XGE_HAL_RPA_SM_ERR_ALARM BIT(23) 643 #define XGE_HAL_RPA_CREDIT_ERR BIT(31) 644 u64 rpa_err_mask; 645 u64 rpa_err_alarm; 646 647 u64 rti_err_reg; 648 #define XGE_HAL_RTI_ECC_SG_ERR BIT(7) 649 #define XGE_HAL_RTI_ECC_DB_ERR BIT(15) 650 #define XGE_HAL_RTI_SM_ERR_ALARM BIT(23) 651 u64 rti_err_mask; 652 u64 rti_err_alarm; 653 654 u8 unused12[0x100 - 0x88]; 655 656 /* DMA arbiter */ 657 u64 rx_queue_priority; 658 #define XGE_HAL_RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) 659 #define XGE_HAL_RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) 660 #define XGE_HAL_RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) 661 #define XGE_HAL_RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) 662 #define XGE_HAL_RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) 663 #define XGE_HAL_RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) 664 #define XGE_HAL_RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) 665 #define XGE_HAL_RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) 666 667 #define XGE_HAL_RX_QUEUE_PRI_0 0 /* highest */ 668 #define XGE_HAL_RX_QUEUE_PRI_1 1 669 #define XGE_HAL_RX_QUEUE_PRI_2 2 670 #define XGE_HAL_RX_QUEUE_PRI_3 3 671 #define XGE_HAL_RX_QUEUE_PRI_4 4 672 #define XGE_HAL_RX_QUEUE_PRI_5 5 673 #define XGE_HAL_RX_QUEUE_PRI_6 6 674 #define XGE_HAL_RX_QUEUE_PRI_7 7 /* lowest */ 675 676 u64 rx_w_round_robin_0; 677 u64 rx_w_round_robin_1; 678 u64 rx_w_round_robin_2; 679 u64 rx_w_round_robin_3; 680 u64 rx_w_round_robin_4; 681 682 /* Per-ring controller regs */ 683 #define XGE_HAL_RX_MAX_RINGS 8 684 u64 prc_rxd0_n[XGE_HAL_RX_MAX_RINGS]; 685 u64 prc_ctrl_n[XGE_HAL_RX_MAX_RINGS]; 686 #define XGE_HAL_PRC_CTRL_RC_ENABLED BIT(7) 687 #define XGE_HAL_PRC_CTRL_RING_MODE (BIT(14)|BIT(15)) 688 #define XGE_HAL_PRC_CTRL_RING_MODE_1 vBIT(0,14,2) 689 #define XGE_HAL_PRC_CTRL_RING_MODE_3 vBIT(1,14,2) 690 #define XGE_HAL_PRC_CTRL_RING_MODE_5 vBIT(2,14,2) 691 #define XGE_HAL_PRC_CTRL_RING_MODE_x vBIT(3,14,2) 692 #define XGE_HAL_PRC_CTRL_NO_SNOOP(n) vBIT(n,22,2) 693 #define XGE_HAL_PRC_CTRL_RTH_DISABLE BIT(31) 694 #define XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT BIT(37) 695 #define XGE_HAL_PRC_CTRL_GROUP_READS BIT(38) 696 #define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) 697 698 u64 prc_alarm_action; 699 #define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP BIT(3) 700 #define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP BIT(7) 701 #define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP BIT(11) 702 #define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP BIT(15) 703 #define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP BIT(19) 704 #define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP BIT(23) 705 #define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP BIT(27) 706 #define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP BIT(31) 707 #define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP BIT(35) 708 #define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP BIT(39) 709 #define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP BIT(43) 710 #define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP BIT(47) 711 #define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP BIT(51) 712 #define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP BIT(55) 713 #define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP BIT(59) 714 #define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP BIT(63) 715 716 /* Receive traffic interrupts */ 717 u64 rti_command_mem; 718 #define XGE_HAL_RTI_CMD_MEM_WE BIT(7) 719 #define XGE_HAL_RTI_CMD_MEM_STROBE BIT(15) 720 #define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 721 #define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15) 722 #define XGE_HAL_RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) 723 724 u64 rti_data1_mem; 725 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) 726 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38) 727 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39) 728 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) 729 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) 730 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) 731 732 u64 rti_data2_mem; 733 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) 734 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) 735 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) 736 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) 737 738 u64 rx_pa_cfg; 739 #define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR BIT(1) 740 #define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 741 #define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 742 #define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n) vBIT(n,6,1) 743 #define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n) vBIT(n,15,1) 744 745 u8 unused13_0[0x8]; 746 747 u64 ring_bump_counter1; 748 u64 ring_bump_counter2; 749 #define XGE_HAL_RING_BUMP_CNT(i, val) (u16)(val >> (48 - (16 * (i % 4)))) 750 751 u8 unused13[0x700 - 0x1f0]; 752 753 u64 rxdma_debug_ctrl; 754 755 u8 unused14[0x2000 - 0x1f08]; 756 757 /* Media Access Controller Register */ 758 u64 mac_int_status; 759 u64 mac_int_mask; 760 #define XGE_HAL_MAC_INT_STATUS_TMAC_INT BIT(0) 761 #define XGE_HAL_MAC_INT_STATUS_RMAC_INT BIT(1) 762 763 u64 mac_tmac_err_reg; 764 #define XGE_HAL_TMAC_ECC_DB_ERR BIT(15) 765 #define XGE_HAL_TMAC_TX_BUF_OVRN BIT(23) 766 #define XGE_HAL_TMAC_TX_CRI_ERR BIT(31) 767 #define XGE_HAL_TMAC_TX_SM_ERR BIT(39) 768 u64 mac_tmac_err_mask; 769 u64 mac_tmac_err_alarm; 770 771 u64 mac_rmac_err_reg; 772 #define XGE_HAL_RMAC_RX_BUFF_OVRN BIT(0) 773 #define XGE_HAL_RMAC_RTH_SPDM_ECC_SG_ERR BIT(0) 774 #define XGE_HAL_RMAC_RTS_ECC_DB_ERR BIT(0) 775 #define XGE_HAL_RMAC_ECC_DB_ERR BIT(0) 776 #define XGE_HAL_RMAC_RTH_SPDM_ECC_DB_ERR BIT(0) 777 #define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT BIT(0) 778 #define XGE_HAL_RMAC_RX_SM_ERR BIT(39) 779 u64 mac_rmac_err_mask; 780 u64 mac_rmac_err_alarm; 781 782 u8 unused15[0x100 - 0x40]; 783 784 u64 mac_cfg; 785 #define XGE_HAL_MAC_CFG_TMAC_ENABLE BIT(0) 786 #define XGE_HAL_MAC_CFG_RMAC_ENABLE BIT(1) 787 #define XGE_HAL_MAC_CFG_LAN_NOT_WAN BIT(2) 788 #define XGE_HAL_MAC_CFG_TMAC_LOOPBACK BIT(3) 789 #define XGE_HAL_MAC_CFG_TMAC_APPEND_PAD BIT(4) 790 #define XGE_HAL_MAC_CFG_RMAC_STRIP_FCS BIT(5) 791 #define XGE_HAL_MAC_CFG_RMAC_STRIP_PAD BIT(6) 792 #define XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE BIT(7) 793 #define XGE_HAL_MAC_RMAC_DISCARD_PFRM BIT(8) 794 #define XGE_HAL_MAC_RMAC_BCAST_ENABLE BIT(9) 795 #define XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE BIT(10) 796 #define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) 797 798 u64 tmac_avg_ipg; 799 #define XGE_HAL_TMAC_AVG_IPG(val) vBIT(val,0,8) 800 801 u64 rmac_max_pyld_len; 802 #define XGE_HAL_RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) 803 804 u64 rmac_err_cfg; 805 #define XGE_HAL_RMAC_ERR_FCS BIT(0) 806 #define XGE_HAL_RMAC_ERR_FCS_ACCEPT BIT(1) 807 #define XGE_HAL_RMAC_ERR_TOO_LONG BIT(1) 808 #define XGE_HAL_RMAC_ERR_TOO_LONG_ACCEPT BIT(1) 809 #define XGE_HAL_RMAC_ERR_RUNT BIT(2) 810 #define XGE_HAL_RMAC_ERR_RUNT_ACCEPT BIT(2) 811 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH BIT(3) 812 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3) 813 814 u64 rmac_cfg_key; 815 #define XGE_HAL_RMAC_CFG_KEY(val) vBIT(val,0,16) 816 817 #define XGE_HAL_MAX_MAC_ADDRESSES 64 818 #define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET 63 819 #define XGE_HAL_MAX_MAC_ADDRESSES_HERC 256 820 #define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET_HERC 255 821 822 u64 rmac_addr_cmd_mem; 823 #define XGE_HAL_RMAC_ADDR_CMD_MEM_WE BIT(7) 824 #define XGE_HAL_RMAC_ADDR_CMD_MEM_RD 0 825 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15) 826 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15) 827 #define XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) 828 829 u64 rmac_addr_data0_mem; 830 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) 831 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_USER BIT(48) 832 833 u64 rmac_addr_data1_mem; 834 #define XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) 835 836 u8 unused16[0x8]; 837 838 /* 839 u64 rmac_addr_cfg; 840 #define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) 841 #define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) 842 #define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48 843 #define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 844 */ 845 u64 tmac_ipg_cfg; 846 847 u64 rmac_pause_cfg; 848 #define XGE_HAL_RMAC_PAUSE_GEN_EN BIT(0) 849 #define XGE_HAL_RMAC_PAUSE_RCV_EN BIT(1) 850 #define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) 851 #define XGE_HAL_RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) 852 853 u64 rmac_red_cfg; 854 855 u64 rmac_red_rate_q0q3; 856 u64 rmac_red_rate_q4q7; 857 858 u64 mac_link_util; 859 #define XGE_HAL_MAC_TX_LINK_UTIL vBIT(0xFE,1,7) 860 #define XGE_HAL_MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4) 861 #define XGE_HAL_MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) 862 #define XGE_HAL_MAC_RX_LINK_UTIL vBIT(0xFE,33,7) 863 #define XGE_HAL_MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4) 864 #define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) 865 866 #define XGE_HAL_MAC_LINK_UTIL_DISABLE (XGE_HAL_MAC_TX_LINK_UTIL_DISABLE | \ 867 XGE_HAL_MAC_RX_LINK_UTIL_DISABLE) 868 869 u64 rmac_invalid_ipg; 870 871 /* rx traffic steering */ 872 #define XGE_HAL_MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) 873 u64 rts_frm_len_n[8]; 874 875 u64 rts_qos_steering; 876 877 #define XGE_HAL_MAX_DIX_MAP 4 878 u64 rts_dix_map_n[XGE_HAL_MAX_DIX_MAP]; 879 #define XGE_HAL_RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) 880 #define XGE_HAL_RTS_DIX_MAP_SCW(val) BIT(val,21) 881 882 u64 rts_q_alternates; 883 u64 rts_default_q; 884 #define XGE_HAL_RTS_DEFAULT_Q(n) vBIT(n,5,3) 885 886 u64 rts_ctrl; 887 #define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI BIT(2) 888 #define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL BIT(3) 889 #define XGE_HAL_RTS_CTRL_ENHANCED_MODE BIT(7) 890 891 u64 rts_pn_cam_ctrl; 892 #define XGE_HAL_RTS_PN_CAM_CTRL_WE BIT(7) 893 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15) 894 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15) 895 #define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) 896 u64 rts_pn_cam_data; 897 #define XGE_HAL_RTS_PN_CAM_DATA_TCP_SELECT BIT(7) 898 #define XGE_HAL_RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) 899 #define XGE_HAL_RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) 900 901 u64 rts_ds_mem_ctrl; 902 #define XGE_HAL_RTS_DS_MEM_CTRL_WE BIT(7) 903 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15) 904 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15) 905 #define XGE_HAL_RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) 906 u64 rts_ds_mem_data; 907 #define XGE_HAL_RTS_DS_MEM_DATA(n) vBIT(n,0,8) 908 909 u8 unused16_1[0x308 - 0x220]; 910 911 u64 rts_vid_mem_ctrl; 912 u64 rts_vid_mem_data; 913 u64 rts_p0_p3_map; 914 u64 rts_p4_p7_map; 915 u64 rts_p8_p11_map; 916 u64 rts_p12_p15_map; 917 918 u64 rts_mac_cfg; 919 #define XGE_HAL_RTS_MAC_SECT0_EN BIT(0) 920 #define XGE_HAL_RTS_MAC_SECT1_EN BIT(1) 921 #define XGE_HAL_RTS_MAC_SECT2_EN BIT(2) 922 #define XGE_HAL_RTS_MAC_SECT3_EN BIT(3) 923 #define XGE_HAL_RTS_MAC_SECT4_EN BIT(4) 924 #define XGE_HAL_RTS_MAC_SECT5_EN BIT(5) 925 #define XGE_HAL_RTS_MAC_SECT6_EN BIT(6) 926 #define XGE_HAL_RTS_MAC_SECT7_EN BIT(7) 927 928 u8 unused16_2[0x380 - 0x340]; 929 930 u64 rts_rth_cfg; 931 #define XGE_HAL_RTS_RTH_EN BIT(3) 932 #define XGE_HAL_RTS_RTH_BUCKET_SIZE(n) vBIT(n,4,4) 933 #define XGE_HAL_RTS_RTH_ALG_SEL_MS BIT(11) 934 #define XGE_HAL_RTS_RTH_TCP_IPV4_EN BIT(15) 935 #define XGE_HAL_RTS_RTH_UDP_IPV4_EN BIT(19) 936 #define XGE_HAL_RTS_RTH_IPV4_EN BIT(23) 937 #define XGE_HAL_RTS_RTH_TCP_IPV6_EN BIT(27) 938 #define XGE_HAL_RTS_RTH_UDP_IPV6_EN BIT(31) 939 #define XGE_HAL_RTS_RTH_IPV6_EN BIT(35) 940 #define XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN BIT(39) 941 #define XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN BIT(43) 942 #define XGE_HAL_RTS_RTH_IPV6_EX_EN BIT(47) 943 944 u64 rts_rth_map_mem_ctrl; 945 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE BIT(7) 946 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE BIT(15) 947 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 948 949 u64 rts_rth_map_mem_data; 950 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN BIT(3) 951 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA(n) vBIT(n,5,3) 952 953 u64 rts_rth_spdm_mem_ctrl; 954 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE BIT(15) 955 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n) vBIT(n,21,3) 956 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 957 958 u64 rts_rth_spdm_mem_data; 959 960 u64 rts_rth_jhash_cfg; 961 #define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n) vBIT(n,0,32) 962 #define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n) vBIT(n,32,32) 963 964 u64 rts_rth_hash_mask[5]; /* rth mask's 0...4 */ 965 u64 rts_rth_hash_mask_5; 966 #define XGE_HAL_RTH_HASH_MASK_5(n) vBIT(n,0,32) 967 968 u64 rts_rth_status; 969 #define XGE_HAL_RTH_STATUS_SPDM_USE_L4 BIT(3) 970 971 u8 unused17[0x400 - 0x3E8]; 972 973 u64 rmac_red_fine_q0q3; 974 u64 rmac_red_fine_q4q7; 975 u64 rmac_pthresh_cross; 976 u64 rmac_rthresh_cross; 977 u64 rmac_pnum_range[32]; 978 979 u64 rmac_mp_crc_0; 980 u64 rmac_mp_mask_a_0; 981 u64 rmac_mp_mask_b_0; 982 983 u64 rmac_mp_crc_1; 984 u64 rmac_mp_mask_a_1; 985 u64 rmac_mp_mask_b_1; 986 987 u64 rmac_mp_crc_2; 988 u64 rmac_mp_mask_a_2; 989 u64 rmac_mp_mask_b_2; 990 991 u64 rmac_mp_crc_3; 992 u64 rmac_mp_mask_a_3; 993 u64 rmac_mp_mask_b_3; 994 995 u64 rmac_mp_crc_4; 996 u64 rmac_mp_mask_a_4; 997 u64 rmac_mp_mask_b_4; 998 999 u64 rmac_mp_crc_5; 1000 u64 rmac_mp_mask_a_5; 1001 u64 rmac_mp_mask_b_5; 1002 1003 u64 rmac_mp_crc_6; 1004 u64 rmac_mp_mask_a_6; 1005 u64 rmac_mp_mask_b_6; 1006 1007 u64 rmac_mp_crc_7; 1008 u64 rmac_mp_mask_a_7; 1009 u64 rmac_mp_mask_b_7; 1010 1011 u64 mac_ctrl; 1012 u64 activity_control; 1013 1014 u8 unused17_2[0x700 - 0x5F0]; 1015 1016 u64 mac_debug_ctrl; 1017 #define XGE_HAL_MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL 1018 1019 u8 unused18[0x2800 - 0x2708]; 1020 1021 /* memory controller registers */ 1022 u64 mc_int_status; 1023 #define XGE_HAL_MC_INT_STATUS_MC_INT BIT(0) 1024 u64 mc_int_mask; 1025 #define XGE_HAL_MC_INT_MASK_MC_INT BIT(0) 1026 1027 u64 mc_err_reg; 1028 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L BIT(2) /* non-Xena */ 1029 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U BIT(3) /* non-Xena */ 1030 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L BIT(4) /* non-Xena */ 1031 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U BIT(5) /* non-Xena */ 1032 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L BIT(6) 1033 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U BIT(7) 1034 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L BIT(10) /* non-Xena */ 1035 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U BIT(11) /* non-Xena */ 1036 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L BIT(12) /* non-Xena */ 1037 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U BIT(13) /* non-Xena */ 1038 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L BIT(14) 1039 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U BIT(15) 1040 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 BIT(17) 1041 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) /* Xena: reset */ 1042 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 BIT(19) 1043 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) /* Xena: reset */ 1044 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22) 1045 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23) 1046 #define XGE_HAL_MC_ERR_REG_SM_ERR BIT(31) 1047 #define XGE_HAL_MC_ERR_REG_PL_LOCK_N BIT(39) 1048 1049 u64 mc_err_mask; 1050 u64 mc_err_alarm; 1051 1052 u8 unused19[0x100 - 0x28]; 1053 1054 /* MC configuration */ 1055 u64 rx_queue_cfg; 1056 #define XGE_HAL_RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) 1057 #define XGE_HAL_RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) 1058 #define XGE_HAL_RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) 1059 #define XGE_HAL_RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) 1060 #define XGE_HAL_RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) 1061 #define XGE_HAL_RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) 1062 #define XGE_HAL_RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) 1063 #define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) 1064 1065 u64 mc_rldram_mrs; 1066 #define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) 1067 #define XGE_HAL_MC_RLDRAM_MRS_ENABLE BIT(47) 1068 1069 u64 mc_rldram_interleave; 1070 1071 u64 mc_pause_thresh_q0q3; 1072 u64 mc_pause_thresh_q4q7; 1073 1074 u64 mc_red_thresh_q[8]; 1075 1076 u8 unused20[0x200 - 0x168]; 1077 u64 mc_rldram_ref_per; 1078 u8 unused21[0x220 - 0x208]; 1079 u64 mc_rldram_test_ctrl; 1080 #define XGE_HAL_MC_RLDRAM_TEST_MODE BIT(47) 1081 #define XGE_HAL_MC_RLDRAM_TEST_WRITE BIT(7) 1082 #define XGE_HAL_MC_RLDRAM_TEST_GO BIT(15) 1083 #define XGE_HAL_MC_RLDRAM_TEST_DONE BIT(23) 1084 #define XGE_HAL_MC_RLDRAM_TEST_PASS BIT(31) 1085 1086 u8 unused22[0x240 - 0x228]; 1087 u64 mc_rldram_test_add; 1088 u8 unused23[0x260 - 0x248]; 1089 u64 mc_rldram_test_d0; 1090 u8 unused24[0x280 - 0x268]; 1091 u64 mc_rldram_test_d1; 1092 u8 unused25[0x300 - 0x288]; 1093 u64 mc_rldram_test_d2; 1094 u8 unused26_1[0x2C00 - 0x2B08]; 1095 u64 mc_rldram_test_read_d0; 1096 u8 unused26_2[0x20 - 0x8]; 1097 u64 mc_rldram_test_read_d1; 1098 u8 unused26_3[0x40 - 0x28]; 1099 u64 mc_rldram_test_read_d2; 1100 u8 unused26_4[0x60 - 0x48]; 1101 u64 mc_rldram_test_add_bkg; 1102 u8 unused26_5[0x80 - 0x68]; 1103 u64 mc_rldram_test_d0_bkg; 1104 u8 unused26_6[0xD00 - 0xC88]; 1105 u64 mc_rldram_test_d1_bkg; 1106 u8 unused26_7[0x20 - 0x8]; 1107 u64 mc_rldram_test_d2_bkg; 1108 u8 unused26_8[0x40 - 0x28]; 1109 u64 mc_rldram_test_read_d0_bkg; 1110 u8 unused26_9[0x60 - 0x48]; 1111 u64 mc_rldram_test_read_d1_bkg; 1112 u8 unused26_10[0x80 - 0x68]; 1113 u64 mc_rldram_test_read_d2_bkg; 1114 u8 unused26_11[0xE00 - 0xD88]; 1115 u64 mc_rldram_generation; 1116 u8 unused26_12[0x20 - 0x8]; 1117 u64 mc_driver; 1118 u8 unused26_13[0x40 - 0x28]; 1119 u64 mc_rldram_ref_per_herc; 1120 #define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n) vBIT(n, 0, 16) 1121 u8 unused26_14[0x660 - 0x648]; 1122 u64 mc_rldram_mrs_herc; 1123 #define XGE_HAL_MC_RLDRAM_MRS(n) vBIT(n, 14, 17) 1124 u8 unused26_15[0x700 - 0x668]; 1125 u64 mc_debug_ctrl; 1126 1127 u8 unused27[0x3000 - 0x2f08]; 1128 1129 /* XGXG */ 1130 /* XGXS control registers */ 1131 1132 u64 xgxs_int_status; 1133 #define XGE_HAL_XGXS_INT_STATUS_TXGXS BIT(0) 1134 #define XGE_HAL_XGXS_INT_STATUS_RXGXS BIT(1) 1135 u64 xgxs_int_mask; 1136 #define XGE_HAL_XGXS_INT_MASK_TXGXS BIT(0) 1137 #define XGE_HAL_XGXS_INT_MASK_RXGXS BIT(1) 1138 1139 u64 xgxs_txgxs_err_reg; 1140 #define XGE_HAL_TXGXS_ECC_SG_ERR BIT(7) 1141 #define XGE_HAL_TXGXS_ECC_DB_ERR BIT(15) 1142 #define XGE_HAL_TXGXS_ESTORE_UFLOW BIT(31) 1143 #define XGE_HAL_TXGXS_TX_SM_ERR BIT(39) 1144 u64 xgxs_txgxs_err_mask; 1145 u64 xgxs_txgxs_err_alarm; 1146 1147 u64 xgxs_rxgxs_err_reg; 1148 #define XGE_HAL_RXGXS_ESTORE_OFLOW BIT(7) 1149 #define XGE_HAL_RXGXS_RX_SM_ERR BIT(39) 1150 u64 xgxs_rxgxs_err_mask; 1151 u64 xgxs_rxgxs_err_alarm; 1152 1153 u64 spi_err_reg; 1154 u64 spi_err_mask; 1155 u64 spi_err_alarm; 1156 1157 u8 unused28[0x100 - 0x58]; 1158 1159 u64 xgxs_cfg; 1160 u64 xgxs_status; 1161 1162 u64 xgxs_cfg_key; 1163 u64 xgxs_efifo_cfg; /* CHANGED */ 1164 u64 rxgxs_ber_0; /* CHANGED */ 1165 u64 rxgxs_ber_1; /* CHANGED */ 1166 1167 u64 spi_control; 1168 u64 spi_data; 1169 u64 spi_write_protect; 1170 1171 u8 unused29[0x80 - 0x48]; 1172 1173 u64 xgxs_cfg_1; 1174 } xge_hal_pci_bar0_t; 1175 1176 /* Using this strcture to calculate offsets */ 1177 typedef struct xge_hal_pci_config_le_t { 1178 u16 vendor_id; // 0x00 1179 u16 device_id; // 0x02 1180 1181 u16 command; // 0x04 1182 u16 status; // 0x06 1183 1184 u8 revision; // 0x08 1185 u8 pciClass[3]; // 0x09 1186 1187 u8 cache_line_size; // 0x0c 1188 u8 latency_timer; // 0x0d 1189 u8 header_type; // 0x0e 1190 u8 bist; // 0x0f 1191 1192 u32 base_addr0_lo; // 0x10 1193 u32 base_addr0_hi; // 0x14 1194 1195 u32 base_addr1_lo; // 0x18 1196 u32 base_addr1_hi; // 0x1C 1197 1198 u32 not_Implemented1; // 0x20 1199 u32 not_Implemented2; // 0x24 1200 1201 u32 cardbus_cis_pointer; // 0x28 1202 1203 u16 subsystem_vendor_id; // 0x2c 1204 u16 subsystem_id; // 0x2e 1205 1206 u32 rom_base; // 0x30 1207 u8 capabilities_pointer; // 0x34 1208 u8 rsvd_35[3]; // 0x35 1209 u32 rsvd_38; // 0x38 1210 1211 u8 interrupt_line; // 0x3c 1212 u8 interrupt_pin; // 0x3d 1213 u8 min_grant; // 0x3e 1214 u8 max_latency; // 0x3f 1215 1216 u8 msi_cap_id; // 0x40 1217 u8 msi_next_ptr; // 0x41 1218 u16 msi_control; // 0x42 1219 u32 msi_lower_address; // 0x44 1220 u32 msi_higher_address; // 0x48 1221 u16 msi_data; // 0x4c 1222 u16 msi_unused; // 0x4e 1223 1224 u8 vpd_cap_id; // 0x50 1225 u8 vpd_next_cap; // 0x51 1226 u16 vpd_addr; // 0x52 1227 u32 vpd_data; // 0x54 1228 1229 u8 rsvd_b0[8]; // 0x58 1230 1231 u8 pcix_cap; // 0x60 1232 u8 pcix_next_cap; // 0x61 1233 u16 pcix_command; // 0x62 1234 1235 u32 pcix_status; // 0x64 1236 1237 u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1238 } xge_hal_pci_config_le_t; // 0x100 1239 1240 typedef struct xge_hal_pci_config_t { 1241 #ifdef XGE_OS_HOST_BIG_ENDIAN 1242 u16 device_id; // 0x02 1243 u16 vendor_id; // 0x00 1244 1245 u16 status; // 0x06 1246 u16 command; // 0x04 1247 1248 u8 pciClass[3]; // 0x09 1249 u8 revision; // 0x08 1250 1251 u8 bist; // 0x0f 1252 u8 header_type; // 0x0e 1253 u8 latency_timer; // 0x0d 1254 u8 cache_line_size; // 0x0c 1255 1256 u32 base_addr0_lo; // 0x10 1257 u32 base_addr0_hi; // 0x14 1258 1259 u32 base_addr1_lo; // 0x18 1260 u32 base_addr1_hi; // 0x1C 1261 1262 u32 not_Implemented1; // 0x20 1263 u32 not_Implemented2; // 0x24 1264 1265 u32 cardbus_cis_pointer; // 0x28 1266 1267 u16 subsystem_id; // 0x2e 1268 u16 subsystem_vendor_id; // 0x2c 1269 1270 u32 rom_base; // 0x30 1271 u8 rsvd_35[3]; // 0x35 1272 u8 capabilities_pointer; // 0x34 1273 u32 rsvd_38; // 0x38 1274 1275 u8 max_latency; // 0x3f 1276 u8 min_grant; // 0x3e 1277 u8 interrupt_pin; // 0x3d 1278 u8 interrupt_line; // 0x3c 1279 1280 u16 msi_control; // 0x42 1281 u8 msi_next_ptr; // 0x41 1282 u8 msi_cap_id; // 0x40 1283 u32 msi_lower_address; // 0x44 1284 u32 msi_higher_address; // 0x48 1285 u16 msi_unused; // 0x4e 1286 u16 msi_data; // 0x4c 1287 1288 u16 vpd_addr; // 0x52 1289 u8 vpd_next_cap; // 0x51 1290 u8 vpd_cap_id; // 0x50 1291 u32 vpd_data; // 0x54 1292 1293 u8 rsvd_b0[8]; // 0x58 1294 1295 u16 pcix_command; // 0x62 1296 u8 pcix_next_cap; // 0x61 1297 u8 pcix_cap; // 0x60 1298 1299 u32 pcix_status; // 0x64 1300 #else 1301 u16 vendor_id; // 0x00 1302 u16 device_id; // 0x02 1303 1304 u16 command; // 0x04 1305 u16 status; // 0x06 1306 1307 u8 revision; // 0x08 1308 u8 pciClass[3]; // 0x09 1309 1310 u8 cache_line_size; // 0x0c 1311 u8 latency_timer; // 0x0d 1312 u8 header_type; // 0x0e 1313 u8 bist; // 0x0f 1314 1315 u32 base_addr0_lo; // 0x10 1316 u32 base_addr0_hi; // 0x14 1317 1318 u32 base_addr1_lo; // 0x18 1319 u32 base_addr1_hi; // 0x1C 1320 1321 u32 not_Implemented1; // 0x20 1322 u32 not_Implemented2; // 0x24 1323 1324 u32 cardbus_cis_pointer; // 0x28 1325 1326 u16 subsystem_vendor_id; // 0x2c 1327 u16 subsystem_id; // 0x2e 1328 1329 u32 rom_base; // 0x30 1330 u8 capabilities_pointer; // 0x34 1331 u8 rsvd_35[3]; // 0x35 1332 u32 rsvd_38; // 0x38 1333 1334 u8 interrupt_line; // 0x3c 1335 u8 interrupt_pin; // 0x3d 1336 u8 min_grant; // 0x3e 1337 u8 max_latency; // 0x3f 1338 1339 u8 msi_cap_id; // 0x40 1340 u8 msi_next_ptr; // 0x41 1341 u16 msi_control; // 0x42 1342 u32 msi_lower_address; // 0x44 1343 u32 msi_higher_address; // 0x48 1344 u16 msi_data; // 0x4c 1345 u16 msi_unused; // 0x4e 1346 1347 u8 vpd_cap_id; // 0x50 1348 u8 vpd_next_cap; // 0x51 1349 u16 vpd_addr; // 0x52 1350 u32 vpd_data; // 0x54 1351 1352 u8 rsvd_b0[8]; // 0x58 1353 1354 u8 pcix_cap; // 0x60 1355 u8 pcix_next_cap; // 0x61 1356 u16 pcix_command; // 0x62 1357 1358 u32 pcix_status; // 0x64 1359 1360 #endif 1361 u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1362 } xge_hal_pci_config_t; // 0x100 1363 1364 #define XGE_HAL_REG_SPACE sizeof(xge_hal_pci_bar0_t) 1365 #define XGE_HAL_EEPROM_SIZE (0x01 << 11) 1366 1367 __EXTERN_END_DECLS 1368 1369 #endif /* XGE_HAL_REGS_H */ 1370