1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #ifndef XGE_HAL_REGS_H 25 #define XGE_HAL_REGS_H 26 27 typedef struct { 28 29 /* General Control-Status Registers */ 30 u64 general_int_status; 31 #define XGE_HAL_GEN_INTR_TXPIC BIT(0) 32 #define XGE_HAL_GEN_INTR_TXDMA BIT(1) 33 #define XGE_HAL_GEN_INTR_TXMAC BIT(2) 34 #define XGE_HAL_GEN_INTR_TXXGXS BIT(3) 35 #define XGE_HAL_GEN_INTR_TXTRAFFIC BIT(8) 36 #define XGE_HAL_GEN_INTR_RXPIC BIT(32) 37 #define XGE_HAL_GEN_INTR_RXDMA BIT(33) 38 #define XGE_HAL_GEN_INTR_RXMAC BIT(34) 39 #define XGE_HAL_GEN_INTR_MC BIT(35) 40 #define XGE_HAL_GEN_INTR_RXXGXS BIT(36) 41 #define XGE_HAL_GEN_INTR_RXTRAFFIC BIT(40) 42 #define XGE_HAL_GEN_ERROR_INTR (XGE_HAL_GEN_INTR_TXPIC | \ 43 XGE_HAL_GEN_INTR_RXPIC | \ 44 XGE_HAL_GEN_INTR_TXDMA | \ 45 XGE_HAL_GEN_INTR_RXDMA | \ 46 XGE_HAL_GEN_INTR_TXMAC | \ 47 XGE_HAL_GEN_INTR_RXMAC | \ 48 XGE_HAL_GEN_INTR_TXXGXS | \ 49 XGE_HAL_GEN_INTR_RXXGXS | \ 50 XGE_HAL_GEN_INTR_MC) 51 52 u64 general_int_mask; 53 54 u8 unused0[0x100 - 0x10]; 55 56 u64 sw_reset; 57 58 /* XGXS must be removed from reset only once. */ 59 #define XGE_HAL_SW_RESET_XENA vBIT(0xA5,0,8) 60 #define XGE_HAL_SW_RESET_FLASH vBIT(0xA5,8,8) 61 #define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8) 62 #define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8) 63 #define XGE_HAL_SW_RESET_ALL (XGE_HAL_SW_RESET_XENA | \ 64 XGE_HAL_SW_RESET_FLASH | \ 65 XGE_HAL_SW_RESET_EOI | \ 66 XGE_HAL_SW_RESET_XGXS) 67 68 /* The SW_RESET register must read this value after a successful reset. */ 69 #if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN) 70 #define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA500000000ULL 71 #define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A500000000ULL 72 #else 73 #define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA5000000ULL 74 #define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A50000ULL 75 #endif 76 77 78 u64 adapter_status; 79 #define XGE_HAL_ADAPTER_STATUS_TDMA_READY BIT(0) 80 #define XGE_HAL_ADAPTER_STATUS_RDMA_READY BIT(1) 81 #define XGE_HAL_ADAPTER_STATUS_PFC_READY BIT(2) 82 #define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3) 83 #define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT BIT(5) 84 #define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6) 85 #define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7) 86 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) 87 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8) 88 #define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR vBIT(0x0F,0,8) 89 90 #define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) 91 #define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY BIT(24) 92 #define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY BIT(25) 93 #define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK BIT(30) 94 #define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK BIT(31) 95 96 u64 adapter_control; 97 #define XGE_HAL_ADAPTER_CNTL_EN BIT(7) 98 #define XGE_HAL_ADAPTER_EOI_TX_ON BIT(15) 99 #define XGE_HAL_ADAPTER_LED_ON BIT(23) 100 #define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4) 101 #define XGE_HAL_ADAPTER_WAIT_INT BIT(48) 102 #define XGE_HAL_ADAPTER_ECC_EN BIT(55) 103 104 u64 serr_source; 105 #define XGE_HAL_SERR_SOURCE_PIC BIT(0) 106 #define XGE_HAL_SERR_SOURCE_TXDMA BIT(1) 107 #define XGE_HAL_SERR_SOURCE_RXDMA BIT(2) 108 #define XGE_HAL_SERR_SOURCE_MAC BIT(3) 109 #define XGE_HAL_SERR_SOURCE_MC BIT(4) 110 #define XGE_HAL_SERR_SOURCE_XGXS BIT(5) 111 #define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \ 112 XGE_HAL_SERR_SOURCE_TXDMA | \ 113 XGE_HAL_SERR_SOURCE_RXDMA | \ 114 XGE_HAL_SERR_SOURCE_MAC | \ 115 XGE_HAL_SERR_SOURCE_MC | \ 116 XGE_HAL_SERR_SOURCE_XGXS) 117 118 u64 pci_info; 119 #define XGE_HAL_PCI_INFO vBIT(0xF,0,4) 120 #define XGE_HAL_PCI_32_BIT BIT(8) 121 122 u8 unused0_1[0x160 - 0x128]; 123 124 u64 ric_status; 125 126 u8 unused0_2[0x558 - 0x168]; 127 128 u64 mbist_status; 129 130 u8 unused0_3[0x800 - 0x560]; 131 132 /* PCI-X Controller registers */ 133 u64 pic_int_status; 134 u64 pic_int_mask; 135 #define XGE_HAL_PIC_INT_TX BIT(0) 136 #define XGE_HAL_PIC_INT_FLSH BIT(1) 137 #define XGE_HAL_PIC_INT_MDIO BIT(2) 138 #define XGE_HAL_PIC_INT_IIC BIT(3) 139 #define XGE_HAL_PIC_INT_MISC BIT(4) 140 #define XGE_HAL_PIC_INT_RX BIT(32) 141 142 u64 txpic_int_reg; 143 #define XGE_HAL_TXPIC_INT_SCHED_INTR BIT(42) 144 u64 txpic_int_mask; 145 #define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR BIT(0) 146 #define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR BIT(1) 147 #define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8) 148 #define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9) 149 #define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR BIT(10) 150 #define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11) 151 #define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR BIT(13) 152 #define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR BIT(14) 153 #define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR BIT(15) 154 #define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21) 155 #define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23) 156 #define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR BIT(48) 157 #define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR BIT(50) 158 /* 159 #define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52) 160 #define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54) 161 #define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58) 162 */ 163 u64 txpic_alarms; 164 u64 rxpic_int_reg; 165 #define XGE_HAL_RX_PIC_INT_REG_SPDM_READY BIT(0) 166 #define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR BIT(44) 167 #define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR BIT(55) 168 u64 rxpic_int_mask; 169 u64 rxpic_alarms; 170 171 u64 flsh_int_reg; 172 u64 flsh_int_mask; 173 #define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63) 174 #define XGE_HAL_PIC_FLSH_INT_REG_ERR BIT(62) 175 u64 flash_alarms; 176 177 u64 mdio_int_reg; 178 u64 mdio_int_mask; 179 #define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR BIT(0) 180 #define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR BIT(8) 181 #define XGE_HAL_MDIO_INT_REG_LASI BIT(39) 182 u64 mdio_alarms; 183 184 u64 iic_int_reg; 185 u64 iic_int_mask; 186 #define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR BIT(4) 187 #define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR BIT(5) 188 #define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR BIT(6) 189 #define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR BIT(7) 190 #define XGE_HAL_IIC_INT_REG_ACK_ERR BIT(8) 191 u64 iic_alarms; 192 193 u64 msi_pending_reg; 194 195 u64 misc_int_reg; 196 #define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0) 197 #define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1) 198 #define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2) 199 u64 misc_int_mask; 200 u64 misc_alarms; 201 202 u64 msi_triggered_reg; 203 204 u64 xfp_gpio_int_reg; 205 u64 xfp_gpio_int_mask; 206 u64 xfp_alarms; 207 208 u8 unused5[0x8E0 - 0x8C8]; 209 210 u64 tx_traffic_int; 211 #define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n) 212 u64 tx_traffic_mask; 213 214 u64 rx_traffic_int; 215 #define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n) 216 u64 rx_traffic_mask; 217 218 /* PIC Control registers */ 219 u64 pic_control; 220 #define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1 BIT(0) 221 #define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT BIT(1) 222 #define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4) 223 224 u64 swapper_ctrl; 225 #define XGE_HAL_SWAPPER_CTRL_PIF_R_FE BIT(0) 226 #define XGE_HAL_SWAPPER_CTRL_PIF_R_SE BIT(1) 227 #define XGE_HAL_SWAPPER_CTRL_PIF_W_FE BIT(8) 228 #define XGE_HAL_SWAPPER_CTRL_PIF_W_SE BIT(9) 229 #define XGE_HAL_SWAPPER_CTRL_RTH_FE BIT(10) 230 #define XGE_HAL_SWAPPER_CTRL_RTH_SE BIT(11) 231 #define XGE_HAL_SWAPPER_CTRL_TXP_FE BIT(16) 232 #define XGE_HAL_SWAPPER_CTRL_TXP_SE BIT(17) 233 #define XGE_HAL_SWAPPER_CTRL_TXD_R_FE BIT(18) 234 #define XGE_HAL_SWAPPER_CTRL_TXD_R_SE BIT(19) 235 #define XGE_HAL_SWAPPER_CTRL_TXD_W_FE BIT(20) 236 #define XGE_HAL_SWAPPER_CTRL_TXD_W_SE BIT(21) 237 #define XGE_HAL_SWAPPER_CTRL_TXF_R_FE BIT(22) 238 #define XGE_HAL_SWAPPER_CTRL_TXF_R_SE BIT(23) 239 #define XGE_HAL_SWAPPER_CTRL_RXD_R_FE BIT(32) 240 #define XGE_HAL_SWAPPER_CTRL_RXD_R_SE BIT(33) 241 #define XGE_HAL_SWAPPER_CTRL_RXD_W_FE BIT(34) 242 #define XGE_HAL_SWAPPER_CTRL_RXD_W_SE BIT(35) 243 #define XGE_HAL_SWAPPER_CTRL_RXF_W_FE BIT(36) 244 #define XGE_HAL_SWAPPER_CTRL_RXF_W_SE BIT(37) 245 #define XGE_HAL_SWAPPER_CTRL_XMSI_FE BIT(40) 246 #define XGE_HAL_SWAPPER_CTRL_XMSI_SE BIT(41) 247 #define XGE_HAL_SWAPPER_CTRL_STATS_FE BIT(48) 248 #define XGE_HAL_SWAPPER_CTRL_STATS_SE BIT(49) 249 250 u64 pif_rd_swapper_fb; 251 #define XGE_HAL_IF_RD_SWAPPER_FB 0x0123456789ABCDEFULL 252 253 u64 scheduled_int_ctrl; 254 #define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0) 255 #define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT BIT(1) 256 #define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) 257 #define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32) 258 #define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL 259 260 261 u64 txreqtimeout; 262 #define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32) 263 #define XGE_HAL_TXREQTO_EN BIT(63) 264 265 u64 statsreqtimeout; 266 #define XGE_HAL_STATREQTO_VAL(n) TBD 267 #define XGE_HAL_STATREQTO_EN BIT(63) 268 269 u64 read_retry_delay; 270 u64 read_retry_acceleration; 271 u64 write_retry_delay; 272 u64 write_retry_acceleration; 273 274 u64 xmsi_control; 275 #define XGE_HAL_XMSI_EN BIT(0) 276 #define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1) 277 #define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3) 278 279 u64 xmsi_access; 280 #define XGE_HAL_XMSI_WR_RDN BIT(7) 281 #define XGE_HAL_XMSI_STROBE BIT(15) 282 #define XGE_HAL_XMSI_NO(val) vBIT(val,26,6) 283 284 u64 xmsi_address; 285 u64 xmsi_data; 286 287 u64 rx_mat; 288 #define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8) 289 290 u8 unused6[0x8]; 291 292 u64 tx_mat[8]; 293 #define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8) 294 295 u64 xmsi_mask_reg; 296 297 /* Automated statistics collection */ 298 u64 stat_byte_cnt; 299 u64 stat_cfg; 300 #define XGE_HAL_STAT_CFG_STAT_EN BIT(0) 301 #define XGE_HAL_STAT_CFG_ONE_SHOT_EN BIT(1) 302 #define XGE_HAL_STAT_CFG_STAT_NS_EN BIT(8) 303 #define XGE_HAL_STAT_CFG_STAT_RO BIT(9) 304 #define XGE_HAL_XENA_PER_SEC 0x208d5 305 #define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32) 306 307 u64 stat_addr; 308 309 /* General Configuration */ 310 u64 mdio_control; 311 #define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16) 312 #define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n) vBIT(n,19,5) 313 #define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n) vBIT(n,27,5) 314 #define XGE_HAL_MDIO_CONTROL_MMD_DATA(n) vBIT(n,32,16) 315 #define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n) vBIT(n,56,4) 316 #define XGE_HAL_MDIO_CONTROL_MMD_OP(n) vBIT(n,60,2) 317 #define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n) ((n>>16)&0xFFFF) 318 #define XGE_HAL_MDIO_MMD_PMA_DEV_ADDR 0x01 319 #define XGE_HAL_MDIO_DOM_REG_ADDR 0xA100 320 #define XGE_HAL_MDIO_ALARM_FLAGS_ADDR 0xA070 321 #define XGE_HAL_MDIO_WARN_FLAGS_ADDR 0xA074 322 #define XGE_HAL_MDIO_CTRL_START 0xE 323 #define XGE_HAL_MDIO_OP_ADDRESS 0x0 324 #define XGE_HAL_MDIO_OP_WRITE 0x1 325 #define XGE_HAL_MDIO_OP_READ 0x3 326 #define XGE_HAL_MDIO_OP_READ_POST_INCREMENT 0x2 327 #define XGE_HAL_MDIO_ALARM_TEMPHIGH 0x0080 328 #define XGE_HAL_MDIO_ALARM_TEMPLOW 0x0040 329 #define XGE_HAL_MDIO_ALARM_BIASHIGH 0x0008 330 #define XGE_HAL_MDIO_ALARM_BIASLOW 0x0004 331 #define XGE_HAL_MDIO_ALARM_POUTPUTHIGH 0x0002 332 #define XGE_HAL_MDIO_ALARM_POUTPUTLOW 0x0001 333 #define XGE_HAL_MDIO_WARN_TEMPHIGH 0x0080 334 #define XGE_HAL_MDIO_WARN_TEMPLOW 0x0040 335 #define XGE_HAL_MDIO_WARN_BIASHIGH 0x0008 336 #define XGE_HAL_MDIO_WARN_BIASLOW 0x0004 337 #define XGE_HAL_MDIO_WARN_POUTPUTHIGH 0x0002 338 #define XGE_HAL_MDIO_WARN_POUTPUTLOW 0x0001 339 340 u64 dtx_control; 341 342 u64 i2c_control; 343 #define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) 344 #define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) 345 #define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) 346 #define XGE_HAL_I2C_CONTROL_READ BIT(24) 347 #define XGE_HAL_I2C_CONTROL_NACK BIT(25) 348 #define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4) 349 #define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) 350 #define XGE_HAL_I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) 351 #define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) 352 353 u64 beacon_control; 354 u64 misc_control; 355 #define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3) 356 #define XGE_HAL_MISC_CONTROL_EXT_REQ_EN BIT(1) 357 358 u64 xfb_control; 359 u64 gpio_control; 360 #define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8) 361 362 u64 txfifo_dw_mask; 363 u64 split_table_line_no; 364 u64 sc_timeout; 365 u64 pic_control_2; 366 #define XGE_HAL_TXD_WRITE_BC(n) vBIT(n, 13, 3) 367 u64 ini_dperr_ctrl; 368 u64 wreq_split_mask; 369 u64 qw_per_rxd; 370 u8 unused7[0x300 - 0x250]; 371 372 u64 pic_status; 373 u64 txp_status; 374 u64 txp_err_context; 375 u64 spdm_bir_offset; 376 #define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset) \ 377 (u8)(spdm_bir_offset >> 61) 378 #define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \ 379 (u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF) 380 u64 spdm_overwrite; 381 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite) \ 382 (u8)((spdm_overwrite >> 48) & 0xff) 383 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \ 384 (u8)((spdm_overwrite >> 40) & 0x3) 385 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite) \ 386 (u8)((spdm_overwrite >> 32) & 0x7) 387 u64 cfg_addr_on_dperr; 388 u64 pif_addr_on_dperr; 389 u64 tags_in_use; 390 u64 rd_req_types; 391 u64 split_table_line; 392 u64 unxp_split_add_ph; 393 u64 unexp_split_attr_ph; 394 u64 split_message; 395 u64 spdm_structure; 396 #define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure) (u16)(spdm_structure >> 48) 397 #define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure) \ 398 (u8)((spdm_structure >> 40) & 0xff) 399 #define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure) \ 400 (u8)((spdm_structure >> 32) & 0xff) 401 402 u64 txdw_ptr_cnt_0; 403 u64 txdw_ptr_cnt_1; 404 u64 txdw_ptr_cnt_2; 405 u64 txdw_ptr_cnt_3; 406 u64 txdw_ptr_cnt_4; 407 u64 txdw_ptr_cnt_5; 408 u64 txdw_ptr_cnt_6; 409 u64 txdw_ptr_cnt_7; 410 u64 rxdw_cnt_ring_0; 411 u64 rxdw_cnt_ring_1; 412 u64 rxdw_cnt_ring_2; 413 u64 rxdw_cnt_ring_3; 414 u64 rxdw_cnt_ring_4; 415 u64 rxdw_cnt_ring_5; 416 u64 rxdw_cnt_ring_6; 417 u64 rxdw_cnt_ring_7; 418 419 u8 unused8[0x410]; 420 421 /* TxDMA registers */ 422 u64 txdma_int_status; 423 u64 txdma_int_mask; 424 #define XGE_HAL_TXDMA_PFC_INT BIT(0) 425 #define XGE_HAL_TXDMA_TDA_INT BIT(1) 426 #define XGE_HAL_TXDMA_PCC_INT BIT(2) 427 #define XGE_HAL_TXDMA_TTI_INT BIT(3) 428 #define XGE_HAL_TXDMA_LSO_INT BIT(4) 429 #define XGE_HAL_TXDMA_TPA_INT BIT(5) 430 #define XGE_HAL_TXDMA_SM_INT BIT(6) 431 u64 pfc_err_reg; 432 u64 pfc_err_mask; 433 u64 pfc_err_alarm; 434 435 u64 tda_err_reg; 436 u64 tda_err_mask; 437 u64 tda_err_alarm; 438 439 u64 pcc_err_reg; 440 u64 pcc_err_mask; 441 u64 pcc_err_alarm; 442 443 u64 tti_err_reg; 444 u64 tti_err_mask; 445 u64 tti_err_alarm; 446 447 u64 lso_err_reg; 448 u64 lso_err_mask; 449 u64 lso_err_alarm; 450 451 u64 tpa_err_reg; 452 u64 tpa_err_mask; 453 u64 tpa_err_alarm; 454 455 u64 sm_err_reg; 456 u64 sm_err_mask; 457 u64 sm_err_alarm; 458 459 u8 unused9[0x100 - 0xB8]; 460 461 /* TxDMA arbiter */ 462 u64 tx_dma_wrap_stat; 463 464 /* Tx FIFO controller */ 465 #define XGE_HAL_X_MAX_FIFOS 8 466 #define XGE_HAL_X_FIFO_MAX_LEN 0x1FFF /*8191 */ 467 u64 tx_fifo_partition_0; 468 #define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0) 469 #define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) 470 #define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) 471 #define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) 472 #define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) 473 474 u64 tx_fifo_partition_1; 475 #define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) 476 #define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) 477 #define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) 478 #define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) 479 480 u64 tx_fifo_partition_2; 481 #define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) 482 #define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) 483 #define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) 484 #define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) 485 486 u64 tx_fifo_partition_3; 487 #define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) 488 #define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) 489 #define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) 490 #define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) 491 492 #define XGE_HAL_TX_FIFO_PARTITION_PRI_0 0 /* highest */ 493 #define XGE_HAL_TX_FIFO_PARTITION_PRI_1 1 494 #define XGE_HAL_TX_FIFO_PARTITION_PRI_2 2 495 #define XGE_HAL_TX_FIFO_PARTITION_PRI_3 3 496 #define XGE_HAL_TX_FIFO_PARTITION_PRI_4 4 497 #define XGE_HAL_TX_FIFO_PARTITION_PRI_5 5 498 #define XGE_HAL_TX_FIFO_PARTITION_PRI_6 6 499 #define XGE_HAL_TX_FIFO_PARTITION_PRI_7 7 /* lowest */ 500 501 u64 tx_w_round_robin_0; 502 u64 tx_w_round_robin_1; 503 u64 tx_w_round_robin_2; 504 u64 tx_w_round_robin_3; 505 u64 tx_w_round_robin_4; 506 507 u64 tti_command_mem; 508 #define XGE_HAL_TTI_CMD_MEM_WE BIT(7) 509 #define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 510 #define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15) 511 #define XGE_HAL_TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) 512 513 u64 tti_data1_mem; 514 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) 515 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) 516 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38) 517 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39) 518 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) 519 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) 520 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) 521 522 u64 tti_data2_mem; 523 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) 524 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) 525 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) 526 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) 527 528 /* Tx Protocol assist */ 529 u64 tx_pa_cfg; 530 #define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR BIT(1) 531 #define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 532 #define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 533 #define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6) 534 535 /* Recent add, used only debug purposes. */ 536 u64 pcc_enable; 537 538 u64 pfc_monitor_0; 539 u64 pfc_monitor_1; 540 u64 pfc_monitor_2; 541 u64 pfc_monitor_3; 542 u64 txd_ownership_ctrl; 543 u64 pfc_read_cntrl; 544 u64 pfc_read_data; 545 546 u8 unused10[0x1700 - 0x11B0]; 547 548 u64 txdma_debug_ctrl; 549 550 u8 unused11[0x1800 - 0x1708]; 551 552 /* RxDMA Registers */ 553 u64 rxdma_int_status; 554 #define XGE_HAL_RXDMA_RC_INT BIT(0) 555 #define XGE_HAL_RXDMA_RPA_INT BIT(1) 556 #define XGE_HAL_RXDMA_RDA_INT BIT(2) 557 #define XGE_HAL_RXDMA_RTI_INT BIT(3) 558 559 u64 rxdma_int_mask; 560 #define XGE_HAL_RXDMA_INT_RC_INT_M BIT(0) 561 #define XGE_HAL_RXDMA_INT_RPA_INT_M BIT(1) 562 #define XGE_HAL_RXDMA_INT_RDA_INT_M BIT(2) 563 #define XGE_HAL_RXDMA_INT_RTI_INT_M BIT(3) 564 565 u64 rda_err_reg; 566 u64 rda_err_mask; 567 u64 rda_err_alarm; 568 569 u64 rc_err_reg; 570 u64 rc_err_mask; 571 u64 rc_err_alarm; 572 573 u64 prc_pcix_err_reg; 574 u64 prc_pcix_err_mask; 575 u64 prc_pcix_err_alarm; 576 577 u64 rpa_err_reg; 578 u64 rpa_err_mask; 579 u64 rpa_err_alarm; 580 581 u64 rti_err_reg; 582 u64 rti_err_mask; 583 u64 rti_err_alarm; 584 585 u8 unused12[0x100 - 0x88]; 586 587 /* DMA arbiter */ 588 u64 rx_queue_priority; 589 #define XGE_HAL_RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) 590 #define XGE_HAL_RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) 591 #define XGE_HAL_RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) 592 #define XGE_HAL_RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) 593 #define XGE_HAL_RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) 594 #define XGE_HAL_RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) 595 #define XGE_HAL_RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) 596 #define XGE_HAL_RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) 597 598 #define XGE_HAL_RX_QUEUE_PRI_0 0 /* highest */ 599 #define XGE_HAL_RX_QUEUE_PRI_1 1 600 #define XGE_HAL_RX_QUEUE_PRI_2 2 601 #define XGE_HAL_RX_QUEUE_PRI_3 3 602 #define XGE_HAL_RX_QUEUE_PRI_4 4 603 #define XGE_HAL_RX_QUEUE_PRI_5 5 604 #define XGE_HAL_RX_QUEUE_PRI_6 6 605 #define XGE_HAL_RX_QUEUE_PRI_7 7 /* lowest */ 606 607 u64 rx_w_round_robin_0; 608 u64 rx_w_round_robin_1; 609 u64 rx_w_round_robin_2; 610 u64 rx_w_round_robin_3; 611 u64 rx_w_round_robin_4; 612 613 /* Per-ring controller regs */ 614 #define XGE_HAL_RX_MAX_RINGS 8 615 u64 prc_rxd0_n[XGE_HAL_RX_MAX_RINGS]; 616 u64 prc_ctrl_n[XGE_HAL_RX_MAX_RINGS]; 617 #define XGE_HAL_PRC_CTRL_RC_ENABLED BIT(7) 618 #define XGE_HAL_PRC_CTRL_RING_MODE (BIT(14)|BIT(15)) 619 #define XGE_HAL_PRC_CTRL_RING_MODE_1 vBIT(0,14,2) 620 #define XGE_HAL_PRC_CTRL_RING_MODE_3 vBIT(1,14,2) 621 #define XGE_HAL_PRC_CTRL_RING_MODE_5 vBIT(2,14,2) 622 #define XGE_HAL_PRC_CTRL_RING_MODE_x vBIT(3,14,2) 623 #define XGE_HAL_PRC_CTRL_NO_SNOOP(n) vBIT(n,22,2) 624 #define XGE_HAL_PRC_CTRL_RTH_DISABLE BIT(31) 625 #define XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT BIT(37) 626 #define XGE_HAL_PRC_CTRL_GROUP_READS BIT(38) 627 #define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) 628 629 u64 prc_alarm_action; 630 #define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP BIT(3) 631 #define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP BIT(7) 632 #define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP BIT(11) 633 #define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP BIT(15) 634 #define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP BIT(19) 635 #define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP BIT(23) 636 #define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP BIT(27) 637 #define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP BIT(31) 638 #define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP BIT(35) 639 #define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP BIT(39) 640 #define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP BIT(43) 641 #define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP BIT(47) 642 #define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP BIT(51) 643 #define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP BIT(55) 644 #define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP BIT(59) 645 #define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP BIT(63) 646 647 /* Receive traffic interrupts */ 648 u64 rti_command_mem; 649 #define XGE_HAL_RTI_CMD_MEM_WE BIT(7) 650 #define XGE_HAL_RTI_CMD_MEM_STROBE BIT(15) 651 #define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD BIT(15) 652 #define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15) 653 #define XGE_HAL_RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) 654 655 u64 rti_data1_mem; 656 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) 657 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38) 658 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39) 659 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) 660 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) 661 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) 662 663 u64 rti_data2_mem; 664 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) 665 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) 666 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) 667 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) 668 669 u64 rx_pa_cfg; 670 #define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR BIT(1) 671 #define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI BIT(2) 672 #define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL BIT(3) 673 #define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n) vBIT(n,6,1) 674 #define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n) vBIT(n,15,1) 675 676 u8 unused13_0[0x8]; 677 678 u64 ring_bump_counter1; 679 u64 ring_bump_counter2; 680 #define XGE_HAL_RING_BUMP_CNT(i, val) (u16)(val >> (48 - (16 * (i % 4)))) 681 682 u8 unused13[0x700 - 0x1f0]; 683 684 u64 rxdma_debug_ctrl; 685 686 u8 unused14[0x2000 - 0x1f08]; 687 688 /* Media Access Controller Register */ 689 u64 mac_int_status; 690 u64 mac_int_mask; 691 #define XGE_HAL_MAC_INT_STATUS_TMAC_INT BIT(0) 692 #define XGE_HAL_MAC_INT_STATUS_RMAC_INT BIT(1) 693 694 u64 mac_tmac_err_reg; 695 #define XGE_HAL_TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15) 696 #define XGE_HAL_TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23) 697 #define XGE_HAL_TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31) 698 u64 mac_tmac_err_mask; 699 u64 mac_tmac_err_alarm; 700 701 u64 mac_rmac_err_reg; 702 #define XGE_HAL_RMAC_ERR_REG_RX_BUFF_OVRN BIT(0) 703 #define XGE_HAL_RMAC_ERR_REG_RTH_SPDM_ECC_SG_ERR BIT(9) 704 #define XGE_HAL_RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14) 705 #define XGE_HAL_RMAC_ERR_REG_ECC_DB_ERR BIT(15) 706 #define XGE_HAL_RMAC_ERR_REG_RTH_SPDM_ECC_DB_ERR BIT(17) 707 #define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT BIT(31) 708 u64 mac_rmac_err_mask; 709 u64 mac_rmac_err_alarm; 710 711 u8 unused15[0x100 - 0x40]; 712 713 u64 mac_cfg; 714 #define XGE_HAL_MAC_CFG_TMAC_ENABLE BIT(0) 715 #define XGE_HAL_MAC_CFG_RMAC_ENABLE BIT(1) 716 #define XGE_HAL_MAC_CFG_LAN_NOT_WAN BIT(2) 717 #define XGE_HAL_MAC_CFG_TMAC_LOOPBACK BIT(3) 718 #define XGE_HAL_MAC_CFG_TMAC_APPEND_PAD BIT(4) 719 #define XGE_HAL_MAC_CFG_RMAC_STRIP_FCS BIT(5) 720 #define XGE_HAL_MAC_CFG_RMAC_STRIP_PAD BIT(6) 721 #define XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE BIT(7) 722 #define XGE_HAL_MAC_RMAC_DISCARD_PFRM BIT(8) 723 #define XGE_HAL_MAC_RMAC_BCAST_ENABLE BIT(9) 724 #define XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE BIT(10) 725 #define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) 726 727 u64 tmac_avg_ipg; 728 #define XGE_HAL_TMAC_AVG_IPG(val) vBIT(val,0,8) 729 730 u64 rmac_max_pyld_len; 731 #define XGE_HAL_RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) 732 733 u64 rmac_err_cfg; 734 #define XGE_HAL_RMAC_ERR_FCS BIT(0) 735 #define XGE_HAL_RMAC_ERR_FCS_ACCEPT BIT(1) 736 #define XGE_HAL_RMAC_ERR_TOO_LONG BIT(1) 737 #define XGE_HAL_RMAC_ERR_TOO_LONG_ACCEPT BIT(1) 738 #define XGE_HAL_RMAC_ERR_RUNT BIT(2) 739 #define XGE_HAL_RMAC_ERR_RUNT_ACCEPT BIT(2) 740 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH BIT(3) 741 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3) 742 743 u64 rmac_cfg_key; 744 #define XGE_HAL_RMAC_CFG_KEY(val) vBIT(val,0,16) 745 746 #define XGE_HAL_MAX_MAC_ADDRESSES 64 747 #define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET 63 748 #define XGE_HAL_MAX_MAC_ADDRESSES_HERC 256 749 #define XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET_HERC 255 750 751 u64 rmac_addr_cmd_mem; 752 #define XGE_HAL_RMAC_ADDR_CMD_MEM_WE BIT(7) 753 #define XGE_HAL_RMAC_ADDR_CMD_MEM_RD 0 754 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15) 755 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15) 756 #define XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) 757 758 u64 rmac_addr_data0_mem; 759 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) 760 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_USER BIT(48) 761 762 u64 rmac_addr_data1_mem; 763 #define XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) 764 765 u8 unused16[0x8]; 766 767 /* 768 u64 rmac_addr_cfg; 769 #define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) 770 #define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) 771 #define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48 772 #define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 773 */ 774 u64 tmac_ipg_cfg; 775 776 u64 rmac_pause_cfg; 777 #define XGE_HAL_RMAC_PAUSE_GEN_EN BIT(0) 778 #define XGE_HAL_RMAC_PAUSE_RCV_EN BIT(1) 779 #define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) 780 #define XGE_HAL_RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) 781 782 u64 rmac_red_cfg; 783 784 u64 rmac_red_rate_q0q3; 785 u64 rmac_red_rate_q4q7; 786 787 u64 mac_link_util; 788 #define XGE_HAL_MAC_TX_LINK_UTIL vBIT(0xFE,1,7) 789 #define XGE_HAL_MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4) 790 #define XGE_HAL_MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) 791 #define XGE_HAL_MAC_RX_LINK_UTIL vBIT(0xFE,33,7) 792 #define XGE_HAL_MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4) 793 #define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) 794 795 #define XGE_HAL_MAC_LINK_UTIL_DISABLE (XGE_HAL_MAC_TX_LINK_UTIL_DISABLE | \ 796 XGE_HAL_MAC_RX_LINK_UTIL_DISABLE) 797 798 u64 rmac_invalid_ipg; 799 800 /* rx traffic steering */ 801 #define XGE_HAL_MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) 802 u64 rts_frm_len_n[8]; 803 804 u64 rts_qos_steering; 805 806 #define XGE_HAL_MAX_DIX_MAP 4 807 u64 rts_dix_map_n[XGE_HAL_MAX_DIX_MAP]; 808 #define XGE_HAL_RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) 809 #define XGE_HAL_RTS_DIX_MAP_SCW(val) BIT(val,21) 810 811 u64 rts_q_alternates; 812 u64 rts_default_q; 813 #define XGE_HAL_RTS_DEFAULT_Q(n) vBIT(n,5,3) 814 815 u64 rts_ctrl; 816 #define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI BIT(2) 817 #define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL BIT(3) 818 #define XGE_HAL_RTS_CTRL_ENHANCED_MODE BIT(7) 819 820 u64 rts_pn_cam_ctrl; 821 #define XGE_HAL_RTS_PN_CAM_CTRL_WE BIT(7) 822 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15) 823 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15) 824 #define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) 825 u64 rts_pn_cam_data; 826 #define XGE_HAL_RTS_PN_CAM_DATA_TCP_SELECT BIT(7) 827 #define XGE_HAL_RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) 828 #define XGE_HAL_RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) 829 830 u64 rts_ds_mem_ctrl; 831 #define XGE_HAL_RTS_DS_MEM_CTRL_WE BIT(7) 832 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15) 833 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15) 834 #define XGE_HAL_RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) 835 u64 rts_ds_mem_data; 836 #define XGE_HAL_RTS_DS_MEM_DATA(n) vBIT(n,0,8) 837 838 u8 unused16_1[0x308 - 0x220]; 839 840 u64 rts_vid_mem_ctrl; 841 u64 rts_vid_mem_data; 842 u64 rts_p0_p3_map; 843 u64 rts_p4_p7_map; 844 u64 rts_p8_p11_map; 845 u64 rts_p12_p15_map; 846 847 u64 rts_mac_cfg; 848 #define XGE_HAL_RTS_MAC_SECT0_EN BIT(0) 849 #define XGE_HAL_RTS_MAC_SECT1_EN BIT(1) 850 #define XGE_HAL_RTS_MAC_SECT2_EN BIT(2) 851 #define XGE_HAL_RTS_MAC_SECT3_EN BIT(3) 852 #define XGE_HAL_RTS_MAC_SECT4_EN BIT(4) 853 #define XGE_HAL_RTS_MAC_SECT5_EN BIT(5) 854 #define XGE_HAL_RTS_MAC_SECT6_EN BIT(6) 855 #define XGE_HAL_RTS_MAC_SECT7_EN BIT(7) 856 857 u8 unused16_2[0x380 - 0x340]; 858 859 u64 rts_rth_cfg; 860 #define XGE_HAL_RTS_RTH_EN BIT(3) 861 #define XGE_HAL_RTS_RTH_BUCKET_SIZE(n) vBIT(n,4,4) 862 #define XGE_HAL_RTS_RTH_ALG_SEL_MS BIT(11) 863 #define XGE_HAL_RTS_RTH_TCP_IPV4_EN BIT(15) 864 #define XGE_HAL_RTS_RTH_UDP_IPV4_EN BIT(19) 865 #define XGE_HAL_RTS_RTH_IPV4_EN BIT(23) 866 #define XGE_HAL_RTS_RTH_TCP_IPV6_EN BIT(27) 867 #define XGE_HAL_RTS_RTH_UDP_IPV6_EN BIT(31) 868 #define XGE_HAL_RTS_RTH_IPV6_EN BIT(35) 869 #define XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN BIT(39) 870 #define XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN BIT(43) 871 #define XGE_HAL_RTS_RTH_IPV6_EX_EN BIT(47) 872 873 u64 rts_rth_map_mem_ctrl; 874 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE BIT(7) 875 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE BIT(15) 876 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 877 878 u64 rts_rth_map_mem_data; 879 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN BIT(3) 880 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA(n) vBIT(n,5,3) 881 882 u64 rts_rth_spdm_mem_ctrl; 883 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE BIT(15) 884 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n) vBIT(n,21,3) 885 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n) vBIT(n,24,8) 886 887 u64 rts_rth_spdm_mem_data; 888 889 u64 rts_rth_jhash_cfg; 890 #define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n) vBIT(n,0,32) 891 #define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n) vBIT(n,32,32) 892 893 u64 rts_rth_hash_mask[5]; /* rth mask's 0...4 */ 894 u64 rts_rth_hash_mask_5; 895 #define XGE_HAL_RTH_HASH_MASK_5(n) vBIT(n,0,32) 896 897 u64 rts_rth_status; 898 #define XGE_HAL_RTH_STATUS_SPDM_USE_L4 BIT(3) 899 900 u8 unused17[0x400 - 0x3E8]; 901 902 u64 rmac_red_fine_q0q3; 903 u64 rmac_red_fine_q4q7; 904 u64 rmac_pthresh_cross; 905 u64 rmac_rthresh_cross; 906 u64 rmac_pnum_range[32]; 907 908 u64 rmac_mp_crc_0; 909 u64 rmac_mp_mask_a_0; 910 u64 rmac_mp_mask_b_0; 911 912 u64 rmac_mp_crc_1; 913 u64 rmac_mp_mask_a_1; 914 u64 rmac_mp_mask_b_1; 915 916 u64 rmac_mp_crc_2; 917 u64 rmac_mp_mask_a_2; 918 u64 rmac_mp_mask_b_2; 919 920 u64 rmac_mp_crc_3; 921 u64 rmac_mp_mask_a_3; 922 u64 rmac_mp_mask_b_3; 923 924 u64 rmac_mp_crc_4; 925 u64 rmac_mp_mask_a_4; 926 u64 rmac_mp_mask_b_4; 927 928 u64 rmac_mp_crc_5; 929 u64 rmac_mp_mask_a_5; 930 u64 rmac_mp_mask_b_5; 931 932 u64 rmac_mp_crc_6; 933 u64 rmac_mp_mask_a_6; 934 u64 rmac_mp_mask_b_6; 935 936 u64 rmac_mp_crc_7; 937 u64 rmac_mp_mask_a_7; 938 u64 rmac_mp_mask_b_7; 939 940 u64 mac_ctrl; 941 u64 activity_control; 942 943 u8 unused17_2[0x700 - 0x5F0]; 944 945 u64 mac_debug_ctrl; 946 #define XGE_HAL_MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL 947 948 u8 unused18[0x2800 - 0x2708]; 949 950 /* memory controller registers */ 951 u64 mc_int_status; 952 #define XGE_HAL_MC_INT_STATUS_MC_INT BIT(0) 953 u64 mc_int_mask; 954 #define XGE_HAL_MC_INT_MASK_MC_INT BIT(0) 955 956 u64 mc_err_reg; 957 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L BIT(2) /* non-Xena */ 958 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U BIT(3) /* non-Xena */ 959 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L BIT(4) /* non-Xena */ 960 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U BIT(5) /* non-Xena */ 961 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L BIT(6) 962 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U BIT(7) 963 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L BIT(10) /* non-Xena */ 964 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U BIT(11) /* non-Xena */ 965 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L BIT(12) /* non-Xena */ 966 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U BIT(13) /* non-Xena */ 967 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L BIT(14) 968 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U BIT(15) 969 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 BIT(17) 970 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) /* Xena: reset */ 971 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 BIT(19) 972 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) /* Xena: reset */ 973 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22) 974 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23) 975 #define XGE_HAL_MC_ERR_REG_SM_ERR BIT(31) 976 #define XGE_HAL_MC_ERR_REG_PL_LOCK_N BIT(39) 977 978 u64 mc_err_mask; 979 u64 mc_err_alarm; 980 981 u8 unused19[0x100 - 0x28]; 982 983 /* MC configuration */ 984 u64 rx_queue_cfg; 985 #define XGE_HAL_RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) 986 #define XGE_HAL_RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) 987 #define XGE_HAL_RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) 988 #define XGE_HAL_RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) 989 #define XGE_HAL_RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) 990 #define XGE_HAL_RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) 991 #define XGE_HAL_RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) 992 #define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) 993 994 u64 mc_rldram_mrs; 995 #define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) 996 #define XGE_HAL_MC_RLDRAM_MRS_ENABLE BIT(47) 997 998 u64 mc_rldram_interleave; 999 1000 u64 mc_pause_thresh_q0q3; 1001 u64 mc_pause_thresh_q4q7; 1002 1003 u64 mc_red_thresh_q[8]; 1004 1005 u8 unused20[0x200 - 0x168]; 1006 u64 mc_rldram_ref_per; 1007 u8 unused21[0x220 - 0x208]; 1008 u64 mc_rldram_test_ctrl; 1009 #define XGE_HAL_MC_RLDRAM_TEST_MODE BIT(47) 1010 #define XGE_HAL_MC_RLDRAM_TEST_WRITE BIT(7) 1011 #define XGE_HAL_MC_RLDRAM_TEST_GO BIT(15) 1012 #define XGE_HAL_MC_RLDRAM_TEST_DONE BIT(23) 1013 #define XGE_HAL_MC_RLDRAM_TEST_PASS BIT(31) 1014 1015 u8 unused22[0x240 - 0x228]; 1016 u64 mc_rldram_test_add; 1017 u8 unused23[0x260 - 0x248]; 1018 u64 mc_rldram_test_d0; 1019 u8 unused24[0x280 - 0x268]; 1020 u64 mc_rldram_test_d1; 1021 u8 unused25[0x300 - 0x288]; 1022 u64 mc_rldram_test_d2; 1023 u8 unused26_1[0x2C00 - 0x2B08]; 1024 u64 mc_rldram_test_read_d0; 1025 u8 unused26_2[0x20 - 0x8]; 1026 u64 mc_rldram_test_read_d1; 1027 u8 unused26_3[0x40 - 0x28]; 1028 u64 mc_rldram_test_read_d2; 1029 u8 unused26_4[0x60 - 0x48]; 1030 u64 mc_rldram_test_add_bkg; 1031 u8 unused26_5[0x80 - 0x68]; 1032 u64 mc_rldram_test_d0_bkg; 1033 u8 unused26_6[0xD00 - 0xC88]; 1034 u64 mc_rldram_test_d1_bkg; 1035 u8 unused26_7[0x20 - 0x8]; 1036 u64 mc_rldram_test_d2_bkg; 1037 u8 unused26_8[0x40 - 0x28]; 1038 u64 mc_rldram_test_read_d0_bkg; 1039 u8 unused26_9[0x60 - 0x48]; 1040 u64 mc_rldram_test_read_d1_bkg; 1041 u8 unused26_10[0x80 - 0x68]; 1042 u64 mc_rldram_test_read_d2_bkg; 1043 u8 unused26_11[0xE00 - 0xD88]; 1044 u64 mc_rldram_generation; 1045 u8 unused26_12[0x20 - 0x8]; 1046 u64 mc_driver; 1047 u8 unused26_13[0x40 - 0x28]; 1048 u64 mc_rldram_ref_per_herc; 1049 #define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n) vBIT(n, 0, 16) 1050 u8 unused26_14[0x660 - 0x648]; 1051 u64 mc_rldram_mrs_herc; 1052 #define XGE_HAL_MC_RLDRAM_MRS(n) vBIT(n, 14, 17) 1053 u8 unused26_15[0x700 - 0x668]; 1054 u64 mc_debug_ctrl; 1055 1056 u8 unused27[0x3000 - 0x2f08]; 1057 1058 /* XGXG */ 1059 /* XGXS control registers */ 1060 1061 u64 xgxs_int_status; 1062 #define XGE_HAL_XGXS_INT_STATUS_TXGXS BIT(0) 1063 #define XGE_HAL_XGXS_INT_STATUS_RXGXS BIT(1) 1064 u64 xgxs_int_mask; 1065 #define XGE_HAL_XGXS_INT_MASK_TXGXS BIT(0) 1066 #define XGE_HAL_XGXS_INT_MASK_RXGXS BIT(1) 1067 1068 u64 xgxs_txgxs_err_reg; 1069 #define XGE_HAL_TXGXS_ECC_DB_ERR BIT(15) 1070 u64 xgxs_txgxs_err_mask; 1071 u64 xgxs_txgxs_err_alarm; 1072 1073 u64 xgxs_rxgxs_err_reg; 1074 u64 xgxs_rxgxs_err_mask; 1075 u64 xgxs_rxgxs_err_alarm; 1076 1077 u8 unused28[0x100 - 0x40]; 1078 1079 u64 spi_err_reg; 1080 u64 spi_err_mask; 1081 u64 spi_err_alarm; 1082 1083 u64 xgxs_cfg; 1084 u64 xgxs_status; 1085 1086 u64 xgxs_cfg_key; 1087 u64 xgxs_efifo_cfg; /* CHANGED */ 1088 u64 rxgxs_ber_0; /* CHANGED */ 1089 u64 rxgxs_ber_1; /* CHANGED */ 1090 1091 u64 spi_control; 1092 u64 spi_data; 1093 u64 spi_write_protect; 1094 1095 u8 unused29[0x80 - 0x48]; 1096 1097 u64 xgxs_cfg_1; 1098 } xge_hal_pci_bar0_t; 1099 1100 /* Using this strcture to calculate offsets */ 1101 typedef struct xge_hal_pci_config_le_t { 1102 u16 vendor_id; // 0x00 1103 u16 device_id; // 0x02 1104 1105 u16 command; // 0x04 1106 u16 status; // 0x06 1107 1108 u8 revision; // 0x08 1109 u8 pciClass[3]; // 0x09 1110 1111 u8 cache_line_size; // 0x0c 1112 u8 latency_timer; // 0x0d 1113 u8 header_type; // 0x0e 1114 u8 bist; // 0x0f 1115 1116 u32 base_addr0_lo; // 0x10 1117 u32 base_addr0_hi; // 0x14 1118 1119 u32 base_addr1_lo; // 0x18 1120 u32 base_addr1_hi; // 0x1C 1121 1122 u32 not_Implemented1; // 0x20 1123 u32 not_Implemented2; // 0x24 1124 1125 u32 cardbus_cis_pointer; // 0x28 1126 1127 u16 subsystem_vendor_id; // 0x2c 1128 u16 subsystem_id; // 0x2e 1129 1130 u32 rom_base; // 0x30 1131 u8 capabilities_pointer; // 0x34 1132 u8 rsvd_35[3]; // 0x35 1133 u32 rsvd_38; // 0x38 1134 1135 u8 interrupt_line; // 0x3c 1136 u8 interrupt_pin; // 0x3d 1137 u8 min_grant; // 0x3e 1138 u8 max_latency; // 0x3f 1139 1140 u8 msi_cap_id; // 0x40 1141 u8 msi_next_ptr; // 0x41 1142 u16 msi_control; // 0x42 1143 u32 msi_lower_address; // 0x44 1144 u32 msi_higher_address; // 0x48 1145 u16 msi_data; // 0x4c 1146 u16 msi_unused; // 0x4e 1147 1148 u8 vpd_cap_id; // 0x50 1149 u8 vpd_next_cap; // 0x51 1150 u16 vpd_addr; // 0x52 1151 u32 vpd_data; // 0x54 1152 1153 u8 rsvd_b0[8]; // 0x58 1154 1155 u8 pcix_cap; // 0x60 1156 u8 pcix_next_cap; // 0x61 1157 u16 pcix_command; // 0x62 1158 1159 u32 pcix_status; // 0x64 1160 1161 u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1162 } xge_hal_pci_config_le_t; // 0x100 1163 1164 typedef struct xge_hal_pci_config_t { 1165 #ifdef XGE_OS_HOST_BIG_ENDIAN 1166 u16 device_id; // 0x02 1167 u16 vendor_id; // 0x00 1168 1169 u16 status; // 0x06 1170 u16 command; // 0x04 1171 1172 u8 pciClass[3]; // 0x09 1173 u8 revision; // 0x08 1174 1175 u8 bist; // 0x0f 1176 u8 header_type; // 0x0e 1177 u8 latency_timer; // 0x0d 1178 u8 cache_line_size; // 0x0c 1179 1180 u32 base_addr0_lo; // 0x10 1181 u32 base_addr0_hi; // 0x14 1182 1183 u32 base_addr1_lo; // 0x18 1184 u32 base_addr1_hi; // 0x1C 1185 1186 u32 not_Implemented1; // 0x20 1187 u32 not_Implemented2; // 0x24 1188 1189 u32 cardbus_cis_pointer; // 0x28 1190 1191 u16 subsystem_id; // 0x2e 1192 u16 subsystem_vendor_id; // 0x2c 1193 1194 u32 rom_base; // 0x30 1195 u8 rsvd_35[3]; // 0x35 1196 u8 capabilities_pointer; // 0x34 1197 u32 rsvd_38; // 0x38 1198 1199 u8 max_latency; // 0x3f 1200 u8 min_grant; // 0x3e 1201 u8 interrupt_pin; // 0x3d 1202 u8 interrupt_line; // 0x3c 1203 1204 u16 msi_control; // 0x42 1205 u8 msi_next_ptr; // 0x41 1206 u8 msi_cap_id; // 0x40 1207 u32 msi_lower_address; // 0x44 1208 u32 msi_higher_address; // 0x48 1209 u16 msi_unused; // 0x4e 1210 u16 msi_data; // 0x4c 1211 1212 u16 vpd_addr; // 0x52 1213 u8 vpd_next_cap; // 0x51 1214 u8 vpd_cap_id; // 0x50 1215 u32 vpd_data; // 0x54 1216 1217 u8 rsvd_b0[8]; // 0x58 1218 1219 u16 pcix_command; // 0x62 1220 u8 pcix_next_cap; // 0x61 1221 u8 pcix_cap; // 0x60 1222 1223 u32 pcix_status; // 0x64 1224 #else 1225 u16 vendor_id; // 0x00 1226 u16 device_id; // 0x02 1227 1228 u16 command; // 0x04 1229 u16 status; // 0x06 1230 1231 u8 revision; // 0x08 1232 u8 pciClass[3]; // 0x09 1233 1234 u8 cache_line_size; // 0x0c 1235 u8 latency_timer; // 0x0d 1236 u8 header_type; // 0x0e 1237 u8 bist; // 0x0f 1238 1239 u32 base_addr0_lo; // 0x10 1240 u32 base_addr0_hi; // 0x14 1241 1242 u32 base_addr1_lo; // 0x18 1243 u32 base_addr1_hi; // 0x1C 1244 1245 u32 not_Implemented1; // 0x20 1246 u32 not_Implemented2; // 0x24 1247 1248 u32 cardbus_cis_pointer; // 0x28 1249 1250 u16 subsystem_vendor_id; // 0x2c 1251 u16 subsystem_id; // 0x2e 1252 1253 u32 rom_base; // 0x30 1254 u8 capabilities_pointer; // 0x34 1255 u8 rsvd_35[3]; // 0x35 1256 u32 rsvd_38; // 0x38 1257 1258 u8 interrupt_line; // 0x3c 1259 u8 interrupt_pin; // 0x3d 1260 u8 min_grant; // 0x3e 1261 u8 max_latency; // 0x3f 1262 1263 u8 msi_cap_id; // 0x40 1264 u8 msi_next_ptr; // 0x41 1265 u16 msi_control; // 0x42 1266 u32 msi_lower_address; // 0x44 1267 u32 msi_higher_address; // 0x48 1268 u16 msi_data; // 0x4c 1269 u16 msi_unused; // 0x4e 1270 1271 u8 vpd_cap_id; // 0x50 1272 u8 vpd_next_cap; // 0x51 1273 u16 vpd_addr; // 0x52 1274 u32 vpd_data; // 0x54 1275 1276 u8 rsvd_b0[8]; // 0x58 1277 1278 u8 pcix_cap; // 0x60 1279 u8 pcix_next_cap; // 0x61 1280 u16 pcix_command; // 0x62 1281 1282 u32 pcix_status; // 0x64 1283 1284 #endif 1285 u8 rsvd_b1[XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE-0x68]; 1286 } xge_hal_pci_config_t; // 0x100 1287 1288 #define XGE_HAL_REG_SPACE sizeof(xge_hal_pci_bar0_t) 1289 #define XGE_HAL_EEPROM_SIZE (0x01 << 11) 1290 1291 #endif /* XGE_HAL_REGS_H */ 1292