1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2002-2005 Neterion, Inc. 24 * All right Reserved. 25 * 26 * FileName : xgehal-mgmt.h 27 * 28 * Description: management API 29 * 30 * Created: 1 September 2004 31 */ 32 33 #ifndef XGE_HAL_MGMT_H 34 #define XGE_HAL_MGMT_H 35 36 #include "xge-os-pal.h" 37 #include "xge-debug.h" 38 #include "xgehal-types.h" 39 #include "xgehal-config.h" 40 #include "xgehal-stats.h" 41 #include "xgehal-regs.h" 42 43 /** 44 * struct xge_hal_mgmt_about_info_t - About info. 45 * @vendor: PCI Vendor ID. 46 * @device: PCI Device ID. 47 * @subsys_vendor: PCI Subsystem Vendor ID. 48 * @subsys_device: PCI Subsystem Device ID. 49 * @board_rev: PCI Board revision, e.g. 3 - for Xena 3. 50 * @vendor_name: Neterion, Inc. 51 * @chip_name: Xframe. 52 * @media: Fiber, copper. 53 * @hal_major: HAL major version number. 54 * @hal_minor: HAL minor version number. 55 * @hal_fix: HAL fix number. 56 * @hal_build: HAL build number. 57 * @ll_major: Link-layer ULD major version number. 58 * @ll_minor: Link-layer ULD minor version number. 59 * @ll_fix: Link-layer ULD fix version number. 60 * @ll_build: Link-layer ULD build number. 61 */ 62 typedef struct xge_hal_mgmt_about_info_t { 63 u16 vendor; 64 u16 device; 65 u16 subsys_vendor; 66 u16 subsys_device; 67 u8 board_rev; 68 char vendor_name[16]; 69 char chip_name[16]; 70 char media[16]; 71 char hal_major[4]; 72 char hal_minor[4]; 73 char hal_fix[4]; 74 char hal_build[16]; 75 char ll_major[4]; 76 char ll_minor[4]; 77 char ll_fix[4]; 78 char ll_build[16]; 79 } xge_hal_mgmt_about_info_t; 80 81 typedef xge_hal_stats_hw_info_t xge_hal_mgmt_hw_stats_t; 82 typedef xge_hal_stats_sw_err_t xge_hal_mgmt_sw_stats_t; 83 typedef xge_hal_stats_device_info_t xge_hal_mgmt_device_stats_t; 84 typedef xge_hal_stats_channel_info_t xge_hal_mgmt_channel_stats_t; 85 typedef xge_hal_device_config_t xge_hal_mgmt_device_config_t; 86 typedef xge_hal_driver_config_t xge_hal_mgmt_driver_config_t; 87 typedef xge_hal_pci_config_t xge_hal_mgmt_pci_config_t; 88 89 xge_hal_status_e 90 xge_hal_mgmt_about(xge_hal_device_h devh, xge_hal_mgmt_about_info_t *about_info, 91 int size); 92 93 xge_hal_status_e 94 xge_hal_mgmt_hw_stats(xge_hal_device_h devh, xge_hal_mgmt_hw_stats_t *hw_stats, 95 int size); 96 97 xge_hal_status_e 98 xge_hal_mgmt_hw_stats_off(xge_hal_device_h devh, int off, int size, char *out); 99 100 xge_hal_status_e 101 xge_hal_mgmt_sw_stats(xge_hal_device_h devh, xge_hal_mgmt_sw_stats_t *hw_stats, 102 int size); 103 104 xge_hal_status_e 105 xge_hal_mgmt_device_stats(xge_hal_device_h devh, 106 xge_hal_mgmt_device_stats_t *device_stats, int size); 107 108 xge_hal_status_e 109 xge_hal_mgmt_channel_stats(xge_hal_channel_h channelh, 110 xge_hal_mgmt_channel_stats_t *channel_stats, int size); 111 112 xge_hal_status_e 113 xge_hal_mgmt_reg_read(xge_hal_device_h devh, int bar_id, unsigned int offset, 114 u64 *value); 115 116 xge_hal_status_e 117 xge_hal_mgmt_reg_write(xge_hal_device_h devh, int bar_id, unsigned int offset, 118 u64 value); 119 120 xge_hal_status_e 121 xge_hal_mgmt_pcireg_read(xge_hal_device_h devh, unsigned int offset, 122 int bits, u32 *value); 123 124 xge_hal_status_e 125 xge_hal_mgmt_device_config(xge_hal_device_h devh, 126 xge_hal_mgmt_device_config_t *dev_config, int size); 127 128 xge_hal_status_e 129 xge_hal_mgmt_driver_config(xge_hal_mgmt_driver_config_t *drv_config, 130 int size); 131 132 xge_hal_status_e 133 xge_hal_mgmt_pci_config(xge_hal_device_h devh, 134 xge_hal_mgmt_pci_config_t *pci_config, int size); 135 136 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR 137 xge_hal_status_e 138 xge_hal_mgmt_trace_read(char *buffer, unsigned buf_size, unsigned *offset, 139 unsigned *read_length); 140 #endif 141 142 void 143 xge_hal_restore_link_led(xge_hal_device_h devh); 144 145 146 void 147 xge_hal_flick_link_led(xge_hal_device_h devh); 148 149 /* 150 * Some set of Xena3 Cards were known to have some link LED 151 * Problems. This macro identifies if the card is among them 152 * given its Sub system ID. 153 */ 154 #define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \ 155 ((((subid >= 0x600B) && (subid <= 0x600D)) || \ 156 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) 157 158 #ifdef XGE_HAL_USE_MGMT_AUX 159 #include "xgehal-mgmtaux.h" 160 #endif 161 162 #endif /* XGE_HAL_MGMT_H */ 163