1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #ifndef XGE_HAL_MGMT_H 25 #define XGE_HAL_MGMT_H 26 27 #include "xge-os-pal.h" 28 #include "xge-debug.h" 29 #include "xgehal-types.h" 30 #include "xgehal-config.h" 31 #include "xgehal-stats.h" 32 #include "xgehal-regs.h" 33 #include "xgehal-device.h" 34 35 __EXTERN_BEGIN_DECLS 36 37 /** 38 * struct xge_hal_mgmt_about_info_t - About info. 39 * @vendor: PCI Vendor ID. 40 * @device: PCI Device ID. 41 * @subsys_vendor: PCI Subsystem Vendor ID. 42 * @subsys_device: PCI Subsystem Device ID. 43 * @board_rev: PCI Board revision, e.g. 3 - for Xena 3. 44 * @vendor_name: Neterion, Inc. 45 * @chip_name: Xframe. 46 * @media: Fiber, copper. 47 * @hal_major: HAL major version number. 48 * @hal_minor: HAL minor version number. 49 * @hal_fix: HAL fix number. 50 * @hal_build: HAL build number. 51 * @ll_major: Link-layer ULD major version number. 52 * @ll_minor: Link-layer ULD minor version number. 53 * @ll_fix: Link-layer ULD fix version number. 54 * @ll_build: Link-layer ULD build number. 55 */ 56 typedef struct xge_hal_mgmt_about_info_t { 57 u16 vendor; 58 u16 device; 59 u16 subsys_vendor; 60 u16 subsys_device; 61 u8 board_rev; 62 char vendor_name[16]; 63 char chip_name[16]; 64 char media[16]; 65 char hal_major[4]; 66 char hal_minor[4]; 67 char hal_fix[4]; 68 char hal_build[16]; 69 char ll_major[4]; 70 char ll_minor[4]; 71 char ll_fix[4]; 72 char ll_build[16]; 73 u32 transponder_temperature; 74 } xge_hal_mgmt_about_info_t; 75 76 typedef xge_hal_stats_hw_info_t xge_hal_mgmt_hw_stats_t; 77 typedef xge_hal_stats_sw_err_t xge_hal_mgmt_sw_stats_t; 78 typedef xge_hal_stats_device_info_t xge_hal_mgmt_device_stats_t; 79 typedef xge_hal_stats_channel_info_t xge_hal_mgmt_channel_stats_t; 80 typedef xge_hal_device_config_t xge_hal_mgmt_device_config_t; 81 typedef xge_hal_driver_config_t xge_hal_mgmt_driver_config_t; 82 typedef xge_hal_pci_config_t xge_hal_mgmt_pci_config_t; 83 84 xge_hal_status_e 85 xge_hal_mgmt_about(xge_hal_device_h devh, xge_hal_mgmt_about_info_t *about_info, 86 int size); 87 88 xge_hal_status_e 89 xge_hal_mgmt_hw_stats(xge_hal_device_h devh, xge_hal_mgmt_hw_stats_t *hw_stats, 90 int size); 91 92 xge_hal_status_e 93 xge_hal_mgmt_hw_stats_off(xge_hal_device_h devh, int off, int size, char *out); 94 95 xge_hal_status_e 96 xge_hal_mgmt_sw_stats(xge_hal_device_h devh, xge_hal_mgmt_sw_stats_t *hw_stats, 97 int size); 98 99 xge_hal_status_e 100 xge_hal_mgmt_device_stats(xge_hal_device_h devh, 101 xge_hal_mgmt_device_stats_t *device_stats, int size); 102 103 xge_hal_status_e 104 xge_hal_mgmt_channel_stats(xge_hal_channel_h channelh, 105 xge_hal_mgmt_channel_stats_t *channel_stats, int size); 106 107 xge_hal_status_e 108 xge_hal_mgmt_reg_read(xge_hal_device_h devh, int bar_id, unsigned int offset, 109 u64 *value); 110 111 xge_hal_status_e 112 xge_hal_mgmt_reg_write(xge_hal_device_h devh, int bar_id, unsigned int offset, 113 u64 value); 114 115 xge_hal_status_e 116 xge_hal_mgmt_pcireg_read(xge_hal_device_h devh, unsigned int offset, 117 int bits, u32 *value); 118 119 xge_hal_status_e 120 xge_hal_mgmt_device_config(xge_hal_device_h devh, 121 xge_hal_mgmt_device_config_t *dev_config, int size); 122 123 xge_hal_status_e 124 xge_hal_mgmt_driver_config(xge_hal_mgmt_driver_config_t *drv_config, 125 int size); 126 127 xge_hal_status_e 128 xge_hal_mgmt_pci_config(xge_hal_device_h devh, 129 xge_hal_mgmt_pci_config_t *pci_config, int size); 130 131 xge_hal_status_e 132 xge_hal_pma_loopback( xge_hal_device_h devh, int enable ); 133 134 xge_hal_status_e 135 xge_hal_rldram_test(xge_hal_device_h devh, u64 * data); 136 137 u16 138 xge_hal_mdio_read( xge_hal_device_h devh, u32 mmd_type, u64 addr ); 139 140 xge_hal_status_e 141 xge_hal_mdio_write( xge_hal_device_h devh, u32 mmd_type, u64 addr, u32 value ); 142 143 u32 144 xge_hal_read_xfp_current_temp(xge_hal_device_h devh); 145 146 void 147 __hal_updt_stats_xpak(xge_hal_device_t *hldev); 148 149 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR 150 xge_hal_status_e 151 xge_hal_mgmt_trace_read(char *buffer, unsigned buf_size, unsigned *offset, 152 unsigned *read_length); 153 #endif 154 155 void 156 xge_hal_restore_link_led(xge_hal_device_h devh); 157 158 159 void 160 xge_hal_flick_link_led(xge_hal_device_h devh); 161 162 /* 163 * Some set of Xena3 Cards were known to have some link LED 164 * Problems. This macro identifies if the card is among them 165 * given its Sub system ID. 166 */ 167 #define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \ 168 ((((subid >= 0x600B) && (subid <= 0x600D)) || \ 169 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) 170 #define CHECKBIT(value, nbit) (value & (1 << nbit)) 171 172 #ifdef XGE_HAL_USE_MGMT_AUX 173 #include "xgehal-mgmtaux.h" 174 #endif 175 176 __EXTERN_END_DECLS 177 178 #endif /* XGE_HAL_MGMT_H */ 179