1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2002-2005 Neterion, Inc. 24 * All right Reserved. 25 * 26 * FileName : xgehal-fifo.h 27 * 28 * Description: Tx fifo object functionality 29 * 30 * Created: 19 May 2004 31 */ 32 33 #ifndef XGE_HAL_FIFO_H 34 #define XGE_HAL_FIFO_H 35 36 #include "xgehal-channel.h" 37 #include "xgehal-config.h" 38 #include "xgehal-mm.h" 39 40 /* HW fifo configuration */ 41 #define XGE_HAL_FIFO_INT_PER_LIST_THRESHOLD 65 42 #define XGE_HAL_FIFO_MAX_WRR 5 43 #define XGE_HAL_FIFO_MAX_PARTITION 4 44 #define XGE_HAL_FIFO_MAX_WRR_STATE 36 45 #define XGE_HAL_FIFO_HW_PAIR_OFFSET 0x20000 46 47 /* 48 * xge_hal_fifo_hw_pair_t 49 * 50 * Represent a single fifo in the BAR1 memory space. 51 */ 52 typedef struct { 53 u64 txdl_pointer; /* offset 0x0 */ 54 55 u64 reserved[2]; 56 57 u64 list_control; /* offset 0x18 */ 58 #define XGE_HAL_TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8) 59 #define XGE_HAL_TX_FIFO_FIRST_LIST BIT(14) 60 #define XGE_HAL_TX_FIFO_LAST_LIST BIT(15) 61 #define XGE_HAL_TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2) 62 #define XGE_HAL_TX_FIFO_SPECIAL_FUNC BIT(23) 63 #define XGE_HAL_TX_FIFO_NO_SNOOP(n) vBIT(n,30,2) 64 } xge_hal_fifo_hw_pair_t; 65 66 67 /* Bad TxDL transfer codes */ 68 #define XGE_HAL_TXD_T_CODE_OK 0x0 69 #define XGE_HAL_TXD_T_CODE_UNUSED_1 0x1 70 #define XGE_HAL_TXD_T_CODE_ABORT_BUFFER 0x2 71 #define XGE_HAL_TXD_T_CODE_ABORT_DTOR 0x3 72 #define XGE_HAL_TXD_T_CODE_UNUSED_5 0x5 73 #define XGE_HAL_TXD_T_CODE_PARITY 0x7 74 #define XGE_HAL_TXD_T_CODE_LOSS_OF_LINK 0xA 75 #define XGE_HAL_TXD_T_CODE_GENERAL_ERR 0xF 76 77 78 /** 79 * struct xge_hal_fifo_txd_t - TxD. 80 * @control_1: Control_1. 81 * @control_2: Control_2. 82 * @buffer_pointer: Buffer_Address. 83 * @host_control: Host_Control.Opaque 64bit data stored by ULD inside the Xframe 84 * descriptor prior to posting the latter on the channel 85 * via xge_hal_fifo_dtr_post() or xge_hal_ring_dtr_post(). 86 * The %host_control is returned as is to the ULD with each 87 * completed descriptor. 88 * 89 * Transmit descriptor (TxD).Fifo descriptor contains configured number 90 * (list) of TxDs. * For more details please refer to Xframe User Guide, 91 * Section 5.4.2 "Transmit Descriptor (TxD) Format". 92 */ 93 typedef struct xge_hal_fifo_txd_t { 94 u64 control_1; 95 #define XGE_HAL_TXD_LIST_OWN_XENA BIT(7) 96 #define XGE_HAL_TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 97 #define XGE_HAL_GET_TXD_T_CODE(val) ((val & XGE_HAL_TXD_T_CODE)>>48) 98 #define XGE_HAL_SET_TXD_T_CODE(x, val) (x |= (((u64)val & 0xF) << 48)) 99 #define XGE_HAL_TXD_GATHER_CODE (BIT(22) | BIT(23)) 100 #define XGE_HAL_TXD_GATHER_CODE_FIRST BIT(22) 101 #define XGE_HAL_TXD_GATHER_CODE_LAST BIT(23) 102 #define XGE_HAL_TXD_NO_LSO 0 103 #define XGE_HAL_TXD_UDF_COF 1 104 #define XGE_HAL_TXD_TCP_LSO 2 105 #define XGE_HAL_TXD_UDP_LSO 3 106 #define XGE_HAL_TXD_LSO_COF_CTRL(val) vBIT(val,30,2) 107 #define XGE_HAL_TXD_TCP_LSO_MSS(val) vBIT(val,34,14) 108 #define XGE_HAL_TXD_BUFFER0_SIZE(val) vBIT(val,48,16) 109 110 u64 control_2; 111 #define XGE_HAL_TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7)) 112 #define XGE_HAL_TXD_TX_CKO_IPV4_EN BIT(5) 113 #define XGE_HAL_TXD_TX_CKO_TCP_EN BIT(6) 114 #define XGE_HAL_TXD_TX_CKO_UDP_EN BIT(7) 115 #define XGE_HAL_TXD_VLAN_ENABLE BIT(15) 116 #define XGE_HAL_TXD_VLAN_TAG(val) vBIT(val,16,16) 117 #define XGE_HAL_TXD_INT_NUMBER(val) vBIT(val,34,6) 118 #define XGE_HAL_TXD_INT_TYPE_PER_LIST BIT(47) 119 #define XGE_HAL_TXD_INT_TYPE_UTILZ BIT(46) 120 #define XGE_HAL_TXD_SET_MARKER vBIT(0x6,0,4) 121 122 u64 buffer_pointer; 123 124 u64 host_control; 125 126 } xge_hal_fifo_txd_t; 127 128 typedef xge_hal_fifo_txd_t* xge_hal_fifo_txdl_t; 129 130 /** 131 * struct xge_hal_fifo_t - Fifo channel. 132 * @channel: Channel "base" of this fifo, the common part of all HAL 133 * channels. 134 * @post_lock_ptr: Points to a lock that serializes (pointer, control) PIOs. 135 * Note that for Xena the serialization is done across all device 136 * fifos. 137 * @hw_pair: Per-fifo (Pointer, Control) pair used to send descriptors to the 138 * Xframe hardware (for details see Xframe user guide). 139 * @config: Fifo configuration, part of device configuration 140 * (see xge_hal_device_config_t{}). 141 * @no_snoop_bits: See xge_hal_fifo_config_t{}. 142 * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock. 143 * on TxDL please refer to Xframe UG. 144 * @interrupt_type: FIXME: to-be-defined. 145 * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus 146 * per-TxDL HAL private space (xge_hal_fifo_txdl_priv_t). 147 * @priv_size: Per-Tx descriptor space reserved for upper-layer driver 148 * usage. 149 * @mempool: Memory pool, from which descriptors get allocated. 150 * 151 * Fifo channel. 152 * Note: The structure is cache line aligned. 153 */ 154 typedef struct xge_hal_fifo_t { 155 xge_hal_channel_t channel; 156 spinlock_t *post_lock_ptr; 157 xge_hal_fifo_hw_pair_t *hw_pair; 158 xge_hal_fifo_config_t *config; 159 int no_snoop_bits; 160 int txdl_per_memblock; 161 u64 interrupt_type; 162 int txdl_size; 163 int priv_size; 164 xge_hal_mempool_t *mempool; 165 } __xge_os_attr_cacheline_aligned xge_hal_fifo_t; 166 167 /** 168 * struct xge_hal_fifo_txdl_priv_t - Transmit descriptor HAL-private 169 * data. 170 * @dma_addr: DMA (mapped) address of _this_ descriptor. 171 * @dma_handle: DMA handle used to map the descriptor onto device. 172 * @dma_offset: Descriptor's offset in the memory block. HAL allocates 173 * descriptors in memory blocks (see 174 * xge_hal_fifo_config_t{}) 175 * Each memblock is a contiguous block of DMA-able memory. 176 * @frags: Total number of fragments (that is, contiguous data buffers) 177 * carried by this TxDL. 178 * @align_vaddr_start: (TODO). 179 * @align_vaddr: Virtual address of the per-TxDL area in memory used for 180 * alignement. Used to place one or more mis-aligned fragments 181 * (the maximum defined by configration variable 182 * @max_aligned_frags). 183 * @align_dma_addr: DMA address translated from the @align_vaddr. 184 * @align_dma_handle: DMA handle that corresponds to @align_dma_addr. 185 * @align_dma_acch: DMA access handle corresponds to @align_dma_addr. 186 * @align_dma_offset: The current offset into the @align_vaddr area. 187 * Grows while filling the descriptor, gets reset. 188 * @align_used_frags: (TODO). 189 * @alloc_frags: Total number of fragments allocated. 190 * @dang_frags: Number of fragments kept from release until this TxDL is freed. 191 * @dang_txdl: (TODO). 192 * @next_txdl_priv: (TODO). 193 * @first_txdp: (TODO). 194 * @dang_dtrh: Pointer to TxDL (list) kept from release until this TxDL 195 * is freed. 196 * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous 197 * TxDL list. 198 * @dtrh: Corresponding dtrh to this TxDL. 199 * @memblock: Pointer to the TxDL memory block or memory page. 200 * on the next send operation. 201 * @dma_object: DMA address and handle of the memory block that contains 202 * the descriptor. This member is used only in the "checked" 203 * version of the HAL (to enforce certain assertions); 204 * otherwise it gets compiled out. 205 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 206 * 207 * Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA 208 * information associated with the descriptor. Note that ULD can ask HAL 209 * to allocate additional per-descriptor space for its own (ULD-specific) 210 * purposes. 211 * 212 * See also: xge_hal_ring_rxd_priv_t{}. 213 */ 214 typedef struct xge_hal_fifo_txdl_priv_t { 215 dma_addr_t dma_addr; 216 pci_dma_h dma_handle; 217 ptrdiff_t dma_offset; 218 int frags; 219 char *align_vaddr_start; 220 char *align_vaddr; 221 dma_addr_t align_dma_addr; 222 pci_dma_h align_dma_handle; 223 pci_dma_acc_h align_dma_acch; 224 ptrdiff_t align_dma_offset; 225 int align_used_frags; 226 int alloc_frags; 227 int dang_frags; 228 xge_hal_fifo_txd_t *dang_txdl; 229 struct xge_hal_fifo_txdl_priv_t *next_txdl_priv; 230 xge_hal_fifo_txd_t *first_txdp; 231 void *memblock; 232 #ifdef XGE_DEBUG_ASSERT 233 xge_hal_mempool_dma_t *dma_object; 234 #endif 235 #ifdef XGE_OS_MEMORY_CHECK 236 int allocated; 237 #endif 238 } xge_hal_fifo_txdl_priv_t; 239 240 /** 241 * xge_hal_fifo_get_max_frags_cnt - Return the max fragments allocated 242 * for the fifo. 243 * @channelh: Channel handle. 244 */ 245 static inline int 246 xge_hal_fifo_get_max_frags_cnt(xge_hal_channel_h channelh) 247 { 248 return ((xge_hal_fifo_t *)channelh)->config->max_frags; 249 } 250 /* ========================= FIFO PRIVATE API ============================= */ 251 252 xge_hal_status_e __hal_fifo_open(xge_hal_channel_h channelh, 253 xge_hal_channel_attr_t *attr); 254 255 void __hal_fifo_close(xge_hal_channel_h channelh); 256 257 void __hal_fifo_hw_initialize(xge_hal_device_h hldev); 258 259 xge_hal_status_e 260 __hal_fifo_dtr_align_alloc_map(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 261 262 void 263 __hal_fifo_dtr_align_free_unmap(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 264 265 #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_FIFO) 266 #define __HAL_STATIC_FIFO 267 #define __HAL_INLINE_FIFO 268 269 __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_fifo_txdl_priv_t* 270 __hal_fifo_txdl_priv(xge_hal_dtr_h dtrh); 271 272 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void 273 __hal_fifo_dtr_post_single(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 274 u64 ctrl_1); 275 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void 276 __hal_fifo_txdl_restore_many(xge_hal_channel_h channelh, 277 xge_hal_fifo_txd_t *txdp, int txdl_count); 278 279 /* ========================= FIFO PUBLIC API ============================== */ 280 281 __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 282 xge_hal_fifo_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh); 283 284 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void* 285 xge_hal_fifo_dtr_private(xge_hal_dtr_h dtrh); 286 287 __HAL_STATIC_FIFO __HAL_INLINE_FIFO int 288 xge_hal_fifo_dtr_buffer_cnt(xge_hal_dtr_h dtrh); 289 290 __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 291 xge_hal_fifo_dtr_reserve_sp(xge_hal_channel_h channel, int dtr_sp_size, 292 xge_hal_dtr_h dtr_sp); 293 294 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void 295 xge_hal_fifo_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 296 297 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void 298 xge_hal_fifo_dtr_post_many(xge_hal_channel_h channelh, int num, 299 xge_hal_dtr_h dtrs[]); 300 301 __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 302 xge_hal_fifo_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, 303 u8 *t_code); 304 305 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void 306 xge_hal_fifo_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtr); 307 308 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void 309 xge_hal_fifo_dtr_buffer_set(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 310 int frag_idx, dma_addr_t dma_pointer, int size); 311 312 __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 313 xge_hal_fifo_dtr_buffer_set_aligned(xge_hal_channel_h channelh, 314 xge_hal_dtr_h dtrh, int frag_idx, void *vaddr, 315 dma_addr_t dma_pointer, int size, int misaligned_size); 316 317 __HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 318 xge_hal_fifo_dtr_buffer_append(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 319 void *vaddr, int size); 320 321 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void 322 xge_hal_fifo_dtr_buffer_finalize(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 323 int frag_idx); 324 325 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void 326 xge_hal_fifo_dtr_mss_set(xge_hal_dtr_h dtrh, int mss); 327 328 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void 329 xge_hal_fifo_dtr_cksum_set_bits(xge_hal_dtr_h dtrh, u64 cksum_bits); 330 331 __HAL_STATIC_FIFO __HAL_INLINE_FIFO void 332 xge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h dtrh, u16 vlan_tag); 333 334 #else /* XGE_FASTPATH_EXTERN */ 335 #define __HAL_STATIC_FIFO static 336 #define __HAL_INLINE_FIFO inline 337 #include "xgehal-fifo-fp.c" 338 #endif /* XGE_FASTPATH_INLINE */ 339 340 #endif /* XGE_HAL_FIFO_H */ 341