1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #ifndef XGE_HAL_DEVICE_H 25 #define XGE_HAL_DEVICE_H 26 27 #include "xge-os-pal.h" 28 #include "xge-queue.h" 29 #include "xgehal-event.h" 30 #include "xgehal-config.h" 31 #include "xgehal-regs.h" 32 #include "xgehal-channel.h" 33 #include "xgehal-stats.h" 34 #include "xgehal-ring.h" 35 #ifdef XGEHAL_RNIC 36 #include "xgehal-lbwrapper.h" 37 #include "xgehal-blockpool.h" 38 #endif 39 40 __EXTERN_BEGIN_DECLS 41 42 #define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500 43 #define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500 44 #define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500 45 #define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50 46 #define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250 47 #define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */ 48 #define XGE_HAL_MAX_MSIX_MESSAGES 64 49 50 #define XGE_HAL_MAGIC 0x12345678 51 #define XGE_HAL_DEAD 0xDEADDEAD 52 #define XGE_HAL_DUMP_BUF_SIZE 0x4000 53 54 #define XGE_HAL_LRO_MAX_BUCKETS 32 55 56 /** 57 * enum xge_hal_card_e - Xframe adapter type. 58 * @XGE_HAL_CARD_UNKNOWN: Unknown device. 59 * @XGE_HAL_CARD_XENA: Xframe I device. 60 * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device. 61 * 62 * Enumerates Xframe adapter types. The corresponding PCI device 63 * IDs are listed in the file xgehal-defs.h. 64 * (See XGE_PCI_DEVICE_ID_XENA_1, etc.) 65 * 66 * See also: xge_hal_device_check_id(). 67 */ 68 typedef enum xge_hal_card_e { 69 XGE_HAL_CARD_UNKNOWN = 0, 70 XGE_HAL_CARD_XENA = 1, 71 XGE_HAL_CARD_HERC = 2, 72 } xge_hal_card_e; 73 74 /** 75 * struct xge_hal_device_attr_t - Device memory spaces. 76 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 77 * (Linux and the rest.) 78 * @regh1: BAR1 mapped memory handle. Same comment as above. 79 * @regh2: BAR2 mapped memory handle. Same comment as above. 80 * @bar0: BAR0 virtual address. 81 * @bar1: BAR1 virtual address. 82 * @bar2: BAR2 virtual address. 83 * @irqh: IRQ handle (Solaris). 84 * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux). 85 * @pdev: PCI device object. 86 * 87 * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device 88 * mapped memories. Also, includes a pointer to OS-specific PCI device object. 89 */ 90 typedef struct xge_hal_device_attr_t { 91 pci_reg_h regh0; 92 pci_reg_h regh1; 93 pci_reg_h regh2; 94 char *bar0; 95 char *bar1; 96 char *bar2; 97 pci_irq_h irqh; 98 pci_cfg_h cfgh; 99 pci_dev_h pdev; 100 } xge_hal_device_attr_t; 101 102 /** 103 * enum xge_hal_device_link_state_e - Link state enumeration. 104 * @XGE_HAL_LINK_NONE: Invalid link state. 105 * @XGE_HAL_LINK_DOWN: Link is down. 106 * @XGE_HAL_LINK_UP: Link is up. 107 * 108 */ 109 typedef enum xge_hal_device_link_state_e { 110 XGE_HAL_LINK_NONE, 111 XGE_HAL_LINK_DOWN, 112 XGE_HAL_LINK_UP 113 } xge_hal_device_link_state_e; 114 115 116 /** 117 * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration. 118 * @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode. 119 * @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode. 120 * @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode. 121 * @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode. 122 * @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode. 123 * @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode. 124 * @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode. 125 * @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode. 126 * @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode. 127 * @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported. 128 * @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported. 129 * @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported. 130 * @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved. 131 * @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved. 132 * @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value. 133 * @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value. 134 * @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode. 135 * 136 */ 137 typedef enum xge_hal_pci_mode_e { 138 XGE_HAL_PCI_33MHZ_MODE = 0x0, 139 XGE_HAL_PCI_66MHZ_MODE = 0x1, 140 XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2, 141 XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3, 142 XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4, 143 XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5, 144 XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6, 145 XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7, 146 XGE_HAL_PCIX_M1_RESERVED = 0x8, 147 XGE_HAL_PCIX_M1_66MHZ_NS = 0xA, 148 XGE_HAL_PCIX_M1_100MHZ_NS = 0xB, 149 XGE_HAL_PCIX_M1_133MHZ_NS = 0xC, 150 XGE_HAL_PCIX_M2_RESERVED = 0xD, 151 XGE_HAL_PCIX_533_RESERVED = 0xE, 152 XGE_HAL_PCI_BASIC_MODE = 0x10, 153 XGE_HAL_PCIX_BASIC_MODE = 0x11, 154 XGE_HAL_PCI_INVALID_MODE = 0x12, 155 } xge_hal_pci_mode_e; 156 157 /** 158 * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration. 159 * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ 160 * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ 161 * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ 162 * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ 163 * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ 164 * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ 165 * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value. 166 * 167 */ 168 typedef enum xge_hal_pci_bus_frequency_e { 169 XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33, 170 XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66, 171 XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100, 172 XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133, 173 XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200, 174 XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266, 175 XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0 176 } xge_hal_pci_bus_frequency_e; 177 178 /** 179 * enum xge_hal_pci_bus_width_e - PCI bus width enumeration. 180 * @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width. 181 * @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width. 182 * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN: unknown bus width. 183 * 184 */ 185 typedef enum xge_hal_pci_bus_width_e { 186 XGE_HAL_PCI_BUS_WIDTH_64BIT = 0, 187 XGE_HAL_PCI_BUS_WIDTH_32BIT = 1, 188 XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2, 189 } xge_hal_pci_bus_width_e; 190 191 #if defined (XGE_HAL_CONFIG_LRO) 192 193 #define IP_TOTAL_LENGTH_OFFSET 2 194 #define IP_FAST_PATH_HDR_MASK 0x45 195 #define TCP_FAST_PATH_HDR_MASK1 0x50 196 #define TCP_FAST_PATH_HDR_MASK2 0x10 197 #define TCP_FAST_PATH_HDR_MASK3 0x18 198 #define IP_SOURCE_ADDRESS_OFFSET 12 199 #define IP_DESTINATION_ADDRESS_OFFSET 16 200 #define TCP_DESTINATION_PORT_OFFSET 2 201 #define TCP_SOURCE_PORT_OFFSET 0 202 #define TCP_DATA_OFFSET_OFFSET 12 203 #define TCP_WINDOW_OFFSET 14 204 #define TCP_SEQUENCE_NUMBER_OFFSET 4 205 #define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8 206 207 typedef struct tcplro { 208 u16 source; 209 u16 dest; 210 u32 seq; 211 u32 ack_seq; 212 u8 doff_res; 213 u8 ctrl; 214 u16 window; 215 u16 check; 216 u16 urg_ptr; 217 } tcplro_t; 218 219 typedef struct iplro { 220 u8 version_ihl; 221 u8 tos; 222 u16 tot_len; 223 u16 id; 224 u16 frag_off; 225 u8 ttl; 226 u8 protocol; 227 u16 check; 228 u32 saddr; 229 u32 daddr; 230 /*The options start here. */ 231 } iplro_t; 232 233 /* 234 * LRO object, one per each LRO session. 235 */ 236 typedef struct lro { 237 /* non-linear: contains scatter-gather list of 238 xframe-mapped received buffers */ 239 OS_NETSTACK_BUF os_buf; 240 OS_NETSTACK_BUF os_buf_end; 241 242 /* link layer header of the first frame; 243 remains intack throughout the processing */ 244 u8 *ll_hdr; 245 246 /* IP header - gets _collapsed_ */ 247 iplro_t *ip_hdr; 248 249 /* transport header - gets _collapsed_ */ 250 tcplro_t *tcp_hdr; 251 252 /* Next tcp sequence number */ 253 u32 tcp_next_seq_num; 254 /* Current tcp seq & ack */ 255 u32 tcp_seq_num; 256 u32 tcp_ack_num; 257 258 /* total number of accumulated (so far) frames */ 259 int sg_num; 260 261 /* total data length */ 262 int total_length; 263 264 /* receive side hash value, available from Hercules */ 265 u32 rth_value; 266 267 /* In use */ 268 u8 in_use; 269 270 /* Total length of the fragments clubbed with the inital frame */ 271 u32 frags_len; 272 273 /* LRO frame contains time stamp, if (ts_off != -1) */ 274 int ts_off; 275 276 } lro_t; 277 #endif 278 279 /* 280 * xge_hal_spdm_entry_t 281 * 282 * Represents a single spdm entry in the SPDM table. 283 */ 284 typedef struct xge_hal_spdm_entry_t { 285 xge_hal_ipaddr_t src_ip; 286 xge_hal_ipaddr_t dst_ip; 287 u32 jhash_value; 288 u16 l4_sp; 289 u16 l4_dp; 290 u16 spdm_entry; 291 u8 in_use; 292 u8 is_tcp; 293 u8 is_ipv4; 294 u8 tgt_queue; 295 } xge_hal_spdm_entry_t; 296 297 #ifdef XGEHAL_RNIC 298 /* 299 * xge_hal_rnic_oid_db_t 300 * 301 * Database used to allocate object Ids. 302 */ 303 typedef struct xge_hal_rnic_oid_db_t { 304 u8 id_map[4096]; 305 u32 id_next_byte; 306 u8 id_inst_number; 307 #define XGE_HAL_RNIC_OID_DB_OID_GET(sid,sin) ((sin<<24)|sid) 308 #define XGE_HAL_RNIC_OID_DB_SID_GET(id) (id&0xFFFFFF) 309 #define XGE_HAL_RNIC_OID_DB_SIN_GET(id) ((id>>24)&0xFF) 310 311 }xge_hal_rnic_oid_db_t; 312 313 #endif 314 315 /* 316 * xge_hal_device_t 317 * 318 * HAL device object. Represents Xframe. 319 */ 320 typedef struct { 321 unsigned int magic; 322 pci_reg_h regh0; 323 pci_reg_h regh1; 324 pci_reg_h regh2; 325 char *bar0; 326 char *isrbar0; 327 char *bar1; 328 char *bar2; 329 pci_irq_h irqh; 330 pci_cfg_h cfgh; 331 pci_dev_h pdev; 332 xge_hal_pci_config_t pci_config_space; 333 #if defined(XGE_HAL_MSI_X) 334 u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES * 2]; 335 #endif 336 xge_hal_device_config_t config; 337 xge_list_t free_channels; 338 xge_list_t fifo_channels; 339 xge_list_t ring_channels; 340 #ifdef XGEHAL_RNIC 341 xge_hal_rnic_oid_db_t nce_oid_db; 342 xge_list_t sq_channels; 343 xge_hal_rnic_oid_db_t sq_oid_db; 344 xge_list_t hrq_channels; 345 xge_hal_rnic_oid_db_t hrq_oid_db; 346 xge_list_t hcq_channels; 347 xge_hal_rnic_oid_db_t hcq_oid_db; 348 xge_list_t lrq_channels; 349 xge_hal_rnic_oid_db_t lrq_oid_db; 350 xge_list_t lcq_channels; 351 xge_hal_rnic_oid_db_t lcq_oid_db; 352 xge_list_t umq_channels; 353 xge_list_t dmq_channels; 354 xge_hal_blockpool_t block_pool; 355 #endif 356 volatile int is_initialized; 357 volatile int terminating; 358 xge_hal_stats_t stats; 359 macaddr_t macaddr[1]; 360 xge_queue_h queueh; 361 volatile int mcast_refcnt; 362 int is_promisc; 363 volatile xge_hal_device_link_state_e link_state; 364 void *upper_layer_info; 365 xge_hal_device_attr_t orig_attr; 366 u16 device_id; 367 u8 revision; 368 int msi_enabled; 369 int hw_is_initialized; 370 u64 inject_serr; 371 u64 inject_ecc; 372 u8 inject_bad_tcode; 373 int inject_bad_tcode_for_chan_type; 374 int reset_needed_after_close; 375 int tti_enabled; 376 xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM]; 377 int bimodal_timer_val_us; 378 int bimodal_urange_a_en; 379 int bimodal_intr_cnt; 380 char *spdm_mem_base; 381 u16 spdm_max_entries; 382 xge_hal_spdm_entry_t **spdm_table; 383 spinlock_t spdm_lock; 384 #if defined(XGE_HAL_MSI) 385 u32 msi_mask; 386 #endif 387 #if defined(XGE_HAL_CONFIG_LRO) 388 lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS]; 389 int lro_next_idx; 390 lro_t *lro_recent; 391 #endif 392 spinlock_t xena_post_lock; 393 394 /* bimodal workload stats */ 395 int irq_workload_rxd[XGE_HAL_MAX_RING_NUM]; 396 int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM]; 397 int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM]; 398 int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM]; 399 int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM]; 400 int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM]; 401 402 int mtu_first_time_set; 403 u64 rxufca_lbolt; 404 u64 rxufca_lbolt_time; 405 u64 rxufca_intr_thres; 406 char* dump_buf; 407 xge_hal_pci_mode_e pci_mode; 408 xge_hal_pci_bus_frequency_e bus_frequency; 409 xge_hal_pci_bus_width_e bus_width; 410 volatile int in_poll; 411 #ifdef XGEHAL_RNIC 412 void *rnic_context; 413 #endif 414 } xge_hal_device_t; 415 416 417 /* ========================== PRIVATE API ================================= */ 418 419 void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, 420 void *addr); 421 422 void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val, 423 void *addr); 424 425 xge_hal_status_e 426 __hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason); 427 428 xge_hal_status_e 429 __hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason); 430 431 xge_hal_status_e 432 __hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason); 433 434 xge_hal_status_e 435 __hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason); 436 437 xge_hal_status_e 438 __hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason); 439 440 xge_hal_status_e 441 __hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason); 442 443 xge_hal_status_e 444 __hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason); 445 446 xge_hal_status_e 447 __hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason); 448 449 xge_hal_status_e 450 __hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason); 451 452 xge_hal_status_e 453 __hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask, 454 int max_millis); 455 xge_hal_status_e 456 __hal_device_rts_mac_configure(xge_hal_device_t *hldev); 457 458 xge_hal_status_e 459 __hal_device_rts_qos_configure(xge_hal_device_t *hldev); 460 461 xge_hal_status_e 462 __hal_device_rti_configure(xge_hal_device_t *hldev, int runtime); 463 464 /* =========================== PUBLIC API ================================= */ 465 466 unsigned int 467 __hal_fix_time_ival_herc(xge_hal_device_t *hldev, 468 unsigned int time_ival); 469 xge_hal_status_e 470 xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable, 471 u32 itable_size); 472 473 void 474 xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type, 475 u16 bucket_size); 476 477 void 478 xge_hal_rts_rth_init(xge_hal_device_t *hldev); 479 480 void 481 xge_hal_rts_rth_clr(xge_hal_device_t *hldev); 482 483 void 484 xge_hal_rts_rth_start(xge_hal_device_t *hldev); 485 486 void 487 xge_hal_rts_rth_stop(xge_hal_device_t *hldev); 488 489 void 490 xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key); 491 492 xge_hal_status_e 493 xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr); 494 495 xge_hal_status_e 496 xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index); 497 498 /** 499 * xge_hal_device_rti_reconfigure 500 */ 501 static inline xge_hal_status_e 502 xge_hal_device_rti_reconfigure(xge_hal_device_t *hldev) 503 { 504 return __hal_device_rti_configure(hldev, 1); 505 } 506 507 /** 508 * xge_hal_device_is_initialized - Returns 0 if device is not 509 * initialized, non-zero otherwise. 510 * @devh: HAL device handle. 511 * 512 * Returns 0 if device is not initialized, non-zero otherwise. 513 */ 514 static inline int 515 xge_hal_device_is_initialized(xge_hal_device_h devh) 516 { 517 return ((xge_hal_device_t*)devh)->is_initialized; 518 } 519 520 521 /** 522 * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing. 523 * @devh: HAL device handle. 524 * 525 * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise. 526 */ 527 static inline int 528 xge_hal_device_in_poll(xge_hal_device_h devh) 529 { 530 return ((xge_hal_device_t*)devh)->in_poll; 531 } 532 533 534 /** 535 * xge_hal_device_inject_ecc - Inject ECC error. 536 * @devh: HAL device, pointer to xge_hal_device_t structure. 537 * @err_reg: Contains the error register. 538 * 539 * This function is used to inject ECC error into the driver flow. 540 * This facility can be used to test the driver flow in the 541 * case of ECC error is reported by the firmware. 542 * 543 * Returns: void 544 * See also: xge_hal_device_inject_serr(), 545 * xge_hal_device_inject_bad_tcode() 546 */ 547 static inline void 548 xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg) 549 { 550 ((xge_hal_device_t*)devh)->inject_ecc = err_reg; 551 } 552 553 554 /** 555 * xge_hal_device_inject_serr - Inject SERR error. 556 * @devh: HAL device, pointer to xge_hal_device_t structure. 557 * @err_reg: Contains the error register. 558 * 559 * This function is used to inject SERR error into the driver flow. 560 * This facility can be used to test the driver flow in the 561 * case of SERR error is reported by firmware. 562 * 563 * Returns: void 564 * See also: xge_hal_device_inject_ecc(), 565 * xge_hal_device_inject_bad_tcode() 566 */ 567 static inline void 568 xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg) 569 { 570 ((xge_hal_device_t*)devh)->inject_serr = err_reg; 571 } 572 573 574 /** 575 * xge_hal_device_inject_bad_tcode - Inject Bad transfer code. 576 * @devh: HAL device, pointer to xge_hal_device_t structure. 577 * @chan_type: Channel type (fifo/ring). 578 * @t_code: Transfer code. 579 * 580 * This function is used to inject bad (Tx/Rx Data)transfer code 581 * into the driver flow. 582 * 583 * This facility can be used to test the driver flow in the 584 * case of bad transfer code reported by firmware for a Tx/Rx data 585 * transfer. 586 * 587 * Returns: void 588 * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr() 589 */ 590 static inline void 591 xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code) 592 { 593 ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type; 594 ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code; 595 } 596 597 void xge_hal_device_msi_enable(xge_hal_device_h devh); 598 599 /* 600 * xge_hal_device_msi_mode - Is MSI enabled? 601 * @devh: HAL device handle. 602 * 603 * Returns 0 if MSI is enabled for the specified device, 604 * non-zero otherwise. 605 */ 606 static inline int 607 xge_hal_device_msi_mode(xge_hal_device_h devh) 608 { 609 return ((xge_hal_device_t*)devh)->msi_enabled; 610 } 611 612 /** 613 * xge_hal_device_queue - Get per-device event queue. 614 * @devh: HAL device handle. 615 * 616 * Returns: event queue associated with the specified HAL device. 617 */ 618 static inline xge_queue_h 619 xge_hal_device_queue (xge_hal_device_h devh) 620 { 621 return ((xge_hal_device_t*)devh)->queueh; 622 } 623 624 /** 625 * xge_hal_device_attr - Get original (user-specified) device 626 * attributes. 627 * @devh: HAL device handle. 628 * 629 * Returns: original (user-specified) device attributes. 630 */ 631 static inline xge_hal_device_attr_t* 632 xge_hal_device_attr(xge_hal_device_h devh) 633 { 634 return &((xge_hal_device_t*)devh)->orig_attr; 635 } 636 637 /** 638 * xge_hal_device_private_set - Set ULD context. 639 * @devh: HAL device handle. 640 * @data: pointer to ULD context 641 * 642 * Use HAL device to set upper-layer driver (ULD) context. 643 * 644 * See also: xge_hal_device_from_private(), xge_hal_device_private() 645 */ 646 static inline void 647 xge_hal_device_private_set(xge_hal_device_h devh, void *data) 648 { 649 ((xge_hal_device_t*)devh)->upper_layer_info = data; 650 } 651 652 /** 653 * xge_hal_device_private - Get ULD context. 654 * @devh: HAL device handle. 655 * 656 * Use HAL device to get upper-layer driver (ULD) context. 657 * 658 * Returns: ULD context. 659 * 660 * See also: xge_hal_device_from_private(), xge_hal_device_private_set() 661 */ 662 static inline void* 663 xge_hal_device_private(xge_hal_device_h devh) 664 { 665 return ((xge_hal_device_t*)devh)->upper_layer_info; 666 } 667 668 /** 669 * xge_hal_device_from_private - Get HAL device object from private. 670 * @info_ptr: ULD context. 671 * 672 * Use ULD context to get HAL device. 673 * 674 * Returns: Device handle. 675 * 676 * See also: xge_hal_device_private(), xge_hal_device_private_set() 677 */ 678 static inline xge_hal_device_h 679 xge_hal_device_from_private(void *info_ptr) 680 { 681 return xge_container_of((void * const* ) info_ptr, xge_hal_device_t, 682 upper_layer_info); 683 } 684 685 /** 686 * xge_hal_device_mtu_check - check MTU value for ranges 687 * @hldev: the device 688 * @new_mtu: new MTU value to check 689 * 690 * Will do sanity check for new MTU value. 691 * 692 * Returns: XGE_HAL_OK - success. 693 * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid. 694 * 695 * See also: xge_hal_device_mtu_set() 696 */ 697 static inline xge_hal_status_e 698 xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu) 699 { 700 if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) { 701 return XGE_HAL_ERR_INVALID_MTU_SIZE; 702 } 703 704 return XGE_HAL_OK; 705 } 706 707 void xge_hal_device_bcast_enable(xge_hal_device_h devh); 708 709 void xge_hal_device_bcast_disable(xge_hal_device_h devh); 710 711 void xge_hal_device_terminating(xge_hal_device_h devh); 712 713 xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev, 714 xge_hal_device_attr_t *attr, xge_hal_device_config_t *config); 715 716 void xge_hal_device_terminate(xge_hal_device_t *hldev); 717 718 xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev); 719 720 xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev, 721 int index, macaddr_t *macaddr); 722 723 xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev, 724 int index, macaddr_t macaddr); 725 726 int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted); 727 728 xge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu); 729 730 xge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status); 731 732 void xge_hal_device_intr_enable(xge_hal_device_t *hldev); 733 734 void xge_hal_device_intr_disable(xge_hal_device_t *hldev); 735 736 xge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev); 737 738 xge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev); 739 740 void xge_hal_device_promisc_enable(xge_hal_device_t *hldev); 741 742 void xge_hal_device_promisc_disable(xge_hal_device_t *hldev); 743 744 xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev); 745 746 xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev); 747 748 xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh, 749 xge_hal_dtr_h dtrh, 750 u8 t_code); 751 752 xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh, 753 xge_hal_device_link_state_e *ls); 754 755 void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us, 756 int one_shot); 757 758 void xge_hal_device_poll(xge_hal_device_h devh); 759 760 xge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh); 761 762 int xge_hal_device_is_slot_freeze(xge_hal_device_h devh); 763 764 xge_hal_status_e 765 xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode, 766 xge_hal_pci_bus_frequency_e *bus_frequency, 767 xge_hal_pci_bus_width_e *bus_width); 768 769 xge_hal_status_e 770 xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, 771 xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, 772 u8 is_tcp, u8 is_ipv4, u8 tgt_queue); 773 774 xge_hal_status_e 775 xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, 776 xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, 777 u8 is_tcp, u8 is_ipv4); 778 779 xge_hal_status_e 780 xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index); 781 782 u32 __hal_calc_jhash(u8 *msg, u32 length, u32 golden_ratio, u32 init_value); 783 784 int 785 xge_hal_device_is_closed (xge_hal_device_h devh); 786 787 #ifdef XGEHAL_RNIC 788 789 xge_hal_status_e 790 __hal_device_oid_allocate(xge_hal_rnic_oid_db_t *objdb, u32 *objid); 791 792 xge_hal_status_e 793 __hal_device_oid_free(xge_hal_rnic_oid_db_t *objdb, u32 objid); 794 795 #endif 796 797 #if defined(XGE_HAL_MSI) 798 /* Some function protoypes for MSI implementation. */ 799 xge_hal_status_e 800 xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi, u32 801 msg_val); 802 void 803 xge_hal_mask_msi(xge_hal_device_t *hldev); 804 void 805 xge_hal_unmask_msi(xge_hal_channel_h channelh); 806 #endif 807 #if defined(XGE_HAL_MSI_X) 808 xge_hal_status_e 809 xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx); 810 #endif 811 812 813 #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE) 814 #define __HAL_STATIC_DEVICE 815 #define __HAL_INLINE_DEVICE 816 817 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int 818 xge_hal_device_rev(xge_hal_device_t *hldev); 819 820 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 821 xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason); 822 823 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 824 xge_hal_device_clear_rx(xge_hal_device_t *hldev); 825 826 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 827 xge_hal_device_clear_tx(xge_hal_device_t *hldev); 828 829 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 830 xge_hal_device_continue_irq(xge_hal_device_t *hldev); 831 832 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 833 xge_hal_device_handle_irq(xge_hal_device_t *hldev); 834 835 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 836 xge_hal_device_bar0(xge_hal_device_t *hldev); 837 838 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 839 xge_hal_device_isrbar0(xge_hal_device_t *hldev); 840 841 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 842 xge_hal_device_bar1(xge_hal_device_t *hldev); 843 844 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 845 xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0); 846 847 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 848 xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0); 849 850 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 851 xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh, 852 char *bar1); 853 854 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 855 xge_hal_device_mask_tx(xge_hal_device_t *hldev); 856 857 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 858 xge_hal_device_mask_rx(xge_hal_device_t *hldev); 859 860 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 861 xge_hal_device_mask_all(xge_hal_device_t *hldev); 862 863 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 864 xge_hal_device_unmask_tx(xge_hal_device_t *hldev); 865 866 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 867 xge_hal_device_unmask_rx(xge_hal_device_t *hldev); 868 869 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 870 xge_hal_device_unmask_all(xge_hal_device_t *hldev); 871 872 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 873 xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx); 874 875 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 876 xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx); 877 878 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 879 xge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx); 880 881 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 882 xge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx); 883 884 #if defined (XGE_HAL_CONFIG_LRO) 885 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8 886 __hal_header_parse_token_u8(u8 *string,u16 offset); 887 888 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 889 __hal_header_parse_token_u16(u8 *string,u16 offset); 890 891 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32 892 __hal_header_parse_token_u32(u8 *string,u16 offset); 893 894 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 895 __hal_header_update_u8(u8 *string, u16 offset, u8 val); 896 897 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 898 __hal_header_update_u16(u8 *string, u16 offset, u16 val); 899 900 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 901 __hal_header_update_u32(u8 *string, u16 offset, u32 val); 902 903 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 904 __hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp); 905 906 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 907 __hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info); 908 909 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 910 __hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off); 911 912 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 913 __hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp, 914 xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev); 915 916 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 917 __hal_get_lro_session(u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro, 918 xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, 919 lro_t **lro_end3); 920 921 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 922 __hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 923 xge_hal_device_t *hldev); 924 925 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 926 __hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 927 xge_hal_device_t *hldev); 928 929 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 930 __hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 931 xge_hal_device_t *hldev); 932 933 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 934 __hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro, 935 xge_hal_device_t *hldev); 936 937 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 938 xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen, 939 lro_t **lro, xge_hal_dtr_info_t *ext_info, 940 xge_hal_device_t *hldev, lro_t **lro_end3); 941 942 void 943 xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev); 944 945 xge_hal_status_e 946 xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev); 947 948 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * 949 xge_hal_lro_get_next_session(xge_hal_device_t *hldev); 950 951 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 952 __hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro, 953 xge_hal_device_t *hldev, int slot, u32 tcp_seg_len, 954 int ts_off); 955 956 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int 957 __hal_lro_get_free_slot (xge_hal_device_t *hldev); 958 #endif 959 960 #else /* XGE_FASTPATH_EXTERN */ 961 #define __HAL_STATIC_DEVICE static 962 #define __HAL_INLINE_DEVICE inline 963 #include "xgehal-device-fp.c" 964 #endif /* XGE_FASTPATH_INLINE */ 965 966 967 __EXTERN_END_DECLS 968 969 #endif /* XGE_HAL_DEVICE_H */ 970