1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2002-2005 Neterion, Inc. 24 * All right Reserved. 25 * 26 * FileName : xgehal-config.h 27 * 28 * Description: Xframe configuration. 29 * 30 * Created: 14 May 2004 31 */ 32 33 #ifndef XGE_HAL_CONFIG_H 34 #define XGE_HAL_CONFIG_H 35 36 #include "xge-os-pal.h" 37 #include "xgehal-types.h" 38 39 /* 40 */ 41 #define XGE_HAL_DEFAULT_USE_HARDCODE -1 42 43 44 /** 45 * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration. 46 * @enabled: Set to 1, if TTI feature is enabled. 47 * @urange_a: Link utilization range A. The value from 0 to 100%. 48 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 49 * each time when (and only when) the line is utilized no more 50 * than @urange_a percent in the transmit direction, 51 * and number of transmitted frames is greater or equal @ufc_a. 52 * @urange_b: Link utilization range B. 53 * @ufc_b: Frame count for the utilization range B. 54 * @urange_c: Link utilization range C. 55 * @ufc_c: Frame count for the utilization range C. 56 * @urange_d: Link utilization range D. 57 * @ufc_d: Frame count for the utilization range D. 58 * @timer_val_us: Interval of time, in microseconds, at which transmit timer 59 * interrupt is to be generated. Note that unless @timer_ci_en 60 * is set, the timer interrupt is generated only in presence 61 * of the transmit traffic. Note also that timer interrupt 62 * and utilization interrupt are two separate interrupt 63 * sources. 64 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 65 * interrupt was generated during the interval. 66 * @timer_ci_en: Enable/disable continuous interrupt. Set this value 67 * to 1 in order to generate continuous interrupt 68 * at fixed @timer_val intervals of time, independently 69 * of whether there is transmit traffic or not. 70 * @enabled: Set to 1, if TTI feature is enabled. 71 * 72 * Xframe transmit interrupt configuration. 73 * See Xframe User Guide, Section 3.5 "Device Interrupts" 74 * for more details. Note also (min, max) 75 * ranges in the body of the xge_hal_tx_intr_config_t structure. 76 * Note: Valid (min, max) range for each attribute is specified in the body of 77 * the xge_hal_tti_config_t{} structure. Please refer to the 78 * corresponding header file. 79 */ 80 typedef struct xge_hal_tti_config_t { 81 82 int enabled; 83 #define XGE_HAL_TTI_ENABLE 1 84 #define XGE_HAL_TTI_DISABLE 0 85 86 /* Line utilization interrupts */ 87 88 int urange_a; 89 #define XGE_HAL_MIN_TX_URANGE_A 0 90 #define XGE_HAL_MAX_TX_URANGE_A 100 91 92 int ufc_a; 93 #define XGE_HAL_MIN_TX_UFC_A 0 94 #define XGE_HAL_MAX_TX_UFC_A 65535 95 96 int urange_b; 97 #define XGE_HAL_MIN_TX_URANGE_B 0 98 #define XGE_HAL_MAX_TX_URANGE_B 100 99 100 int ufc_b; 101 #define XGE_HAL_MIN_TX_UFC_B 0 102 #define XGE_HAL_MAX_TX_UFC_B 65535 103 104 int urange_c; 105 #define XGE_HAL_MIN_TX_URANGE_C 0 106 #define XGE_HAL_MAX_TX_URANGE_C 100 107 108 int ufc_c; 109 #define XGE_HAL_MIN_TX_UFC_C 0 110 #define XGE_HAL_MAX_TX_UFC_C 65535 111 112 int urange_d; 113 #define XGE_HAL_MIN_TX_URANGE_D 0 114 #define XGE_HAL_MAX_TX_URANGE_D 100 115 116 int ufc_d; 117 #define XGE_HAL_MIN_TX_UFC_D 0 118 #define XGE_HAL_MAX_TX_UFC_D 65535 119 120 int timer_val_us; 121 #define XGE_HAL_MIN_TX_TIMER_VAL 0 122 #define XGE_HAL_MAX_TX_TIMER_VAL 65535 123 124 int timer_ac_en; 125 #define XGE_HAL_MIN_TX_TIMER_AC_EN 0 126 #define XGE_HAL_MAX_TX_TIMER_AC_EN 1 127 128 int timer_ci_en; 129 #define XGE_HAL_MIN_TX_TIMER_CI_EN 0 130 #define XGE_HAL_MAX_TX_TIMER_CI_EN 1 131 132 133 } xge_hal_tti_config_t; 134 135 /** 136 * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration. 137 * @urange_a: Link utilization range A. The value from 0 to 100%. 138 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 139 * each time when (and only when) the line is utilized no more 140 * than @urange_a percent inbound, 141 * and number of received frames is greater or equal @ufc_a. 142 * @urange_b: Link utilization range B. 143 * @ufc_b: Frame count for the utilization range B. 144 * @urange_c: Link utilization range C. 145 * @ufc_c: Frame count for the utilization range C. 146 * @urange_d: Link utilization range D. 147 * @ufc_d: Frame count for the utilization range D. 148 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 149 * interrupt was generated during the interval. 150 * @timer_val_us: Interval of time, in microseconds, at which receive timer 151 * interrupt is to be generated. The timer interrupt is generated 152 * only in presence of the inbound traffic. Note also that timer 153 * interrupt and utilization interrupt are two separate interrupt 154 * sources. 155 * 156 * Xframe receive interrupt configuration. 157 * See Xframe User Guide, Section 3.5 "Device Interrupts" 158 * for more details. Note also (min, max) 159 * ranges in the body of the xge_hal_intr_config_t structure. 160 * Note: Valid (min, max) range for each attribute is specified in the body of 161 * the xge_hal_rti_config_t{} structure. Please refer to the 162 * corresponding header file. 163 */ 164 typedef struct xge_hal_rti_config_t { 165 166 int urange_a; 167 #define XGE_HAL_MIN_RX_URANGE_A 0 168 #define XGE_HAL_MAX_RX_URANGE_A 127 169 170 int ufc_a; 171 #define XGE_HAL_MIN_RX_UFC_A 0 172 #define XGE_HAL_MAX_RX_UFC_A 65535 173 174 int urange_b; 175 #define XGE_HAL_MIN_RX_URANGE_B 0 176 #define XGE_HAL_MAX_RX_URANGE_B 127 177 178 int ufc_b; 179 #define XGE_HAL_MIN_RX_UFC_B 0 180 #define XGE_HAL_MAX_RX_UFC_B 65535 181 182 int urange_c; 183 #define XGE_HAL_MIN_RX_URANGE_C 0 184 #define XGE_HAL_MAX_RX_URANGE_C 127 185 186 int ufc_c; 187 #define XGE_HAL_MIN_RX_UFC_C 0 188 #define XGE_HAL_MAX_RX_UFC_C 65535 189 190 int ufc_d; 191 #define XGE_HAL_MIN_RX_UFC_D 0 192 #define XGE_HAL_MAX_RX_UFC_D 65535 193 194 int timer_ac_en; 195 #define XGE_HAL_MIN_RX_TIMER_AC_EN 0 196 #define XGE_HAL_MAX_RX_TIMER_AC_EN 1 197 198 int timer_val_us; 199 #define XGE_HAL_MIN_RX_TIMER_VAL 0 200 #define XGE_HAL_MAX_RX_TIMER_VAL 65535 201 202 } xge_hal_rti_config_t; 203 204 /** 205 * struct xge_hal_fifo_queue_t - Single fifo configuration. 206 * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue. 207 * @initial: Initial numbers of TxDLs per queue (can grow up to @max). 208 * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. 209 * Use 0 otherwise. 210 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 211 * which generally improves latency of the host bridge operation 212 * (see PCI specification). For valid values please refer 213 * to xge_hal_fifo_queue_t{} in the driver sources. 214 * @configured: Boolean. Use 1 to specify that the fifo is configured. 215 * Only "configured" fifos can be activated and used to post 216 * Tx descriptors. Any subset of 8 available fifos can be 217 * "configured". 218 * 219 * Single fifo configuration. 220 * Note: Valid (min, max) range for each attribute is specified in the body of 221 * the xge_hal_fifo_queue_t{} structure. Please refer to the 222 * corresponding header file. 223 * See also: xge_hal_fifo_config_t{} 224 */ 225 typedef struct xge_hal_fifo_queue_t { 226 int max; 227 int initial; 228 #define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2 229 #define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192 230 231 int intr; 232 #define XGE_HAL_MIN_FIFO_QUEUE_INTR 0 233 #define XGE_HAL_MAX_FIFO_QUEUE_INTR 1 234 235 int no_snoop_bits; 236 #define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0 237 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1 238 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2 239 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3 240 241 int configured; 242 #define XGE_HAL_MIN_FIFO_CONFIGURED 0 243 #define XGE_HAL_MAX_FIFO_CONFIGURED 1 244 245 } xge_hal_fifo_queue_t; 246 247 /** 248 * struct xge_hal_fifo_config_t - Configuration of all 8 fifos. 249 * @max_frags: Max number of Tx buffers per TxDL (that is, per single 250 * transmit operation). 251 * No more than 256 transmit buffers can be specified. 252 * @max_aligned_frags: Number of fragments to be aligned out of 253 * maximum fragments (see @max_frags). 254 * @reserve_threshold: Descriptor reservation threshold. 255 * At least @reserve_threshold descriptors will remain 256 * unallocated at all times. 257 * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size 258 * bytes. Setting @memblock_size to page size ensures 259 * by-page allocation of descriptors. 128K bytes is the 260 * maximum supported block size. 261 * @queue: Array of per-fifo configurations. 262 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data 263 * (e.g., to align on a cache line). 264 * 265 * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t 266 * structures. 267 * Note: Valid (min, max) range for each attribute is specified in the body of 268 * the xge_hal_fifo_config_t{} structure. Please refer to the 269 * corresponding header file. 270 * See also: xge_hal_ring_queue_t{}. 271 */ 272 typedef struct xge_hal_fifo_config_t { 273 int max_frags; 274 #define XGE_HAL_MIN_FIFO_FRAGS 1 275 #define XGE_HAL_MAX_FIFO_FRAGS 256 276 277 int reserve_threshold; 278 #define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0 279 #define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192 280 281 int memblock_size; 282 #define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096 283 #define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072 284 285 int alignment_size; 286 #define XGE_HAL_MIN_ALIGNMENT_SIZE 0 287 #define XGE_HAL_MAX_ALIGNMENT_SIZE 65536 288 289 int max_aligned_frags; 290 /* range: (1, @max_frags) */ 291 292 #define XGE_HAL_MIN_FIFO_NUM 1 293 #define XGE_HAL_MAX_FIFO_NUM 8 294 xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM]; 295 } xge_hal_fifo_config_t; 296 297 /** 298 * struct xge_hal_ring_queue_t - Single ring configuration. 299 * @max: Max numbers of RxD blocks per queue 300 * @initial: Initial numbers of RxD blocks per queue 301 * (can grow up to @max) 302 * @buffer_mode: Receive buffer mode (1, 3, or 5); for details please refer 303 * to Xframe User Guide. 304 * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring. 305 * Note that 64MB of available 306 * on-board DRAM is shared between receive rings. 307 * If a single ring is used, @dram_size_mb can be set to 64. 308 * Sum of all rings' @dram_size_mb cannot exceed 64. 309 * @backoff_interval_us: Time (in microseconds), after which Xframe 310 * tries to download RxDs posted by the host. 311 * Note that the "backoff" does not happen if host posts receive 312 * descriptors in the timely fashion. 313 * @max_frm_len: Maximum frame length that can be received on _that_ ring. 314 * Setting this field to -1 ensures that the ring will 315 * "accept" MTU-size frames (note that MTU can be changed at 316 * runtime). 317 * Any value other than (-1) specifies a certain "hard" 318 * limit on the receive frame sizes. 319 * The field can be used to activate receive frame-length based 320 * steering. 321 * @priority: Ring priority. 0 - highest, 7 - lowest. The value is used 322 * to give prioritized access to PCI-X. See Xframe documentation 323 * for details. 324 * @rth_en: Enable Receive Traffic Hashing (RTH). 325 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 326 * which generally improves latency of the host bridge operation 327 * (see PCI specification). For valid values please refer 328 * to xge_hal_ring_queue_t{} in the driver sources. 329 * @indicate_max_pkts: Sets maximum number of received frames to be processed 330 * within single interrupt. 331 * @configured: Boolean. Use 1 to specify that the ring is configured. 332 * Only "configured" rings can be activated and used to post 333 * Rx descriptors. Any subset of 8 available rings can be 334 * "configured". 335 * @rts_mac_en: 1 - To enable Receive MAC address steering. 336 * 0 - To disable Receive MAC address steering. 337 * @rti: Xframe receive interrupt configuration. 338 * 339 * Single ring configuration. 340 * Note: Valid (min, max) range for each attribute is specified in the body of 341 * the xge_hal_ring_queue_t{} structure. Please refer to the 342 * corresponding header file. 343 * See also: xge_hal_fifo_config_t{}. 344 */ 345 typedef struct xge_hal_ring_queue_t { 346 int max; 347 int initial; 348 #define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1 349 #define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64 350 351 int buffer_mode; 352 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1 353 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3 354 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5 355 356 int dram_size_mb; 357 #define XGE_HAL_MIN_RING_QUEUE_SIZE 0 358 #define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64 359 #define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32 360 361 int backoff_interval_us; 362 #define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1 363 #define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 364 365 int max_frm_len; 366 #define XGE_HAL_MIN_MAX_FRM_LEN -1 367 #define XGE_HAL_MAX_MAX_FRM_LEN 9622 368 369 int priority; 370 #define XGE_HAL_MIN_RING_PRIORITY 0 371 #define XGE_HAL_MAX_RING_PRIORITY 7 372 373 int rth_en; 374 #define XGE_HAL_MIN_RING_RTH_EN 0 375 #define XGE_HAL_MAX_RING_RTH_EN 1 376 377 int no_snoop_bits; 378 #define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0 379 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1 380 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2 381 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3 382 383 int indicate_max_pkts; 384 #define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 385 #define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 386 387 int configured; 388 #define XGE_HAL_MIN_RING_CONFIGURED 0 389 #define XGE_HAL_MAX_RING_CONFIGURED 1 390 391 int rts_mac_en; 392 #define XGE_HAL_MIN_RING_RTS_MAC_EN 0 393 #define XGE_HAL_MAX_RING_RTS_MAC_EN 1 394 395 xge_hal_rti_config_t rti; 396 397 } xge_hal_ring_queue_t; 398 399 /** 400 * struct xge_hal_ring_config_t - Array of ring configurations. 401 * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size 402 * bytes. Setting @memblock_size to page size ensures 403 * by-page allocation of descriptors. 128K bytes is the 404 * upper limit. 405 * @scatter_mode: Xframe supports two receive scatter modes: A and B. 406 * For details please refer to Xframe User Guide. 407 * @queue: Array of all Xframe ring configurations. 408 * 409 * Array of ring configurations. 410 * See also: xge_hal_ring_queue_t{}. 411 */ 412 typedef struct xge_hal_ring_config_t { 413 414 int memblock_size; 415 #define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096 416 #define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072 417 418 int scatter_mode; 419 #define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0 420 #define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1 421 422 int strip_vlan_tag; 423 #define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0 424 #define XGE_HAL_RING_STRIP_VLAN_TAG 1 425 426 #define XGE_HAL_MIN_RING_NUM 1 427 #define XGE_HAL_MAX_RING_NUM 8 428 xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM]; 429 430 } xge_hal_ring_config_t; 431 432 /** 433 * struct xge_hal_mac_config_t - MAC configuration. 434 * @tmac_util_period: The sampling period over which the transmit utilization 435 * is calculated. 436 * @rmac_util_period: The sampling period over which the receive utilization 437 * is calculated. 438 * @rmac_strip_pad: Determines whether padding of received frames is removed by 439 * the MAC or sent to the host. 440 * @rmac_bcast_en: Enable frames containing broadcast address to be 441 * passed to the host. 442 * @rmac_pause_time: The value to be inserted in outgoing pause frames. 443 * Has units of pause quanta (one pause quanta = 512 bit times). 444 * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation 445 * for queues 0 through 3. The threshold value indicates portion of the 446 * individual receive buffer queue size. Thresholds have a range of 0 to 447 * 255, allowing 256 possible watermarks in a queue. 448 * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation 449 * for queues 4 through 7. The threshold value indicates portion of the 450 * individual receive buffer queue size. Thresholds have a range of 0 to 451 * 255, allowing 256 possible watermarks in a queue. 452 * 453 * MAC configuration. This includes various aspects of configuration, including: 454 * - Pause frame threshold; 455 * - sampling rate to calculate link utilization; 456 * - enabling/disabling broadcasts. 457 * 458 * See Xframe User Guide for more details. 459 * Note: Valid (min, max) range for each attribute is specified in the body of 460 * the xge_hal_mac_config_t{} structure. Please refer to the 461 * corresponding include file. 462 */ 463 typedef struct xge_hal_mac_config_t { 464 int media; 465 #define XGE_HAL_MIN_MEDIA 0 466 #define XGE_HAL_MEDIA_SR 0 467 #define XGE_HAL_MEDIA_SW 1 468 #define XGE_HAL_MEDIA_LR 2 469 #define XGE_HAL_MEDIA_LW 3 470 #define XGE_HAL_MEDIA_ER 4 471 #define XGE_HAL_MEDIA_EW 5 472 #define XGE_HAL_MAX_MEDIA 5 473 474 int tmac_util_period; 475 #define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0 476 #define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15 477 478 int rmac_util_period; 479 #define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0 480 #define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15 481 482 int rmac_bcast_en; 483 #define XGE_HAL_MIN_RMAC_BCAST_EN 0 484 #define XGE_HAL_MAX_RMAC_BCAST_EN 1 485 486 int rmac_pause_gen_en; 487 #define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0 488 #define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1 489 490 int rmac_pause_rcv_en; 491 #define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0 492 #define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1 493 494 int rmac_pause_time; 495 #define XGE_HAL_MIN_RMAC_HIGH_PTIME 16 496 #define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535 497 498 int mc_pause_threshold_q0q3; 499 #define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0 500 #define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254 501 502 int mc_pause_threshold_q4q7; 503 #define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0 504 #define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254 505 506 } xge_hal_mac_config_t; 507 508 /** 509 * struct xge_hal_device_config_t - Device configuration. 510 * @mtu: Current mtu size. 511 * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx 512 * completions. Used in xge_hal_device_handle_irq(). 513 * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance 514 * with the PCI Specification, the value of the Latency Timer 515 * for this PCI bus master. 516 * Specify either zero or -1 to use BIOS default. 517 * @napi_weight: (TODO) 518 * @max_splits_trans: Maximum number of PCI-X split transactions. 519 * Specify (-1) to use BIOS default. 520 * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default 521 * BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B; 522 * 1 - 1KB, 2 - 2KB, and 3 - 4KB. 523 * @shared_splits: The number of Outstanding Split Transactions that is 524 * shared by Tx and Rx requests. The device stops issuing Tx 525 * requests once the number of Outstanding Split Transactions is 526 * equal to the value of Shared_Splits. 527 * A value of zero indicates that the Tx and Rx share all allocated 528 * Split Requests, i.e. the device can issue both types (Tx and Rx) 529 * of read requests until the number of Maximum Outstanding Split 530 * Transactions is reached. 531 * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer 532 * to the host. This includes MAC stats as well as PCI stats. 533 * See xge_hal_stats_hw_info_t{}. 534 * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz. 535 * @intr_mode: Line, MSI, or MSI-X interrupt. 536 * @sched_timer_us: If greater than zero, specifies time interval 537 * (in microseconds) for the device to generate 538 * interrupt. Note that unlike tti and rti interrupts, 539 * the scheduled interrupt is generated independently of 540 * whether there is transmit or receive traffic, respectively. 541 * @sched_timer_one_shot: 1 - generate scheduled interrupt only once. 542 * 0 - generate scheduled interrupt periodically at the specified 543 * @sched_timer_us interval. 544 * 545 * @ring: See xge_hal_ring_config_t{}. 546 * @mac: See xge_hal_mac_config_t{}. 547 * @tti: See xge_hal_tti_config_t{}. 548 * @fifo: See xge_hal_fifo_config_t{}. 549 * 550 * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#. 551 * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on 552 * ECC error. 553 * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on 554 * parity error. 555 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). 556 * @rth_bucket_size: RTH bucket width (in bits). For valid range please see 557 * xge_hal_device_config_t{} in the driver sources. 558 * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair 559 * Direct Match). 560 * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of 561 * hash value in the RTH SPDM based steering. 562 * @rxufca_intr_thres: (TODO) 563 * @rxufca_lo_lim: (TODO) 564 * @rxufca_hi_lim: (TODO) 565 * @rxufca_lbolt_period: (TODO) 566 * @link_valid_cnt: link-valid counting is done only at device-open time, 567 * to determine with the specified certainty that the link is up. See also 568 * @link_retry_cnt. 569 * @link_retry_cnt: Max number of polls for link-up. Done only at device 570 * open time. Reducing this value as well as the previous @link_valid_cnt, 571 * speeds up device startup, which may be important if the driver 572 * is compiled into OS. 573 * @link_stability_period: Specify the period for which the link must be 574 * stable in order for the adapter to declare "LINK UP". 575 * The enumerated settings (see Xframe-II UG) are: 576 * 0 ........... instantaneous 577 * 1 ........... 500 �s 578 * 2 ........... 1 ms 579 * 3 ........... 64 ms 580 * 4 ........... 256 ms 581 * 5 ........... 512 ms 582 * 6 ........... 1 s 583 * 7 ........... 2 s 584 * 585 * @device_poll_millis: Specify the interval (in mulliseconds) between 586 * successive xge_hal_device_poll() runs. 587 * stable in order for the adapter to declare "LINK UP". 588 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address 589 * 590 * Xframe configuration. 591 * Contains per-device configuration parameters, including: 592 * - latency timer (settable via PCI configuration space); 593 * - maximum number of split transactions; 594 * - maximum number of shared splits; 595 * - stats sampling interval, etc. 596 * 597 * In addition, xge_hal_device_config_t{} includes "subordinate" 598 * configurations, including: 599 * - fifos and rings; 600 * - MAC (see xge_hal_mac_config_t{}). 601 * 602 * See Xframe User Guide for more details. 603 * Note: Valid (min, max) range for each attribute is specified in the body of 604 * the xge_hal_device_config_t{} structure. Please refer to the 605 * corresponding include file. 606 * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{}, 607 * xge_hal_mac_config_t{}. 608 */ 609 typedef struct xge_hal_device_config_t { 610 int mtu; 611 #define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU 612 #define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU 613 614 int isr_polling_cnt; 615 #define XGE_HAL_MIN_ISR_POLLING_CNT 0 616 #define XGE_HAL_MAX_ISR_POLLING_CNT 65536 617 618 int latency_timer; 619 #define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1 620 #define XGE_HAL_MIN_LATENCY_TIMER 8 621 #define XGE_HAL_MAX_LATENCY_TIMER 255 622 623 int napi_weight; 624 #define XGE_HAL_DEF_NAPI_WEIGHT 64 625 626 int max_splits_trans; 627 #define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1 628 #define XGE_HAL_ONE_SPLIT_TRANSACTION 0 629 #define XGE_HAL_TWO_SPLIT_TRANSACTION 1 630 #define XGE_HAL_THREE_SPLIT_TRANSACTION 2 631 #define XGE_HAL_FOUR_SPLIT_TRANSACTION 3 632 #define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4 633 #define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5 634 #define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6 635 #define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7 636 637 int mmrb_count; 638 #define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 639 #define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */ 640 #define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */ 641 642 int shared_splits; 643 #define XGE_HAL_MIN_SHARED_SPLITS 0 644 #define XGE_HAL_MAX_SHARED_SPLITS 31 645 646 int stats_refresh_time_sec; 647 #define XGE_HAL_STATS_REFRESH_DISABLE 0 648 #define XGE_HAL_MIN_STATS_REFRESH_TIME 1 649 #define XGE_HAL_MAX_STATS_REFRESH_TIME 300 650 651 int pci_freq_mherz; 652 #define XGE_HAL_PCI_FREQ_MHERZ_33 33 653 #define XGE_HAL_PCI_FREQ_MHERZ_66 66 654 #define XGE_HAL_PCI_FREQ_MHERZ_100 100 655 #define XGE_HAL_PCI_FREQ_MHERZ_133 133 656 #define XGE_HAL_PCI_FREQ_MHERZ_266 266 657 658 int intr_mode; 659 #define XGE_HAL_INTR_MODE_IRQLINE 0 660 #define XGE_HAL_INTR_MODE_MSI 1 661 #define XGE_HAL_INTR_MODE_MSIX 2 662 663 int sched_timer_us; 664 #define XGE_HAL_SCHED_TIMER_DISABLED 0 665 #define XGE_HAL_SCHED_TIMER_MIN 0 666 #define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF 667 668 int sched_timer_one_shot; 669 #define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0 670 #define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1 671 672 xge_hal_ring_config_t ring; 673 xge_hal_mac_config_t mac; 674 xge_hal_tti_config_t tti; 675 xge_hal_fifo_config_t fifo; 676 677 int dump_on_serr; 678 #define XGE_HAL_DUMP_ON_SERR_DISABLE 0 679 #define XGE_HAL_DUMP_ON_SERR_ENABLE 1 680 681 int dump_on_eccerr; 682 #define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0 683 #define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1 684 685 int dump_on_parityerr; 686 #define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0 687 #define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1 688 689 int rth_en; 690 #define XGE_HAL_RTH_DISABLE 0 691 #define XGE_HAL_RTH_ENABLE 1 692 693 int rth_bucket_size; 694 #define XGE_HAL_MIN_RTH_BUCKET_SIZE 1 695 #define XGE_HAL_MAX_RTH_BUCKET_SIZE 8 696 697 int rth_spdm_en; 698 #define XGE_HAL_RTH_SPDM_DISABLE 0 699 #define XGE_HAL_RTH_SPDM_ENABLE 1 700 701 int rth_spdm_use_l4; 702 #define XGE_HAL_RTH_SPDM_USE_L4 1 703 704 int rxufca_intr_thres; 705 #define XGE_HAL_RXUFCA_INTR_THRES_MIN 1 706 #define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096 707 708 int rxufca_lo_lim; 709 #define XGE_HAL_RXUFCA_LO_LIM_MIN 1 710 #define XGE_HAL_RXUFCA_LO_LIM_MAX 16 711 712 int rxufca_hi_lim; 713 #define XGE_HAL_RXUFCA_HI_LIM_MIN 1 714 #define XGE_HAL_RXUFCA_HI_LIM_MAX 256 715 716 int rxufca_lbolt_period; 717 #define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1 718 #define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024 719 720 int link_valid_cnt; 721 #define XGE_HAL_LINK_VALID_CNT_MIN 0 722 #define XGE_HAL_LINK_VALID_CNT_MAX 127 723 724 int link_retry_cnt; 725 #define XGE_HAL_LINK_RETRY_CNT_MIN 0 726 #define XGE_HAL_LINK_RETRY_CNT_MAX 127 727 728 int link_stability_period; 729 #define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */ 730 #define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */ 731 #define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */ 732 733 int device_poll_millis; 734 #define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000 735 #define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1 736 #define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 737 738 int no_isr_events; 739 #define XGE_HAL_NO_ISR_EVENTS_MIN 0 740 #define XGE_HAL_NO_ISR_EVENTS_MAX 1 741 742 int rts_mac_en; 743 #define XGE_HAL_RTS_MAC_DISABLE 0 744 #define XGE_HAL_RTS_MAC_ENABLE 1 745 746 } xge_hal_device_config_t; 747 748 /** 749 * struct xge_hal_driver_config_t - HAL (layer) configuration. 750 * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to 751 * periodically poll HAL, i.e, invoke 752 * xge_hal_device_poll(). 753 * Note that HAL does not maintain its own 754 * polling context. HAL relies on ULD to 755 * provide one. 756 * @queue_size_initial: Initial size of the HAL protected event queue. 757 * The queue is shared by HAL and upper-layer drivers. 758 * The queue is used to exchange and process slow-path 759 * events. See xge_hal_event_e. 760 * @queue_size_max: Maximum size of the HAL queue. Depending on the load, 761 * the queue may grow at run-time up to @queue_max_size. 762 * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable. 763 * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple) 764 * HAL devices.) 765 * Currently this structure contains just a few basic values. 766 * Note: Valid (min, max) range for each attribute is specified in the body of 767 * the structure. Please refer to the corresponding header file. 768 * See also: xge_hal_device_poll() 769 */ 770 typedef struct xge_hal_driver_config_t { 771 int queue_size_initial; 772 #define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1 773 #define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16 774 775 int queue_size_max; 776 #define XGE_HAL_MIN_QUEUE_SIZE_MAX 1 777 #define XGE_HAL_MAX_QUEUE_SIZE_MAX 16 778 779 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR 780 int tracebuf_size; 781 #define XGE_HAL_MIN_CIRCULAR_ARR 4096 782 #define XGE_HAL_MAX_CIRCULAR_ARR 65536 783 #define XGE_HAL_DEF_CIRCULAR_ARR 16384 784 #endif 785 786 } xge_hal_driver_config_t; 787 788 789 /* ========================== PRIVATE API ================================= */ 790 791 xge_hal_status_e 792 __hal_device_config_check_common (xge_hal_device_config_t *new_config); 793 794 xge_hal_status_e 795 __hal_device_config_check_xena (xge_hal_device_config_t *new_config); 796 797 xge_hal_status_e 798 __hal_device_config_check_herc (xge_hal_device_config_t *new_config); 799 800 xge_hal_status_e 801 __hal_driver_config_check (xge_hal_driver_config_t *new_config); 802 803 #endif /* XGE_HAL_CONFIG_H */ 804