1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #ifndef XGE_HAL_CONFIG_H 25 #define XGE_HAL_CONFIG_H 26 27 #include "xge-os-pal.h" 28 #include "xgehal-types.h" 29 30 __EXTERN_BEGIN_DECLS 31 32 #define XGE_HAL_DEFAULT_USE_HARDCODE -1 33 34 35 /** 36 * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration. 37 * @enabled: Set to 1, if TTI feature is enabled. 38 * @urange_a: Link utilization range A. The value from 0 to 100%. 39 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 40 * each time when (and only when) the line is utilized no more 41 * than @urange_a percent in the transmit direction, 42 * and number of transmitted frames is greater or equal @ufc_a. 43 * @urange_b: Link utilization range B. 44 * @ufc_b: Frame count for the utilization range B. 45 * @urange_c: Link utilization range C. 46 * @ufc_c: Frame count for the utilization range C. 47 * @urange_d: Link utilization range D. 48 * @ufc_d: Frame count for the utilization range D. 49 * @timer_val_us: Interval of time, in microseconds, at which transmit timer 50 * interrupt is to be generated. Note that unless @timer_ci_en 51 * is set, the timer interrupt is generated only in presence 52 * of the transmit traffic. Note also that timer interrupt 53 * and utilization interrupt are two separate interrupt 54 * sources. 55 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 56 * interrupt was generated during the interval. 57 * @timer_ci_en: Enable/disable continuous interrupt. Set this value 58 * to 1 in order to generate continuous interrupt 59 * at fixed @timer_val intervals of time, independently 60 * of whether there is transmit traffic or not. 61 * @enabled: Set to 1, if TTI feature is enabled. 62 * 63 * Xframe transmit interrupt configuration. 64 * See Xframe User Guide, Section 3.5 "Device Interrupts" 65 * for more details. Note also (min, max) 66 * ranges in the body of the xge_hal_tx_intr_config_t structure. 67 * Note: Valid (min, max) range for each attribute is specified in the body of 68 * the xge_hal_tti_config_t{} structure. Please refer to the 69 * corresponding header file. 70 */ 71 typedef struct xge_hal_tti_config_t { 72 73 int enabled; 74 #define XGE_HAL_TTI_ENABLE 1 75 #define XGE_HAL_TTI_DISABLE 0 76 77 /* Line utilization interrupts */ 78 79 int urange_a; 80 #define XGE_HAL_MIN_TX_URANGE_A 0 81 #define XGE_HAL_MAX_TX_URANGE_A 100 82 83 int ufc_a; 84 #define XGE_HAL_MIN_TX_UFC_A 0 85 #define XGE_HAL_MAX_TX_UFC_A 65535 86 87 int urange_b; 88 #define XGE_HAL_MIN_TX_URANGE_B 0 89 #define XGE_HAL_MAX_TX_URANGE_B 100 90 91 int ufc_b; 92 #define XGE_HAL_MIN_TX_UFC_B 0 93 #define XGE_HAL_MAX_TX_UFC_B 65535 94 95 int urange_c; 96 #define XGE_HAL_MIN_TX_URANGE_C 0 97 #define XGE_HAL_MAX_TX_URANGE_C 100 98 99 int ufc_c; 100 #define XGE_HAL_MIN_TX_UFC_C 0 101 #define XGE_HAL_MAX_TX_UFC_C 65535 102 103 int ufc_d; 104 #define XGE_HAL_MIN_TX_UFC_D 0 105 #define XGE_HAL_MAX_TX_UFC_D 65535 106 107 int timer_val_us; 108 #define XGE_HAL_MIN_TX_TIMER_VAL 0 109 #define XGE_HAL_MAX_TX_TIMER_VAL 65535 110 111 int timer_ac_en; 112 #define XGE_HAL_MIN_TX_TIMER_AC_EN 0 113 #define XGE_HAL_MAX_TX_TIMER_AC_EN 1 114 115 int timer_ci_en; 116 #define XGE_HAL_MIN_TX_TIMER_CI_EN 0 117 #define XGE_HAL_MAX_TX_TIMER_CI_EN 1 118 119 120 } xge_hal_tti_config_t; 121 122 /** 123 * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration. 124 * @urange_a: Link utilization range A. The value from 0 to 100%. 125 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 126 * each time when (and only when) the line is utilized no more 127 * than @urange_a percent inbound, 128 * and number of received frames is greater or equal @ufc_a. 129 * @urange_b: Link utilization range B. 130 * @ufc_b: Frame count for the utilization range B. 131 * @urange_c: Link utilization range C. 132 * @ufc_c: Frame count for the utilization range C. 133 * @urange_d: Link utilization range D. 134 * @ufc_d: Frame count for the utilization range D. 135 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 136 * interrupt was generated during the interval. 137 * @timer_val_us: Interval of time, in microseconds, at which receive timer 138 * interrupt is to be generated. The timer interrupt is generated 139 * only in presence of the inbound traffic. Note also that timer 140 * interrupt and utilization interrupt are two separate interrupt 141 * sources. 142 * 143 * Xframe receive interrupt configuration. 144 * See Xframe User Guide, Section 3.5 "Device Interrupts" 145 * for more details. Note also (min, max) 146 * ranges in the body of the xge_hal_intr_config_t structure. 147 * Note: Valid (min, max) range for each attribute is specified in the body of 148 * the xge_hal_rti_config_t{} structure. Please refer to the 149 * corresponding header file. 150 */ 151 typedef struct xge_hal_rti_config_t { 152 153 int urange_a; 154 #define XGE_HAL_MIN_RX_URANGE_A 0 155 #define XGE_HAL_MAX_RX_URANGE_A 127 156 157 int ufc_a; 158 #define XGE_HAL_MIN_RX_UFC_A 0 159 #define XGE_HAL_MAX_RX_UFC_A 65535 160 161 int urange_b; 162 #define XGE_HAL_MIN_RX_URANGE_B 0 163 #define XGE_HAL_MAX_RX_URANGE_B 127 164 165 int ufc_b; 166 #define XGE_HAL_MIN_RX_UFC_B 0 167 #define XGE_HAL_MAX_RX_UFC_B 65535 168 169 int urange_c; 170 #define XGE_HAL_MIN_RX_URANGE_C 0 171 #define XGE_HAL_MAX_RX_URANGE_C 127 172 173 int ufc_c; 174 #define XGE_HAL_MIN_RX_UFC_C 0 175 #define XGE_HAL_MAX_RX_UFC_C 65535 176 177 int ufc_d; 178 #define XGE_HAL_MIN_RX_UFC_D 0 179 #define XGE_HAL_MAX_RX_UFC_D 65535 180 181 int timer_ac_en; 182 #define XGE_HAL_MIN_RX_TIMER_AC_EN 0 183 #define XGE_HAL_MAX_RX_TIMER_AC_EN 1 184 185 int timer_val_us; 186 #define XGE_HAL_MIN_RX_TIMER_VAL 0 187 #define XGE_HAL_MAX_RX_TIMER_VAL 65535 188 189 } xge_hal_rti_config_t; 190 191 /** 192 * struct xge_hal_fifo_queue_t - Single fifo configuration. 193 * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue. 194 * @initial: Initial numbers of TxDLs per queue (can grow up to @max). 195 * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. 196 * Use 0 otherwise. 197 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 198 * which generally improves latency of the host bridge operation 199 * (see PCI specification). For valid values please refer 200 * to xge_hal_fifo_queue_t{} in the driver sources. 201 * @configured: Boolean. Use 1 to specify that the fifo is configured. 202 * Only "configured" fifos can be activated and used to post 203 * Tx descriptors. Any subset of 8 available fifos can be 204 * "configured". 205 * 206 * Single fifo configuration. 207 * Note: Valid (min, max) range for each attribute is specified in the body of 208 * the xge_hal_fifo_queue_t{} structure. Please refer to the 209 * corresponding header file. 210 * See also: xge_hal_fifo_config_t{} 211 */ 212 typedef struct xge_hal_fifo_queue_t { 213 int max; 214 int initial; 215 #define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2 216 #define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192 217 218 int intr; 219 #define XGE_HAL_MIN_FIFO_QUEUE_INTR 0 220 #define XGE_HAL_MAX_FIFO_QUEUE_INTR 1 221 222 int no_snoop_bits; 223 #define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0 224 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1 225 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2 226 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3 227 228 int priority; 229 #define XGE_HAL_MIN_FIFO_PRIORITY 0 230 #define XGE_HAL_MAX_FIFO_PRIORITY 63 231 232 int configured; 233 #define XGE_HAL_MIN_FIFO_CONFIGURED 0 234 #define XGE_HAL_MAX_FIFO_CONFIGURED 1 235 236 #define XGE_HAL_MAX_FIFO_TTI_NUM 7 237 #define XGE_HAL_MAX_FIFO_TTI_RING_0 56 238 xge_hal_tti_config_t tti[XGE_HAL_MAX_FIFO_TTI_NUM]; 239 240 } xge_hal_fifo_queue_t; 241 242 /** 243 * struct xge_hal_fifo_config_t - Configuration of all 8 fifos. 244 * @max_frags: Max number of Tx buffers per TxDL (that is, per single 245 * transmit operation). 246 * No more than 256 transmit buffers can be specified. 247 * @max_aligned_frags: Number of fragments to be aligned out of 248 * maximum fragments (see @max_frags). 249 * @reserve_threshold: Descriptor reservation threshold. 250 * At least @reserve_threshold descriptors will remain 251 * unallocated at all times. 252 * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size 253 * bytes. Setting @memblock_size to page size ensures 254 * by-page allocation of descriptors. 128K bytes is the 255 * maximum supported block size. 256 * @queue: Array of per-fifo configurations. 257 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data 258 * (e.g., to align on a cache line). 259 * 260 * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t 261 * structures. 262 * Note: Valid (min, max) range for each attribute is specified in the body of 263 * the xge_hal_fifo_config_t{} structure. Please refer to the 264 * corresponding header file. 265 * See also: xge_hal_ring_queue_t{}. 266 */ 267 typedef struct xge_hal_fifo_config_t { 268 int max_frags; 269 #define XGE_HAL_MIN_FIFO_FRAGS 1 270 #define XGE_HAL_MAX_FIFO_FRAGS 256 271 272 int reserve_threshold; 273 #define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0 274 #define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192 275 276 int memblock_size; 277 #define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096 278 #define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072 279 280 int alignment_size; 281 #define XGE_HAL_MIN_ALIGNMENT_SIZE 0 282 #define XGE_HAL_MAX_ALIGNMENT_SIZE 65536 283 284 int max_aligned_frags; 285 /* range: (1, @max_frags) */ 286 287 #define XGE_HAL_MIN_FIFO_NUM 1 288 #define XGE_HAL_MAX_FIFO_NUM 8 289 xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM]; 290 } xge_hal_fifo_config_t; 291 292 /** 293 * struct xge_hal_ring_queue_t - Single ring configuration. 294 * @max: Max numbers of RxD blocks per queue 295 * @initial: Initial numbers of RxD blocks per queue 296 * (can grow up to @max) 297 * @buffer_mode: Receive buffer mode (1, 3, or 5); for details please refer 298 * to Xframe User Guide. 299 * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring. 300 * Note that 64MB of available 301 * on-board DRAM is shared between receive rings. 302 * If a single ring is used, @dram_size_mb can be set to 64. 303 * Sum of all rings' @dram_size_mb cannot exceed 64. 304 * @backoff_interval_us: Time (in microseconds), after which Xframe 305 * tries to download RxDs posted by the host. 306 * Note that the "backoff" does not happen if host posts receive 307 * descriptors in the timely fashion. 308 * @max_frm_len: Maximum frame length that can be received on _that_ ring. 309 * Setting this field to -1 ensures that the ring will 310 * "accept" MTU-size frames (note that MTU can be changed at 311 * runtime). 312 * Any value other than (-1) specifies a certain "hard" 313 * limit on the receive frame sizes. 314 * The field can be used to activate receive frame-length based 315 * steering. 316 * @priority: Ring priority. 0 - highest, 7 - lowest. The value is used 317 * to give prioritized access to PCI-X. See Xframe documentation 318 * for details. 319 * @rth_en: Enable Receive Traffic Hashing (RTH). 320 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 321 * which generally improves latency of the host bridge operation 322 * (see PCI specification). For valid values please refer 323 * to xge_hal_ring_queue_t{} in the driver sources. 324 * @indicate_max_pkts: Sets maximum number of received frames to be processed 325 * within single interrupt. 326 * @configured: Boolean. Use 1 to specify that the ring is configured. 327 * Only "configured" rings can be activated and used to post 328 * Rx descriptors. Any subset of 8 available rings can be 329 * "configured". 330 * @rts_mac_en: 1 - To enable Receive MAC address steering. 331 * 0 - To disable Receive MAC address steering. 332 * @rti: Xframe receive interrupt configuration. 333 * 334 * Single ring configuration. 335 * Note: Valid (min, max) range for each attribute is specified in the body of 336 * the xge_hal_ring_queue_t{} structure. Please refer to the 337 * corresponding header file. 338 * See also: xge_hal_fifo_config_t{}. 339 */ 340 typedef struct xge_hal_ring_queue_t { 341 int max; 342 int initial; 343 #define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1 344 #define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64 345 346 int buffer_mode; 347 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1 348 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3 349 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5 350 351 int dram_size_mb; 352 #define XGE_HAL_MIN_RING_QUEUE_SIZE 0 353 #define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64 354 #define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32 355 356 int backoff_interval_us; 357 #define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1 358 #define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 359 360 int max_frm_len; 361 #define XGE_HAL_MIN_MAX_FRM_LEN -1 362 #define XGE_HAL_MAX_MAX_FRM_LEN 9622 363 364 int priority; 365 #define XGE_HAL_MIN_RING_PRIORITY 0 366 #define XGE_HAL_MAX_RING_PRIORITY 7 367 368 int rth_en; 369 #define XGE_HAL_MIN_RING_RTH_EN 0 370 #define XGE_HAL_MAX_RING_RTH_EN 1 371 372 int no_snoop_bits; 373 #define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0 374 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1 375 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2 376 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3 377 378 int indicate_max_pkts; 379 #define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 380 #define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 381 382 int configured; 383 #define XGE_HAL_MIN_RING_CONFIGURED 0 384 #define XGE_HAL_MAX_RING_CONFIGURED 1 385 386 int rts_mac_en; 387 #define XGE_HAL_MIN_RING_RTS_MAC_EN 0 388 #define XGE_HAL_MAX_RING_RTS_MAC_EN 1 389 390 xge_hal_rti_config_t rti; 391 392 } xge_hal_ring_queue_t; 393 394 /** 395 * struct xge_hal_ring_config_t - Array of ring configurations. 396 * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size 397 * bytes. Setting @memblock_size to page size ensures 398 * by-page allocation of descriptors. 128K bytes is the 399 * upper limit. 400 * @scatter_mode: Xframe supports two receive scatter modes: A and B. 401 * For details please refer to Xframe User Guide. 402 * @strip_vlan_tag: TBD 403 * @queue: Array of all Xframe ring configurations. 404 * 405 * Array of ring configurations. 406 * See also: xge_hal_ring_queue_t{}. 407 */ 408 typedef struct xge_hal_ring_config_t { 409 410 int memblock_size; 411 #define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096 412 #define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072 413 414 int scatter_mode; 415 #define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0 416 #define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1 417 418 int strip_vlan_tag; 419 #define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0 420 #define XGE_HAL_RING_STRIP_VLAN_TAG 1 421 422 #define XGE_HAL_MIN_RING_NUM 1 423 #define XGE_HAL_MAX_RING_NUM 8 424 xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM]; 425 426 } xge_hal_ring_config_t; 427 428 /** 429 * struct xge_hal_mac_config_t - MAC configuration. 430 * @media: Transponder type. 431 * @tmac_util_period: The sampling period over which the transmit utilization 432 * is calculated. 433 * @rmac_util_period: The sampling period over which the receive utilization 434 * is calculated. 435 * @rmac_strip_pad: Determines whether padding of received frames is removed by 436 * the MAC or sent to the host. 437 * @rmac_bcast_en: Enable frames containing broadcast address to be 438 * passed to the host. 439 * @rmac_pause_gen_en: Received pause generation enable. 440 * @rmac_pause_rcv_en: Receive pause enable. 441 * @rmac_pause_time: The value to be inserted in outgoing pause frames. 442 * Has units of pause quanta (one pause quanta = 512 bit times). 443 * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation 444 * for queues 0 through 3. The threshold value indicates portion of the 445 * individual receive buffer queue size. Thresholds have a range of 0 to 446 * 255, allowing 256 possible watermarks in a queue. 447 * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation 448 * for queues 4 through 7. The threshold value indicates portion of the 449 * individual receive buffer queue size. Thresholds have a range of 0 to 450 * 255, allowing 256 possible watermarks in a queue. 451 * 452 * MAC configuration. This includes various aspects of configuration, including: 453 * - Pause frame threshold; 454 * - sampling rate to calculate link utilization; 455 * - enabling/disabling broadcasts. 456 * 457 * See Xframe User Guide for more details. 458 * Note: Valid (min, max) range for each attribute is specified in the body of 459 * the xge_hal_mac_config_t{} structure. Please refer to the 460 * corresponding include file. 461 */ 462 typedef struct xge_hal_mac_config_t { 463 int media; 464 #define XGE_HAL_MIN_MEDIA 0 465 #define XGE_HAL_MEDIA_SR 0 466 #define XGE_HAL_MEDIA_SW 1 467 #define XGE_HAL_MEDIA_LR 2 468 #define XGE_HAL_MEDIA_LW 3 469 #define XGE_HAL_MEDIA_ER 4 470 #define XGE_HAL_MEDIA_EW 5 471 #define XGE_HAL_MAX_MEDIA 5 472 473 int tmac_util_period; 474 #define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0 475 #define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15 476 477 int rmac_util_period; 478 #define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0 479 #define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15 480 481 int rmac_bcast_en; 482 #define XGE_HAL_MIN_RMAC_BCAST_EN 0 483 #define XGE_HAL_MAX_RMAC_BCAST_EN 1 484 485 int rmac_pause_gen_en; 486 #define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0 487 #define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1 488 489 int rmac_pause_rcv_en; 490 #define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0 491 #define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1 492 493 int rmac_pause_time; 494 #define XGE_HAL_MIN_RMAC_HIGH_PTIME 16 495 #define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535 496 497 int mc_pause_threshold_q0q3; 498 #define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0 499 #define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254 500 501 int mc_pause_threshold_q4q7; 502 #define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0 503 #define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254 504 505 } xge_hal_mac_config_t; 506 507 /** 508 * struct xge_hal_device_config_t - Device configuration. 509 * @mtu: Current mtu size. 510 * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx 511 * completions. Used in xge_hal_device_handle_irq(). 512 * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance 513 * with the PCI Specification, the value of the Latency Timer 514 * for this PCI bus master. 515 * Specify either zero or -1 to use BIOS default. 516 * @napi_weight: (TODO) 517 * @max_splits_trans: Maximum number of PCI-X split transactions. 518 * Specify (-1) to use BIOS default. 519 * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default 520 * BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B; 521 * 1 - 1KB, 2 - 2KB, and 3 - 4KB. 522 * @shared_splits: The number of Outstanding Split Transactions that is 523 * shared by Tx and Rx requests. The device stops issuing Tx 524 * requests once the number of Outstanding Split Transactions is 525 * equal to the value of Shared_Splits. 526 * A value of zero indicates that the Tx and Rx share all allocated 527 * Split Requests, i.e. the device can issue both types (Tx and Rx) 528 * of read requests until the number of Maximum Outstanding Split 529 * Transactions is reached. 530 * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer 531 * to the host. This includes MAC stats as well as PCI stats. 532 * See xge_hal_stats_hw_info_t{}. 533 * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz. 534 * @intr_mode: Line, MSI, or MSI-X interrupt. 535 * @sched_timer_us: If greater than zero, specifies time interval 536 * (in microseconds) for the device to generate 537 * interrupt. Note that unlike tti and rti interrupts, 538 * the scheduled interrupt is generated independently of 539 * whether there is transmit or receive traffic, respectively. 540 * @sched_timer_one_shot: 1 - generate scheduled interrupt only once. 541 * 0 - generate scheduled interrupt periodically at the specified 542 * @sched_timer_us interval. 543 * 544 * @ring: See xge_hal_ring_config_t{}. 545 * @mac: See xge_hal_mac_config_t{}. 546 * @tti: See xge_hal_tti_config_t{}. 547 * @fifo: See xge_hal_fifo_config_t{}. 548 * 549 * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#. 550 * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on 551 * ECC error. 552 * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on 553 * parity error. 554 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). 555 * @rth_bucket_size: RTH bucket width (in bits). For valid range please see 556 * xge_hal_device_config_t{} in the driver sources. 557 * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair 558 * Direct Match). 559 * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of 560 * hash value in the RTH SPDM based steering. 561 * @rxufca_intr_thres: (TODO) 562 * @rxufca_lo_lim: (TODO) 563 * @rxufca_hi_lim: (TODO) 564 * @rxufca_lbolt_period: (TODO) 565 * @link_valid_cnt: link-valid counting is done only at device-open time, 566 * to determine with the specified certainty that the link is up. See also 567 * @link_retry_cnt. 568 * @link_retry_cnt: Max number of polls for link-up. Done only at device 569 * open time. Reducing this value as well as the previous @link_valid_cnt, 570 * speeds up device startup, which may be important if the driver 571 * is compiled into OS. 572 * @link_stability_period: Specify the period for which the link must be 573 * stable in order for the adapter to declare "LINK UP". 574 * The enumerated settings (see Xframe-II UG) are: 575 * 0 ........... instantaneous 576 * 1 ........... 500 �s 577 * 2 ........... 1 ms 578 * 3 ........... 64 ms 579 * 4 ........... 256 ms 580 * 5 ........... 512 ms 581 * 6 ........... 1 s 582 * 7 ........... 2 s 583 * @no_isr_events: TBD 584 * @device_poll_millis: Specify the interval (in mulliseconds) between 585 * successive xge_hal_device_poll() runs. 586 * stable in order for the adapter to declare "LINK UP". 587 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address 588 * @lro_sg_size: TBD 589 * @lro_frm_len: TBD 590 * @bimodal_interrupts: Enable bimodal interrupts in device 591 * @bitmap_intr_num: Interrupt Number associated with the bitmap 592 * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ 593 * can own at any one time. 594 * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that 595 * this S-RQ can own at any one time. 596 * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for 597 * WQEs before generating a message or interrupt. 598 * @max_cqrq_per_bit: Maximum number of CQRQs allowed to share a bitmap bit 599 * @max_sess_per_bit: Maximum number of sessions allowed to share a bitmap bit 600 * @refill_threshold_high:This field provides a hysteresis upper bound for 601 * automatic adapter refill operations. 602 * @refill_threshold_low:This field provides a hysteresis lower bound for 603 * automatic adapter refill operations. 604 * @eol_policy:This field sets the policy for handling the end of list condition. 605 * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0. 606 * 2'b01 - Send UMQ message when EOL is reached. 607 * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message 608 * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for 609 * a non-zero block wrapper before giving up and sending a UMQ message 610 * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be held 611 * by a session at any one time. 612 * 613 * Xframe configuration. 614 * Contains per-device configuration parameters, including: 615 * - latency timer (settable via PCI configuration space); 616 * - maximum number of split transactions; 617 * - maximum number of shared splits; 618 * - stats sampling interval, etc. 619 * 620 * In addition, xge_hal_device_config_t{} includes "subordinate" 621 * configurations, including: 622 * - fifos and rings; 623 * - MAC (see xge_hal_mac_config_t{}). 624 * 625 * See Xframe User Guide for more details. 626 * Note: Valid (min, max) range for each attribute is specified in the body of 627 * the xge_hal_device_config_t{} structure. Please refer to the 628 * corresponding include file. 629 * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{}, 630 * xge_hal_mac_config_t{}. 631 */ 632 typedef struct xge_hal_device_config_t { 633 int mtu; 634 #define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU 635 #define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU 636 637 int isr_polling_cnt; 638 #define XGE_HAL_MIN_ISR_POLLING_CNT 0 639 #define XGE_HAL_MAX_ISR_POLLING_CNT 65536 640 641 int latency_timer; 642 #define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1 643 #define XGE_HAL_MIN_LATENCY_TIMER 8 644 #define XGE_HAL_MAX_LATENCY_TIMER 255 645 646 int napi_weight; 647 #define XGE_HAL_DEF_NAPI_WEIGHT 64 648 649 int max_splits_trans; 650 #define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1 651 #define XGE_HAL_ONE_SPLIT_TRANSACTION 0 652 #define XGE_HAL_TWO_SPLIT_TRANSACTION 1 653 #define XGE_HAL_THREE_SPLIT_TRANSACTION 2 654 #define XGE_HAL_FOUR_SPLIT_TRANSACTION 3 655 #define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4 656 #define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5 657 #define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6 658 #define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7 659 660 int mmrb_count; 661 #define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 662 #define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */ 663 #define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */ 664 665 int shared_splits; 666 #define XGE_HAL_MIN_SHARED_SPLITS 0 667 #define XGE_HAL_MAX_SHARED_SPLITS 31 668 669 int stats_refresh_time_sec; 670 #define XGE_HAL_STATS_REFRESH_DISABLE 0 671 #define XGE_HAL_MIN_STATS_REFRESH_TIME 1 672 #define XGE_HAL_MAX_STATS_REFRESH_TIME 300 673 674 int pci_freq_mherz; 675 #define XGE_HAL_PCI_FREQ_MHERZ_33 33 676 #define XGE_HAL_PCI_FREQ_MHERZ_66 66 677 #define XGE_HAL_PCI_FREQ_MHERZ_100 100 678 #define XGE_HAL_PCI_FREQ_MHERZ_133 133 679 #define XGE_HAL_PCI_FREQ_MHERZ_266 266 680 681 int intr_mode; 682 #define XGE_HAL_INTR_MODE_IRQLINE 0 683 #define XGE_HAL_INTR_MODE_MSI 1 684 #define XGE_HAL_INTR_MODE_MSIX 2 685 686 int sched_timer_us; 687 #define XGE_HAL_SCHED_TIMER_DISABLED 0 688 #define XGE_HAL_SCHED_TIMER_MIN 0 689 #define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF 690 691 int sched_timer_one_shot; 692 #define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0 693 #define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1 694 695 xge_hal_ring_config_t ring; 696 xge_hal_mac_config_t mac; 697 xge_hal_fifo_config_t fifo; 698 699 int dump_on_serr; 700 #define XGE_HAL_DUMP_ON_SERR_DISABLE 0 701 #define XGE_HAL_DUMP_ON_SERR_ENABLE 1 702 703 int dump_on_eccerr; 704 #define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0 705 #define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1 706 707 int dump_on_parityerr; 708 #define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0 709 #define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1 710 711 int rth_en; 712 #define XGE_HAL_RTH_DISABLE 0 713 #define XGE_HAL_RTH_ENABLE 1 714 715 int rth_bucket_size; 716 #define XGE_HAL_MIN_RTH_BUCKET_SIZE 1 717 #define XGE_HAL_MAX_RTH_BUCKET_SIZE 8 718 719 int rth_spdm_en; 720 #define XGE_HAL_RTH_SPDM_DISABLE 0 721 #define XGE_HAL_RTH_SPDM_ENABLE 1 722 723 int rth_spdm_use_l4; 724 #define XGE_HAL_RTH_SPDM_USE_L4 1 725 726 int rxufca_intr_thres; 727 #define XGE_HAL_RXUFCA_INTR_THRES_MIN 1 728 #define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096 729 730 int rxufca_lo_lim; 731 #define XGE_HAL_RXUFCA_LO_LIM_MIN 1 732 #define XGE_HAL_RXUFCA_LO_LIM_MAX 16 733 734 int rxufca_hi_lim; 735 #define XGE_HAL_RXUFCA_HI_LIM_MIN 1 736 #define XGE_HAL_RXUFCA_HI_LIM_MAX 256 737 738 int rxufca_lbolt_period; 739 #define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1 740 #define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024 741 742 int link_valid_cnt; 743 #define XGE_HAL_LINK_VALID_CNT_MIN 0 744 #define XGE_HAL_LINK_VALID_CNT_MAX 127 745 746 int link_retry_cnt; 747 #define XGE_HAL_LINK_RETRY_CNT_MIN 0 748 #define XGE_HAL_LINK_RETRY_CNT_MAX 127 749 750 int link_stability_period; 751 #define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */ 752 #define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */ 753 #define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */ 754 755 int device_poll_millis; 756 #define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000 757 #define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1 758 #define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 759 760 int no_isr_events; 761 #define XGE_HAL_NO_ISR_EVENTS_MIN 0 762 #define XGE_HAL_NO_ISR_EVENTS_MAX 1 763 764 int rts_mac_en; 765 #define XGE_HAL_RTS_MAC_DISABLE 0 766 #define XGE_HAL_RTS_MAC_ENABLE 1 767 768 int lro_sg_size; 769 #define XGE_HAL_LRO_DEFAULT_SG_SIZE 10 770 #define XGE_HAL_LRO_MIN_SG_SIZE 1 771 #define XGE_HAL_LRO_MAX_SG_SIZE 64 772 773 int lro_frm_len; 774 #define XGE_HAL_LRO_DEFAULT_FRM_LEN 65536 775 #define XGE_HAL_LRO_MIN_FRM_LEN 4096 776 #define XGE_HAL_LRO_MAX_FRM_LEN 65536 777 778 int bimodal_interrupts; 779 #define XGE_HAL_BIMODAL_INTR_MIN -1 780 #define XGE_HAL_BIMODAL_INTR_MAX 1 781 782 int bimodal_timer_lo_us; 783 #define XGE_HAL_BIMODAL_TIMER_LO_US_MIN 1 784 #define XGE_HAL_BIMODAL_TIMER_LO_US_MAX 127 785 786 int bimodal_timer_hi_us; 787 #define XGE_HAL_BIMODAL_TIMER_HI_US_MIN 128 788 #define XGE_HAL_BIMODAL_TIMER_HI_US_MAX 65535 789 790 int rts_qos_steering_config; 791 #define XGE_HAL_RTS_QOS_STEERING_DISABLE 0 792 #define XGE_HAL_RTS_QOS_STEERING_ENABLE 1 793 794 #ifdef XGEHAL_RNIC 795 796 int bitmap_intr_num; 797 #define XGE_HAL_BITMAP_INTR_NUM_MIN 1 798 #define XGE_HAL_BITMAP_INTR_NUM_MAX 64 799 800 int max_cqe_groups; 801 #define XGE_HAL_MAX_CQE_GROUPS_MIN 1 802 #define XGE_HAL_MAX_CQE_GROUPS_MAX 16 803 804 int max_num_wqe_od_groups; 805 #define XGE_HAL_MAX_NUM_OD_GROUPS_MIN 1 806 #define XGE_HAL_MAX_NUM_OD_GROUPS_MAX 16 807 808 int no_wqe_threshold; 809 #define XGE_HAL_NO_WQE_THRESHOLD_MIN 1 810 #define XGE_HAL_NO_WQE_THRESHOLD_MAX 16 811 812 int max_cqrq_per_bit; 813 #define XGE_HAL_MAX_CQRQ_PER_BIT_MIN 1 814 #define XGE_HAL_MAX_CQRQ_PER_BIT_MAX 16 815 816 int max_sess_per_bit; 817 #define XGE_HAL_MAX_SESS_PER_BIT_MIN 1 818 #define XGE_HAL_MAX_SESS_PER_BIT_MAX 16 819 820 int refill_threshold_high; 821 #define XGE_HAL_REFILL_THRESHOLD_HIGH_MIN 1 822 #define XGE_HAL_REFILL_THRESHOLD_HIGH_MAX 16 823 824 int refill_threshold_low; 825 #define XGE_HAL_REFILL_THRESHOLD_LOW_MIN 1 826 #define XGE_HAL_REFILL_THRESHOLD_LOW_MAX 16 827 828 int ack_blk_limit; 829 #define XGE_HAL_ACK_BLOCK_LIMIT_MIN 1 830 #define XGE_HAL_ACK_BLOCK_LIMIT_MAX 16 831 832 int poll_or_doorbell; 833 #define XGE_HAL_POLL_OR_DOORBELL_POLL 1 834 #define XGE_HAL_POLL_OR_DOORBELL_DOORBELL 0 835 836 837 #endif 838 839 } xge_hal_device_config_t; 840 841 /** 842 * struct xge_hal_driver_config_t - HAL (layer) configuration. 843 * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to 844 * periodically poll HAL, i.e, invoke 845 * xge_hal_device_poll(). 846 * Note that HAL does not maintain its own 847 * polling context. HAL relies on ULD to 848 * provide one. 849 * @queue_size_initial: Initial size of the HAL protected event queue. 850 * The queue is shared by HAL and upper-layer drivers. 851 * The queue is used to exchange and process slow-path 852 * events. See xge_hal_event_e. 853 * @queue_size_max: Maximum size of the HAL queue. Depending on the load, 854 * the queue may grow at run-time up to @queue_max_size. 855 * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable. 856 * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple) 857 * HAL devices.) 858 * Currently this structure contains just a few basic values. 859 * Note: Valid (min, max) range for each attribute is specified in the body of 860 * the structure. Please refer to the corresponding header file. 861 * See also: xge_hal_device_poll() 862 */ 863 typedef struct xge_hal_driver_config_t { 864 int queue_size_initial; 865 #define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1 866 #define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16 867 868 int queue_size_max; 869 #define XGE_HAL_MIN_QUEUE_SIZE_MAX 1 870 #define XGE_HAL_MAX_QUEUE_SIZE_MAX 16 871 872 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR 873 int tracebuf_size; 874 #define XGE_HAL_MIN_CIRCULAR_ARR 4096 875 #define XGE_HAL_MAX_CIRCULAR_ARR 65536 876 #define XGE_HAL_DEF_CIRCULAR_ARR 16384 877 #endif 878 879 } xge_hal_driver_config_t; 880 881 882 /* ========================== PRIVATE API ================================= */ 883 884 xge_hal_status_e 885 __hal_device_config_check_common (xge_hal_device_config_t *new_config); 886 887 xge_hal_status_e 888 __hal_device_config_check_xena (xge_hal_device_config_t *new_config); 889 890 xge_hal_status_e 891 __hal_device_config_check_herc (xge_hal_device_config_t *new_config); 892 893 xge_hal_status_e 894 __hal_driver_config_check (xge_hal_driver_config_t *new_config); 895 896 __EXTERN_END_DECLS 897 898 #endif /* XGE_HAL_CONFIG_H */ 899