1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #ifndef XGE_HAL_CONFIG_H 25 #define XGE_HAL_CONFIG_H 26 27 #include "xge-os-pal.h" 28 #include "xgehal-types.h" 29 #include "xge-queue.h" 30 31 __EXTERN_BEGIN_DECLS 32 33 #define XGE_HAL_DEFAULT_USE_HARDCODE -1 34 35 #define XGE_HAL_MAX_VIRTUAL_PATHS 8 36 #define XGE_HAL_MAX_INTR_PER_VP 4 37 38 39 /** 40 * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration. 41 * @enabled: Set to 1, if TTI feature is enabled. 42 * @urange_a: Link utilization range A. The value from 0 to 100%. 43 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 44 * each time when (and only when) the line is utilized no more 45 * than @urange_a percent in the transmit direction, 46 * and number of transmitted frames is greater or equal @ufc_a. 47 * @urange_b: Link utilization range B. 48 * @ufc_b: Frame count for the utilization range B. 49 * @urange_c: Link utilization range C. 50 * @ufc_c: Frame count for the utilization range C. 51 * @urange_d: Link utilization range D. 52 * @ufc_d: Frame count for the utilization range D. 53 * @timer_val_us: Interval of time, in microseconds, at which transmit timer 54 * interrupt is to be generated. Note that unless @timer_ci_en 55 * is set, the timer interrupt is generated only in presence 56 * of the transmit traffic. Note also that timer interrupt 57 * and utilization interrupt are two separate interrupt 58 * sources. 59 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 60 * interrupt was generated during the interval. 61 * @timer_ci_en: Enable/disable continuous interrupt. Set this value 62 * to 1 in order to generate continuous interrupt 63 * at fixed @timer_val intervals of time, independently 64 * of whether there is transmit traffic or not. 65 * @enabled: Set to 1, if TTI feature is enabled. 66 * 67 * Xframe transmit interrupt configuration. 68 * See Xframe User Guide, Section 3.5 "Device Interrupts" 69 * for more details. Note also (min, max) 70 * ranges in the body of the xge_hal_tx_intr_config_t structure. 71 * Note: Valid (min, max) range for each attribute is specified in the body of 72 * the xge_hal_tti_config_t{} structure. Please refer to the 73 * corresponding header file. 74 */ 75 typedef struct xge_hal_tti_config_t { 76 77 int enabled; 78 #define XGE_HAL_TTI_ENABLE 1 79 #define XGE_HAL_TTI_DISABLE 0 80 81 /* Line utilization interrupts */ 82 83 int urange_a; 84 #define XGE_HAL_MIN_TX_URANGE_A 0 85 #define XGE_HAL_MAX_TX_URANGE_A 100 86 87 int ufc_a; 88 #define XGE_HAL_MIN_TX_UFC_A 0 89 #define XGE_HAL_MAX_TX_UFC_A 65535 90 91 int urange_b; 92 #define XGE_HAL_MIN_TX_URANGE_B 0 93 #define XGE_HAL_MAX_TX_URANGE_B 100 94 95 int ufc_b; 96 #define XGE_HAL_MIN_TX_UFC_B 0 97 #define XGE_HAL_MAX_TX_UFC_B 65535 98 99 int urange_c; 100 #define XGE_HAL_MIN_TX_URANGE_C 0 101 #define XGE_HAL_MAX_TX_URANGE_C 100 102 103 int ufc_c; 104 #define XGE_HAL_MIN_TX_UFC_C 0 105 #define XGE_HAL_MAX_TX_UFC_C 65535 106 107 int ufc_d; 108 #define XGE_HAL_MIN_TX_UFC_D 0 109 #define XGE_HAL_MAX_TX_UFC_D 65535 110 111 int timer_val_us; 112 #define XGE_HAL_MIN_TX_TIMER_VAL 0 113 #define XGE_HAL_MAX_TX_TIMER_VAL 65535 114 115 int timer_ac_en; 116 #define XGE_HAL_MIN_TX_TIMER_AC_EN 0 117 #define XGE_HAL_MAX_TX_TIMER_AC_EN 1 118 119 int timer_ci_en; 120 #define XGE_HAL_MIN_TX_TIMER_CI_EN 0 121 #define XGE_HAL_MAX_TX_TIMER_CI_EN 1 122 123 124 } xge_hal_tti_config_t; 125 126 /** 127 * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration. 128 * @urange_a: Link utilization range A. The value from 0 to 100%. 129 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 130 * each time when (and only when) the line is utilized no more 131 * than @urange_a percent inbound, 132 * and number of received frames is greater or equal @ufc_a. 133 * @urange_b: Link utilization range B. 134 * @ufc_b: Frame count for the utilization range B. 135 * @urange_c: Link utilization range C. 136 * @ufc_c: Frame count for the utilization range C. 137 * @urange_d: Link utilization range D. 138 * @ufc_d: Frame count for the utilization range D. 139 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 140 * interrupt was generated during the interval. 141 * @timer_val_us: Interval of time, in microseconds, at which receive timer 142 * interrupt is to be generated. The timer interrupt is generated 143 * only in presence of the inbound traffic. Note also that timer 144 * interrupt and utilization interrupt are two separate interrupt 145 * sources. 146 * 147 * Xframe receive interrupt configuration. 148 * See Xframe User Guide, Section 3.5 "Device Interrupts" 149 * for more details. Note also (min, max) 150 * ranges in the body of the xge_hal_intr_config_t structure. 151 * Note: Valid (min, max) range for each attribute is specified in the body of 152 * the xge_hal_rti_config_t{} structure. Please refer to the 153 * corresponding header file. 154 */ 155 typedef struct xge_hal_rti_config_t { 156 157 int urange_a; 158 #define XGE_HAL_MIN_RX_URANGE_A 0 159 #define XGE_HAL_MAX_RX_URANGE_A 127 160 161 int ufc_a; 162 #define XGE_HAL_MIN_RX_UFC_A 0 163 #define XGE_HAL_MAX_RX_UFC_A 65535 164 165 int urange_b; 166 #define XGE_HAL_MIN_RX_URANGE_B 0 167 #define XGE_HAL_MAX_RX_URANGE_B 127 168 169 int ufc_b; 170 #define XGE_HAL_MIN_RX_UFC_B 0 171 #define XGE_HAL_MAX_RX_UFC_B 65535 172 173 int urange_c; 174 #define XGE_HAL_MIN_RX_URANGE_C 0 175 #define XGE_HAL_MAX_RX_URANGE_C 127 176 177 int ufc_c; 178 #define XGE_HAL_MIN_RX_UFC_C 0 179 #define XGE_HAL_MAX_RX_UFC_C 65535 180 181 int ufc_d; 182 #define XGE_HAL_MIN_RX_UFC_D 0 183 #define XGE_HAL_MAX_RX_UFC_D 65535 184 185 int timer_ac_en; 186 #define XGE_HAL_MIN_RX_TIMER_AC_EN 0 187 #define XGE_HAL_MAX_RX_TIMER_AC_EN 1 188 189 int timer_val_us; 190 #define XGE_HAL_MIN_RX_TIMER_VAL 0 191 #define XGE_HAL_MAX_RX_TIMER_VAL 65535 192 193 } xge_hal_rti_config_t; 194 195 /** 196 * struct xge_hal_fifo_queue_t - Single fifo configuration. 197 * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue. 198 * @initial: Initial numbers of TxDLs per queue (can grow up to @max). 199 * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. 200 * Use 0 otherwise. 201 * @intr_vector: TBD 202 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 203 * which generally improves latency of the host bridge operation 204 * (see PCI specification). For valid values please refer 205 * to xge_hal_fifo_queue_t{} in the driver sources. 206 * @priority: TBD 207 * @configured: Boolean. Use 1 to specify that the fifo is configured. 208 * Only "configured" fifos can be activated and used to post 209 * Tx descriptors. Any subset of 8 available fifos can be 210 * "configured". 211 * @tti: TBD 212 * 213 * Single fifo configuration. 214 * Note: Valid (min, max) range for each attribute is specified in the body of 215 * the xge_hal_fifo_queue_t{} structure. Please refer to the 216 * corresponding header file. 217 * See also: xge_hal_fifo_config_t{} 218 */ 219 typedef struct xge_hal_fifo_queue_t { 220 int max; 221 int initial; 222 #define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2 223 #define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192 224 225 int intr; 226 #define XGE_HAL_MIN_FIFO_QUEUE_INTR 0 227 #define XGE_HAL_MAX_FIFO_QUEUE_INTR 1 228 229 int intr_vector; 230 #define XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR 0 231 #define XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR 64 232 233 int no_snoop_bits; 234 #define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0 235 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1 236 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2 237 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3 238 239 int priority; 240 #define XGE_HAL_MIN_FIFO_PRIORITY 0 241 #define XGE_HAL_MAX_FIFO_PRIORITY 63 242 243 int configured; 244 #define XGE_HAL_MIN_FIFO_CONFIGURED 0 245 #define XGE_HAL_MAX_FIFO_CONFIGURED 1 246 247 #define XGE_HAL_MAX_FIFO_TTI_NUM 7 248 #define XGE_HAL_MAX_FIFO_TTI_RING_0 56 249 xge_hal_tti_config_t tti[XGE_HAL_MAX_FIFO_TTI_NUM]; 250 251 } xge_hal_fifo_queue_t; 252 253 /** 254 * struct xge_hal_fifo_config_t - Configuration of all 8 fifos. 255 * @max_frags: Max number of Tx buffers per TxDL (that is, per single 256 * transmit operation). 257 * No more than 256 transmit buffers can be specified. 258 * @max_aligned_frags: Number of fragments to be aligned out of 259 * maximum fragments (see @max_frags). 260 * @reserve_threshold: Descriptor reservation threshold. 261 * At least @reserve_threshold descriptors will remain 262 * unallocated at all times. 263 * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size 264 * bytes. Setting @memblock_size to page size ensures 265 * by-page allocation of descriptors. 128K bytes is the 266 * maximum supported block size. 267 * @queue: Array of per-fifo configurations. 268 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data 269 * (e.g., to align on a cache line). 270 * 271 * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t 272 * structures. 273 * Note: Valid (min, max) range for each attribute is specified in the body of 274 * the xge_hal_fifo_config_t{} structure. Please refer to the 275 * corresponding header file. 276 * See also: xge_hal_ring_queue_t{}. 277 */ 278 typedef struct xge_hal_fifo_config_t { 279 int max_frags; 280 #define XGE_HAL_MIN_FIFO_FRAGS 1 281 #define XGE_HAL_MAX_FIFO_FRAGS 256 282 283 int reserve_threshold; 284 #define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0 285 #define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192 286 287 int memblock_size; 288 #define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096 289 #define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072 290 291 int alignment_size; 292 #define XGE_HAL_MIN_ALIGNMENT_SIZE 0 293 #define XGE_HAL_MAX_ALIGNMENT_SIZE 65536 294 295 int max_aligned_frags; 296 /* range: (1, @max_frags) */ 297 298 #define XGE_HAL_MIN_FIFO_NUM 1 299 #define XGE_HAL_MAX_FIFO_NUM_HERC 8 300 #define XGE_HAL_MAX_FIFO_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 301 #define XGE_HAL_MAX_FIFO_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 302 xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM]; 303 } xge_hal_fifo_config_t; 304 305 /** 306 * struct xge_hal_rts_port_t - RTS port entry 307 * @num: Port number 308 * @udp: Port is UDP (default TCP) 309 * @src: Port is Source (default Destination) 310 */ 311 typedef struct xge_hal_rts_port_t { 312 int num; 313 int udp; 314 int src; 315 } xge_hal_rts_port_t; 316 317 /** 318 * struct xge_hal_ring_queue_t - Single ring configuration. 319 * @max: Max numbers of RxD blocks per queue 320 * @initial: Initial numbers of RxD blocks per queue 321 * (can grow up to @max) 322 * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer 323 * to Xframe User Guide. 324 * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring. 325 * Note that 64MB of available 326 * on-board DRAM is shared between receive rings. 327 * If a single ring is used, @dram_size_mb can be set to 64. 328 * Sum of all rings' @dram_size_mb cannot exceed 64. 329 * @intr_vector: TBD 330 * @backoff_interval_us: Time (in microseconds), after which Xframe 331 * tries to download RxDs posted by the host. 332 * Note that the "backoff" does not happen if host posts receive 333 * descriptors in the timely fashion. 334 * @max_frm_len: Maximum frame length that can be received on _that_ ring. 335 * Setting this field to -1 ensures that the ring will 336 * "accept" MTU-size frames (note that MTU can be changed at 337 * runtime). 338 * Any value other than (-1) specifies a certain "hard" 339 * limit on the receive frame sizes. 340 * The field can be used to activate receive frame-length based 341 * steering. 342 * @priority: Ring priority. 0 - highest, 7 - lowest. The value is used 343 * to give prioritized access to PCI-X. See Xframe documentation 344 * for details. 345 * @rth_en: Enable Receive Traffic Hashing (RTH). 346 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 347 * which generally improves latency of the host bridge operation 348 * (see PCI specification). For valid values please refer 349 * to xge_hal_ring_queue_t{} in the driver sources. 350 * @indicate_max_pkts: Sets maximum number of received frames to be processed 351 * within single interrupt. 352 * @configured: Boolean. Use 1 to specify that the ring is configured. 353 * Only "configured" rings can be activated and used to post 354 * Rx descriptors. Any subset of 8 available rings can be 355 * "configured". 356 * @rts_mac_en: 1 - To enable Receive MAC address steering. 357 * 0 - To disable Receive MAC address steering. 358 * @rth_en: TBD 359 * @rts_port_en: TBD 360 * @rts_ports: TBD 361 * @rti: Xframe receive interrupt configuration. 362 * 363 * Single ring configuration. 364 * Note: Valid (min, max) range for each attribute is specified in the body of 365 * the xge_hal_ring_queue_t{} structure. Please refer to the 366 * corresponding header file. 367 * See also: xge_hal_fifo_config_t{}. 368 */ 369 typedef struct xge_hal_ring_queue_t { 370 int max; 371 int initial; 372 #define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1 373 #define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64 374 375 int buffer_mode; 376 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1 377 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_2 2 378 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3 379 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5 380 381 int dram_size_mb; 382 #define XGE_HAL_MIN_RING_QUEUE_SIZE 0 383 #define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64 384 #define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32 385 386 int intr_vector; 387 #define XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR 0 388 #define XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR 64 389 390 int backoff_interval_us; 391 #define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1 392 #define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 393 394 int max_frm_len; 395 #define XGE_HAL_MIN_MAX_FRM_LEN -1 396 #define XGE_HAL_MAX_MAX_FRM_LEN 9622 397 398 int priority; 399 #define XGE_HAL_MIN_RING_PRIORITY 0 400 #define XGE_HAL_MAX_RING_PRIORITY 7 401 402 int no_snoop_bits; 403 #define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0 404 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1 405 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2 406 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3 407 408 int indicate_max_pkts; 409 #define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 410 #define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 411 412 int configured; 413 #define XGE_HAL_MIN_RING_CONFIGURED 0 414 #define XGE_HAL_MAX_RING_CONFIGURED 1 415 416 int rts_mac_en; 417 #define XGE_HAL_MIN_RING_RTS_MAC_EN 0 418 #define XGE_HAL_MAX_RING_RTS_MAC_EN 1 419 420 int rth_en; 421 #define XGE_HAL_MIN_RING_RTH_EN 0 422 #define XGE_HAL_MAX_RING_RTH_EN 1 423 424 int rts_port_en; 425 #define XGE_HAL_MIN_RING_RTS_PORT_EN 0 426 #define XGE_HAL_MAX_RING_RTS_PORT_EN 1 427 428 #define XGE_HAL_MAX_STEERABLE_PORTS 32 429 xge_hal_rts_port_t rts_ports[XGE_HAL_MAX_STEERABLE_PORTS]; 430 431 xge_hal_rti_config_t rti; 432 433 } xge_hal_ring_queue_t; 434 435 /** 436 * struct xge_hal_ring_config_t - Array of ring configurations. 437 * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size 438 * bytes. Setting @memblock_size to page size ensures 439 * by-page allocation of descriptors. 128K bytes is the 440 * upper limit. 441 * @scatter_mode: Xframe supports two receive scatter modes: A and B. 442 * For details please refer to Xframe User Guide. 443 * @strip_vlan_tag: TBD 444 * @queue: Array of all Xframe ring configurations. 445 * 446 * Array of ring configurations. 447 * See also: xge_hal_ring_queue_t{}. 448 */ 449 typedef struct xge_hal_ring_config_t { 450 451 int memblock_size; 452 #define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096 453 #define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072 454 455 int scatter_mode; 456 #define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0 457 #define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1 458 459 int strip_vlan_tag; 460 #define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0 461 #define XGE_HAL_RING_STRIP_VLAN_TAG 1 462 463 #define XGE_HAL_MIN_RING_NUM 1 464 #define XGE_HAL_MAX_RING_NUM_HERC 8 465 #define XGE_HAL_MAX_RING_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 466 #define XGE_HAL_MAX_RING_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 467 xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM]; 468 469 } xge_hal_ring_config_t; 470 471 /** 472 * struct xge_hal_mac_config_t - MAC configuration. 473 * @media: Transponder type. 474 * @tmac_util_period: The sampling period over which the transmit utilization 475 * is calculated. 476 * @rmac_util_period: The sampling period over which the receive utilization 477 * is calculated. 478 * @rmac_strip_pad: Determines whether padding of received frames is removed by 479 * the MAC or sent to the host. 480 * @rmac_bcast_en: Enable frames containing broadcast address to be 481 * passed to the host. 482 * @rmac_pause_gen_en: Received pause generation enable. 483 * @rmac_pause_rcv_en: Receive pause enable. 484 * @rmac_pause_time: The value to be inserted in outgoing pause frames. 485 * Has units of pause quanta (one pause quanta = 512 bit times). 486 * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation 487 * for queues 0 through 3. The threshold value indicates portion of the 488 * individual receive buffer queue size. Thresholds have a range of 0 to 489 * 255, allowing 256 possible watermarks in a queue. 490 * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation 491 * for queues 4 through 7. The threshold value indicates portion of the 492 * individual receive buffer queue size. Thresholds have a range of 0 to 493 * 255, allowing 256 possible watermarks in a queue. 494 * 495 * MAC configuration. This includes various aspects of configuration, including: 496 * - Pause frame threshold; 497 * - sampling rate to calculate link utilization; 498 * - enabling/disabling broadcasts. 499 * 500 * See Xframe User Guide for more details. 501 * Note: Valid (min, max) range for each attribute is specified in the body of 502 * the xge_hal_mac_config_t{} structure. Please refer to the 503 * corresponding include file. 504 */ 505 typedef struct xge_hal_mac_config_t { 506 int media; 507 #define XGE_HAL_MIN_MEDIA 0 508 #define XGE_HAL_MEDIA_SR 0 509 #define XGE_HAL_MEDIA_SW 1 510 #define XGE_HAL_MEDIA_LR 2 511 #define XGE_HAL_MEDIA_LW 3 512 #define XGE_HAL_MEDIA_ER 4 513 #define XGE_HAL_MEDIA_EW 5 514 #define XGE_HAL_MAX_MEDIA 5 515 516 int tmac_util_period; 517 #define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0 518 #define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15 519 520 int rmac_util_period; 521 #define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0 522 #define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15 523 524 int rmac_bcast_en; 525 #define XGE_HAL_MIN_RMAC_BCAST_EN 0 526 #define XGE_HAL_MAX_RMAC_BCAST_EN 1 527 528 int rmac_pause_gen_en; 529 #define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0 530 #define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1 531 532 int rmac_pause_rcv_en; 533 #define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0 534 #define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1 535 536 int rmac_pause_time; 537 #define XGE_HAL_MIN_RMAC_HIGH_PTIME 16 538 #define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535 539 540 int mc_pause_threshold_q0q3; 541 #define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0 542 #define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254 543 544 int mc_pause_threshold_q4q7; 545 #define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0 546 #define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254 547 548 } xge_hal_mac_config_t; 549 550 /** 551 * struct xge_hal_device_config_t - Device configuration. 552 * @mtu: Current mtu size. 553 * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx 554 * completions. Used in xge_hal_device_handle_irq(). 555 * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance 556 * with the PCI Specification, the value of the Latency Timer 557 * for this PCI bus master. 558 * Specify either zero or -1 to use BIOS default. 559 * @napi_weight: (TODO) 560 * @max_splits_trans: Maximum number of PCI-X split transactions. 561 * Specify (-1) to use BIOS default. 562 * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default 563 * BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B; 564 * 1 - 1KB, 2 - 2KB, and 3 - 4KB. 565 * @shared_splits: The number of Outstanding Split Transactions that is 566 * shared by Tx and Rx requests. The device stops issuing Tx 567 * requests once the number of Outstanding Split Transactions is 568 * equal to the value of Shared_Splits. 569 * A value of zero indicates that the Tx and Rx share all allocated 570 * Split Requests, i.e. the device can issue both types (Tx and Rx) 571 * of read requests until the number of Maximum Outstanding Split 572 * Transactions is reached. 573 * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer 574 * to the host. This includes MAC stats as well as PCI stats. 575 * See xge_hal_stats_hw_info_t{}. 576 * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz. 577 * @intr_mode: Line, MSI, or MSI-X interrupt. 578 * @sched_timer_us: If greater than zero, specifies time interval 579 * (in microseconds) for the device to generate 580 * interrupt. Note that unlike tti and rti interrupts, 581 * the scheduled interrupt is generated independently of 582 * whether there is transmit or receive traffic, respectively. 583 * @sched_timer_one_shot: 1 - generate scheduled interrupt only once. 584 * 0 - generate scheduled interrupt periodically at the specified 585 * @sched_timer_us interval. 586 * 587 * @ring: See xge_hal_ring_config_t{}. 588 * @mac: See xge_hal_mac_config_t{}. 589 * @tti: See xge_hal_tti_config_t{}. 590 * @fifo: See xge_hal_fifo_config_t{}. 591 * 592 * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#. 593 * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on 594 * ECC error. 595 * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on 596 * parity error. 597 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). 598 * @rth_bucket_size: RTH bucket width (in bits). For valid range please see 599 * xge_hal_device_config_t{} in the driver sources. 600 * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair 601 * Direct Match). 602 * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of 603 * hash value in the RTH SPDM based steering. 604 * @rxufca_intr_thres: (TODO) 605 * @rxufca_lo_lim: (TODO) 606 * @rxufca_hi_lim: (TODO) 607 * @rxufca_lbolt_period: (TODO) 608 * @link_valid_cnt: link-valid counting is done only at device-open time, 609 * to determine with the specified certainty that the link is up. See also 610 * @link_retry_cnt. 611 * @link_retry_cnt: Max number of polls for link-up. Done only at device 612 * open time. Reducing this value as well as the previous @link_valid_cnt, 613 * speeds up device startup, which may be important if the driver 614 * is compiled into OS. 615 * @link_stability_period: Specify the period for which the link must be 616 * stable in order for the adapter to declare "LINK UP". 617 * The enumerated settings (see Xframe-II UG) are: 618 * 0 ........... instantaneous 619 * 1 ........... 500 �s 620 * 2 ........... 1 ms 621 * 3 ........... 64 ms 622 * 4 ........... 256 ms 623 * 5 ........... 512 ms 624 * 6 ........... 1 s 625 * 7 ........... 2 s 626 * @device_poll_millis: Specify the interval (in mulliseconds) between 627 * successive xge_hal_device_poll() runs. 628 * stable in order for the adapter to declare "LINK UP". 629 * @no_isr_events: TBD 630 * @lro_sg_size: TBD 631 * @lro_frm_len: TBD 632 * @bimodal_interrupts: Enable bimodal interrupts in device 633 * @bimodal_timer_lo_us: TBD 634 * @bimodal_timer_hi_us: TBD 635 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address 636 * @rts_qos_en: TBD 637 * @rts_port_en: TBD 638 * @vp_config: Configuration for virtual paths 639 * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ 640 * can own at any one time. 641 * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that 642 * this S-RQ can own at any one time. 643 * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for 644 * WQEs before generating a message or interrupt. 645 * @refill_threshold_high:This field provides a hysteresis upper bound for 646 * automatic adapter refill operations. 647 * @refill_threshold_low:This field provides a hysteresis lower bound for 648 * automatic adapter refill operations. 649 * @eol_policy:This field sets the policy for handling the end of list condition. 650 * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0. 651 * 2'b01 - Send UMQ message when EOL is reached. 652 * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message 653 * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for 654 * a non-zero block wrapper before giving up and sending a UMQ message 655 * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be held 656 * by a session at any one time. 657 * @poll_or_doorbell: TBD 658 * 659 * Xframe configuration. 660 * Contains per-device configuration parameters, including: 661 * - latency timer (settable via PCI configuration space); 662 * - maximum number of split transactions; 663 * - maximum number of shared splits; 664 * - stats sampling interval, etc. 665 * 666 * In addition, xge_hal_device_config_t{} includes "subordinate" 667 * configurations, including: 668 * - fifos and rings; 669 * - MAC (see xge_hal_mac_config_t{}). 670 * 671 * See Xframe User Guide for more details. 672 * Note: Valid (min, max) range for each attribute is specified in the body of 673 * the xge_hal_device_config_t{} structure. Please refer to the 674 * corresponding include file. 675 * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{}, 676 * xge_hal_mac_config_t{}. 677 */ 678 typedef struct xge_hal_device_config_t { 679 int mtu; 680 #define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU 681 #define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU 682 683 int isr_polling_cnt; 684 #define XGE_HAL_MIN_ISR_POLLING_CNT 0 685 #define XGE_HAL_MAX_ISR_POLLING_CNT 65536 686 687 int latency_timer; 688 #define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1 689 #define XGE_HAL_MIN_LATENCY_TIMER 8 690 #define XGE_HAL_MAX_LATENCY_TIMER 255 691 692 int napi_weight; 693 #define XGE_HAL_DEF_NAPI_WEIGHT 64 694 695 int max_splits_trans; 696 #define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1 697 #define XGE_HAL_ONE_SPLIT_TRANSACTION 0 698 #define XGE_HAL_TWO_SPLIT_TRANSACTION 1 699 #define XGE_HAL_THREE_SPLIT_TRANSACTION 2 700 #define XGE_HAL_FOUR_SPLIT_TRANSACTION 3 701 #define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4 702 #define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5 703 #define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6 704 #define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7 705 706 int mmrb_count; 707 #define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 708 #define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */ 709 #define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */ 710 711 int shared_splits; 712 #define XGE_HAL_MIN_SHARED_SPLITS 0 713 #define XGE_HAL_MAX_SHARED_SPLITS 31 714 715 int stats_refresh_time_sec; 716 #define XGE_HAL_STATS_REFRESH_DISABLE 0 717 #define XGE_HAL_MIN_STATS_REFRESH_TIME 1 718 #define XGE_HAL_MAX_STATS_REFRESH_TIME 300 719 720 int pci_freq_mherz; 721 #define XGE_HAL_PCI_FREQ_MHERZ_33 33 722 #define XGE_HAL_PCI_FREQ_MHERZ_66 66 723 #define XGE_HAL_PCI_FREQ_MHERZ_100 100 724 #define XGE_HAL_PCI_FREQ_MHERZ_133 133 725 #define XGE_HAL_PCI_FREQ_MHERZ_266 266 726 727 int intr_mode; 728 #define XGE_HAL_INTR_MODE_IRQLINE 0 729 #define XGE_HAL_INTR_MODE_MSI 1 730 #define XGE_HAL_INTR_MODE_MSIX 2 731 732 int sched_timer_us; 733 #define XGE_HAL_SCHED_TIMER_DISABLED 0 734 #define XGE_HAL_SCHED_TIMER_MIN 0 735 #define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF 736 737 int sched_timer_one_shot; 738 #define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0 739 #define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1 740 741 xge_hal_ring_config_t ring; 742 xge_hal_mac_config_t mac; 743 xge_hal_fifo_config_t fifo; 744 745 int dump_on_serr; 746 #define XGE_HAL_DUMP_ON_SERR_DISABLE 0 747 #define XGE_HAL_DUMP_ON_SERR_ENABLE 1 748 749 int dump_on_eccerr; 750 #define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0 751 #define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1 752 753 int dump_on_parityerr; 754 #define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0 755 #define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1 756 757 int rth_en; 758 #define XGE_HAL_RTH_DISABLE 0 759 #define XGE_HAL_RTH_ENABLE 1 760 761 int rth_bucket_size; 762 #define XGE_HAL_MIN_RTH_BUCKET_SIZE 1 763 #define XGE_HAL_MAX_RTH_BUCKET_SIZE 8 764 765 int rth_spdm_en; 766 #define XGE_HAL_RTH_SPDM_DISABLE 0 767 #define XGE_HAL_RTH_SPDM_ENABLE 1 768 769 int rth_spdm_use_l4; 770 #define XGE_HAL_RTH_SPDM_USE_L4 1 771 772 int rxufca_intr_thres; 773 #define XGE_HAL_RXUFCA_INTR_THRES_MIN 1 774 #define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096 775 776 int rxufca_lo_lim; 777 #define XGE_HAL_RXUFCA_LO_LIM_MIN 1 778 #define XGE_HAL_RXUFCA_LO_LIM_MAX 16 779 780 int rxufca_hi_lim; 781 #define XGE_HAL_RXUFCA_HI_LIM_MIN 1 782 #define XGE_HAL_RXUFCA_HI_LIM_MAX 256 783 784 int rxufca_lbolt_period; 785 #define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1 786 #define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024 787 788 int link_valid_cnt; 789 #define XGE_HAL_LINK_VALID_CNT_MIN 0 790 #define XGE_HAL_LINK_VALID_CNT_MAX 127 791 792 int link_retry_cnt; 793 #define XGE_HAL_LINK_RETRY_CNT_MIN 0 794 #define XGE_HAL_LINK_RETRY_CNT_MAX 127 795 796 int link_stability_period; 797 #define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */ 798 #define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */ 799 #define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */ 800 801 int device_poll_millis; 802 #define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000 803 #define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1 804 #define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 805 806 int no_isr_events; 807 #define XGE_HAL_NO_ISR_EVENTS_MIN 0 808 #define XGE_HAL_NO_ISR_EVENTS_MAX 1 809 810 int lro_sg_size; 811 #define XGE_HAL_LRO_DEFAULT_SG_SIZE 10 812 #define XGE_HAL_LRO_MIN_SG_SIZE 1 813 #define XGE_HAL_LRO_MAX_SG_SIZE 64 814 815 int lro_frm_len; 816 #define XGE_HAL_LRO_DEFAULT_FRM_LEN 65536 817 #define XGE_HAL_LRO_MIN_FRM_LEN 4096 818 #define XGE_HAL_LRO_MAX_FRM_LEN 65536 819 820 int bimodal_interrupts; 821 #define XGE_HAL_BIMODAL_INTR_MIN -1 822 #define XGE_HAL_BIMODAL_INTR_MAX 1 823 824 int bimodal_timer_lo_us; 825 #define XGE_HAL_BIMODAL_TIMER_LO_US_MIN 1 826 #define XGE_HAL_BIMODAL_TIMER_LO_US_MAX 127 827 828 int bimodal_timer_hi_us; 829 #define XGE_HAL_BIMODAL_TIMER_HI_US_MIN 128 830 #define XGE_HAL_BIMODAL_TIMER_HI_US_MAX 65535 831 832 int rts_mac_en; 833 #define XGE_HAL_RTS_MAC_DISABLE 0 834 #define XGE_HAL_RTS_MAC_ENABLE 1 835 836 int rts_qos_en; 837 #define XGE_HAL_RTS_QOS_DISABLE 0 838 #define XGE_HAL_RTS_QOS_ENABLE 1 839 840 int rts_port_en; 841 #define XGE_HAL_RTS_PORT_DISABLE 0 842 #define XGE_HAL_RTS_PORT_ENABLE 1 843 844 } xge_hal_device_config_t; 845 846 /** 847 * struct xge_hal_driver_config_t - HAL (layer) configuration. 848 * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to 849 * periodically poll HAL, i.e, invoke 850 * xge_hal_device_poll(). 851 * Note that HAL does not maintain its own 852 * polling context. HAL relies on ULD to 853 * provide one. 854 * @queue_size_initial: Initial size of the HAL protected event queue. 855 * The queue is shared by HAL and upper-layer drivers. 856 * The queue is used to exchange and process slow-path 857 * events. See xge_hal_event_e. 858 * @queue_size_max: Maximum size of the HAL queue. Depending on the load, 859 * the queue may grow at run-time up to @queue_max_size. 860 * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable. 861 * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple) 862 * HAL devices.) 863 * Currently this structure contains just a few basic values. 864 * Note: Valid (min, max) range for each attribute is specified in the body of 865 * the structure. Please refer to the corresponding header file. 866 * See also: xge_hal_device_poll() 867 */ 868 typedef struct xge_hal_driver_config_t { 869 int queue_size_initial; 870 #define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1 871 #define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16 872 873 int queue_size_max; 874 #define XGE_HAL_MIN_QUEUE_SIZE_MAX 1 875 #define XGE_HAL_MAX_QUEUE_SIZE_MAX 16 876 877 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR 878 int tracebuf_size; 879 #define XGE_HAL_MIN_CIRCULAR_ARR 4096 880 #define XGE_HAL_MAX_CIRCULAR_ARR 1048576 881 #define XGE_HAL_DEF_CIRCULAR_ARR XGE_OS_HOST_PAGE_SIZE 882 883 int tracebuf_timestamp_en; 884 #define XGE_HAL_MIN_TIMESTAMP_EN 0 885 #define XGE_HAL_MAX_TIMESTAMP_EN 1 886 #endif 887 888 } xge_hal_driver_config_t; 889 890 891 /* ========================== PRIVATE API ================================= */ 892 893 xge_hal_status_e 894 __hal_device_config_check_common (xge_hal_device_config_t *new_config); 895 896 xge_hal_status_e 897 __hal_device_config_check_xena (xge_hal_device_config_t *new_config); 898 899 xge_hal_status_e 900 __hal_device_config_check_herc (xge_hal_device_config_t *new_config); 901 902 xge_hal_status_e 903 __hal_driver_config_check (xge_hal_driver_config_t *new_config); 904 905 __EXTERN_END_DECLS 906 907 #endif /* XGE_HAL_CONFIG_H */ 908