1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24 #ifndef XGE_HAL_CHANNEL_H 25 #define XGE_HAL_CHANNEL_H 26 27 #include "xge-os-pal.h" 28 #include "xge-list.h" 29 #include "xgehal-types.h" 30 #include "xgehal-stats.h" 31 32 __EXTERN_BEGIN_DECLS 33 34 /** 35 * enum xge_hal_channel_type_e - Enumerated channel types. 36 * @XGE_HAL_CHANNEL_TYPE_FIFO: fifo. 37 * @XGE_HAL_CHANNEL_TYPE_RING: ring. 38 * @XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: Send Queue 39 * @XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: Receive Queue 40 * @XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: Receive queue completion queue 41 * @XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: Up message queue 42 * @XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: Down message queue 43 * @XGE_HAL_CHANNEL_TYPE_MAX: Maximum number of HAL-supported 44 * (and recognized) channel types. Currently: two. 45 * 46 * Enumerated channel types. Currently there are only two link-layer 47 * channels - Xframe fifo and Xframe ring. In the future the list will grow. 48 */ 49 typedef enum xge_hal_channel_type_e { 50 XGE_HAL_CHANNEL_TYPE_FIFO, 51 XGE_HAL_CHANNEL_TYPE_RING, 52 XGE_HAL_CHANNEL_TYPE_SEND_QUEUE, 53 XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE, 54 XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE, 55 XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE, 56 XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE, 57 XGE_HAL_CHANNEL_TYPE_MAX 58 } xge_hal_channel_type_e; 59 60 /** 61 * enum xge_hal_channel_flag_e - Channel flags. 62 * @XGE_HAL_CHANNEL_FLAG_NONE: zero (nil) flag. 63 * @XGE_HAL_CHANNEL_FLAG_USE_TX_LOCK: use lock when posting transmit 64 * descriptor. 65 * @XGE_HAL_CHANNEL_FLAG_FREE_RXD: to-be-defined. 66 * 67 * Channel opening flags. Reserved for future usage. 68 */ 69 typedef enum xge_hal_channel_flag_e { 70 XGE_HAL_CHANNEL_FLAG_NONE = 0x0, 71 XGE_HAL_CHANNEL_FLAG_USE_TX_LOCK = 0x1, 72 XGE_HAL_CHANNEL_FLAG_FREE_RXD = 0x2 73 } xge_hal_channel_flag_e; 74 75 /** 76 * enum xge_hal_dtr_state_e - Descriptor (DTR) state. 77 * @XGE_HAL_DTR_STATE_NONE: Invalid state. 78 * @XGE_HAL_DTR_STATE_AVAIL: Descriptor is available for reservation 79 * (via xge_hal_fifo_dtr_reserve(), xge_hal_ring_dtr_reserve(), etc.). 80 * @XGE_HAL_DTR_STATE_POSTED: Descriptor is posted for processing by the 81 * device. 82 * @XGE_HAL_DTR_STATE_FREED: Descriptor is free and can be reused for 83 * filling-in and posting later. 84 * 85 * Xframe/HAL descriptor states. For more on descriptor states and transitions 86 * please refer to ch_intern{}. 87 * 88 * See also: xge_hal_channel_dtr_term_f{}. 89 */ 90 typedef enum xge_hal_dtr_state_e { 91 XGE_HAL_DTR_STATE_NONE = 0, 92 XGE_HAL_DTR_STATE_AVAIL = 1, 93 XGE_HAL_DTR_STATE_POSTED = 2, 94 XGE_HAL_DTR_STATE_FREED = 3 95 } xge_hal_dtr_state_e; 96 97 /** 98 * enum xge_hal_channel_reopen_e - Channel open, close, or reopen option. 99 * @XGE_HAL_CHANNEL_RESET_ONLY: Do not (de)allocate channel; used with 100 * xge_hal_channel_open(), xge_hal_channel_close(). 101 * @XGE_HAL_CHANNEL_OC_NORMAL: Do (de)allocate channel; used with 102 * xge_hal_channel_open(), xge_hal_channel_close(). 103 * 104 * Enumerates options used with channel open and close operations. 105 * The @XGE_HAL_CHANNEL_RESET_ONLY can be used when resetting the device; 106 * in this case there is actually no need to free and then again malloc 107 * the memory (including DMA-able memory) used for channel operation. 108 */ 109 typedef enum xge_hal_channel_reopen_e { 110 XGE_HAL_CHANNEL_RESET_ONLY = 1, 111 XGE_HAL_CHANNEL_OC_NORMAL = 2 112 } xge_hal_channel_reopen_e; 113 114 /** 115 * function xge_hal_channel_callback_f - Channel callback. 116 * @channelh: Channel "containing" 1 or more completed descriptors. 117 * @dtrh: First completed descriptor. 118 * @t_code: Transfer code, as per Xframe User Guide. 119 * Returned by HAL. 120 * @host_control: Opaque 64bit data stored by ULD inside the Xframe 121 * descriptor prior to posting the latter on the channel 122 * via xge_hal_fifo_dtr_post() or xge_hal_ring_dtr_post(). 123 * The @host_control is returned as is to the ULD with each 124 * completed descriptor. 125 * @userdata: Opaque per-channel data specified at channel open 126 * time, via xge_hal_channel_open(). 127 * 128 * Channel completion callback (type declaration). A single per-channel 129 * callback is specified at channel open time, via 130 * xge_hal_channel_open(). 131 * Typically gets called as part of the processing of the Interrupt 132 * Service Routine. 133 * 134 * Channel callback gets called by HAL if, and only if, there is at least 135 * one new completion on a given ring or fifo channel. Upon processing the 136 * first @dtrh ULD is _supposed_ to continue consuming completions 137 * using�one of the following HAL APIs: 138 * - xge_hal_fifo_dtr_next_completed() 139 * or 140 * - xge_hal_ring_dtr_next_completed(). 141 * 142 * Note that failure to process new completions in a timely fashion 143 * leads to XGE_HAL_INF_OUT_OF_DESCRIPTORS condition. 144 * 145 * Non-zero @t_code means failure to process (transmit or receive, depending 146 * on the channel type) the descriptor. 147 * 148 * In the "transmit" case the failure could happen, for instance, when the 149 * link is down, in which case Xframe completes the descriptor because it 150 * is not able to send the data out. 151 * 152 * For details please refer to Xframe User Guide. 153 * 154 * See also: xge_hal_fifo_dtr_next_completed(), 155 * xge_hal_ring_dtr_next_completed(), xge_hal_channel_dtr_term_f{}. 156 */ 157 typedef xge_hal_status_e (*xge_hal_channel_callback_f) 158 (xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 159 u8 t_code, void *userdata); 160 161 /** 162 * function xge_hal_channel_dtr_init_f - Initialize descriptor callback. 163 * @channelh: Channel "containing" the @dtrh descriptor. 164 * @dtrh: Descriptor. 165 * @index: Index of the descriptor in the channel's set of descriptors. 166 * @userdata: Per-channel user data (a.k.a. context) specified at 167 * channel open time, via xge_hal_channel_open(). 168 * @reopen: See xge_hal_channel_reopen_e{}. 169 * 170 * Initialize descriptor callback. Unless NULL is specified in the 171 * xge_hal_channel_attr_t{} structure passed to xge_hal_channel_open()), 172 * HAL invokes the callback as part of the xge_hal_channel_open() 173 * implementation. 174 * For the ring type of channel the ULD is expected to fill in this descriptor 175 * with buffer(s) and control information. 176 * For the fifo type of channel the ULD could use the callback to 177 * pre-set DMA mappings and/or alignment buffers. 178 * 179 * See also: xge_hal_channel_attr_t{}, xge_hal_channel_dtr_term_f{}. 180 */ 181 typedef xge_hal_status_e (*xge_hal_channel_dtr_init_f) 182 (xge_hal_channel_h channelh, 183 xge_hal_dtr_h dtrh, 184 int index, 185 void *userdata, 186 xge_hal_channel_reopen_e reopen); 187 188 /** 189 * function xge_hal_channel_dtr_term_f - Terminate descriptor callback. 190 * @channelh: Channel "containing" the @dtrh descriptor. 191 * @dtrh: First completed descriptor. 192 * @state: One of the xge_hal_dtr_state_e{} enumerated states. 193 * @userdata: Per-channel user data (a.k.a. context) specified at 194 * channel open time, via xge_hal_channel_open(). 195 * @reopen: See xge_hal_channel_reopen_e{}. 196 * 197 * Terminate descriptor callback. Unless NULL is specified in the 198 * xge_hal_channel_attr_t{} structure passed to xge_hal_channel_open()), 199 * HAL invokes the callback as part of closing the corresponding 200 * channel, prior to de-allocating the channel and associated data 201 * structures (including descriptors). 202 * ULD should utilize the callback to (for instance) unmap 203 * and free DMA data buffers associated with the posted (state = 204 * XGE_HAL_DTR_STATE_POSTED) descriptors, 205 * as well as other relevant cleanup functions. 206 * 207 * See also: xge_hal_channel_attr_t{}, xge_hal_channel_dtr_init_f{}. 208 */ 209 typedef void (*xge_hal_channel_dtr_term_f) (xge_hal_channel_h channelh, 210 xge_hal_dtr_h dtrh, 211 xge_hal_dtr_state_e state, 212 void *userdata, 213 xge_hal_channel_reopen_e reopen); 214 215 216 /** 217 * struct xge_hal_channel_attr_t - Channel open "template". 218 * @type: xge_hal_channel_type_e channel type. 219 * @vp_id: Virtual path id 220 * @post_qid: Queue ID to post descriptors. For the link layer this 221 * number should be in the 0..7 range. 222 * @compl_qid: Completion queue ID. Must be set to zero for the link layer. 223 * @callback: Channel completion callback. HAL invokes the callback when there 224 * are new completions on that channel. In many implementations 225 * the @callback executes in the hw interrupt context. 226 * @dtr_init: Channel's descriptor-initialize callback. 227 * See xge_hal_channel_dtr_init_f{}. 228 * If not NULL, HAL invokes the callback when opening 229 * the channel via xge_hal_channel_open(). 230 * @dtr_term: Channel's descriptor-terminate callback. If not NULL, 231 * HAL invokes the callback when closing the corresponding channel. 232 * See also xge_hal_channel_dtr_term_f{}. 233 * @userdata: User-defined "context" of _that_ channel. Passed back to the 234 * user as one of the @callback, @dtr_init, and @dtr_term arguments. 235 * @per_dtr_space: If specified (i.e., greater than zero): extra space 236 * reserved by HAL per each transmit or receive (depending on the 237 * channel type) descriptor. Can be used to store, 238 * and retrieve on completion, information specific 239 * to the upper-layer. 240 * @flags: xge_hal_channel_flag_e enumerated flags. 241 * 242 * Channel open "template". User fills the structure with channel 243 * attributes and passes it to xge_hal_channel_open(). 244 * Usage: See ex_open{}. 245 */ 246 typedef struct xge_hal_channel_attr_t { 247 xge_hal_channel_type_e type; 248 int post_qid; 249 int compl_qid; 250 xge_hal_channel_callback_f callback; 251 xge_hal_channel_dtr_init_f dtr_init; 252 xge_hal_channel_dtr_term_f dtr_term; 253 void *userdata; 254 int per_dtr_space; 255 xge_hal_channel_flag_e flags; 256 } xge_hal_channel_attr_t; 257 258 /* 259 * xge_hal_channel_t 260 * ---------- complete/free section --------------- 261 * @item: List item; used to maintain a list of open channels. 262 * @callback: Channel completion callback. See 263 * xge_hal_channel_callback_f. 264 * @compl_index: Completion index. At any point in time points on the 265 * position in the channel, which will contain next 266 * to-be-completed descriptor. 267 * @length: Channel length. Currently allocated number of descriptors. 268 * The channel length "grows" when more descriptors get allocated. 269 * See _hal_mempool_grow. 270 * @free_arr: Free array. Contains completed descriptors that were freed 271 * (i.e., handed over back to HAL) by ULD. 272 * See xge_hal_fifo_dtr_free(), xge_hal_ring_dtr_free(). 273 * @free_lock: Lock to protect @free_arr. 274 * ----------- reserve/post section --------------- 275 * @post_index: Post index. At any point in time points on the 276 * position in the channel, which'll contain next to-be-posted 277 * descriptor. 278 * @post_lock: Lock to serialize multiple concurrent "posters" of descriptors 279 * on the given channel. 280 * @reserve_arr: Reserve array. Contains descriptors that can be reserved 281 * by ULD for the subsequent send or receive operation. 282 * See xge_hal_fifo_dtr_reserve(), 283 * xge_hal_ring_dtr_reserve(). 284 * @reserve_length: Length of the @reserve_arr. The length dynamically 285 * changes: it decrements each time descriptor is reserved. 286 * @reserve_lock: Lock to serialize multiple concurrent threads accessing 287 * @reserve_arr. 288 * @reserve_threshold: Reserve threshold. Minimal number of free descriptors 289 * that ought to be preserved in the channel at all times. 290 * Note that @reserve_threshold >= 0 && 291 * @reserve_threshold < @reserve_max. 292 * ------------ common section -------------------- 293 * @devh: Device handle. HAL device object that contains _this_ channel. 294 * @dmah: Channel's DMA address. Used to synchronize (to/from device) 295 * descriptors. 296 * @regh0: Base address of the device memory space handle. Copied from HAL device 297 * at channel open time. 298 * @regh1: Base address of the device memory space handle. Copied from HAL device 299 * at channel open time. 300 * @userdata: Per-channel opaque (void*) user-defined context, which may be 301 * upper-layer driver object, ULP connection, etc. 302 * Once channel is open, @userdata is passed back to user via 303 * xge_hal_channel_callback_f. 304 * @work_arr: Work array. Contains descriptors posted to the channel. 305 * Note that at any point in time @work_arr contains 3 types of 306 * descriptors: 307 * 1) posted but not yet consumed by Xframe device; 308 * 2) consumed but not yet completed; 309 * 3) completed but not yet freed 310 * (via xge_hal_fifo_dtr_free() or xge_hal_ring_dtr_free()) 311 * @saved_arr: Array used internally to optimize channel full-duplex 312 * operation. 313 * @stats: Channel statistcis. Includes HAL internal counters, including 314 * for instance, number of times out-of-descriptors 315 * (see XGE_HAL_INF_OUT_OF_DESCRIPTORS) condition happened. 316 * ------------- "slow" section ------------------ 317 * @type: Channel type. See xge_hal_channel_type_e{}. 318 * @vp_id: Virtual path id 319 * @post_qid: Identifies Xframe queue used for posting descriptors. 320 * @compl_qid: Identifies Xframe completion queue. 321 * @flags: Channel flags. See xge_hal_channel_flag_e{}. 322 * @reserve_initial: Initial number of descriptors allocated at channel open 323 * time (see xge_hal_channel_open()). The number of 324 * channel descriptors can grow at runtime 325 * up to @reserve_max value. 326 * @reserve_max: Maximum number of channel descriptors. See @reserve_initial. 327 * @is_open: True, if channel is open; false - otherwise. 328 * @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize 329 * to store per-operation control information. 330 * HAL channel object. HAL devices (see xge_hal_device_t{}) contains 331 * zero or more channels. HAL channel contains zero or more descriptors. The 332 * latter are used by ULD(s) to manage the device and/or send and receive data 333 * to remote peer(s) via the channel. 334 * 335 * See also: xge_hal_channel_type_e{}, xge_hal_channel_flag_e, 336 * xge_hal_channel_callback_f{} 337 */ 338 typedef struct { 339 /* complete/free section */ 340 xge_list_t item; 341 xge_hal_channel_callback_f callback; 342 void **free_arr; 343 int length; 344 int free_length; 345 #if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ) || \ 346 defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE) 347 spinlock_t free_lock; 348 #endif 349 int compl_index; 350 unsigned int usage_cnt; 351 unsigned int poll_bytes; 352 353 /* reserve/post data path section */ 354 int terminating; 355 #ifdef __XGE_WIN__ 356 int __xge_os_attr_cacheline_aligned 357 post_index; 358 #else 359 int post_index 360 __xge_os_attr_cacheline_aligned; 361 #endif 362 spinlock_t reserve_lock; 363 spinlock_t post_lock; 364 365 void **reserve_arr; 366 int reserve_length; 367 int reserve_threshold; 368 int reserve_top; 369 int unused1; 370 371 /* common section */ 372 xge_hal_device_h devh; 373 pci_dev_h pdev; 374 pci_reg_h regh0; 375 pci_reg_h regh1; 376 void *userdata; 377 void **work_arr; 378 void **saved_arr; 379 void **orig_arr; 380 xge_hal_stats_channel_info_t stats; 381 382 /* slow section */ 383 xge_hal_channel_type_e type; 384 int post_qid; 385 int compl_qid; 386 xge_hal_channel_flag_e flags; 387 int reserve_initial; 388 int reserve_max; 389 int is_open; 390 int per_dtr_space; 391 xge_hal_channel_dtr_term_f dtr_term; 392 xge_hal_channel_dtr_init_f dtr_init; 393 /* MSI stuff */ 394 u32 msi_msg; 395 u8 rti; 396 u8 tti; 397 u16 unused2; 398 /* MSI-X stuff */ 399 u64 msix_address; 400 u32 msix_data; 401 int msix_idx; 402 volatile int in_interrupt; 403 unsigned int magic; 404 #ifdef __XGE_WIN__ 405 } __xge_os_attr_cacheline_aligned xge_hal_channel_t ; 406 #else 407 } xge_hal_channel_t __xge_os_attr_cacheline_aligned; 408 #endif 409 410 /* ========================== CHANNEL PRIVATE API ========================= */ 411 412 xge_hal_status_e 413 __hal_channel_initialize(xge_hal_channel_h channelh, 414 xge_hal_channel_attr_t *attr, void **reserve_arr, 415 int reserve_initial, int reserve_max, int reserve_threshold); 416 417 void __hal_channel_terminate(xge_hal_channel_h channelh); 418 419 xge_hal_channel_t* 420 __hal_channel_allocate(xge_hal_device_h devh, int post_qid, 421 xge_hal_channel_type_e type); 422 423 void __hal_channel_free(xge_hal_channel_t *channel); 424 425 #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_CHANNEL) 426 #define __HAL_STATIC_CHANNEL 427 #define __HAL_INLINE_CHANNEL 428 429 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 430 __hal_channel_dtr_alloc(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh); 431 432 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 433 __hal_channel_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 434 435 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 436 __hal_channel_dtr_try_complete(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh); 437 438 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 439 __hal_channel_dtr_complete(xge_hal_channel_h channelh); 440 441 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 442 __hal_channel_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 443 444 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 445 __hal_channel_dtr_dealloc(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 446 447 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 448 __hal_channel_dtr_restore(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 449 int offset); 450 451 /* ========================== CHANNEL PUBLIC API ========================= */ 452 453 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int 454 xge_hal_channel_dtr_count(xge_hal_channel_h channelh); 455 456 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void* 457 xge_hal_channel_userdata(xge_hal_channel_h channelh); 458 459 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int 460 xge_hal_channel_id(xge_hal_channel_h channelh); 461 462 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int 463 xge_hal_check_alignment(dma_addr_t dma_pointer, int size, int alignment, 464 int copy_size); 465 466 #else /* XGE_FASTPATH_EXTERN */ 467 #define __HAL_STATIC_CHANNEL static 468 #define __HAL_INLINE_CHANNEL inline 469 #include "xgehal-channel-fp.c" 470 #endif /* XGE_FASTPATH_INLINE */ 471 472 xge_hal_status_e 473 xge_hal_channel_open(xge_hal_device_h hldev, xge_hal_channel_attr_t *attr, 474 xge_hal_channel_h *channel, 475 xge_hal_channel_reopen_e reopen); 476 477 void xge_hal_channel_close(xge_hal_channel_h channelh, 478 xge_hal_channel_reopen_e reopen); 479 480 void xge_hal_channel_abort(xge_hal_channel_h channelh, 481 xge_hal_channel_reopen_e reopen); 482 483 __EXTERN_END_DECLS 484 485 #endif /* XGE_HAL_CHANNEL_H */ 486