1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2002-2005 Neterion, Inc. 29 * All right Reserved. 30 * 31 * FileName : xgell.h 32 * 33 * Description: Link Layer driver declaration 34 * 35 */ 36 37 #ifndef _SYS_XGELL_H 38 #define _SYS_XGELL_H 39 40 #pragma ident "%Z%%M% %I% %E% SMI" 41 42 #include <sys/types.h> 43 #include <sys/errno.h> 44 #include <sys/param.h> 45 #include <sys/stropts.h> 46 #include <sys/stream.h> 47 #include <sys/strsubr.h> 48 #include <sys/kmem.h> 49 #include <sys/conf.h> 50 #include <sys/devops.h> 51 #include <sys/ksynch.h> 52 #include <sys/stat.h> 53 #include <sys/modctl.h> 54 #include <sys/debug.h> 55 #include <sys/pci.h> 56 #include <sys/ethernet.h> 57 #include <sys/vlan.h> 58 #include <sys/dlpi.h> 59 #include <sys/taskq.h> 60 #include <sys/cyclic.h> 61 62 #include <sys/pattr.h> 63 #include <sys/strsun.h> 64 65 #include <sys/mac.h> 66 #include <sys/mac_ether.h> 67 68 #ifdef __cplusplus 69 extern "C" { 70 #endif 71 72 #define XGELL_DESC "Xframe I/II 10Gb Ethernet %I%" 73 #define XGELL_IFNAME "xge" 74 #define XGELL_TX_LEVEL_LOW 8 75 #define XGELL_TX_LEVEL_HIGH 32 76 77 #include <xgehal.h> 78 79 /* 80 * These default values can be overridden by vaules in xge.conf. 81 * In xge.conf user has to specify actual (not percentages) values. 82 */ 83 #define XGELL_RX_BUFFER_TOTAL XGE_HAL_RING_RXDS_PER_BLOCK(1) * 6 84 #define XGELL_RX_BUFFER_POST_HIWAT XGE_HAL_RING_RXDS_PER_BLOCK(1) * 5 85 86 /* Control driver to copy or DMA received packets */ 87 #define XGELL_RX_DMA_LOWAT 256 88 89 #define XGELL_RING_MAIN_QID 0 90 91 #if defined(__x86) 92 #define XGELL_TX_DMA_LOWAT 128 93 #else 94 #define XGELL_TX_DMA_LOWAT 1024 95 #endif 96 97 /* 98 * Try to collapse up to XGELL_RX_PKT_BURST packets into single mblk 99 * sequence before mac_rx() is called. 100 */ 101 #define XGELL_RX_PKT_BURST 32 102 103 /* About 1s */ 104 #define XGE_DEV_POLL_TICKS drv_usectohz(1000000) 105 106 #define XGELL_LSO_MAXLEN 65535 107 #define XGELL_CONF_ENABLE_BY_DEFAULT 1 108 #define XGELL_CONF_DISABLE_BY_DEFAULT 0 109 110 /* LRO configuration */ 111 #define XGE_HAL_DEFAULT_LRO_SG_SIZE 8 /* <=2 LRO fix not required */ 112 #define XGE_HAL_DEFAULT_LRO_FRM_LEN 65535 113 114 /* 115 * If HAL could provide defualt values to all tunables, we'll remove following 116 * macros. 117 * Before removing, please refer to xgehal-config.h for more details. 118 */ 119 #define XGE_HAL_DEFAULT_USE_HARDCODE -1 120 121 /* bimodal adaptive schema defaults - ENABLED */ 122 #define XGE_HAL_DEFAULT_BIMODAL_INTERRUPTS -1 123 #define XGE_HAL_DEFAULT_BIMODAL_TIMER_LO_US 24 124 #define XGE_HAL_DEFAULT_BIMODAL_TIMER_HI_US 256 125 126 /* interrupt moderation/utilization defaults */ 127 #define XGE_HAL_DEFAULT_TX_URANGE_A 5 128 #define XGE_HAL_DEFAULT_TX_URANGE_B 15 129 #define XGE_HAL_DEFAULT_TX_URANGE_C 30 130 #define XGE_HAL_DEFAULT_TX_UFC_A 15 131 #define XGE_HAL_DEFAULT_TX_UFC_B 30 132 #define XGE_HAL_DEFAULT_TX_UFC_C 45 133 #define XGE_HAL_DEFAULT_TX_UFC_D 60 134 #define XGE_HAL_DEFAULT_TX_TIMER_CI_EN 1 135 #define XGE_HAL_DEFAULT_TX_TIMER_AC_EN 1 136 #define XGE_HAL_DEFAULT_TX_TIMER_VAL 10000 137 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_B 512 /* bimodal */ 138 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_N 256 /* normal UFC */ 139 #define XGE_HAL_DEFAULT_RX_URANGE_A 10 140 #define XGE_HAL_DEFAULT_RX_URANGE_B 30 141 #define XGE_HAL_DEFAULT_RX_URANGE_C 50 142 #define XGE_HAL_DEFAULT_RX_UFC_A 1 143 #define XGE_HAL_DEFAULT_RX_UFC_B_J 2 144 #define XGE_HAL_DEFAULT_RX_UFC_B_N 8 145 #define XGE_HAL_DEFAULT_RX_UFC_C_J 4 146 #define XGE_HAL_DEFAULT_RX_UFC_C_N 16 147 #define XGE_HAL_DEFAULT_RX_UFC_D 32 148 #define XGE_HAL_DEFAULT_RX_TIMER_AC_EN 1 149 #define XGE_HAL_DEFAULT_RX_TIMER_VAL 384 150 151 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_J 2048 152 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_N 4096 153 #define XGE_HAL_DEFAULT_FIFO_QUEUE_INTR 0 154 #define XGE_HAL_DEFAULT_FIFO_RESERVE_THRESHOLD 0 155 #define XGE_HAL_DEFAULT_FIFO_MEMBLOCK_SIZE PAGESIZE 156 157 /* 158 * this will force HAL to allocate extra copied buffer per TXDL which 159 * size calculated by formula: 160 * 161 * (ALIGNMENT_SIZE * ALIGNED_FRAGS) 162 */ 163 #define XGE_HAL_DEFAULT_FIFO_ALIGNMENT_SIZE 4096 164 #define XGE_HAL_DEFAULT_FIFO_MAX_ALIGNED_FRAGS 1 165 #if defined(__x86) 166 #define XGE_HAL_DEFAULT_FIFO_FRAGS 128 167 #else 168 #define XGE_HAL_DEFAULT_FIFO_FRAGS 64 169 #endif 170 #define XGE_HAL_DEFAULT_FIFO_FRAGS_THRESHOLD 18 171 172 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_J 2 173 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_N 2 174 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_DEFAULT 1 175 #define XGE_HAL_DEFAULT_BACKOFF_INTERVAL_US 64 176 #define XGE_HAL_DEFAULT_RING_PRIORITY 0 177 #define XGE_HAL_DEFAULT_RING_MEMBLOCK_SIZE PAGESIZE 178 179 #define XGE_HAL_DEFAULT_RING_NUM 8 180 #define XGE_HAL_DEFAULT_TMAC_UTIL_PERIOD 5 181 #define XGE_HAL_DEFAULT_RMAC_UTIL_PERIOD 5 182 #define XGE_HAL_DEFAULT_RMAC_HIGH_PTIME 65535 183 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q0Q3 187 184 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q4Q7 187 185 #define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_EN 1 186 #define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_DIS 0 187 #define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_EN 1 188 #define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_DIS 0 189 #define XGE_HAL_DEFAULT_INITIAL_MTU XGE_HAL_DEFAULT_MTU /* 1500 */ 190 #define XGE_HAL_DEFAULT_ISR_POLLING_CNT 0 191 #define XGE_HAL_DEFAULT_LATENCY_TIMER 255 192 #define XGE_HAL_DEFAULT_SPLIT_TRANSACTION XGE_HAL_TWO_SPLIT_TRANSACTION 193 #define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 194 #define XGE_HAL_DEFAULT_MMRB_COUNT 1 /* 1k */ 195 #define XGE_HAL_DEFAULT_SHARED_SPLITS 1 196 #define XGE_HAL_DEFAULT_STATS_REFRESH_TIME 1 197 198 /* 199 * default the size of buffers allocated for ndd interface functions 200 */ 201 #define XGELL_STATS_BUFSIZE 4096 202 #define XGELL_PCICONF_BUFSIZE 2048 203 #define XGELL_ABOUT_BUFSIZE 512 204 #define XGELL_IOCTL_BUFSIZE 64 205 #define XGELL_DEVCONF_BUFSIZE 4096 206 207 /* 208 * xgell_event_e 209 * 210 * This enumeration derived from xgehal_event_e. It extends it 211 * for the reason to get serialized context. 212 */ 213 /* Renamb the macro from HAL */ 214 #define XGELL_EVENT_BASE XGE_LL_EVENT_BASE 215 typedef enum xgell_event_e { 216 /* LL events */ 217 XGELL_EVENT_RESCHED_NEEDED = XGELL_EVENT_BASE + 1, 218 } xgell_event_e; 219 220 typedef struct { 221 int rx_pkt_burst; 222 int rx_buffer_total; 223 int rx_buffer_post_hiwat; 224 int rx_dma_lowat; 225 int tx_dma_lowat; 226 int msi_enable; 227 int lso_enable; 228 } xgell_config_t; 229 230 typedef struct xgell_rx_buffer_t { 231 struct xgell_rx_buffer_t *next; 232 void *vaddr; 233 dma_addr_t dma_addr; 234 ddi_dma_handle_t dma_handle; 235 ddi_acc_handle_t dma_acch; 236 void *lldev; 237 frtn_t frtn; 238 } xgell_rx_buffer_t; 239 240 /* Buffer pool for all rings */ 241 typedef struct xgell_rx_buffer_pool_t { 242 uint_t total; /* total buffers */ 243 uint_t size; /* buffer size */ 244 xgell_rx_buffer_t *head; /* header pointer */ 245 uint_t free; /* free buffers */ 246 uint_t post; /* posted buffers */ 247 uint_t post_hiwat; /* hiwat to stop post */ 248 spinlock_t pool_lock; /* buffer pool lock */ 249 } xgell_rx_buffer_pool_t; 250 251 typedef struct xgelldev xgelldev_t; 252 253 typedef struct xgell_ring_t { 254 xge_hal_channel_h channelh; 255 xgelldev_t *lldev; 256 mac_resource_handle_t handle; /* per ring cookie */ 257 } xgell_ring_t; 258 259 struct xgelldev { 260 caddr_t ndp; 261 mac_handle_t mh; 262 int instance; 263 dev_info_t *dev_info; 264 xge_hal_device_h devh; 265 xgell_ring_t ring_main; 266 xgell_rx_buffer_pool_t bf_pool; 267 int resched_avail; 268 int resched_send; 269 int resched_retry; 270 int tx_copied_max; 271 xge_hal_channel_h fifo_channel; 272 volatile int is_initialized; 273 xgell_config_t config; 274 volatile int in_reset; 275 timeout_id_t timeout_id; 276 kmutex_t genlock; 277 }; 278 279 typedef struct { 280 mblk_t *mblk; 281 ddi_dma_handle_t dma_handles[XGE_HAL_DEFAULT_FIFO_FRAGS]; 282 int handle_cnt; 283 } xgell_txd_priv_t; 284 285 typedef struct { 286 xgell_rx_buffer_t *rx_buffer; 287 } xgell_rxd_priv_t; 288 289 int xgell_device_alloc(xge_hal_device_h devh, dev_info_t *dev_info, 290 xgelldev_t **lldev_out); 291 292 void xgell_device_free(xgelldev_t *lldev); 293 294 int xgell_device_register(xgelldev_t *lldev, xgell_config_t *config); 295 296 int xgell_device_unregister(xgelldev_t *lldev); 297 298 void xgell_callback_link_up(void *userdata); 299 300 void xgell_callback_link_down(void *userdata); 301 302 int xgell_onerr_reset(xgelldev_t *lldev); 303 304 void xge_device_poll_now(void *data); 305 306 #ifdef __cplusplus 307 } 308 #endif 309 310 #endif /* _SYS_XGELL_H */ 311